Embedded RRAM structure, resistive random access memory and preparation method thereof

Abstract

The invention discloses an embedded RRAM (Resistive Random Access Memory) structure, a resistive random access memory and a preparation method thereof, and belongs to the field of semiconductors. By changing the orientation of an electrode plate of a resistive random access memory unit, the plate surface direction of the electrode plate is embedded into one metal layer in the direction perpendicular to a semiconductor substrate panel; inserting a resistive layer between the two electrode plates to prepare a resistive memory unit, and preparing a resistive random access memory on the basis of the resistive memory unit; the distribution orientation of the electrode plates of the resistive random access memory unit in the prior art is changed, and unexpectedly, the situation that in the prior art, after the resistive random access memory unit is inserted, an existing technological process between the two metal interconnection layers is changed and needs to be researched and developed again is avoided, and the resistive random access memory unit can be compatible with an MOS (Metal Oxide Semiconductor) process in the prior art; and the whole resistive random access memory is compact. Through simulation verification, the reliability and operability of the method are not obviously different from those of a conventional technical scheme of stacking wafers in the thickness direction, and the read-write speed is higher than that of the prior art under the same condition.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, relates to a resistive random access memory technology, and specifically relates to an embedded RRAM structure, a resistive random access memory, and a preparation method thereof. Background Art

[0002] A resistive random access memory (RRAM) is a non-volatile memory. The resistive random access memory cell is the core of the resistive random access memory technology. It usually adopts a structure similar to a parallel plate capacitor, that is, a sandwich structure formed by stacking a top electrode (TE), a switch layer, and a bottom electrode (BE) in the wafer thickness direction. Among them, the top and bottom electrodes are conductive metals, and the switch layer is usually a transition metal oxide; by applying an external electric field, a conductive filament channel based on oxygen vacancies is induced to form in the oxide switch layer. Under the excitation of the external electric field, the switch layer can reversibly transform between high and low resistance states, and its high and low resistance states can still be maintained after the electric field is withdrawn; specifically in use, the forming process refers to the process in which the RRAM first jumps from the initial high resistance state to the low resistance state. On the contrary, the RRAM in the low resistance state can be converted to the high resistance state after being applied with a certain voltage excitation. The process of the low resistance state jumping to the high resistance state is called Reset. The RRAM that enters the high resistance state after the Reset process can also be converted to the low resistance state by applying a voltage excitation, and this process is different from the first high resistance state jumping to the low resistance state, and is called the Set process.

[0003] In terms of process implementation, this sandwich structure can usually be directly embedded in the back-end of line (BEOL) to form between two metal layers. Although it can be directly compatible with the existing manufacturing process, the development of the RRAM structure needs to be re-embedded in the process development, and it will make the inter-metal dielectric (IMD) between the two metal layers thicker. The vias in the corresponding interconnect structure cannot reuse the existing process and new processes need to be developed, which invisibly causes the process cycle and cost of secondary development.

[0004] Therefore, it is necessary to improve and research the structure of the resistive random access memory cell to reduce costs, improve structural compactness and yield on the basis of being compatible with the existing CMOS process. Summary of the Invention

[0005] One of the purposes of the present invention is to provide an embedded RRAM structure, which reduces the design and manufacturing costs while retaining the advantages of the RRAM.

[0006] Another object of the present invention is to provide a method for fabricating an embedded RRAM structure, which fabricates the above-mentioned embedded RRAM structure in a low-cost manner to shorten the product development cycle, reduce costs, and improve competitiveness.

[0007] To solve the above technical problems, the technical solution adopted by the present invention is as follows: On the one hand, the present invention provides an embedded RRAM structure, including a first metal interconnect layer, a second metal interconnect layer, and a resistive memory cell, and the resistive memory cell includes a first electrode plate, which is perpendicular to and embedded in the first metal interconnect layer; a second electrode plate, which is parallel to and opposite to the first electrode plate and embedded in the first metal interconnect layer; and a resistive layer, which is embedded between the two electrode plates in the first metal interconnect layer.

[0008] Further, the embedded RRAM structure further includes a third metal interconnect layer, and the third metal interconnect layer has a third metal line for leading out the first electrode plate and the second electrode plate through the third metal line.

[0009] Further, the areas and sizes of the two electrode plates are the same, and the resistive layer is embedded between the two electrode plates.

[0010] Further, the thickness of the electrode plate is 5 - 100 nm, and the thickness of the resistive layer is 3 - 30 nm.

[0011] Further, the area of the electrode plate is 100 - 20000 nm 2 .

[0012] Further, the resistive memory cell is embedded in the second metal interconnect layer.

[0013] Further, the first electrode plates or the second electrode plates of adjacent resistive memory cells share metal leads.

[0014] Further, the materials of the first electrode plate and the second electrode plate are metal conductive materials or metal nitride conductive materials.

[0015] Further, the material of the resistive layer is a transition metal oxide.

[0016] On the other hand, the present invention provides a method for fabricating an embedded RRAM structure, including the following steps: Providing a first semiconductor structure with an interlayer dielectric layer thereon; Fabricating a first metal interconnect layer on the interlayer dielectric layer, and the first metal interconnect layer includes a first metal line, a first electrode plate, a second electrode plate, and a first inter-metal dielectric layer for isolating the three; Prepare a first barrier layer on the first metal interconnect layer; Use an etching process to open a first inter-metal dielectric layer between two electrode plates to form a first groove; Fill the first groove with a resistive switching material; Use a planarization process to planarize the resistive switching material and stop on the first barrier layer to form a resistive switching layer; Deposit a second inter-metal dielectric layer on the first barrier layer; Prepare a second metal line, a first electrode plate lead, and a second electrode plate lead in the second inter-metal dielectric layer to form a second metal interconnect layer, completing the preparation of the embedded RRAM structure.

[0017] Furthermore, preparing the first metal interconnect layer on the inter-layer dielectric layer includes the following steps: Prepare a second barrier layer on the inter-layer dielectric layer of the first semiconductor structure; Prepare a first inter-metal dielectric layer on the second barrier layer; Use an etching process to prepare a metal wire groove, a first electrode plate groove, and a second electrode plate groove on the first inter-metal dielectric layer; Fill the metal wire groove, the first electrode plate groove, and the second electrode plate groove with a conductive material and planarize to complete the preparation of the first metal interconnect layer.

[0018] Furthermore, using an etching process to open a first inter-metal dielectric layer between two electrode plates to form a first groove includes the following steps: Coat a photoresist layer on the first barrier layer, and use photolithography and development techniques to open the photoresist layer above the area between the two electrode plates; Use the second barrier layer as a stop layer and etch to form a first groove; Remove the photoresist material through wet cleaning to complete the opening of the first groove.

[0019] Furthermore, use atomic layer etching or high-selectivity dry etching to form a first groove.

[0020] Furthermore, at least the metal line for leading out the first electrode plate lead and / or the second electrode plate lead is included in the second metal line.

[0021] Furthermore, prepare a third metal interconnect layer on the second metal interconnect layer. The third metal interconnect layer at least includes a third metal line for leading out the second metal line, the first electrode plate lead, and the second electrode plate lead.

[0022] On the other hand, the present invention provides a method for preparing an embedded RRAM structure, including the following steps: Provide a first semiconductor structure with an inter-layer dielectric layer on it; Prepare a first metal interconnection layer on the interlayer dielectric layer; Prepare a second metal interconnection layer on the first metal interconnection layer. The second metal interconnection layer includes second metal lines, a first electrode plate, a second electrode plate, and a second inter-metal dielectric layer that isolates the three; Prepare a first barrier layer on the second metal interconnection layer; Use an etching process to open the second inter-metal dielectric layer between the two electrode plates to form a second groove; Fill the resistive switching material in the second groove; Use a planarization process to planarize the resistive switching material and stop on the first barrier layer to form a resistive switching layer; Deposit a third inter-metal dielectric on the first barrier layer; Prepare third metal lines, a first plate lead, and a second plate lead in the third inter-metal dielectric to form a third metal interconnection layer, completing the preparation of the embedded RRAM structure.

[0023] Furthermore, prepare a fourth metal interconnection layer on the third metal interconnection layer. The fourth metal interconnection layer includes at least fourth metal lines for leading out the third metal lines, the first plate lead, and the second plate lead.

[0024] On the other hand, the present invention provides a resistive random access memory including a semiconductor structure and at least one of the above-mentioned embedded RRAM structures.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows: By changing the orientation of the electrode plates of the resistive memory cell, the present invention changes the stacked electrode plates in the prior art to be inserted vertically (in the direction perpendicular to the panel of the semiconductor substrate), obtaining a resistive memory cell with a new structure. Together with the resistive logic unit in the prior art, it can form a complete resistive random access memory. The unexpected technical effect is that it avoids the situation in the prior art where the existing process between two metal interconnection layers needs to be re-developed after inserting the resistive memory cell, can be compatible with the MOS process in the prior art, and also makes the overall resistive random access memory compact. After simulation verification, the reliability and operability of the present invention have no obvious difference from the conventional technical solutions stacked in the wafer thickness direction in the prior art, and the read and write speed is faster than that of the prior art under the same conditions. Description of the Drawings

[0026] Figure 1 It is a schematic diagram of a common structure of RRAM in the prior art.

[0027] Figure 2 It is a schematic diagram of the structure in which the resistive memory cell is embedded in the first metal interconnection layer in Embodiment 1 of the present invention.

[0028] Figure 3 Schematic diagram of metal line wiring in the second metal interconnection layer in Embodiment 1 of the present invention in a top view state.

[0029] Figure 4 For Figure 2 Schematic diagram showing the distribution of electrode plates and resistive switching layers in a cross-sectional view along the A-A direction in

[0030] Figure 5 Flow chart for fabricating an embedded RRAM structure in the first metal interconnection layer in Embodiment 2 of the present invention.

[0031] Figure 6 Schematic diagram of the first semiconductor structure in Embodiment 2 of the present invention.

[0032] Figure 7 Schematic diagram of fabricating a second barrier layer on the first semiconductor structure in Embodiment 2 of the present invention.

[0033] Figure 8 Schematic diagram of fabricating a first metal interlayer dielectric layer on the second barrier layer in Embodiment 2 of the present invention.

[0034] Figure 9 Schematic diagram of grooving on the first metal interlayer dielectric layer in Embodiment 2 of the present invention.

[0035] Figure 10 Schematic diagram of completing the fabrication of electrode plates in the first metal interconnection layer in Embodiment 2 of the present invention.

[0036] Figure 11 Schematic diagram of fabricating a first barrier layer on the first metal interconnection layer in Embodiment 2 of the present invention.

[0037] Figure 12 Schematic diagram of coating a photoresist layer on the first barrier layer and completing photoresist layer patterning in Embodiment 2 of the present invention.

[0038] Figure 13 Schematic diagram of completing the opening of the first groove on the first metal interconnection layer in Embodiment 2 of the present invention.

[0039] Figure 14 Schematic diagram of filling a resistive switching material in the first groove in Embodiment 2 of the present invention.

[0040] Figure 15 Schematic diagram of planarizing the filled resistive switching material to complete the fabrication of the first metal interconnection layer in Embodiment 2 of the present invention.

[0041] Figure 16 Schematic diagram of fabricating a second metal interlayer dielectric layer on the first metal interconnection layer in Embodiment 2 of the present invention.

[0042] Figure 17Schematic diagram of the resistive memory cell embedded in the second metal interconnect layer in Embodiment 4 of the present invention.

[0043] Figure 18 Flow chart of fabricating an embedded RRAM structure in the second metal interconnect layer in Embodiment 5 of the present invention.

[0044] 30 - RRAM cell, 30a - bottom electrode, 30b - resistive layer, 30c - top electrode, 30d - interlayer dielectric; 100 - first semiconductor structure; 110 - semiconductor substrate, 120 - STI structure, 130 - source electrode, 140 - drain electrode, 150 - gate electrode, 160 - interlayer dielectric layer, 170 - contact hole; 200 - first metal interconnect layer, 210 - second barrier layer, 220 - first metal - insulator layer, 230 - first metal line, 231 - first source lead, 232 - first drain lead, 240 - first groove, 241 - first metal wire groove, 242 - first plate groove, 243 - second plate groove; 300 - resistive memory cell, 310 - first electrode plate, 320 - resistive layer, 321 - resistive material, 330 - second electrode plate; 340 - photoresist layer; 400 - second metal interconnect layer, 410 - first barrier layer, 420 - second metal - insulator layer, 430 - second metal line, 431 - second source lead, 432 - second drain lead, 440 - first plate lead, 450 - second plate lead; 500 - third metal interconnect layer; 510 - third metal line, 520 - first plate lead, 530 - second plate lead, 540 - first barrier layer, 550 - third metal - insulator; 600 - fourth metal interconnect layer, 610 - fourth metal line. Detailed implementation manners

[0045] The following further describes in detail the embodiments of the present invention in conjunction with the drawings and embodiments. The following embodiments are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

[0046] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0047] In the description of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "connected" and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0048] As Figure 1 described, it is a common structure of RRAM in the prior art. Figure 1 The first semiconductor structure 100 shown has a MOS unit. The MOS unit includes an active region isolated on a semiconductor substrate 110 by two STI structures 120 (shallow trench isolation structures). An active electrode 130, a drain electrode 140, and a gate electrode 150 are provided in the active region. Among them, the gate electrode 150 is protected by an interlayer dielectric layer 160, and the source electrode 130 and the drain electrode 140 are led out through contact holes 170; on the interlayer dielectric layer 160 is the first metal interconnection layer 200, and a first metal line 230 for leading out the MOS unit is provided on the first metal interconnection layer 200. It should be noted that Figure 1 It is only a schematic diagram for display. Multiple MOS units can be provided according to needs, and the connection and leading-out methods of the MOS units are not limited to the structure shown in the figure. For example, Figure 1Only the source lead and the drain lead are shown, and there must actually be a gate lead as well. There is a second metal interconnect layer 400 above the first metal interconnect layer 200. The second metal interconnect layer 400 has second metal lines 430. The RRAM cell 30 is disposed between the first metal interconnect layer 200 and the second metal interconnect layer 400 and is wrapped by an interlayer dielectric 30d (IMD); the RRAM cell 30 includes a bottom electrode 30a, a resistive switching layer 30b, and a top electrode 30c stacked in the thickness direction on the blocking layer 20; the bottom electrode 30a is electrically connected to the first metal line 230 through a via; the top electrode 30c is electrically connected to the second metal line 430 through a via; in this structure, limited by the fact that the growth of the semiconductor structure is all deposited in the thickness direction, the RRAM cells designed habitually in the prior art are stacked in the thickness direction, that is, the bottom electrode 30a, the resistive switching layer 30b, and the top electrode 30c are all flat structures and parallel to the semiconductor substrate 110; in this way, between the first metal interconnect layer 200 and the second metal interconnect layer 400, the RRAM cells need to be redesigned, and the connection vias cannot reuse the existing processes, and new processes need to be developed, which invisibly causes the process cycle and cost of secondary development.

[0049] Embodiment 1: To solve the above problems, the present invention redesigned the RRAM cell and provided an embedded RRAM structure fabricated on a semiconductor structure, such as Figures 2 to 4 shown, Figure 2 As shown, a MOS cell is provided on a semiconductor structure for display. The MOS cell includes an active region isolated on the semiconductor substrate 110 through two STI structures 120. A source electrode 130, a drain electrode 140, and a gate electrode 150 are disposed in the active region, wherein the gate electrode 150 is protected by an interlayer dielectric layer 160, and the source electrode 130 and the drain electrode 140 are led out through contact holes 170; above the interlayer dielectric layer 160 is the first metal interconnect layer 200, and the first metal interconnect layer 200 is provided with first metal lines 230 for leading out the MOS cell. It should be noted that Figure 2 This is only a display schematic diagram. Multiple MOS cells can be provided according to needs, and the lead connection method of the MOS cells is not limited to the structure in the figure. For example, Figure 2 only the source lead and the drain lead are shown, and there must actually be a gate lead.

[0050] In this embodiment, the resistive memory cell 300 is embedded in one of the metal interconnect layers. Taking the embedding into the first metal interconnect layer 200 as an example, as Figures 2 to 4 shown, the resistive memory cell 300 includes: A first electrode plate 310, perpendicular to the embedding into the first metal interconnect layer 200; A second electrode plate 330 is embedded in the first metal interconnection layer 200 in parallel and opposite to the first electrode plate 310; and A resistive switching layer 320 is embedded between the first electrode plate 310 and the second electrode plate 330.

[0051] In the present invention, by changing the orientation of the electrode plates of the resistive switching memory cell, the stacked electrode plates in the prior art are changed to be inserted in the vertical direction, that is, the plane of the electrode plate is perpendicular to the panel direction of the semiconductor substrate 110 (or perpendicular to the plane direction of the metal interconnection layer), and a resistive switching memory cell 300 with a new structure is obtained. Together with the resistive switching logic unit in the prior art, it can form a complete resistive switching memory. The unexpected technical effect is that it avoids the situation that the existing process between two metal interconnection layers needs to be re-developed due to the insertion of the resistive switching memory cell in the prior art, can be compatible with the MOS process in the prior art, and also makes the overall resistive switching memory compact. After simulation verification, the reliability and operability of the present invention have no obvious difference from the effects of the conventional technical solutions stacked in the wafer thickness direction in the prior art, and the read and write speed is faster than that of the prior art under the same conditions.

[0052] For the display of functional integrity, a first metal line 230 is also provided in the first metal interconnection layer 200, as Figure 2 shown, at least including a first source lead 231 and a first drain lead 232, which are respectively connected to the source 130 and drain 140 of the MOS unit through contact holes 170; in order to electrically connect and lead out the resistive switching memory cell 300, a second metal line 430, a first electrode plate lead 440 and a second electrode plate lead 450 are provided in the second metal interconnection layer 400. The first electrode plate lead 440 and the second electrode plate lead 450 are respectively connected to the first electrode plate 310 and the second electrode plate 330 through through holes. The second metal line 430 includes a second source lead 431 and a second drain lead 432. The second source lead 431 and the second drain lead 432 are respectively connected to the first source lead 231 and the first drain lead 232 in the first metal interconnection layer 200 through through holes, and are used to lead out the MOS unit.

[0053] The materials of the first electrode plate 310 and the second electrode plate 330 are metal conductive materials, metal nitride conductive materials or similar conductive materials. The metal materials include at least one selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The metal nitrides include nitrides formed by at least one metal selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. In one embodiment, the first electrode plate 310 and the second electrode plate 330 can be of different materials or the same materials, and preferably both are made of TiN.

[0054] The material of the resistive switching layer 320 is a transition metal oxide, a lanthanide metal oxide, or a main group metal oxide of Group IV, V, or VI. Specifically, TiO x , HfO x , AlO x , TaO x , and ZrO x or any one of the like materials, which can be well compatible with the traditional CMOS process.

[0055] In some embodiments, the areas and sizes of the two electrode plates are the same, and the resistive switching layer 320 is just embedded between the two electrode plates. Taking the electrode plates as rectangular plates as an example, the corresponding resistive switching layer 320 is also a rectangular plate sandwiched between two rectangular plates.

[0056] In some embodiments, the thickness of the electrode plates is 5 - 100 nm, and the thickness of the resistive switching layer 320 is 3 - 30 nm. The thickness designs of the electrode plates and the resistive switching layer 320 both need to meet the design rules in the current metal interconnection layer.

[0057] In some embodiments, the area of the electrode plates is 100 - 200000 nm 2 . The area designs of the electrode plates all need to meet the design rules in the current metal interconnection layer. On the premise of meeting the storage function, the smaller the area of the electrode plates, the better, so as to improve the density of the resistive random access memory (RRAM) cells. Therefore, the preferred area range is 100 - 20000 nm 2 .

[0058] In some embodiments, two adjacent resistive random access memory (RRAM) cells 300 can be set in mirror symmetry, so that the adjacent electrode plates can share a lead wire for extraction. Refer to Figure 2 . Among two adjacent resistive random access memory (RRAM) cells 300, two first electrode plates 310 are adjacent and share a first plate lead wire 440, which can save lead wires and simplify the design and manufacturing costs.

[0059] Embodiment 2: As Figure 5 shown, this embodiment provides a preparation method for an embedded RRAM structure, including the following steps: S100. Provide a first semiconductor structure 100, as Figure 6As shown, a MOS unit is schematically shown on the first semiconductor structure 100. The MOS unit includes an active region isolated by two STI structures 120. An active electrode, a drain electrode, and a gate electrode are respectively fabricated in the active region. The gate electrode is encapsulated by an interlayer dielectric layer 160. Contact holes 170 for leading out the source electrode 130 and the drain electrode 140 are provided on the interlayer dielectric layer 160. It should be emphasized that the first semiconductor structure 100 is only a schematic diagram, and different designs are actually required according to the application scenario, which does not affect the solution of the technical problems of the present invention.

[0060] S200. Fabricate a first metal interconnect layer 200 on the interlayer dielectric layer 160. The first metal interconnect layer 200 includes a first metal line 230, a first electrode plate 310, a second electrode plate 330, and a first metal inter-dielectric layer 220 that isolates the three. As Figure 10 shown, electrode plates of two resistive memory cells are fabricated. The first electrode plates 310 of the two resistive memory cells are arranged adjacent to each other. The first metal line 230 includes a first source lead 231 and a first drain lead 232, which are respectively connected to the source electrode 130 and the drain electrode 140 through corresponding contact holes 170.

[0061] S300. Fabricate a first barrier layer 410 on the first metal interconnect layer 200, as Figure 11 shown; S400. Use an etching process to open the first metal inter-dielectric layer 220 between the first electrode plate 310 and the second electrode plate 330 to form a first groove 240, as Figure 13 shown; S500. Fill the first groove 240 with a resistive material 321, as Figure 14 shown; S600. Use a planarization process to planarize the resistive material 321 and stop on the first barrier layer 410 to obtain a resistive layer 320, as Figure 15 shown; S700. Deposit a second metal inter-dielectric layer 420 on the first barrier layer 410, as Figure 16 shown; S800. Fabricate a second metal line 430, a first plate lead 440, and a second plate lead 450 in the second metal inter-dielectric layer 420 to form a second metal interconnect layer 400, as Figure 2 and Figure 3 shown, thus completing the fabrication of the embedded RRAM structure.

[0062] In step S200, fabricating the first metal interconnect layer 200 on the interlayer dielectric layer 160 includes the following steps: Step S210. Fabricate a second barrier layer 210 on the interlayer dielectric layer 160 of the first semiconductor structure 100, as Figure 7as shown; Specifically, it can be formed by physical vapor deposition or chemical vapor deposition. The material of the second barrier layer 210 is a silicon carbide (SiC) layer, a silicon oxynitride (SiON) layer, a silicon carbonitride (SiCN), etc., preferably silicon carbonitride (SiCN).

[0063] Step S220: Prepare the first intermetallic dielectric layer 220 on the second barrier layer 210, such as Figure 8 as shown; The material of the first intermetallic dielectric layer 220 includes oxides formed by tetraethyl orthosilicate (TEOS), undoped silicate glass or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), organosilicate glass (OSG), SiOC), and / or any suitable low-k dielectric material (for example, a material having a dielectric constant lower than that of silicon dioxide), and can be deposited by spin coating, CVD, FCVD, PECVD, PVD or any suitable deposition technique.

[0064] Step S230: Using the second barrier layer 210 as an etch stop layer, prepare the first metal wire groove 241, the first plate groove 242 and the second plate groove 243 on the first intermetallic dielectric layer 220 by an etching process, such as Figure 9 as shown; The etching process can be dry etching (Dry ETCH), wet etching (WET ETCH) or a combination of both. Preferably, dry etching is used for etching, and then wet cleaning is used to remove residues.

[0065] Step S240: Fill the first metal wire groove 241, the first plate groove 242 and the second plate groove 243 with a conductive material and planarize to complete the preparation of the first metal interconnect layer 200, such as Figure 10 as shown; The conductive material is a metal conductive material or a metal nitride conductive material. The metal material includes at least one selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, Ge. The metal nitride includes nitrides formed by at least one metal selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, Ge, such as TiN.

[0066] The thickness of the electrode plate is 5 - 100 nm, and the area is 100 - 20000 nm 2 . For the electrode plate, generally there is no special requirement for the thickness, as long as the electrical performance and process requirements are met. The area of the electrode plate should be such that it can apply enough voltage to generate high and low resistance conversion.

[0067] In step S230, using the second barrier layer 210 as an etch stop layer, preparing the first metal wire groove 241, the first electrode plate groove 242, and the second electrode plate groove 243 on the first inter-metal dielectric layer 220 by an etching process includes the following steps: S231. Coat a photoresist on the first inter-metal dielectric layer 220; S232. Pattern the photoresist using an exposure and development technique; S233. Using the second barrier layer 210 as an etch stop layer, perform dry etching (Dry ETCH), wet etching (WET ETCH), or a combination of both processes. Preferably, perform dry etching, and then use wet cleaning to remove residues, and open the first metal wire groove 241, the first electrode plate groove 242, and the second electrode plate groove 243 on the first inter-metal dielectric layer 220; S234. Use a wet cleaning process to remove the photoresist, obtaining the first metal wire groove 241, the first electrode plate groove 242, and the second electrode plate groove 243, as Figure 9 shown.

[0068] In step S300, the function of the first barrier layer 410 is to isolate between the first electrode plate 310, the second electrode plate 330, and the second metal interconnection layer 400. The preparation process can use physical vapor deposition or chemical vapor deposition methods, and the material is a silicon carbide (SiC) layer, a silicon oxynitride (SiON) layer, a silicon carbonitride (SiCN), etc. Preferably, it is silicon carbonitride (SiCN); the thickness of the first barrier layer 410 is a bit thicker than that in the prior art to provide for grinding and polishing consumption during the subsequent preparation of the resistive switching layer 320. Generally, it is 100 - 200 nm, so that after consumption, it is approximately the same thickness as the barrier layer in the prior art.

[0069] In step S400, using an etching process to open the first inter-metal dielectric layer 220 between the two electrode plates to form the first groove 240 includes the following steps: S410. Coat a photoresist layer 340 on the first barrier layer 410, and use an exposure and development technique to open the photoresist layer 340 above the area between the two electrode plates, as Figure 12 shown; S420. Using the second barrier layer 210 as a stop layer, etch to form the first groove 240; the etching process uses a dry etching with a high selectivity, wet etching, or atomic layer etching to avoid damaging the first electrode plate 310 and the second electrode plate 330 during the etching process; preferably, perform dry etching and wet etching alternately, or use a plasma dry etching (DryPlasma Etching) process, generating active free radicals and ions through a plasma (such as gases like Cl2, HBr, CF4, etc.), and under the action of an electric field, bombarding the wafer surface directionally to achieve anisotropic (vertical) etching.

[0070] S430. Remove the photoresist material by wet cleaning to complete the opening of the first groove 240. As Figure 13 shown, wet cleaning can efficiently remove the residual particles or impurities in the first groove 240, preventing voids or defects from being generated when filling the resistive switching material 321 subsequently, thereby affecting the reliability of the resistive switching memory cell 300.

[0071] In S500, the resistive switching material 321 is a transition metal oxide or a lanthanide metal oxide and a main group metal oxide of IV, V, and VI. Specifically, TiO x , HfO x , AlO x , TaO x and ZrO x and any one of other materials. After selecting the resistive switching material 321, select the corresponding filling process for filling; the present invention can fill a single resistive switching material or a composite resistive switching material, as long as the function of the RRAM cell can be completed.

[0072] The thickness of the resistive switching layer 320 is 3 - 30 nm. Generally, there are no special requirements for the thickness. It is based on the ability to generate high and low resistance conversions when a voltage is applied through the electrode plate, and this conversion can stably exist under voltage control; it should be noted that since the present invention changes the distribution direction of the electrode plate and the resistive switching layer 320, and the thickness of the resistive switching layer 320 is only 3 - 30 nm, which is relatively narrow, and the depth is relatively deep during filling, so a resistive switching material 321 with small particles and high filling efficiency should be preferably selected to obtain a resistive switching layer 320 with good performance.

[0073] In step S700, the materials and processes of the second intermetal dielectric layer 420 and the first intermetal dielectric layer 220 are similar. It can include oxides formed by tetraethyl orthosilicate (TEOS), undoped silicate glass or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), organosilicate glass (OSG), SiOC), and / or any suitable low-k dielectric material (for example, a material having a dielectric constant lower than that of silicon dioxide), and can be deposited by spin coating, CVD, FCVD, PECVD, PVD or any suitable deposition technique.

[0074] In step S800, as Figure 2 shown, prepare the second metal line 430, the first electrode lead 440, and the second electrode lead 450 in the second intermetal dielectric layer 420 to form the second metal interconnect layer 400, including the following steps: S810. Coat a photoresist on the second intermetal dielectric layer 420; S820, patterning the photoresist using an exposure and development technology; S830, performing etching by using an etching process to open a second metal line groove, a first electrode lead groove, and a second electrode lead groove on the second intermetallic dielectric layer 420; S840, removing the photoresist using a wet cleaning process; S850, using a deposition process to fill the conductive material and planarize to complete the preparation of the second metal interconnection layer 400, such as Figure 2 As shown, the conductive material is a metal conductive material or a metal nitride conductive material, and the metal material includes at least one selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The metal nitride includes a nitride formed by at least one metal selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge, such as TiN.

[0075] It should be noted that the second metal line groove should at least include a second source lead groove, a second drain lead groove, a first electrode lead groove and a second electrode lead groove, which are used to prepare the second source lead 431, the second drain lead 432, the first electrode lead 440 and the second electrode lead 450 respectively.

[0076] Embodiment 3: This embodiment provides a resistive random access memory, such as Figure 3 As shown, based on the embedded RRAM structure prepared in Example 2, a third metal interconnection layer 500 is further prepared on the second metal interconnection layer 400, and the third metal interconnection layer 500 includes a third metal line 510 to realize the lead-out of the first electrode lead 440 and the second electrode lead 450, as shown in FIG. Figure 3 As shown, the first electrode plate 310 is equivalent to the bottom electrode plate (BE), and the second electrode plate 330 is equivalent to the top electrode plate (TE). By continuing to prepare more metal interconnection layers or semiconductor structures, the preparation of the resistive random access memory can be completed.

[0077] Embodiment 4: In this embodiment, the resistive memory cell 300 is disposed in the second metal interconnection layer 400, and a third metal interconnection layer 500 needs to be prepared, such as Figure 17 As shown, the resistive memory unit 300 of the present invention needs to occupy space in the metal interconnect layer. In fact, in the process of semiconductor structure stacking, the higher the metal interconnect layer, the sparser the wiring is, the more space there is, and the layout is more flexible. For example, the second metal interconnect layer 400 has more space than the first metal interconnect layer 200, and can be flexibly laid out; therefore, the resistive memory unit 300 can be set in the second metal interconnect layer 400, and the layout is more flexible, and will not affect the original layout of the metal lines.

[0078] In this embodiment, the third metal interconnect layer 500 includes a third metal line 510, a first plate lead 520, and a second plate lead 530. The interconnection between metal layers is achieved through the third metal line 510, and the leads of the first electrode plate 310 and the second electrode plate 330 are achieved through the first plate lead 520 and the second plate lead 530. And at least the fourth metal interconnect layer 600 needs to be fabricated. The fourth metal interconnect layer 600 has a fourth metal line 610 to form a complete control of a single resistive random access memory (RRAM) cell 300, as Figure 17 shown.

[0079] Embodiment 5: As Figure 18 shown, the preparation method of disposing the RRAM cell 300 in the second metal interconnect layer 400 in this embodiment is as follows: S100. Provide a first semiconductor structure 100, and a specific interlayer dielectric layer 160 is formed on the first semiconductor structure 100; S200. Fabricate a first metal interconnect layer 200 on the interlayer dielectric layer 160. The first metal interconnect layer 200 has a first metal line 230, as Figure 17 shown; S300. Fabricate a second metal interconnect layer 400 on the first metal interconnect layer 200. The second metal interconnect layer 400 includes a second metal line 430, a first electrode plate 310, a second electrode plate 330, and a second metal inter-dielectric layer 420 that isolates the three; S400. Deposit a first barrier layer 540 on the second metal interconnect layer 400; S500. Use an etching process to open the second metal inter-dielectric layer 420 between the first electrode plate 310 and the second electrode plate 330 to form a second groove; S600. Fill the second groove with a resistive material; S700. Use a planarization process to planarize the resistive material and stop on the first barrier layer 540 to form a resistive layer 320; the preparation of the RRAM cell is completed.

[0080] S800. Deposit a third metal inter-dielectric 550 on the first barrier layer 540; S900. Fabricate a third metal line 510, a first plate lead 520, and a second plate lead 530 in the third metal inter-dielectric 550 to form a third metal interconnect layer 500; continue to fabricate a fourth metal interconnect layer 600, including a fourth metal line 610, for leading out the third metal line 510, the first plate lead 520, and the second plate lead 530; the preparation of the embedded RRAM structure is completed, and by continuing to fabricate more metal interconnect layers, the fabrication of the resistive random access memory can be completed.

[0081] The above embodiments are only used to illustrate the present invention, rather than to limit the present invention. Although the present invention has been described in detail with reference to the embodiments, those of ordinary skill in the art should understand that various combinations, modifications or equivalent replacements of the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and should all be covered within the scope of the claims of the present invention.

Claims

1. An embedded RRAM structure, comprising a first metal interconnect layer, a second metal interconnect layer and a resistive switching memory cell, characterized in that: The resistive memory unit comprises: a first electrode plate, vertically embedded in the first metal interconnect layer; A second electrode plate, embedded in the first metal interconnect layer and parallel to the first electrode plate; and The resistive switching layer is embedded between two electrode plates in the first metal interconnection layer.

2. The embedded RRAM structure according to claim 1, characterized in that: The resistive memory unit is embedded in the second metal interconnection layer.

3. The embedded RRAM structure according to claim 1, characterized in that: The first electrode plates or the second electrode plates of adjacent resistive memory cells share a metal lead.

4. A method for preparing an embedded RRAM structure, characterized in that: The following steps are involved: Providing a first semiconductor structure, wherein the first semiconductor structure has an interlayer dielectric layer; A first metal interconnection layer is prepared on the interlayer dielectric layer, wherein the first metal interconnection layer includes a first metal line, a first electrode plate, a second electrode plate, and a first intermetallic dielectric layer isolating the three; forming a first barrier layer on the first metal interconnect layer; Using an etching process to open a first intermetallic dielectric layer between two electrode plates to form a first groove; Filling the first groove with a resistive material; The resistive material is flattened by a flattening process and stays on the first barrier layer to form a resistive layer; depositing a second intermetal dielectric layer on the first barrier layer; A second metal line, a first plate lead, and a second plate lead are prepared in the second intermetallic dielectric layer to form a second metal interconnect layer, thereby completing the preparation of the embedded RRAM structure.

5. The method for preparing the embedded RRAM structure according to claim 4, characterized in that: Preparing a first metal interconnection layer on the interlayer dielectric layer comprises the following steps: preparing a second barrier layer on the interlayer dielectric layer of the first semiconductor structure; forming a first intermetallic dielectric layer on the second barrier layer; Using an etching process to prepare a metal line groove, a first electrode plate groove and a second electrode plate groove on the first intermetallic dielectric layer; Conductive material is filled in the metal wire groove, the first electrode plate groove and the second electrode plate groove and planarized to complete the preparation of the first metal interconnection layer.

6. The method for preparing the embedded RRAM structure according to claim 5, characterized in that: The first intermetallic dielectric layer between the two electrode plates is opened by an etching process to form a first groove, comprising the following steps: Coating a photoresist layer on the first barrier layer, and opening the photoresist layer above the area between the two electrode plates by using an exposure and development technology; Using the second barrier layer as a stop layer, etching to form a first groove; The photoresist material is removed by wet cleaning to complete the opening of the first groove.

7. The method for preparing the embedded RRAM structure according to claim 6, characterized in that: The first groove is formed by atomic layer etching or high selectivity dry etching.

8. The method for preparing the embedded RRAM structure according to claim 6, characterized in that: The second metal circuit at least includes a metal circuit leading out the first electrode plate lead and / or the second electrode plate lead.

9. The method for preparing the embedded RRAM structure according to claim 5, characterized in that: A third metal interconnection layer is prepared on the second metal interconnection layer. The third metal interconnection layer at least includes a third metal line for leading out the second metal line, the first electrode lead, and the second electrode lead.

10. A method for preparing an embedded RRAM structure, characterized in that: The following steps are involved: Providing a first semiconductor structure, wherein the first semiconductor structure has an interlayer dielectric layer; preparing a first metal interconnection layer on the interlayer dielectric layer; Preparing a second metal interconnection layer on the first metal interconnection layer, the second metal interconnection layer comprising a second metal line, a first electrode plate, a second electrode plate, and a second intermetallic dielectric layer isolating the three; forming a first barrier layer on the second metal interconnect layer; Using an etching process to open the second intermetallic dielectric layer between the two electrode plates to form a second groove; Filling the second groove with a resistive material; The resistive material is flattened by a flattening process and stays on the first barrier layer to form a resistive layer; depositing a third intermetal dielectric on the first barrier layer; A third metal line, a first plate lead, and a second plate lead are prepared in the third intermetallic dielectric to form a third metal interconnect layer, thereby completing the preparation of the embedded RRAM structure.

11. The method for preparing the embedded RRAM structure according to claim 10, characterized in that: A fourth metal interconnection layer is prepared on the third metal interconnection layer. The fourth metal interconnection layer at least includes a fourth metal line for leading out the third metal line, the first electrode lead, and the second electrode lead.

12. A resistive random access memory, characterized in that: The invention comprises a semiconductor structure and at least one embedded RRAM structure according to any one of claims 1 to 3.

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