Embedded RRAM structure, resistive random access memory and preparation method thereof

Abstract

The present invention discloses an embedded RRAM structure, a resistive random access memory (RRAM), and a method for preparing the same, belonging to the field of semiconductors. The present invention changes the orientation of the electrode plates of the resistive random access memory cell, embedding the electrode plate surface perpendicular to the direction of the semiconductor substrate panel into one of the metal layers, and then inserting a resistive random access layer between the two electrode plates to produce a resistive random access memory cell, which is then used as a basis for preparing the resistive random access memory. This change in the orientation of the electrode plates of the resistive random access memory cell in the prior art surprisingly avoids the situation in the prior art where the insertion of the resistive random access memory cell results in the existing process between the two metal interconnect layers being altered and requiring redevelopment. This method is compatible with the prior art MOS process and makes the resistive random access memory more compact overall. Simulations have shown that the reliability and operability of the present invention are no significantly different from those of conventional technical solutions stacked in the wafer thickness direction, and the read and write speeds are faster than those of the prior art under the same conditions.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors and relates to a resistive random access memory technology, and in particular to an embedded RRAM structure, a resistive random access memory and a preparation method thereof. Background Art

[0002] Resistive Random Access Memory (RRAM) is a non-volatile memory. The RRAM cell is the core of RRAM technology. It usually adopts a structure similar to a parallel plate capacitor, namely a sandwich structure formed by stacking a top electrode (TE), a switch layer (SWITCH LAYER), and a bottom electrode (BE) in the thickness direction of the wafer. The top and bottom electrodes are conductive metals, and the BE is usually a transition metal oxide. An external electric field induces the formation of conductive filament channels based on oxygen vacancies in the oxide BE. Under the stimulation of the external electric field, the BE can undergo a reversible transition between high and low resistance states, and its high and low resistance states can be maintained after the electric field is removed. In specific use, the forming process refers to the process in which the RRAM first jumps from the initial high resistance state to the low resistance state. Conversely, the RRAM in the low resistance state can be converted to the high resistance state after applying a certain voltage. The process of jumping from the low resistance state to the high resistance state is called reset. After the reset process, the RRAM that enters the high-resistance state can also be converted to the low-resistance state by applying voltage stimulation. This process is different from the first high-resistance state jump to the low-resistance state and is called the Set (reset) process.

[0003] In terms of process implementation, this sandwich structure can usually be directly embedded in the back-end of Line (BEOL) between two metal layers. Although it is directly compatible with existing processes, the process development implementation requires the re-embedding of RRAM structure development, and the inter-metal dielectric (IMD) between the two metal layers will become thicker. The corresponding connecting vias (Via) in the interconnect structure cannot reuse the existing process and need to be redeveloped, which invisibly causes the process cycle and cost of secondary development.

[0004] Therefore, it is necessary to improve and develop the structure of the resistive memory unit to reduce costs, improve structural compactness and yield while being compatible with existing CMOS processes. Summary of the Invention

[0005] One of the objectives of the present invention is to provide an embedded RRAM structure that reduces design and manufacturing costs while retaining the advantages of RRAM.

[0006] Another object of the present invention is to provide a method for preparing an embedded RRAM structure, which can be manufactured in a low-cost manner to shorten product development cycle, reduce costs, and improve competitiveness.

[0007] In order to solve the above technical problems, the technical solutions adopted by the present invention are as follows:

[0008] On the one hand, the present invention provides an embedded RRAM structure, a first metal interconnection layer, a second metal interconnection layer and a resistive switching memory unit, wherein the resistive switching memory unit includes

[0009] a first electrode plate, perpendicular to and embedded in the first metal interconnect layer;

[0010] a second electrode plate, embedded in the first metal interconnect layer and parallel to and opposite to the first electrode plate; and

[0011] The resistive switching layer is embedded between the two electrode plates in the first metal interconnection layer.

[0012] Furthermore, the embedded RRAM structure further includes a third metal interconnection layer, wherein the third metal interconnection layer has a third metal line, and the first electrode plate and the second electrode plate are led out through the third metal line.

[0013] Furthermore, the two electrode plates have the same area and size, and the resistive switching layer is embedded between the two electrode plates.

[0014] Furthermore, the thickness of the electrode plate is 5-100 nm, and the thickness of the resistive layer is 3-30 nm.

[0015] Furthermore, the area of the electrode plate is 100-20000nm 2 .

[0016] Furthermore, the resistive switching memory unit is embedded in the second metal interconnection layer.

[0017] Furthermore, the first electrode plates or the second electrode plates of adjacent resistive memory cells share a metal lead.

[0018] Furthermore, the first electrode plate and the second electrode plate are made of metal conductive material or metal nitride conductive material.

[0019] Furthermore, the material of the resistive switching layer is transition metal oxide.

[0020] In another aspect, the present invention provides a method for preparing an embedded RRAM structure, comprising the following steps:

[0021] Providing a first semiconductor structure, wherein the first semiconductor structure has an interlayer dielectric layer;

[0022] A first metal interconnection layer is prepared on the interlayer dielectric layer, wherein the first metal interconnection layer includes a first metal line, a first electrode plate, a second electrode plate, and a first intermetallic dielectric layer isolating the three;

[0023] forming a first barrier layer on the first metal interconnection layer;

[0024] Using an etching process to open a first intermetallic dielectric layer between the two electrode plates to form a first groove;

[0025] Filling the first groove with a resistive material;

[0026] Using a planarization process to planarize the resistive material and allow it to remain on the first barrier layer to form a resistive layer;

[0027] depositing a second intermetallic dielectric layer on the first barrier layer;

[0028] A second metal line, a first plate lead, and a second plate lead are prepared in the second intermetallic dielectric layer to form a second metal interconnect layer, thereby completing the preparation of the embedded RRAM structure.

[0029] Furthermore, preparing a first metal interconnection layer on the interlayer dielectric layer includes the following steps:

[0030] forming a second barrier layer on the interlayer dielectric layer of the first semiconductor structure;

[0031] forming a first intermetallic dielectric layer on the second barrier layer;

[0032] Using an etching process to prepare a metal line groove, a first electrode plate groove and a second electrode plate groove on the first intermetallic dielectric layer;

[0033] Conductive material is filled into the metal wire groove, the first electrode plate groove and the second electrode plate groove and planarized to complete the preparation of the first metal interconnection layer.

[0034] Furthermore, an etching process is used to open the first intermetallic dielectric layer between the two electrode plates to form a first groove, comprising the following steps:

[0035] Coating a photoresist layer on the first barrier layer, and opening the photoresist layer above the area between the two electrode plates by using exposure and development technology;

[0036] Using the second barrier layer as a stop layer, etching to form a first groove;

[0037] The photoresist material is removed by wet cleaning to complete the opening of the first groove.

[0038] Furthermore, the first groove is formed by atomic layer etching or high selectivity dry etching.

[0039] Furthermore, the second metal circuit at least includes a metal circuit leading out the first electrode plate lead and / or the second electrode plate lead.

[0040] Furthermore, a third metal interconnection layer is prepared on the second metal interconnection layer. The third metal interconnection layer at least includes a third metal line for leading out the second metal line, the first electrode lead, and the second electrode lead.

[0041] In another aspect, the present invention provides a method for preparing an embedded RRAM structure, comprising the following steps:

[0042] Providing a first semiconductor structure, wherein the first semiconductor structure has an interlayer dielectric layer;

[0043] preparing a first metal interconnection layer on the interlayer dielectric layer;

[0044] A second metal interconnection layer is formed on the first metal interconnection layer, wherein the second metal interconnection layer includes a second metal line, a first electrode plate, a second electrode plate, and a second intermetallic dielectric layer isolating the three;

[0045] forming a first barrier layer on the second metal interconnection layer;

[0046] Using an etching process to open the second intermetallic dielectric layer between the two electrode plates to form a second groove;

[0047] Filling the second groove with a resistive material;

[0048] Using a planarization process to planarize the resistive material and allow it to remain on the first barrier layer to form a resistive layer;

[0049] depositing a third intermetallic dielectric on the first barrier layer;

[0050] A third metal line, a first plate lead, and a second plate lead are prepared in the third intermetallic dielectric to form a third metal interconnect layer, thereby completing the preparation of the embedded RRAM structure.

[0051] Furthermore, a fourth metal interconnection layer is prepared on the third metal interconnection layer. The fourth metal interconnection layer at least includes a fourth metal line for leading out the third metal line, the first electrode lead, and the second electrode lead.

[0052] In another aspect, the present invention provides a resistive random access memory, comprising a semiconductor structure and at least one of the above-mentioned embedded RRAM structures.

[0053] Compared with the prior art, the present invention has the following beneficial effects:

[0054] By changing the orientation of the electrode plates of the resistive memory cell, the present invention replaces the stacked electrode plates used in the prior art with vertically inserted plates (perpendicular to the direction of the semiconductor substrate). This creates a completely new resistive memory cell structure, which, together with the resistive logic unit used in the prior art, can form a complete resistive memory. This unexpected technical effect avoids the prior art situation in which the insertion of the resistive memory cell requires changes to the existing process between the two metal interconnect layers, requiring redevelopment. This solution is compatible with the prior art MOS process and makes the resistive memory more compact. Simulations have shown that the reliability and operability of the present invention are no different from those of the conventional prior art solution stacked along the wafer thickness, and the read and write speeds are faster than those of the prior art solution under the same conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 Schematic diagram of a common RRAM structure in the prior art.

[0056] Figure 2 This is a structural diagram of a resistive memory unit embedded in a first metal interconnection layer in Example 1 of the present invention.

[0057] Figure 3 This is a schematic diagram of the metal line wiring in the second metal interconnection layer in a top view in Example 1 of the present invention.

[0058] Figure 4 for Figure 2 The cross section in the middle AA direction shows the distribution diagram of the electrode plate and the resistive switching layer.

[0059] Figure 5 This is a flow chart of preparing an embedded RRAM structure in the first metal interconnect layer in Example 2 of the present invention.

[0060] Figure 6 This is a schematic diagram of the first semiconductor structure in Example 2 of the present invention.

[0061] Figure 7 Schematic diagram of the structure of preparing a second barrier layer on the first semiconductor structure in Example 2 of the present invention.

[0062] Figure 8 Schematic diagram of the structure of preparing a first intermetallic dielectric layer on the second barrier layer in Example 2 of the present invention.

[0063] Figure 9 Schematic diagram of trenching on the first intermetallic dielectric layer in Example 2 of the present invention.

[0064] Figure 10 This is a schematic structural diagram of the preparation of the electrode plate in the first metal interconnection layer in Example 2 of the present invention.

[0065] Figure 11Schematic diagram of preparing a first barrier layer on the first metal interconnection layer in Example 2 of the present invention.

[0066] Figure 12 This is a schematic diagram of coating a photoresist layer on the first barrier layer and completing patterning of the photoresist layer in Example 2 of the present invention.

[0067] Figure 13 This is a schematic diagram of completing the opening of the first groove on the first metal interconnection layer in Example 2 of the present invention.

[0068] Figure 14 This is a schematic diagram of filling the resistive material in the first groove in Example 2 of the present invention.

[0069] Figure 15 Schematic diagram of the preparation of the first metal interconnection layer after planarizing the resistive charging material in Example 2 of the present invention.

[0070] Figure 16 Schematic diagram of preparing a second intermetallic dielectric layer on the first metal interconnect layer in Example 2 of the present invention.

[0071] Figure 17 This is a schematic diagram of a resistive memory unit embedded in the second metal interconnect layer in Example 4 of the present invention.

[0072] Figure 18 This is a flow chart of preparing an embedded RRAM structure in the second metal interconnect layer in Example 5 of the present invention.

[0073] 30-RRAM cell, 30a-bottom electrode, 30b-resistive layer, 30c-top electrode, 30d-interlayer dielectric;

[0074] 100 - first semiconductor structure; 110 - semiconductor substrate, 120 - STI structure, 130 - source, 140 - drain, 150 - gate, 160 - interlayer dielectric layer, 170 - contact hole;

[0075] 200 - first metal interconnect layer, 210 - second barrier layer, 220 - first intermetallic dielectric layer, 230 - first metal line, 231 - first source lead, 232 - first drain lead, 240 - first groove, 241 - first metal line groove, 242 - first plate groove, 243 - second plate groove;

[0076] 300 - resistive memory unit, 310 - first electrode plate, 320 - resistive layer, 321 - resistive material, 330 - second electrode plate; 340 - photoresist layer;

[0077] 400 - second metal interconnect layer, 410 - first barrier layer, 420 - second intermetallic dielectric layer, 430 - second metal line, 431 - second source lead, 432 - second drain lead, 440 - first plate lead, 450 - second plate lead;

[0078] 500 - third metal interconnect layer; 510 - third metal line, 520 - first plate lead, 530 - second plate lead, 540 - first barrier layer, 550 - third intermetallic dielectric;

[0079] 600 - fourth metal interconnection layer, 610 - fourth metal line. DETAILED DESCRIPTION

[0080] The following embodiments of the present invention are described in further detail with reference to the accompanying drawings and examples. The following examples are used to illustrate the present invention but are not intended to limit the scope of the present invention.

[0081] In the description of the present invention, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0082] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integral connection; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediary. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0083] like Figure 1 The above is a common structure of RRAM in the prior art. Figure 1The first semiconductor structure 100 shown has a MOS cell. The MOS cell includes an active region isolated on a semiconductor substrate 110 by two STI structures 120 (shallow trench isolation structures). A source 130, a drain 140, and a gate 150 are provided in the active region. The gate 150 is protected by an interlayer dielectric layer 160. The source 130 and the drain 140 are led out through contact holes 170. A first metal interconnect layer 200 is provided on the interlayer dielectric layer 160. A first metal line 230 for leading out of the MOS cell is provided on the first metal interconnect layer 200. It should be noted that Figure 1 This is just a schematic diagram. Multiple MOS units can be provided as needed, and the lead connection method of the MOS unit is not limited to the structure in the figure. For example, Figure 1 Only the source and drain leads are shown in the figure, but there must be a gate lead in reality. A second metal interconnect layer 400 is provided above the first metal interconnect layer 200, and a second metal line 430 is provided in the second metal interconnect layer 400. The RRAM cell 30 is provided between the first metal interconnect layer 200 and the second metal interconnect layer 400, and is wrapped by an interlayer dielectric 30d (IMD). The RRAM cell 30 includes a bottom electrode 30a, a resistive switching layer 30b, and a top electrode 30c stacked on the barrier layer 20 in the thickness direction. The bottom electrode 30a is connected to the first metal line 230 through a via. The top electrode 30c is connected to the second metal line 230 through a via. The two metal lines 430 are conductive. In this structure, due to the limitation that the growth of the semiconductor structure is all deposited in the thickness direction, the conventional art usually designs RRAM cells stacked in the thickness direction, that is, the bottom electrode 30a, the resistive layer 30b and the top electrode 30c are all flat-plate structures and parallel to the semiconductor substrate 110. As a result, the RRAM cell needs to be redesigned between the first metal interconnect layer 200 and the second metal interconnect layer 400, and the connecting through hole cannot reuse the existing process, and a new process needs to be redeveloped, which invisibly increases the process cycle and cost of secondary development.

[0084] Example 1: In order to solve the above problems, the present invention redesigns the RRAM unit and provides an embedded RRAM structure, which is prepared on a semiconductor structure, such as Figures 2 to 4 As shown, Figure 2 A semiconductor structure is shown having a MOS cell. The MOS cell includes an active region isolated on a semiconductor substrate 110 by two STI structures 120. A source 130, a drain 140, and a gate 150 are provided in the active region. The gate 150 is protected by an interlayer dielectric layer 160. The source 130 and the drain 140 are led out through contact holes 170. A first metal interconnect layer 200 is provided on the interlayer dielectric layer 160. A first metal line 230 for leading out of the MOS cell is provided on the first metal interconnect layer 200. It should be noted that Figure 2This is just a schematic diagram. Multiple MOS units can be provided as needed, and the lead connection method of the MOS unit is not limited to the structure in the figure. For example, Figure 2 Only the source and drain leads are shown; in practice there must also be a gate lead.

[0085] In this embodiment, the resistive memory unit 300 is embedded in one of the metal interconnection layers, for example, the first metal interconnection layer 200 is embedded in the resistive memory unit 300. Figures 2 to 4 As shown, the resistive memory unit 300 includes:

[0086] A first electrode plate 310 , vertically embedded in the first metal interconnect layer 200 ;

[0087] A second electrode plate 330 , parallel to and opposite to the first electrode plate 310 , is embedded in the first metal interconnection layer 200 ; and

[0088] The resistive layer 320 is embedded between the first electrode plate 310 and the second electrode plate 330 .

[0089] By changing the orientation of the electrode plates of the resistive memory cell, the present invention replaces the stacked electrode plates of the prior art with vertical insertion, i.e., the electrode plate surfaces are perpendicular to the panel direction of the semiconductor substrate 110 (or perpendicular to the layer direction of the metal interconnect layer). This results in a completely new resistive memory cell structure 300, which, together with the resistive logic unit of the prior art, can form a complete resistive memory. This unexpected technical effect avoids the prior art situation in which the insertion of the resistive memory cell requires changes to the existing process between the two metal interconnect layers, requiring redevelopment. This allows compatibility with the prior art MOS process and makes the resistive memory more compact overall. Simulations have shown that the reliability and operability of the present invention are no significantly different from those of the conventional prior art solution stacked along the wafer thickness, and the read and write speeds are faster than those of the prior art under the same conditions.

[0090] In order to demonstrate the functional integrity, the first metal interconnection layer 200 is further provided with a first metal line 230, such as Figure 2As shown, it at least includes a first source lead 231 and a first drain lead 232, which are respectively connected to the source 130 and the drain 140 of the MOS unit through the contact hole 170; in order to electrically connect and lead out the resistive memory unit 300, a second metal line 430, a first electrode lead 440 and a second electrode lead 450 are provided in the second metal interconnection layer 400, and the first electrode lead 440 and the second electrode lead 450 are respectively connected to the first electrode plate 310 and the second electrode plate 330 through through holes, and the second metal line 430 includes a second source lead 431 and a second drain lead 432, and the second source lead 431 and the second drain lead 432 are respectively connected to the first source lead 231 and the first drain lead 232 in the first metal interconnection layer 200 through through holes, for leading out the MOS unit.

[0091] The first electrode plate 310 and the second electrode plate 330 are made of a metal conductive material, a metal nitride conductive material, or a similar conductive material. The metal material includes at least one selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The metal nitride includes a nitride formed from at least one metal selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. In one embodiment, the first electrode plate 310 and the second electrode plate 330 can be made of different materials or the same material, and preferably, both are made of TiN.

[0092] The material of the resistive layer 320 is a transition metal oxide or a lanthanide metal oxide or a metal oxide of Group IV, V, or VI. x , HfO x 、AlO x 、TaO x and ZrO x Any of the materials mentioned above can be well compatible with traditional CMOS process.

[0093] In some embodiments, the two electrode plates have the same area and size, and the resistive layer 320 is just embedded between the two electrode plates. Taking the electrode plates as rectangular plates as an example, the corresponding resistive layer 320 is also a rectangular plate sandwiched between the two rectangular plates.

[0094] In some embodiments, the thickness of the electrode plate is 5-100 nm, and the thickness of the resistive layer 320 is 3-30 nm. The thickness designs of the electrode plate and the resistive layer 320 need to meet the design rules of the current metal interconnection layer.

[0095] In some embodiments, the area of the electrode plate is 100-200000 nm 2The area design of the electrode plate needs to meet the design rules of the current metal interconnect layer. Under the premise of meeting the storage function, the smaller the area of the electrode plate, the better, in order to improve the density of the resistive memory cell. Therefore, the preferred area range is 100-20000nm 2 .

[0096] In some embodiments, two adjacent resistive memory cells 300 can be arranged in a mirror-symmetrical manner, so that adjacent electrode plates can share a common lead wire. Figure 2 In two adjacent resistive memory cells 300 , two adjacent first electrode plates 310 share a first electrode plate lead 440 , which can save leads and simplify design and manufacturing costs.

[0097] Example 2: Figure 5 As shown, this embodiment provides a method for preparing an embedded RRAM structure, comprising the following steps:

[0098] S100, providing a first semiconductor structure 100, such as Figure 6 As shown, a MOS unit is schematically illustrated on the first semiconductor structure 100. The MOS unit includes an active area isolated by two STI structures 120. The source, drain and gate are respectively prepared in the active area. The gate is encapsulated by an interlayer dielectric layer 160. The interlayer dielectric layer 160 is provided with a contact hole 170 for leading out the source 130 and the drain 140. It should be emphasized that the first semiconductor structure 100 is only a schematic diagram. Different designs are actually required according to the application scenario, which does not affect the technical problem solved by the present invention.

[0099] S200, preparing a first metal interconnection layer 200 on the interlayer dielectric layer 160, the first metal interconnection layer 200 including a first metal line 230, a first electrode plate 310, a second electrode plate 330 and a first intermetallic dielectric layer 220 isolating the three; Figure 10 As shown, two electrode plates of resistive memory cells are prepared, the first electrode plates 310 of the two resistive memory cells are arranged adjacent to each other, and the first metal line 230 includes a first source lead 231 and a first drain lead 232, which are connected to the source 130 and the drain 140 through corresponding contact holes 170 respectively.

[0100] S300, preparing a first barrier layer 410 on the first metal interconnection layer 200, such as Figure 11 As shown;

[0101] S400, using an etching process to open the first intermetallic dielectric layer 220 between the first electrode plate 310 and the second electrode plate 330 to form a first groove 240, such as Figure 13 As shown;

[0102] S500, filling the first groove 240 with a resistive material 321, such as Figure 14 As shown;

[0103] S600, planarizing the resistive material 321 using a planarization process and leaving it on the first barrier layer 410 to obtain a resistive layer 320, such as Figure 15 As shown;

[0104] S700, depositing a second intermetallic dielectric layer 420 on the first barrier layer 410, as shown in FIG. Figure 16 As shown;

[0105] S800, prepare the second metal line 430, the first electrode lead 440, and the second electrode lead 450 in the second intermetallic dielectric layer 420 to form the second metal interconnect layer 400, such as Figure 2 and Figure 3 As shown, the preparation of the embedded RRAM structure is completed.

[0106] In step S200, forming the first metal interconnection layer 200 on the interlayer dielectric layer 160 includes the following steps:

[0107] Step S210: Prepare a second barrier layer 210 on the interlayer dielectric layer 160 of the first semiconductor structure 100. Figure 7 As shown;

[0108] Specifically, the second barrier layer 210 may be formed by physical vapor deposition or chemical vapor deposition. The material of the second barrier layer 210 is silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), etc., preferably silicon carbonitride (SiCN).

[0109] Step S220: Prepare a first intermetallic dielectric layer 220 on the second barrier layer 210. Figure 8 As shown; the material of the first intermetallic dielectric layer 220 includes an oxide formed of tetraethyl orthosilicate (TEOS), undoped silicate glass or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), organosilicate glass (OSG), SiOC) and / or any suitable low-k dielectric material (e.g., a material having a dielectric constant lower than that of silicon dioxide), and can be deposited by spin coating, CVD, FCVD, PECVD, PVD or any suitable deposition technique.

[0110] Step S230: Using the second barrier layer 210 as an etching stop layer, an etching process is used to prepare a first metal line groove 241, a first electrode groove 242, and a second electrode groove 243 on the first intermetallic dielectric layer 220. Figure 9As shown; the etching process can be dry etching (Dry ETCH), wet etching (WET ETCH) or a combination of the two processes. Preferably, dry etching is used for etching, and then wet cleaning is used to remove residues.

[0111] Step S240: Fill the first metal wire groove 241, the first electrode groove 242 and the second electrode groove 243 with conductive material and planarize them to complete the preparation of the first metal interconnection layer 200. Figure 10 As shown; the conductive material is a metal conductive material or a metal nitride conductive material, the metal material includes at least one selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The metal nitride includes a nitride formed by at least one metal selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge, such as TiN.

[0112] The thickness of the electrode plate is 5-100nm and the area is 100-20000nm 2 For the electrode plate, there is generally no special requirement for thickness, as long as it meets the electrical performance and process requirements. The area of the electrode plate can be such that sufficient voltage can be applied to produce high and low resistance conversion.

[0113] In step S230, the second barrier layer 210 is used as an etch stop layer, and an etching process is used to prepare the first metal line trench 241, the first electrode plate trench 242, and the second electrode plate trench 243 on the first intermetallic dielectric layer 220, including the following steps:

[0114] S231, coating photoresist on the first intermetallic dielectric layer 220;

[0115] S232, patterning the photoresist using exposure and development technology;

[0116] S233, using the second barrier layer 210 as an etch stop layer, performing dry etching, wet etching, or a combination thereof, preferably dry etching, and then performing wet cleaning to remove residues, thereby forming a first metal line trench 241, a first electrode plate trench 242, and a second electrode plate trench 243 on the first intermetallic dielectric layer 220;

[0117] S234, using a wet cleaning process to remove the photoresist, to obtain the first metal line groove 241, the first electrode groove 242 and the second electrode groove 243, as shown in FIG. Figure 9 shown.

[0118] In step S300, the first barrier layer 410 serves to isolate the first electrode plate 310, the second electrode plate 330, and the second metal interconnect layer 400. The preparation process may be physical vapor deposition or chemical vapor deposition, and the material may be silicon carbide (SiC) layer, silicon oxynitride (SiON) layer, silicon carbonitride (SiCN), etc., preferably silicon carbonitride (SiCN). The thickness of the first barrier layer 410 is thicker than that in the prior art to allow for subsequent grinding and polishing consumption during the preparation of the resistive switching layer 320. The thickness is generally 100-200 nm, so that the thickness after consumption is roughly the same as that of the barrier layer in the prior art.

[0119] In step S400, an etching process is used to open the first intermetallic dielectric layer 220 between the two electrode plates to form a first groove 240, including the following steps:

[0120] S410, coating a photoresist layer 340 on the first barrier layer 410, and opening the photoresist layer 340 above the area between the two electrode plates by using exposure and development technology, such as Figure 12 As shown;

[0121] S420, using the second barrier layer 210 as a stop layer, etching to form a first groove 240; the etching process adopts dry etching, wet etching or atomic layer etching with a high selectivity to avoid damaging the first electrode plate 310 and the second electrode plate 330 during the etching process; preferably, dry etching and wet etching are performed alternately, and a plasma dry etching (Dry Plasma Etching) process can also be used to generate active free radicals and ions through plasma (such as Cl2, HBr, CF4 and other gases), which directionally bombard the wafer surface under the action of an electric field to achieve anisotropic (vertical) etching.

[0122] S430, remove the photoresist material by wet cleaning to complete the opening of the first groove 240, such as Figure 13 As shown, wet cleaning can effectively remove particles or impurities remaining in the first groove 240 , preventing the impurities from generating voids or defects when the resistive material 321 is subsequently filled, thereby affecting the reliability of the resistive memory unit 300 .

[0123] In S500, the resistive material 321 is a transition metal oxide or a lanthanide metal oxide or a metal oxide of Group IV, V, or VI. Specifically, TiO x , HfO x 、AlO x 、TaO x and ZrO x After selecting the resistive material 321, a corresponding filling process can be selected; the present invention can be filled with a single resistive material or a composite resistive material, as long as the RRAM unit function can be completed.

[0124] The thickness of the resistive layer 320 is 3-30nm. There is generally no special requirement for the thickness. The standard is to be able to generate high and low resistance conversion when voltage is applied through the electrode plate, and this conversion can exist stably under voltage control. It should be noted that since the present invention changes the distribution direction of the electrode plate and the resistive layer 320, and the thickness of the resistive layer 320 is only 3-30nm, which is relatively narrow, the depth is relatively deep when filled. Therefore, it should be given priority to select a resistive material 321 with small particles and high filling efficiency to obtain a resistive layer 320 with good performance.

[0125] In step S700, the second intermetal dielectric layer 420 is made of a material and a process similar to that of the first intermetal dielectric layer 220, and may include an oxide formed of tetraethyl orthosilicate (TEOS), undoped silicate glass or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), organosilicate glass (OSG), SiOC, and / or any suitable low-k dielectric material (e.g., a material having a dielectric constant lower than that of silicon dioxide), and may be deposited by spin coating, CVD, FCVD, PECVD, PVD, or any suitable deposition technique.

[0126] In step S800, if Figure 2 As shown, preparing a second metal line 430, a first plate lead 440, and a second plate lead 450 in the second intermetallic dielectric layer 420 to form a second metal interconnect layer 400 includes the following steps:

[0127] S810, coating photoresist on the second intermetallic dielectric layer 420;

[0128] S820, patterning the photoresist using exposure and development technology;

[0129] S830, performing etching using an etching process to open a second metal line groove, a first electrode plate lead groove, and a second electrode plate lead groove on the second intermetallic dielectric layer 420;

[0130] S840, removing the photoresist using a wet cleaning process;

[0131] S850, using a deposition process to fill the conductive material and planarize it to complete the preparation of the second metal interconnection layer 400, such as Figure 2As shown, the conductive material is a metal conductive material or a metal nitride conductive material, wherein the metal material includes at least one selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The metal nitride includes a nitride formed from at least one metal selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge, such as TiN.

[0132] It should be noted that the second metal line groove should at least include a second source lead groove, a second drain lead groove, a first electrode lead groove and a second electrode lead groove, which are used to prepare the second source lead 431, the second drain lead 432, the first electrode lead 440 and the second electrode lead 450 respectively.

[0133] Embodiment 3: This embodiment provides a resistive random access memory, such as Figure 3 As shown, based on the embedded RRAM structure prepared in Example 2, a third metal interconnection layer 500 is further prepared on the second metal interconnection layer 400. The third metal interconnection layer 500 includes a third metal line 510 to realize the lead-out of the first electrode lead 440 and the second electrode lead 450. Figure 3 As shown, the first electrode plate 310 is equivalent to the bottom electrode plate (BE), and the second electrode plate 330 is equivalent to the top electrode plate (TE). By continuing to prepare more metal interconnect layers or semiconductor structures, the preparation of the resistive random access memory can be completed.

[0134] Example 4: In this example, the resistive memory cell 300 is disposed in the second metal interconnection layer 400, and a third metal interconnection layer 500 needs to be prepared, such as Figure 17 As shown, the resistive memory unit 300 of the present invention needs to occupy space in the metal interconnect layer. In fact, in the process of stacking the semiconductor structure, the higher the metal interconnect layer is, the sparser the wiring is, the more space it has and the more flexible the layout is. For example, the second metal interconnect layer 400 has more space than the first metal interconnect layer 200 and can be flexibly arranged; therefore, the resistive memory unit 300 can be set in the second metal interconnect layer 400, which has a more flexible layout and will not affect the layout of the original metal lines.

[0135] In this embodiment, the third metal interconnection layer 500 includes a third metal line 510, a first electrode lead 520, and a second electrode lead 530. The third metal line 510 is used to interconnect the metal layers, and the first electrode plate 310 and the second electrode plate 330 are led out through the first electrode lead 520 and the second electrode lead 530. At least a fourth metal interconnection layer 600 needs to be manufactured, and the fourth metal interconnection layer 600 has a fourth metal line 610 in order to form a complete control of a single resistive memory cell 300. Figure 17 shown.

[0136] Example 5: Figure 18 As shown, the manufacturing method of setting the resistive memory unit 300 in the second metal interconnection layer 400 in this embodiment is as follows:

[0137] S100, providing a first semiconductor structure 100, and an interlayer dielectric layer 160 on the first semiconductor structure 100;

[0138] S200, preparing a first metal interconnection layer 200 on the interlayer dielectric layer 160, wherein the first metal interconnection layer 200 includes a first metal line 230, such as Figure 17 As shown;

[0139] S300, forming a second metal interconnection layer 400 on the first metal interconnection layer 200, wherein the second metal interconnection layer 400 includes a second metal line 430, a first electrode plate 310, a second electrode plate 330, and a second intermetallic dielectric layer 420 isolating the three.

[0140] S400, forming a first barrier layer 540 on the second metal interconnection layer 400;

[0141] S500, using an etching process to open the second intermetallic dielectric layer 420 between the first electrode plate 310 and the second electrode plate 330 to form a second groove;

[0142] S600, filling the second groove with a resistive switching material;

[0143] S700 , planarizing the resistive switching material using a planarization process and allowing the planarized material to remain on the first barrier layer 540 to form a resistive switching layer 320 ; thus completing the preparation of the resistive switching unit.

[0144] S800 , depositing a third intermetallic dielectric 550 on the first barrier layer 540 ;

[0145] S900, prepare a third metal line 510, a first plate lead 520, and a second plate lead 530 in the third intermetallic dielectric 550 to form a third metal interconnect layer 500; continue to prepare a fourth metal interconnect layer 600, including a fourth metal line 610, which is used to lead out the third metal line 510, the first plate lead 520, and the second plate lead 530; complete the preparation of the embedded RRAM structure, continue to prepare more metal interconnect layers, and the production of the resistive random access memory can be completed.

[0146] The above embodiments are intended to illustrate the present invention only and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that various combinations, modifications, or equivalent substitutions of the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention and should be encompassed by the scope of the claims of the present invention.

Claims

1. A method for preparing an embedded RRAM structure, characterized in that: The following steps are involved: Providing a first semiconductor structure, wherein the first semiconductor structure has an interlayer dielectric layer; A first metal interconnection layer is prepared on the interlayer dielectric layer, wherein the first metal interconnection layer includes a first metal line, a first electrode plate, a second electrode plate, and a first intermetallic dielectric layer isolating the three; forming a first barrier layer on the first metal interconnection layer; Using an etching process to open a first intermetallic dielectric layer between the two electrode plates to form a first groove; Filling the first groove with a resistive material; Using a planarization process to planarize the resistive material and allow it to remain on the first barrier layer to form a resistive layer; depositing a second intermetallic dielectric layer on the first barrier layer; A second metal line, a first plate lead, and a second plate lead are prepared in the second intermetallic dielectric layer to form a second metal interconnect layer, thereby completing the preparation of the embedded RRAM structure.

2. The method for preparing the embedded RRAM structure according to claim 1, wherein: The process of preparing a first metal interconnection layer on the interlayer dielectric layer comprises the following steps: forming a second barrier layer on the interlayer dielectric layer of the first semiconductor structure; forming a first intermetallic dielectric layer on the second barrier layer; Using an etching process to prepare a metal line groove, a first electrode plate groove and a second electrode plate groove on the first intermetallic dielectric layer; Conductive material is filled into the metal wire groove, the first electrode plate groove and the second electrode plate groove and planarized to complete the preparation of the first metal interconnection layer.

3. The method for preparing the embedded RRAM structure according to claim 2, wherein: The first intermetallic dielectric layer between the two electrode plates is opened by an etching process to form a first groove, comprising the following steps: Coating a photoresist layer on the first barrier layer, and opening the photoresist layer above the area between the two electrode plates by using exposure and development technology; Using the second barrier layer as a stop layer, etching to form a first groove; The photoresist material is removed by wet cleaning to complete the opening of the first groove.

4. The method for preparing the embedded RRAM structure according to claim 3, wherein: The first groove is formed by atomic layer etching or high-selectivity dry etching.

5. The method for preparing the embedded RRAM structure according to claim 3, wherein: The second metal circuit at least includes a metal circuit leading out the first electrode plate lead and / or the second electrode plate lead.

6. The method for preparing the embedded RRAM structure according to claim 2, wherein: A third metal interconnection layer is prepared on the second metal interconnection layer. The third metal interconnection layer at least includes a third metal line for leading out the second metal line, the first electrode lead, and the second electrode lead.

7. An embedded RRAM structure, characterized in that: The embedded RRAM structure obtained by the preparation method according to any one of claims 1 to 6 includes a first metal interconnection layer, a second metal interconnection layer and a resistive memory unit, wherein the resistive memory unit includes: a first electrode plate, perpendicular to and embedded in the first metal interconnect layer; a second electrode plate, embedded in the first metal interconnect layer and parallel to and opposite to the first electrode plate; and The resistive switching layer is embedded between the two electrode plates in the first metal interconnection layer.

8. The embedded RRAM structure according to claim 7, wherein: The resistive memory unit is embedded in the second metal interconnection layer.

9. The embedded RRAM structure according to claim 7, wherein: The first electrode plates or the second electrode plates of adjacent resistive memory cells share a metal lead.

10. A method for preparing an embedded RRAM structure, characterized in that: The following steps are involved: Providing a first semiconductor structure, wherein the first semiconductor structure has an interlayer dielectric layer; preparing a first metal interconnection layer on the interlayer dielectric layer; A second metal interconnection layer is formed on the first metal interconnection layer, wherein the second metal interconnection layer includes a second metal line, a first electrode plate, a second electrode plate, and a second intermetallic dielectric layer isolating the three; forming a first barrier layer on the second metal interconnection layer; Using an etching process to open the second intermetallic dielectric layer between the two electrode plates to form a second groove; Filling the second groove with a resistive material; Using a planarization process to planarize the resistive material and allow it to remain on the first barrier layer to form a resistive layer; depositing a third intermetallic dielectric on the first barrier layer; A third metal line, a first plate lead, and a second plate lead are prepared in the third intermetallic dielectric to form a third metal interconnect layer, thereby completing the preparation of the embedded RRAM structure.

11. The method for preparing the embedded RRAM structure according to claim 10, wherein: A fourth metal interconnection layer is prepared on the third metal interconnection layer. The fourth metal interconnection layer includes at least a fourth metal line for leading out the third metal line, the first electrode lead, and the second electrode lead.

12. A resistive random access memory, characterized in that: The method comprises a semiconductor structure and at least one embedded RRAM structure according to any one of claims 7 to 9.

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