Low-capacity TVS tube and preparation method thereof

Abstract

The invention provides a low-capacity TVS (Transient Voltage Suppressor) tube and a preparation method thereof. The low-capacity TVS tube is provided with a P-type substrate provided with a groove, and a first N + layer and a first N-layer which are sequentially arranged on the groove; wherein two sides of the first N + layer perpendicular to the epitaxial growth direction are provided with first isolation dielectric layers, two sides of the first N-layer perpendicular to the epitaxial growth direction are provided with second isolation dielectric layers, one side, far away from the first N + layer, of the first N-layer is doped with P-type ions, and a first region, doped with the P-type ions, in the first N-layer is connected with an electrode. The grooves are etched by using a relatively large depth-to-width ratio, so that the risks of difficulty in digging deep grooves and insufficient filling of isolation dielectric layers are avoided, the process difficulty is greatly reduced, meanwhile, isolation is performed in advance by using the isolation dielectric layers, isolation failure caused by the problems of diffusion, alignment and the like is avoided, in addition, the width of the PN junction can be flexibly adjusted according to design requirements, and the manufacturing cost is reduced. And therefore, the surge capacity can be improved, and the capacitance can also be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and particularly relates to a low-capacitance TVS tube and a preparation method thereof. Background Art

[0002] When today's electronic industry is booming, various electronic products such as smart phones, Internet of Things devices, and high-speed communication base stations have increasingly stringent requirements for circuit protection components. The low-capacitance TVS tube has been widely used due to its advantage of effectively suppressing transient overvoltage in a capacitance-sensitive environment in high-speed signal lines.

[0003] However, the structural design of traditional low-capacitance TVS tubes limits their surge current-carrying capacity. When encountering high-intensity transient surges, it is often difficult to effectively protect the circuit, resulting in equipment failures or even damage.

[0004] The traditional low-capacitance TVS tube structure uses deep trenches for isolation. There are two problems. One is that the deep trenches require extremely high equipment capabilities, and both the trench digging and filling processes are difficult. The other is that the low-capacitance diode and the TVS diode are stacked vertically and have the same junction area. Although the surge capacity of the TVS can be improved by increasing the junction area, the capacitance of the upper low-capacitance diode will increase with the increase in area, which is not worth the loss. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to provide a low-capacitance TVS tube and a preparation method thereof, aiming to reduce the process difficulty, reduce the failures caused by trench digging and filling, and at the same time, increase the surge capacity of the TVS tube and reduce the capacitance of the low-capacitance diode.

[0006] According to an embodiment of the present invention, a low-capacitance TVS tube includes a first P-type substrate with a groove formed therein, a first N+ layer and a first N- layer sequentially disposed on the groove. Wherein, first isolation dielectric layers are disposed on both sides of the first N+ layer in a direction perpendicular to the epitaxial growth direction, second isolation dielectric layers are disposed on both sides of the first N- layer in a direction perpendicular to the epitaxial growth direction, the side of the first N- layer away from the first N+ layer is doped with P-type ions, and a first region doped with P-type ions in the first N- layer is connected to an electrode.

[0007] Further, the doping concentration of the first P-type substrate is 1E17 atom / cm 3 ~9E19 atom / cm 3 .

[0008] Further, the depth of the groove is 2 μm to 10 μm.

[0009] Further, the thickness of the first isolation dielectric layer is 1 μm to 3 μm.

[0010] Further, the impurity in the first N+ layer is As element, and the doping concentration is 1E13 atom / cm 3 ~9E17 atom / cm 3 。

[0011] Further, the thickness of the second isolation dielectric layer is 10μm - 20μm.

[0012] Further, the impurity in the first N- layer is P element or As element, and the doping concentration is 1E12 atom / cm 3 ~9E14 atom / cm 3 。

[0013] Further, the impurity doped with P-type ions in the first N- layer is B element, and the concentration is 1E14 atom / cm 3 ~9E16 atom / cm 3 。 According to a method for manufacturing a low-capacitance TVS diode in an embodiment of the present invention, for manufacturing the above low-capacitance TVS diode, the method includes: Providing a P-type substrate, and etching a groove on the P-type substrate; Depositing an oxide layer in the groove, and etching the middle part of the oxide layer to obtain a first isolation dielectric layer; Epitaxially growing an initial N+ layer, and obtaining a first N+ layer after grinding; Depositing an oxide layer as a whole, and etching the middle part of the oxide layer to obtain a second isolation dielectric layer; Depositing an initial N- layer in the groove formed by the second isolation dielectric layer and the first N+ layer, and obtaining a first N- layer after grinding; Doping P-type ions on the side of the first N- layer away from the first N+ layer, and depositing an electrode to connect with the first region doped with P-type ions in the first N- layer.

[0014] Compared with the prior art: By providing a P-type substrate with a groove, a first N+ layer and a first N- layer sequentially disposed on the groove; wherein, first isolation dielectric layers are disposed on both sides of the first N+ layer perpendicular to the epitaxial growth direction, and second isolation dielectric layers are disposed on both sides of the first N- layer perpendicular to the epitaxial growth direction. The side of the first N- layer away from the first N+ layer is doped with P-type ions, and the first region doped with P-type ions in the first N- layer is connected to the electrode. Specifically, since a larger aspect ratio is used to etch the groove, there is no risk of difficulty in digging a deep groove and the isolation dielectric layer not being filled completely, which greatly reduces the process difficulty. At the same time, isolation is achieved in advance using the isolation dielectric layer, and there is no problem of isolation failure caused by diffusion and alignment. In addition, the widths of the TVS PN junction and the low-capacitance PN junction can be flexibly adjusted according to design requirements, and they no longer restrict each other, which can not only increase the surge capacity but also reduce the capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. is a schematic structural diagram of a low-capacitance TVS tube provided by an embodiment of the present invention; Figure 2 FIG. is a flowchart of the implementation of a method for manufacturing a low-capacitance TVS tube provided by an embodiment of the present invention; Figure 3 FIG. is a schematic process flow diagram of a low-capacitance TVS tube provided by Embodiment 1 of the present invention; Figure 4 FIG. is a schematic structural diagram of a low-capacitance TVS tube provided for Comparative Example 1.

[0016] MAIN SYMBOL DESCRIPTION OF COMPONENTS:

[0017] The following specific embodiments will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Several embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0019] It should be noted that when an element is referred to as being "fixedly disposed on" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for the purpose of illustration.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention belongs. The terms used in the description of the present invention herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0021] Reference Figure 1 , Figure 1 FIG. 1 is a schematic structural diagram of a low-capacitance TVS diode provided by an embodiment of the present invention. Specifically, the low-capacitance TVS diode includes a first P-type substrate 1 with a groove formed therein, a first N+ layer 2 and a first N- layer 3 sequentially disposed on the groove. The width of the first N- layer 3 is smaller than that of the first N+ layer 2, and the height of the first N+ layer 2 is consistent with the depth of the groove. The impurity of the first N+ layer 2 is As element, and the doping concentration is 1E13 atom / cm 3 ~9E17 atom / cm 3 , the impurity of the first N- layer 3 is P element or As element, and the doping concentration is 1E12 atom / cm 3 ~9E14 atom / cm 3 ; Wherein, first isolation dielectric layers 4 are disposed on both sides of the first N+ layer 2 perpendicular to the epitaxial growth direction, and second isolation dielectric layers 5 are disposed on both sides of the first N- layer 3 perpendicular to the epitaxial growth direction. The side of the first N- layer 3 away from the first N+ layer 2 is doped with P-type ions. The impurity of the P-type ions doped in the first N- layer 3 is B element, and the concentration is 1E14 atom / cm 3 ~9E16 atom / cm 3 , the first region 6 doped with P-type ions in the N- layer is connected to the first electrode 8. In the embodiment of the present invention, the material of the first electrode 8 is aluminum. It should be noted that both the first isolation dielectric layer 4 and the second isolation dielectric layer 5 are oxide layers.

[0022] In some other embodiments of the present invention, it further includes a third isolation dielectric layer 7 deposited on the second isolation dielectric layer 5 and the first region 6 doped with P-type ions, and the first electrode 8 is led out through a channel formed by the third isolation dielectric layer 7.

[0023] Specifically, the doping concentration of the first P-type substrate 1 is 1E17 atom / cm 3 ~9E19 atom / cm 3 , the depth of the groove is 2μm to 10μm. Exemplarily, the depth of the groove is 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm or 10μm, etc., but not limited thereto.

[0024] Further, the thickness of the first isolation dielectric layer 4 is 1 μm to 3 μm, and the thickness of the second isolation dielectric layer 5 is 10 μm to 20 μm. Exemplarily, the thickness of the second isolation dielectric layer 5 is 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm, 20 μm, etc., but not limited thereto.

[0025] Reference Figure 2 , Figure 2 FIG. is a flowchart of the implementation of a method for manufacturing a low-capacitance TVS tube provided by an embodiment of the present invention. The manufacturing method specifically includes the following steps: S100: Provide a P-type substrate, and etch a groove on the P-type substrate.

[0026] Wherein, the width of the groove is the width of the TVS PN junction, and the doping concentration of the first P-type substrate on which the groove is opened is 1E17 atom / cm 3 ~9E19 atom / cm 3 .

[0027] S200: Deposit an oxide layer in the groove, and etch the middle part of the oxide layer to obtain a first isolation dielectric layer.

[0028] It can be understood that after depositing an oxide layer in the groove, the middle part of the oxide layer is etched until a part of the P-type substrate is exposed, and finally a first isolation dielectric layer is obtained.

[0029] S300: Epitaxially grow an initial N+ layer, and obtain a first N+ layer after grinding.

[0030] Specifically, the impurity of the first N+ layer is As element, and the doping concentration is 1E13 atom / cm 3 ~9E17atom / cm 3 .

[0031] S400: Deposit an oxide layer as a whole, and etch the middle part of the oxide layer to obtain a second isolation dielectric layer.

[0032] It should be noted that an oxide layer is deposited as a whole, and the middle part of the oxide layer is etched until a part of the first N+ layer is exposed, and finally a second isolation dielectric layer is obtained. The thickness of the second isolation dielectric layer is 10 μm to 20 μm.

[0033] S500: Deposit an initial N- layer in the groove formed by the second isolation dielectric layer and the first N+ layer, and obtain a first N- layer after grinding.

[0034] Among them, the impurity in the first N-layer is P element or As element, and the doping concentration is 1E12 atom / cm 3 ~9E14 atom / cm 3 .

[0035] S600: Dope P-type ions on the side of the first N-layer far from the first N+ layer, and deposit an electrode to connect with the first region doped with P-type ions in the first N-layer.

[0036] Specifically, the impurity doped with P-type ions in the N-layer is B element, and the concentration is 1E14 atom / cm 3 ~9E16 atom / cm 3 , and the growth temperature is 700°C to 1100°C.

[0037] Furthermore, continue to deposit an oxide layer on the second isolation dielectric layer and the first region doped with P-type ions, then etch through holes until part of the first region doped with P-type ions is exposed, and deposit aluminum metal at the through holes to form the electrodes of the low-capacitance TVS tube.

[0038] The following further illustrates the present invention with specific embodiments: Embodiment 1 Embodiment 1 of the present invention provides a method for manufacturing a low-capacitance TVS tube and a low-capacitance TVS tube. Please refer to Figure 3 , which is a schematic process flow diagram of a low-capacitance TVS tube provided by Embodiment 1 of the present invention. Specifically, it includes the following steps: (1) Provide a P-type substrate, and etch a groove on the P-type substrate to obtain a first P-type substrate 1 with a groove opened.

[0039] Among them, the doping concentration of the P-type substrate is 1E17 atom / cm 3 ~9E19 atom / cm 3 .

[0040] (2) Deposit an oxide layer in the groove, and etch the middle part of the oxide layer to obtain a first isolation dielectric layer 4.

[0041] It can be understood that after depositing an oxide layer in the groove, the middle part of the oxide layer is etched until part of the P-type substrate is exposed, and finally the first isolation dielectric layer 4 is obtained.

[0042] (3) Epitaxially grow an initial N+ layer, and after grinding, obtain a first N+ layer 2.

[0043] Specifically, the impurity of the first N+ layer 2 is As element, and the doping concentration is 1E13 atom / cm 3 ~9E17 atom / cm 3 .

[0044] (4) Deposit an oxide layer as a whole and etch the oxide layer in the middle part to obtain the second isolation dielectric layer 5.

[0045] It should be noted that an oxide layer is deposited as a whole, and the oxide layer in the middle part is etched until part of the first N+ layer 2 is exposed, and finally the second isolation dielectric layer 5 is obtained. The thickness of the second isolation dielectric layer 5 is 10 μm to 20 μm.

[0046] (5) Deposit an initial N- layer in the groove formed by the second isolation dielectric layer 5 and the first N+ layer 2, and after grinding flat, obtain the first N- layer 3.

[0047] Among them, the impurity of the first N- layer 3 is P element or As element, and the doping concentration is 1E12 atom / cm 3 ~9E14 atom / cm 3 .

[0048] (6) Dope P-type ions on the side of the first N- layer 3 away from the first N+ layer 2, and deposit the first electrode 8 to connect with the first region 6 doped with P-type ions in the first N- layer 3.

[0049] Specifically, the impurity of the first N- layer 3 doped with P-type ions is B element, and the concentration is 1E14 atom / cm 3 ~9E16 atom / cm 3 , and the growth temperature is 700 °C to 1100 °C.

[0050] Further, continue to deposit an oxide layer on the second isolation dielectric layer 5 and the first region 6 doped with P-type ions, and then etch through holes until part of the first region 6 doped with P-type ions is exposed to obtain the third isolation dielectric layer 7. Deposit metal aluminum at the through holes to form the first electrode 8 of the low-capacitance TVS tube.

[0051] Finally, a low-capacitance TVS tube is prepared by the above method.

[0052] Comparative Example 1 Comparative Example 1 provides a method for manufacturing a low-capacitance TVS tube and a low-capacitance TVS tube, including the following steps: (1) Provide a second P-type substrate 11.

[0053] (2) Perform ion implantation doping at a preset position on the second P-type substrate 11. It should be noted that after the second N- layer 21 is deposited, ion doping will diffuse, and finally the N+ region 41 is obtained.

[0054] (3) Deposit a second N-layer 21 on the second P-type substrate 11, and dope P-type ions on the side of the second N-layer 21 away from the second P-type substrate 11 to obtain a second region 31 doped with P-type ions.

[0055] (4) Avoid the N+ region 41 and perform trench etching, and deposit an oxide layer in the trench to serve as the isolation dielectric layer 51.

[0056] (5) Continuously deposit an oxide layer on the isolation dielectric layer 51 and the second region 31 doped with P-type ions, and then perform via etching until the second region 31 doped with P-type ions in the middle part is exposed. Deposit aluminum metal at the via to form the second electrode 61 of the low-capacitance TVS tube.

[0057] Finally, a low-capacitance TVS tube is prepared by the above method. Please refer to Figure 4 , which provides a schematic structural diagram of a low-capacitance TVS tube for Comparative Example 1, including a second P-type substrate 11, a second N-layer 21, and a second region 31 arranged in sequence. Among them, an N+ region 41 is provided at the junction of the second P-type substrate 11 and the second N-layer 21, and grooves etched from the P-type ion region to the second P-type substrate 11 are provided on both sides of the N+ region 41, and the grooves are filled with an oxide layer.

[0058] It should be noted that in the solution of Comparative Example 1, since a low capacitance requires a relatively thick low-doped epitaxial layer, the N+ layer needs to be ion-implanted and doped first, and then the trench is dug deeper for isolation. There are alignment problems and it is easy to cause N+ diffusion problems, which will cause the isolation effect of the deep trench dielectric to fail. If other functional diodes are integrated beside it, it will cause device failure. Moreover, the depth of the deep trench is relatively deep, and the process of digging the trench and filling the dielectric layer is difficult, and the requirements for equipment are extremely high, resulting in an increase in cost. In addition, the low-capacitance PN junction formed by PN- and the TVS PN junction formed by P-subN+ have the same junction area, and the low capacitance and high surge capacity limit each other, and the performance of the device cannot be improved.

[0059] In summary, a low-capacitance TVS diode and its manufacturing method in the embodiments of the present invention are provided. The P-type substrate with a groove is provided, and the first N+ layer and the first N- layer are sequentially arranged on the groove. Among them, the first isolation dielectric layer is arranged on both sides of the first N+ layer perpendicular to the epitaxial growth direction, and the second isolation dielectric layer is arranged on both sides of the first N- layer perpendicular to the epitaxial growth direction. The side of the first N- layer away from the first N+ layer is doped with P-type ions, and the first region doped with P-type ions in the first N- layer is connected to the electrode. Specifically, since a relatively large aspect ratio is used to etch the groove, there is no risk of difficulty in etching deep grooves and incomplete filling of the isolation dielectric layer, which greatly reduces the process difficulty. At the same time, the isolation is done in advance using the isolation dielectric layer, and there is no problem of isolation failure caused by diffusion and alignment. In addition, according to the design requirements, the widths of the TVS PN junction and the low-capacitance PN junction can be flexibly adjusted without mutual restriction, which can not only increase the surge capacity but also reduce the capacitance.

[0060] The above has introduced in detail a low-capacitance TVS diode and its manufacturing method provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. At the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention. It should be noted that the embodiments in this specification are all described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method part. It should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements inherent to the process, method, article or device, but also other identical elements inherent to these process, method, article or device. Without further limitation, the element defined by the statement "including a..." does not exclude the existence of another identical element in the process, method, article or device including the said element. The foregoing description of the disclosed embodiments enables those skilled in the art to practice or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A low-capacitance TVS tube, characterized in that, It includes a first P-type substrate with a groove formed thereon, a first N+ layer and a first N- layer sequentially disposed on the groove; Wherein, first isolation dielectric layers are disposed on both sides of the first N+ layer perpendicular to the epitaxial growth direction, and second isolation dielectric layers are disposed on both sides of the first N- layer perpendicular to the epitaxial growth direction. The side of the first N- layer away from the first N+ layer is doped with P-type ions, and a first region doped with P-type ions in the first N- layer is connected to an electrode.

2. The low-capacitance TVS diode according to claim 1, wherein The doping concentration of the first P-type substrate is 1E17 atom / cm 3 ~9E19 atom / cm 3 .

3. The low-capacitance TVS tube according to claim 1, wherein, The depth of the groove is 2 μm to 10 μm.

4. The low-capacitance TVS diode according to claim 1, characterized in that, The thickness of the first isolation dielectric layer is 1 μm to 3 μm.

5. The low-capacitance TVS diode according to claim 1, wherein The impurity of the first N+ layer is As element, and the doping concentration is 1E13 atom / cm 3 ~9E17 atom / cm 3 .

6. The low-capacitance TVS diode according to claim 1, characterized in that, The thickness of the second isolation dielectric layer is 10 μm to 20 μm.

7. The low-capacitance TVS diode according to claim 1, wherein, The impurity of the first N-layer is P element or As element, and the doping concentration is 1E12 atom / cm 3 ~9E14 atom / cm 3 .

8. The low-capacitance TVS diode according to claim 1, wherein The impurity doped with P-type ions in the first N-layer is element B, and the concentration is 1E14 atom / cm 3 ~9E16 atom / cm 3 .

9. A preparation method of a low-capacitance TVS tube, characterized in that, For manufacturing the low-capacitance TVS tube according to any one of claims 1 to 8, the method includes: Providing a P-type substrate and etching a groove on the P-type substrate; Depositing an oxide layer in the groove and etching the middle part of the oxide layer to obtain the first isolation dielectric layer; Epitaxially growing an initial N+ layer and polishing it to obtain the first N+ layer; Depositing an oxide layer as a whole and etching the middle part of the oxide layer to obtain the second isolation dielectric layer; Depositing an initial N- layer in the groove formed by the second isolation dielectric layer and the first N+ layer and polishing it to obtain the first N- layer; Doping P-type ions on the side of the first N- layer away from the first N+ layer and depositing an electrode to connect to the first region doped with P-type ions in the first N- layer.

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