Super-junction IGBT (Insulated Gate Bipolar Translator) with split gate structure and manufacturing method thereof

Abstract

The invention belongs to the technical field of power semiconductor devices, and relates to a super-junction IGBT (Insulated Gate Bipolar Translator) with a split gate structure and a manufacturing method thereof. The device comprises collector metal, a P-type collector, an N-type field stop layer, a super junction N column, a super junction N column contact, a trench gate structure and a trench emitter structure which are sequentially stacked from bottom to top, a P-type doped region is injected into the bottom of a trench gate, and the trench gate structure and the trench emitter structure are connected with an N-type charge storage layer, a P-type base region and an N + emitter region. The P columns / N columns of the device are alternately arranged in the Y direction, cells are reduced, meanwhile, the P columns and the N columns act on a parasitic PMOS, and the device has high channel density and a wide short-circuit safe working area. In addition, the Miller capacitance of the super-junction IGBT is reduced, the negative gate capacitance effect is suppressed, the surge current is reduced, and the control capability of the device on dv / dt is improved. According to the invention, an extra path is provided for redundant holes stored in the drift region, the turn-off speed of the device is obviously improved, and the switching loss is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor devices, and particularly relates to a superjunction IGBT with a split gate structure and a manufacturing method thereof. Background Art

[0002] The insulated gate bipolar transistor (IGBT) combines the advantages of the field effect transistor (MOSFET) and the bipolar crystalline transistor (BJT), and has developed into one of the core electronic components in modern power electronic circuits. The IGBT has both the advantages of the MOSFET, such as easy driving, low input impedance, and fast switching speed, and the advantages of the BJT, such as large on-state current density, low on-state voltage drop, small loss, and good stability. As the mainstream power switching device in medium and high power power electronic circuits, the insulated gate bipolar transistor (IGBT) is widely used in the power electronic systems of new energy vehicles, new energy power generation, smart grid, high-speed railway, ship drive, motor drive, industrial control, uninterruptible power supply, frequency conversion household appliances, etc., and has a crucial impact on the performance and reliability of the system, and is known as the "CPU" in the industrial field. Since the advent of the IGBT, through continuous technological innovation, the device structure and process technology of the IGBT have achieved great development, significantly improving the performance and reliability of the device. Due to its excellent performance, the IGBT has become a research hotspot and the main development direction of power devices.

[0003] The IGBT uses a drift region with a low doping concentration to achieve high breakdown voltage. However, there is a certain proportional relationship limitation between the breakdown voltage and the on-resistance, that is, the "silicon limit". In order to break the "silicon limit", the superjunction theory was proposed: alternately arranged N and P columns are introduced into the drift region, and the lateral depletion of the N and P columns is used to improve the electric field distribution, thereby obtaining a higher breakdown voltage. Superjunction devices are widely used in Schottky diodes, MOSFETs, and IGBTs due to their high breakdown voltage and low on-resistance performance. Compared with traditional silicon-based IGBT devices, the superjunction IGBT has a higher breakdown voltage under the same drift region length. When the device is turned off, the depletion of the PN junction between the N and P columns will accelerate the extraction of carriers, thereby reducing the turn-off loss. For the superjunction IGBT structure, since the P column region is directly connected to the P-type base region, when the device is conducting forward, the P column region provides a hole extraction channel, which affects the conductance modulation level in the SJ drift region during forward conduction, making the carrier concentration distribution in the device drift region not optimized, and restricting the improvement of the trade-off relationship between the forward on-state voltage drop and the turn-off loss of the device. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to propose a superjunction IGBT with a split-gate structure and a manufacturing method thereof in view of the problems existing in the prior art, so as to reduce the cell width, reduce the switching loss of the superjunction IGBT device, improve the short-circuit withstand ability of the device, and improve the trade-off between the forward conduction voltage Vceon and the turn-off loss Eoff of the device.

[0005] To solve the above technical problems, the technical solution of the present invention is as follows:

[0006] A superjunction IGBT with a split-gate structure defines the three-dimensional directions of the device in a three-dimensional rectangular coordinate system: the lateral direction of the device is defined as the X-axis direction, the vertical direction of the device is defined as the Z-axis direction, and the longitudinal direction of the device, i.e., the third dimension direction, is the Y-axis direction;

[0007] Its cell structure includes: a collector metal 1, a P-type collector region electrode, and an N-type field-stop layer 3 stacked in sequence from bottom to top along the Z-axis direction. Above the N-type field-stop layer 3, there are superjunction N-columns 5 and superjunction P-columns 4 with side surfaces in contact. Above the superjunction N-columns 5 and superjunction P-columns 4 along the X-axis direction, there are a trench-gate structure and a trench-emitter structure;

[0008] The trench-gate structure includes a split-gate dielectric layer 7-1, a split-gate electrode 8 above the split-gate dielectric layer 7-1, a polysilicon-gate structure trench dielectric 7-2 above the split-gate electrode 8, and a polysilicon-gate electrode 9 in the polysilicon-gate structure trench dielectric 7-2;

[0009] The trench-emitter structure includes a split-gate dielectric layer 7-1, a split-gate electrode 15 above the split-gate dielectric layer 7-1, an emitter-structure trench dielectric layer 7-3 above the split-gate electrode 15, and a polysilicon-emitter electrode 13 in the emitter-structure trench dielectric layer 7-3;

[0010] At the bottom of the trench-gate structure and the trench-emitter structure, there is a P-type doped region 6; between the superjunction N-columns 5 and superjunction P-columns 4 and above, between the trench-gate structure and the trench-emitter structure, there is an N-type charge storage layer 14. Along the Z-axis direction, above the N-type charge storage layer 14, there is a P-type base region 12, above the P-type base region 12, there are an N+ emitter region 10 and a P+ contact region 11, and above the N+ emitter region 10 and above the P+ contact region 11, there is an emitter metal 16; the P-type doped region 6 is perpendicular to the superjunction N-columns 5 and superjunction P-columns 4 along the Z-axis direction; the P-type doped region 6 is in contact with the N-type charge storage layer 14 along the Z-axis direction;

[0011] The superjunction N-columns 5 and superjunction P-columns 4 are arranged alternately along the Y-axis direction; the N+ emitter region 10 and the P+ contact region 11 are arranged in sequence along the X-axis direction; the split-gate electrode 8, the polysilicon-emitter electrode 13, the split-gate electrode 15, and the emitter metal 16 are at the same potential;

[0012] The polysilicon gate electrode 9 is connected to the N-type charge storage layer 14, the P-type base region 12, the N+ emitter region 10, and the isolation gate electrode 8 through the polysilicon gate structure trench dielectric layer 7-2; the polysilicon emitter electrode 13 is connected to the N-type charge storage layer 14, the P-type base region 12, and the P+ contact region 11 through the emitter structure trench dielectric layer 7-3; the isolation gate electrode 8 and the split gate electrode 15 are connected to the P-type doped region 6 through the isolation gate dielectric layer 7-1; the split gate electrode 15 is connected to the P-type doped region 6 through the emitter structure trench dielectric layer 7-3; the depth of the polysilicon gate electrode 9 exceeds the depth of the P-type base region 12; the depth of the polysilicon emitter electrode 13 exceeds the depth of the P-type base region 12; the depth of the trench gate structure and the trench emitter structure is greater than the junction depth of the N-type charge storage layer 14 and less than the junction depth of the P-type doped region 6; the thickness of the isolation gate dielectric layer 7-1 is greater than the thicknesses of the polysilicon gate structure trench dielectric layer 7-2 and the emitter structure trench dielectric layer 7-3; the doping concentration of the P-type doped region 6 is greater than or equal to the doping concentration of the superjunction P column 4; the P-type doped region 6 cannot be fully depleted before the device breakdown.

[0013] As a preferred embodiment, an N- drift region 17 is introduced between the superjunction N column 5, the superjunction P column 4, and the N-type field stop layer 3 in the Z direction, and the doping concentration of the N- drift region 17 is lower than the doping concentration of the superjunction N column 5.

[0014] As a preferred embodiment, the polysilicon gate electrode 13 is connected to the split gate electrode 15 through the emitter structure trench dielectric layer 7-3, and the split gate electrode 15 is connected to the N-type charge storage layer 14 and the P-type buried layer 6 at the bottom of the right trench through the dielectric layer 7-1; the split gate electrode 15 is led out from the top of the device.

[0015] As a preferred embodiment, the extension depth of the N+ emitter region 10 at the top layer of the P-type base region 12 is less than the extension depth of the P+ contact region 11 at the top layer of the P-type base region 12; the isolation gate electrode 8 is led out from the top of the device.

[0016] As a preferred embodiment, a trench collector structure penetrating the N-type field stop layer 3 and the P-type collector 2 is introduced on the back of the device. The trench collector structure includes a trench collector 20 and a trench collector dielectric layer 19 on its periphery. The trench collector 20 is at the same potential as the collector metal 1, and the trench collector 20 is isolated from the P-type collector 2, the N-type field stop layer 3, the superjunction P column 4, and the superjunction N column 5 through the trench collector dielectric layer 19.

[0017] As a preferred embodiment, the extension depth of the N+ emitter region 10 at the top layer of the P-type base region 12 is less than the extension depth of the P+ contact region 11 at the top layer of the P-type base region 12; the isolation gate electrode 8 is led out from the top of the device.

[0018] As a preferred embodiment, an N-drift region 17 is introduced between the superjunction N-column 5 and the superjunction P-column 4 and the N-type field-stop layer 3 in the Z direction, and the doping concentration of the N-drift region 17 is lower than that of the superjunction N-column 5.

[0019] The present invention provides a second superjunction IGBT with a split-gate structure. The three-dimensional directions of the device are defined in a three-dimensional rectangular coordinate system: the lateral direction of the device is defined as the X-axis direction, the vertical direction of the device is defined as the Z-axis direction, and the longitudinal direction of the device, i.e., the third-dimensional direction, is defined as the Y-axis direction;

[0020] Its cell structure includes: a collector metal 1, a P-type collector 2, and an N-type field-stop layer 3 stacked in sequence from bottom to top along the Z-axis direction. Above the N-type field-stop layer 3, there are a superjunction N-column 5 and a superjunction P-column 4 in contact with each other on the side. Above the superjunction N-column 5 and the superjunction P-column 4 along the X-axis direction, there are a trench-gate structure and a trench-emitter structure;

[0021] The trench-gate structure includes a split-gate dielectric layer 7-1, a split-gate electrode 8 above the split-gate dielectric layer 7-1, a polysilicon-gate structure trench dielectric 7-2 above the split-gate electrode 8, and a polysilicon-gate electrode 9 in the polysilicon-gate structure trench dielectric 7-2;

[0022] The trench-emitter structure includes a split-gate dielectric layer 7-1 and a polysilicon trench-emitter electrode 18 above the split-gate dielectric layer 7-1;

[0023] A P-type doped region 6 is provided at the bottom of the trench-gate structure and the trench-emitter structure; an N-type charge storage layer 14 is provided above the superjunction N-column 5 and the superjunction P-column 4 and between the trench-gate structure and the trench-emitter structure. Along the Z-axis direction, a P-type base region 12 is provided above the N-type charge storage layer 14, an N+ emitter region 10 and a P+ contact region 11 are provided above the P-type base region 12, and an emitter metal 16 is provided above the N+ emitter region 10 and above the P+ contact region 11; the P-type doped region 6 is perpendicular to the superjunction N-column 5 and the superjunction P-column 4 along the Z-axis direction; the P-type doped region 6 is in contact with the N-type charge storage layer 14 along the Z-axis direction;

[0024] The superjunction N-column 5 and the superjunction P-column 4 are arranged alternately along the Y-axis direction; the N+ emitter region 10 and the P+ contact region 11 are arranged in sequence along the X-axis direction; the polysilicon trench-emitter electrode 18, the split-gate electrode 8, the split-gate electrode 15, and the emitter metal 16 are at the same potential;

[0025] The polysilicon-gate electrode 9 is connected to the N-type charge storage layer 14, the P-type base region 12, the N+ emitter region 10, and the split-gate electrode 8 through the polysilicon-gate structure trench dielectric layer 7-2; the polysilicon trench-emitter electrode 18 is connected to the P+ contact region 11, the P-type base region 12, the N-type charge storage layer 14, and the right-side trench bottom P-type buried layer 6 through the dielectric layer 7-1;

[0026] The depth of the polysilicon gate electrode 9 exceeds the depth of the P-type base region 12; the depths of the trench gate structure and the trench emitter structure are greater than the junction depth of the N-type charge storage layer 14 and less than the junction depth of the P-type doped region 6; the thickness of the isolation gate dielectric layer 7-1 is greater than the thickness of the trench dielectric layer 7-2 of the polysilicon gate structure; the doping concentration of the P-type doped region 6 is greater than or equal to the doping concentration of the superjunction P column 4; the P-type doped region 6 cannot be fully depleted before the device breakdown.

[0027] The present invention also provides a method for manufacturing a superjunction IGBT with a split gate structure, including the following steps:

[0028] Step 1: Use an N-type doped single-crystal silicon wafer as the substrate;

[0029] Step 2: Epitaxially grow N-type doped silicon on the single-crystal silicon wafer, and then etch back the excess silicon on the surface to form an N-type doped drift region;

[0030] Step 3: Deposit a protective layer on the silicon wafer surface, lithographically expose a window for trench silicon etching, and etch out the P column region trench;

[0031] Step 4: Epitaxially grow P-type doped silicon in the P column region trench, fill the P column trench, and then remove the excess P-type silicon through chemical mechanical planarization;

[0032] Step 5: Epitaxially grow N-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form the N-type charge storage layer 14;

[0033] Step 6: Epitaxially grow P-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form the P-type base region 12;

[0034] Step 7: Deposit a protective layer on the silicon wafer surface, lithographically expose a window for trench silicon etching, and simultaneously etch out the gate electrode trench and the emitter trench;

[0035] Step 8: Grow a sacrificial oxide layer on the trench sidewalls in an O2 atmosphere at 1050°C to 1150°C, then remove the sacrificial oxide layer, and then grow a gate oxide layer on the trench sidewalls in an O2 atmosphere at 1050°C to 1150°C;

[0036] Step 9: Deposit polysilicon on the dielectric layer at 750°C to 950°C, and then etch back the excess polysilicon on the surface;

[0037] Step 10: Etch the gate electrode trench and the emitter trench;

[0038] Step 11: Grow a gate oxide layer in the etched gate electrode trench and emitter trench in an O2 atmosphere at 1050°C to 1150°C;

[0039] Step 12: Deposit polysilicon on the dielectric layer in step 8 at 750°C to 950°C, and then etch back the excess polysilicon on the surface;

[0040] Step 13: Grow a pre-oxidation layer on the silicon wafer surface, and obtain a P-type doped region 6 by ion implantation of P-type impurities. The ion implantation energy is 100 - 200 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ;

[0041] Step 14: Grow a pre-oxidation layer on the silicon wafer surface, and obtain an N+ emitter region 10 by ion implantation of N-type impurities. The ion implantation energy is 60 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 , and obtain a P+ contact region 11 by ion implantation of P-type impurities. The ion implantation energy is 50 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ;

[0042] Step 15: Deposit metal on the front side of the device to fabricate an emitter metal 16;

[0043] Step 16: Flip the silicon wafer, and obtain an N-type field stop layer 3 by ion implantation of N-type impurities. The ion implantation energy is 200 - 500 keV; the ion implantation dose is 10 12 ~10 14 / cm 2 , and perform laser annealing; obtain a P+ collector 2 by ion implantation of P-type impurities. The ion implantation energy is 50 - 100 keV, and the ion implantation dose is 10 12 ~10 15 / cm 2 ;

[0044] Step 17: Deposit metal to fabricate a collector metal 1.

[0045] The present invention also provides a manufacturing method for a second superjunction IGBT with a split gate structure, including the following steps:

[0046] Step 1: Use an N-type doped single-crystalline silicon wafer as a substrate;

[0047] Step 2: Epitaxially grow N-type doped silicon on the single-crystalline silicon wafer, and then etch back the excess silicon on the surface to form an N-type doped drift region;

[0048] Step 3: Deposit a protective layer on the silicon wafer surface, lithographically expose a window for trench silicon etching, and etch out a trench in the P pillar region;

[0049] Step 4: Epitaxially grow P-type doped silicon in the trench of the P pillar region, fill the P pillar trench, and then remove the excess P-type silicon by chemical mechanical planarization;

[0050] Step 5: Epitaxially grow N-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form the N-type charge storage layer 14;

[0051] Step 6: Epitaxially grow P-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form the P-type base region 12;

[0052] Step 7: Grow a pre-oxidation layer on the silicon wafer surface, and obtain the P-doped region 6 by ion implantation of P-type impurities. The ion implantation energy is 100 - 200 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ;

[0053] Step 8: Grow a pre-oxidation layer on the silicon wafer surface, obtain the N+ emitter region 10 by ion implantation of N-type impurities. The ion implantation energy is 60 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 , and obtain the P+ contact region 11 by ion implantation of P-type impurities. The ion implantation energy is 50 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ;

[0054] Step 9: Deposit a protective layer on the silicon wafer surface, lithographically expose a window for trench silicon etching, and simultaneously etch out the gate electrode trench and the emitter trench;

[0055] Step 10: Grow a sacrificial oxide layer on the sidewalls of the trenches in an O2 atmosphere at 1050 °C - 1150 °C, then remove the sacrificial oxide layer, and then grow a gate oxide layer on the sidewalls of the trenches in an O2 atmosphere at 1050 °C - 1150 °C;

[0056] Step 11: Deposit polysilicon on the dielectric layer at 750 °C - 950 °C, and then etch back the excess polysilicon on the surface;

[0057] Step 12: Etch the gate electrode trench and the emitter trench;

[0058] Step 13: Grow a gate oxide layer in the etched gate electrode trench and emitter trench in an O2 atmosphere at 1050 °C - 1150 °C;

[0059] Step 14: Deposit polysilicon on the dielectric layer in Step 9 at 750 °C - 950 °C, and then etch back the excess polysilicon on the surface;

[0060] Step 15: Deposit metal on the front side of the device to fabricate the emitter metal 16;

[0061] Step 16: Flip the silicon wafer, ion implant N-type impurities to obtain the N-type field stop layer 3, with the ion implantation energy being 200 - 500 keV; the ion implantation dose is 10 12 ~10 14 / cm 2 , and use laser annealing; ion implant P-type impurities to obtain the P+ collector 2, with the ion implantation energy being 50 - 100 keV, and the ion implantation dose is 10 12 ~10 15 / cm 2 ;

[0062] Step 17: Deposit metal to fabricate the collector metal 1.

[0063] The working principle of the present invention is as follows:

[0064] Different from the traditional superjunction IGBT, the P-columns / N-columns of the newly proposed superjunction IGBT are arranged in the Y direction, which not only optimizes the separation of the surface MOS structure and the superjunction structure in terms of size, but also releases the binding relationship between the widths of the N-columns, P-columns and the device cell width of the traditional superjunction IGBT, enabling the device to have a smaller cell width, increasing the channel density, reducing its forward conduction voltage drop, and obtaining a high-performance device with high channel density and a wide short-circuit safe operating area through the parasitic PMOS formed by the combination of structures such as the P-type base region 12, N-type charge storage layer 14, P-type doped region 6, split gate electrode 15, and polysilicon emitter electrode 13, greatly reducing the switching loss.

[0065] When the polysilicon gate electrode 9 of the device is connected to a high potential higher than the device threshold voltage, the collector metal 1 is connected to a high potential, and the emitter metal 16, isolation gate electrode 8, split gate electrode 15, and polysilicon emitter electrode 13 are connected to a low potential, the device operates in the on state. Only the P-type doped region 6 located at the bottom of the trench enables the superjunction N-column 5 and superjunction P-column 4 to be directly connected to the N-type charge storage layer 14, providing a shorter flow path for the carriers when injecting into the superjunction N-column 5 and superjunction P-column 4, reducing the forward conduction voltage drop of the device. At the same time, the self-biased PMOS structure composed of the P-type base region 12, N-type charge storage layer 14, P-type doped region 6, split gate electrode 15, and polysilicon emitter electrode 13 is in the off state, ensuring that the superjunction P-column 4 in the drift region floats, further increasing the hole concentration in the drift region on the emitter side of the device when the cell width is reduced, enhancing the conductance modulation level in the on state, improving the performance of the device in the forward conduction state, and only the P-type doped region 6 located at the bottom of the trench enables the N-type charge storage layer 14 to be directly connected to the superjunction P-column 4 and superjunction N-column 5, providing a shorter conduction path for the carriers, and further reducing the forward conduction voltage drop of the device.

[0066] When the voltage of the device collector metal 1 is very high, the device enters the saturation state. As the potential of the collector metal 1 increases, the N-type charge storage layer 14 also increases. Due to the non-full depletion caused by the high doping of the P-type doping region 6, the voltages of the P-type doping region 6 and the N-type charge storage layer 14 are clamped, reducing the high saturation current density caused by the reduction of the cell width, fully improving the short-circuit safety problem caused by the reduction of the cell width, and enabling the proposed superjunction IGBT device to have both a high channel density and a wide short-circuit safe operating area at the same time.

[0067] When the polysilicon gate electrode 9, the emitter metal 16, the isolation gate electrode 8, the split gate electrode 15, and the polysilicon emitter electrode 13 of the device are connected to a low potential and the collector metal 1 is connected to a high potential, the device operates in the blocking state. The lateral depletion of the superjunction N pillar 5 and the superjunction P pillar 4 flattens the electric field in three dimensions, improving the breakdown voltage. Moreover, the P-type doping region 6 and the trench emitter structure can effectively shield the influence of the N-type charge storage layer on the breakdown voltage of the device, thereby improving the limitation of the doping concentration of the charge storage layer on the breakdown characteristics of the device. In addition, the thick isolation gate dielectric layer at the bottom of the trench is beneficial to alleviating the electric field concentration effect at the bottom of the trench, further increasing the breakdown voltage.

[0068] When the emitter metal 16, the isolation gate electrode 8, the split gate electrode 15, and the polysilicon emitter electrode 13 of the device are connected to a low potential, the collector metal 1 is connected to a high potential, and the polysilicon gate electrode 9 is switched from a low potential to a high potential, the device switches from the off state to the on state. When the gate voltage is relatively low, the PMOS conducts, and part of the hole current flows through the PMOS, effectively suppressing the increase in the potential below the N-type charge storage layer, thereby suppressing the negative gate capacitance effect, reducing the device surge current, and improving the device's gate control ability for dv / dt.

[0069] When the emitter metal 16, the isolation gate electrode 8, the split gate electrode 15, and the polysilicon emitter electrode 13 of the device are connected to a low potential, the collector metal 1 is connected to a high potential, and the polysilicon gate electrode 9 is switched from a high potential to a low potential, the device switches from the on state to the off state. The lateral PN junction between the superjunction N pillar 5 and the superjunction P pillar 4 will be quickly depleted. At the same time, the turn-on of the PMOS provides a path for the extraction of holes from the superjunction P pillar 4 to the P+ contact region 11, improving the switching speed of the device, reducing the switching loss of the device, and the shorter polysilicon gate 9 reduces the gate area. And the grounded isolation gate electrode 8 below the polysilicon gate 9 converts a part of the gate capacitance C GC into the gate-emitter capacitance C GE ,further reducing the Miller capacitance C GC ,further increasing the switching speed and reducing the switching loss.

[0070] The beneficial effects of the present invention are manifested in:

[0071] Based on the traditional trench superjunction IGBT, the present invention introduces a trench gate structure, an emitter trench gate structure, and a P-type doping region. Different from the traditional superjunction IGBT, the P-columns / N-columns of the newly proposed superjunction IGBT are arranged in the Y direction, which not only optimizes the separation of the surface MOS structure and the superjunction structure in size, but also unbinds the binding relationship between the width of the N-column / P-column and the device cell width of the traditional superjunction IGBT, enabling it to have a smaller cell width, increasing the channel density, reducing its forward conduction voltage drop. Moreover, the self-biased PMOS composed of the P-type base region 12, the N-type charge storage layer 14, the P-type doping region 6, the separated gate electrode 8, and the polysilicon emitter electrode 13 not only further reduces the forward conduction voltage drop of the device, but also when the device is saturated, due to the non-full depletion caused by the high doping of the P-type doping region 6, the voltages of the P-type doping region 6 and the N-type charge storage layer 14 are clamped, reducing the saturation current density of the superjunction IGBT, and can fully improve the short-circuit safety problem caused by the reduction of the cell width, enabling the proposed superjunction IGBT device to have both a high channel density and a wide short-circuit safe operating area. And because the P-type doping region 6 is located at the bottom of the trench, the superjunction N-column 5 and the superjunction P-column 4 are directly connected to the N-type charge storage layer 14, providing a shorter conduction path for the carriers and further reducing the conduction voltage drop of the device. In addition, the presence of the separated gate structure can significantly reduce the Miller capacitance of the superjunction IGBT device. Even when the device cell width is reduced and the channel density is increased, its Miller capacitance is still significantly reduced. Additionally, during the turn-on process of the device, when the collector voltage is relatively low, the PMOS conducts, and part of the hole current flows through the PMOS, effectively suppressing the increase in the potential under the N-type charge storage layer, thereby suppressing the negative gate capacitance effect, reducing the device surge current, and improving the device's gate control ability for dv / dt. When the device is turned off, the novel superjunction IGBT device structure, due to its lower Miller capacitance C GC , improves the turn-off speed of the device. And as VCE increases, the PMOS turns on, and the excess holes stored in the drift region obtain an additional path, further improving the turn-off speed of the device and greatly reducing the switching loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 is a schematic diagram of the cell structure of a traditional superjunction IGBT;

[0073] Figure 2 is a schematic diagram of the cell structure of a superjunction IGBT with a split gate structure provided by Embodiment 1 of the present invention;

[0074] Figure 3 is a schematic diagram of the cell structure of a superjunction IGBT with a split gate structure provided by Embodiment 2 of the present invention;

[0075] Figure 4Schematic diagram of the cell structure of a superjunction IGBT with a split-gate structure provided in Embodiment 3 of the present invention;

[0076] Figure 5 Schematic diagram of the cell structure of a superjunction IGBT with a split-gate structure provided in Embodiment 4 of the present invention;

[0077] Figure 6 Schematic diagram of the cell structure of a superjunction IGBT with a split-gate structure provided in Embodiment 5 of the present invention;

[0078] Figure 7 Schematic diagram of the cell structure of a superjunction IGBT with a split-gate structure provided in Embodiment 5 of the present invention after removing the emitter metal 16;

[0079] Figure 8 Schematic diagram of the cell structure of a superjunction IGBT with a split-gate structure provided in Embodiment 6 of the present invention;

[0080] Figure 9 Schematic diagram of the cell structure of a superjunction IGBT with a split-gate structure provided in Embodiment 6 of the present invention after removing the emitter metal 16;

[0081] Figure 10 Schematic diagram of the cell structure of a superjunction IGBT with a split-gate structure provided in Embodiment 7 of the present invention;

[0082] Figure 11 Schematic diagram of the cell structure of a superjunction IGBT with a split-gate structure provided in Embodiment 8 of the present invention;

[0083] Figure 12 Schematic diagram of the process for forming an N-type substrate of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0084] Figure 13 Schematic diagram of the process for forming an N-type drift region of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0085] Figure 14 Schematic diagram of the process for etching to form trenches in the P-column region of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0086] Figure 15 Schematic diagram of the process for filling to form a superjunction P-column 4 of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0087] Figure 16 Schematic diagram of the process for forming an N-type charge storage layer 14 of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0088] Figure 17 It is a process schematic diagram after forming the P-type base region 12 of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0089] Figure 18 It is a process schematic diagram of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention after etching to form the gate electrode trench

[0090] and the emitter trench;

[0091] Figure 19 It is a process schematic diagram after forming the gate dielectric layer 7-1 of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0092] Figure 20 It is a process schematic diagram after depositing polycrystalline to form the isolation gate electrode 8 and the split-gate electrode 15 of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0093] Figure 21 It is a process schematic diagram of etching the gate electrode trench and the emitter trench of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0094] Figure 22 It is a process schematic diagram after growing the dielectric layer 7-2 and the dielectric layer 7-3 of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0095] Figure 23 It is a process schematic diagram after depositing polycrystalline to form the polysilicon gate electrode 9 and the polysilicon emitter electrode 13 of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0096] Figure 24 It is a process schematic diagram after forming the P-type doped region 6 of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0097] Figure 25 It is a process schematic diagram after forming the N+ emitter region 10 and the P+ contact region 11 of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0098] Figure 26 It is a process schematic diagram after forming the emitter metal 16 of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0099] Figure 27 It is a process schematic diagram after forming the N-type field stop layer 3 and the P-type collector 2 of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0100] Figure 28 It is a process schematic diagram after forming the collector metal 1 of a superjunction IGBT with a split-gate structure provided in Embodiment 1 of the present invention;

[0101] In the drawings, the list of components represented by each reference numeral is as follows:

[0102] 1 is the collector metal, 2 is the P-type collector, 3 is the N-type field stop layer, 4 is the superjunction P pillar, 5 is the superjunction N pillar, 6 is the P-type doping region, 7-1 is the isolation gate dielectric layer, 7-2 is the polysilicon gate structure trench dielectric layer, 7-3 is the emitter structure trench dielectric layer, 8 is the isolation gate electrode, 9 is the polysilicon gate electrode, 10 is the N+ emitter region, 11 is the P+ contact region, 12 is the P-type base region, 13 is the polysilicon emitter electrode, 14 is the N-type charge storage layer, 15 is the split gate electrode, 16 is the emitter metal, 17 is the N-drift region, 18 is the polysilicon trench emitter electrode, 19 is the trench collector dielectric layer, 20 is the trench collector. Detailed implementation manners

[0103] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0104] Embodiment 1

[0105] As Figure 2 shown, this embodiment provides a superjunction IGBT with a split-gate structure. The three-dimensional directions of the device are defined in a three-dimensional rectangular coordinate system: the three-dimensional directions of the device are defined in a three-dimensional rectangular coordinate system: the lateral direction of the device is defined as the X-axis direction, the vertical direction of the device is defined as the Z-axis direction, and the longitudinal direction of the device, that is, the third dimension direction, is defined as the Y-axis direction;

[0106] Its cell structure includes: a collector metal 1, a P-type collector 2, and an N-type field stop layer 3 stacked in sequence from bottom to top along the Z-axis direction. Above the N-type field stop layer 3, there are a superjunction N pillar 5 and a superjunction P pillar 4 in contact with each other on the side. Above the superjunction N pillar 5 and the superjunction P pillar 4 along the X-axis direction, there are a trench gate structure and a trench emitter structure;

[0107] The trench gate structure includes an isolation gate dielectric layer 7-1, an isolation gate electrode 8 above the isolation gate dielectric layer 7-1, a polysilicon gate structure trench dielectric 7-2 above the isolation gate electrode 8, and a polysilicon gate electrode 9 in the polysilicon gate structure trench dielectric 7-2;

[0108] The trench emitter structure includes a split gate dielectric layer 7-1, a split gate electrode 15 above the split gate dielectric layer 7-1, an emitter structure trench dielectric layer 7-3 above the split gate electrode 15, and a polysilicon emitter electrode 13 within the emitter structure trench dielectric layer 7-3;

[0109] A P-type doped region 6 is provided at the bottom of the trench gate structure and the trench emitter structure; above the superjunction N pillar 5 and the superjunction P pillar 4, and between the trench gate structure and the trench emitter structure, an N-type charge storage layer 14 is provided. Along the Z-axis direction, a P-type base region 12 is provided above the N-type charge storage layer 14, an N+ emitter region 10 and a P+ contact region 11 are provided above the P-type base region 12, and an emitter metal 16 is provided above the N+ emitter region 10 and above the P+ contact region 11; the P-type doped region 6 is perpendicular to the superjunction N pillar 5 and the superjunction P pillar 4 along the Z-axis direction; the P-type doped region 6 is in contact with the N-type charge storage layer 14 along the Z-axis direction;

[0110] The superjunction N pillars 5 and the superjunction P pillars 4 are arranged alternately along the Y-axis direction; the N+ emitter regions 10 and the P+ contact regions 11 are arranged in sequence along the X-axis direction; the split gate electrodes 8, the polysilicon emitter electrodes 13, the split gate electrodes 15, and the emitter metal 16 are of equal potential;

[0111] The polysilicon gate electrode 9 is connected to the N-type charge storage layer 14, the P-type base region 12, the N+ emitter region 10, and the split gate electrode 8 through the polysilicon gate structure trench dielectric layer 7-2; the polysilicon emitter electrode 13 is connected to the N-type charge storage layer 14, the P-type base region 12, and the P+ emitter region 11 through the emitter structure trench dielectric layer 7-3; the split gate electrodes 8 and the split gate electrodes 15 are connected to the P-type doped region 6 through the split gate dielectric layer 7-1; the split gate electrode 15 is connected to the P-type doped region 6 through the emitter structure trench dielectric layer 7-3; the depth of the polysilicon gate electrode 9 exceeds the depth of the P-type base region 12; the depth of the polysilicon emitter electrode 13 exceeds the depth of the P-type base region 12; the depth of the trench gate structure and the trench emitter structure is greater than the junction depth of the N-type charge storage layer 14 and less than the junction depth of the P-type doped region 6; the thickness of the split gate dielectric layer 7-1 is greater than the thicknesses of the polysilicon gate structure trench dielectric layer 7-2 and the emitter structure trench dielectric layer 7-3; the doping concentration of the P-type doped region 6 is greater than or equal to the doping concentration of the superjunction P pillar 4. The P-type doped region 6 cannot be completely depleted before the device breaks down. The superjunction IGBT device has a smaller cell width compared to the traditional superjunction IGBT.

[0112] This embodiment also provides a manufacturing method of a superjunction IGBT with a split gate structure, including the following manufacturing steps:

[0113] Step 1: Use an N-type doped single-crystal silicon wafer as the substrate; as Figure 12 shown;

[0114] Step 2: Epitaxially grow N-type doped silicon on the single-crystalline silicon wafer, and then etch back the excess silicon on the surface to form an N-type doped drift region; as Figure 13 shown;

[0115] Step 3: Deposit a protective layer on the silicon wafer surface, lithographically expose a window for trench silicon etching, and etch out the P-pillar region trenches; as Figure 14 shown;

[0116] Step 4: Epitaxially grow P-type doped silicon in the P-pillar region trenches, fill the P-pillar trenches, and then remove the excess P-type silicon by chemical mechanical planarization; as Figure 15 shown;

[0117] Step 5: Epitaxially grow N-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form an N-type charge storage layer 14; as Figure 16 shown;

[0118] Step 6: Epitaxially grow P-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form a P-type base region 12; as Figure 17 shown;

[0119] Step 7: Deposit a protective layer on the silicon wafer surface, lithographically expose a window for trench silicon etching, and simultaneously etch out the gate electrode trenches and emitter trenches; as Figure 18 shown;

[0120] Step 8: Grow a sacrificial oxide layer on the sidewalls of the trenches in an O2 atmosphere at 1050°C to 1150°C, then remove the sacrificial oxide layer, and then grow a gate oxide layer on the sidewalls of the trenches in an O2 atmosphere at 1050°C to 1150°C; as Figure 19 shown;

[0121] Step 9: Deposit polysilicon on the dielectric layer at 750°C to 950°C, and then etch back the excess polysilicon on the surface; as Figure 20 shown;

[0122] Step 10: Etch the gate electrode trenches and emitter trenches; as Figure 21 shown;

[0123] Step 11: Grow a gate oxide layer in the etched gate electrode trenches and emitter trenches in an O2 atmosphere at 1050°C to 1150°C; as Figure 22 shown;

[0124] Step 12: Deposit polysilicon on the dielectric layer in Step 8 at 750°C to 950°C, and then etch back the excess polysilicon on the surface; as Figure 23 shown;

[0125] Step 13: Grow a pre-oxidation layer on the silicon wafer surface. Obtain the P-doped region 6 by ion implantation of P-type impurities. The ion implantation energy is 100 - 200 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ; As Figure 24 shown;

[0126] Step 14: Grow a pre-oxidation layer on the silicon wafer surface. Obtain the N+ emitter region 10 by ion implantation of N-type impurities. The ion implantation energy is 60 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 , and obtain the P+ contact region 11 by ion implantation of P-type impurities. The ion implantation energy is 50 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ; As Figure 25 shown;

[0127] Step 15: Deposit metal on the front side of the device to fabricate the emitter metal 16; As Figure 26 shown;

[0128] Step 16: Flip the silicon wafer, and obtain the N-type field stop layer 3 by ion implantation of N-type impurities. The ion implantation energy is 200 - 500 keV; the ion implantation dose is 10 12 ~10 14 / cm 2 , and perform laser annealing; obtain the P+ collector 2 by ion implantation of P-type impurities. The ion implantation energy is 50 - 100 keV, and the ion implantation dose is 10 12 ~10 15 / cm 2 ; As Figure 27 shown;

[0129] Step 17: Deposit metal to fabricate the collector metal 1. As Figure 28 shown.

[0130] This embodiment also provides a manufacturing method of a second superjunction IGBT with a split gate structure, including the following steps:

[0131] Step 1: Use an N-type doped single-crystalline silicon wafer as the substrate;

[0132] Step 2: Epitaxially grow N-type doped silicon on the single-crystalline silicon wafer, and then etch back the excess silicon on the surface to form the N-type doped drift region;

[0133] Step 3: Deposit a protective layer on the silicon wafer surface, lithographically expose a window for trench silicon etching, and etch out the P-column region trenches;

[0134] Step 4: Epitaxially grow P-type doped silicon in the trench of the P column region, fill the P column trench, and then remove the excess P-type silicon by chemical mechanical planarization;

[0135] Step 5: Epitaxially grow N-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form the N-type charge storage layer 14;

[0136] Step 6: Epitaxially grow P-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form the P-type base region 12;

[0137] Step 7: Grow a pre-oxidation layer on the silicon wafer surface, and obtain the P-doped region 6 by ion implantation of P-type impurities. The ion implantation energy is 100 - 200 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ;

[0138] Step 8: Grow a pre-oxidation layer on the silicon wafer surface, obtain the N+ emitter region 10 by ion implantation of N-type impurities. The ion implantation energy is 60 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 , and obtain the P+ contact region 11 by ion implantation of P-type impurities. The ion implantation energy is 50 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ;

[0139] Step 9: Deposit a protective layer on the silicon wafer surface, lithographically expose a window for trench silicon etching, and simultaneously etch out the gate electrode trench and the emitter trench;

[0140] Step 10: Grow a sacrificial oxide layer on the sidewalls of the trenches in an O2 atmosphere at 1050 °C - 1150 °C, then remove the sacrificial oxide layer, and then grow a gate oxide layer on the sidewalls of the trenches in an O2 atmosphere at 1050 °C - 1150 °C;

[0141] Step 11: Deposit polysilicon on the dielectric layer at 750 °C - 950 °C, and then etch back the excess polysilicon on the surface;

[0142] Step 12: Etch the gate electrode trench and the emitter trench;

[0143] Step 13: Grow a gate oxide layer in the etched gate electrode trench and emitter trench in an O2 atmosphere at 1050 °C - 1150 °C;

[0144] Step 14: Deposit polysilicon on the dielectric layer in Step 9 at 750 °C - 950 °C, and then etch back the excess polysilicon on the surface;

[0145] Step 15: Deposit metal on the front side of the device to fabricate the emitter metal 16;

[0146] Step 16: Flip the silicon wafer, implant N-type impurities to form the N-type field stop layer 3, with an implantation energy of 200 - 500 keV; the implantation dose is 10 12 ~10 14 / cm 2 , and use laser annealing; implant P-type impurities to form the P+ collector 2, with an implantation energy of 50 - 100 keV and an implantation dose of 10 12 ~10 15 / cm 2 ;

[0147] Step 17: Deposit metal to fabricate the collector metal 1.

[0148] Example 2

[0149] A superjunction IGBT with a split-gate structure, as Figure 3 shown. The difference between this example and Example 1 is that: an N-drift region 17 is introduced between the superjunction N-column 5, the superjunction P-column 4 and the N-type field stop layer 3 in the Z direction, and the doping concentration of the N-drift region 17 is lower than that of the superjunction N-column 5.

[0150] The introduction of the N-drift region helps to make up for the limitations in the superjunction process and manufacture a superjunction IGBT with a higher voltage rating.

[0151] Example 3

[0152] As Figure 4 shown, this example provides a superjunction IGBT with a split-gate structure. Define the three-dimensional directions of the device in a three-dimensional rectangular coordinate system: define the lateral direction of the device as the X-axis direction, define the vertical direction of the device as the Z-axis direction, and the longitudinal direction of the device, i.e., the third dimension direction, as the Y-axis direction;

[0153] Its cell structure includes: the collector metal 1, the P-type collector 2, and the N-type field stop layer 3 stacked in sequence from bottom to top along the Z-axis direction. Above the N-type field stop layer 3, there are a superjunction N-column 5 and a superjunction P-column 4 with side surfaces in contact. Along the X-axis direction above the superjunction N-column 5 and the superjunction P-column 4, there are a trench gate structure and a trench emitter structure;

[0154] The trench gate structure includes a split-gate dielectric layer 7-1, a split-gate electrode 8 above the split-gate dielectric layer 7-1, a polysilicon gate structure trench dielectric 7-2 above the split-gate electrode 8, and a polysilicon gate electrode 9 inside the polysilicon gate structure trench dielectric 7-2;

[0155] The trench emitter structure includes a split gate dielectric layer 7-1 and a polysilicon trench emitter electrode 18 above the split gate dielectric layer 7-1;

[0156] A P-type doped region 6 is provided at the bottom of the trench gate structure and the trench emitter structure; an N-type charge storage layer 14 is provided above the superjunction N pillar 5 and the superjunction P pillar 4 and between the trench gate structure and the trench emitter structure. Along the Z-axis direction, a P-type base region 12 is provided above the N-type charge storage layer 14, an N+ emitter region 10 and a P+ contact region 11 are provided above the P-type base region 12, and an emitter metal 16 is provided above the N+ emitter region 10 and above the P+ contact region 11; the P-type doped region 6 is perpendicular to the superjunction N pillar 5 and the superjunction P pillar 4 along the Z-axis direction; the P-type doped region 6 is in contact with the N-type charge storage layer 14 along the Z-axis direction;

[0157] The superjunction N pillars 5 and the superjunction P pillars 4 are arranged alternately along the Y-axis direction; the N+ emitter regions 10 and the P+ contact regions 11 are arranged in sequence along the X-axis direction; the polysilicon trench emitter electrode 18, the split gate electrode 8, and the emitter metal 16 are at the same potential;

[0158] The polysilicon gate electrode 9 is connected to the N-type charge storage layer 14, the P-type base region 12, the N+ emitter region 10, and the split gate electrode 8 through the polysilicon gate structure trench dielectric layer 7-2; the polysilicon trench emitter electrode 18 is connected to the P+ contact region 11, the P-type base region 12, the N-type charge storage layer 14, and the P-type buried layer 6 at the bottom of the right trench through the dielectric layer 7-1;

[0159] The depth of the polysilicon gate electrode 9 exceeds the depth of the P-type base region 12; the depths of the trench gate structure and the trench emitter structure are greater than the junction depth of the N-type charge storage layer 14 and less than the junction depth of the P-type doped region 6; the thickness of the split gate dielectric layer 7-1 is greater than the thickness of the polysilicon gate structure trench dielectric layer 7-2; the doping concentration of the P-type doped region 6 is greater than or equal to the doping concentration of the superjunction P pillar 4; the P-type doped region 6 cannot be completely depleted before the device breaks down.

[0160] By introducing the polysilicon gate electrode 18, it helps with electrode extraction, simplifies the process flow, reduces parasitics, improves device reliability, and increases the yield.

[0161] Example 4

[0162] A superjunction IGBT with a split gate structure, as Figure 5 shown. The difference between this example and Example 1 is:

[0163] The polysilicon gate electrode 13 is connected to the split gate electrode 15 through the emitter structure trench dielectric layer 7-3. The split gate electrode 15 is connected to the N-type charge storage layer 14 and the right trench bottom P-type doped region 6 through the dielectric layer 7-1. The split gate electrode 15 is led out from the top of the device.

[0164] Leading out the split gate electrode 15 from the top of the device helps to simplify the process flow and reduce parasitics. Moreover, the enlarged area of the split gate electrode 15 helps to improve the electric field distribution at the trench bottom and enhance the device reliability.

[0165] Embodiment 5

[0166] A superjunction IGBT with a split gate structure, as Figure 6 shown. The difference between this embodiment and Embodiment 1 lies in:

[0167] As Figure 7 shown, the extension depth of the N+ emitter region 10 at the top layer of the P-type base region 12 is less than that of the P+ contact region 11 at the top layer of the P-type base region 12; the isolation gate electrode 8 is led out from the top of the device.

[0168] In this embodiment, by reducing the extension depth of the emitter region along the top layer of the base region, the channel density of the MOS structure is reduced. As the extension depth of the emitter region along the top layer of the base region decreases, the depth of the gate electrode connected to the emitter region through the gate dielectric layer and extending in the same direction can also be reduced, reducing the saturation current density, improving the safe operating area SCSOA of the device, enhancing the uniformity of the conduction current, improving the reliability of the device, improving its temperature characteristics, facilitating the reduction of the gate capacitance, and thus increasing the switching speed of the device, reducing the switching loss of the device and the requirement for the gate drive circuit ability, and improving the trade-off relationship between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device.

[0169] Embodiment 6

[0170] A superjunction IGBT with a split gate structure, as Figure 8 shown. The difference between this embodiment and Embodiment 4 lies in: the extension depth of the N+ emitter region 10 at the top layer of the P-type base region 12 is less than that of the P+ contact region 11 at the top layer of the P-type base region 12. As Figure 9 shown, the isolation gate electrode 8 is led out from the top of the device.

[0171] In this embodiment, a semi-surrounding split gate is introduced in the right trench, which is symmetrical to the left side, optimizing the overall internal electric field distribution of the device and enhancing the device reliability.

[0172] Embodiment 7

[0173] A superjunction IGBT with a split gate structure, as Figure 10As shown, the difference between this embodiment and Embodiment 4 is that an N-drift region 17 is introduced between the superjunction N pillar 5 and the superjunction P pillar 4 and the N-type field stop layer 3 in the Z direction, and the doping concentration of the N-drift region 17 is lower than that of the superjunction N pillar 5.

[0174] Embodiment 8

[0175] A superjunction IGBT with a split-gate structure, as Figure 11 shown, the difference between this embodiment and Embodiment 1 is that a trench collector structure penetrating the N-type field stop layer 3 and the P-type collector 2 is introduced at the back of the device. The trench collector structure includes a trench collector 20 and a trench collector dielectric layer 19 on its periphery. The trench collector 20 is at the same potential as the collector metal 1, and the trench collector 20 is isolated from the P-type collector 2, the N-type field stop layer 3, the superjunction P pillar 4, and the superjunction N pillar 5 through the trench collector dielectric layer 19.

[0176] This embodiment introduces a trench collector structure with a trench collector electrode 20 through the trench collector dielectric layer 19. A depletion layer will be formed on the surface of the N-type field stop layer 3 in contact with it to withstand part of the reverse voltage. Thus, the reverse breakdown voltage of the device can be greatly improved, the reliability of the device can be improved, and the problem that the reverse breakdown voltage of the device is lower than the forward breakdown voltage due to the existence of the FS layer in the traditional structure and the voltage withstand of the device decreases during AC application is solved.

[0177] The above embodiments merely illustrate the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A super junction IGBT with a split gate structure, characterized in that: The three-dimensional direction of the device is defined in a three-dimensional rectangular coordinate system: the lateral direction of the device is defined as the X-axis direction, the vertical direction of the device is defined as the Z-axis direction, and the longitudinal direction of the device, i.e. the third dimension, is defined as the Y-axis direction; The cell structure comprises: a collector metal (1), a P-type collector (2), and an N-type field stop layer (3) which are stacked in sequence from bottom to top along the Z-axis direction; a super-junction N column (5) and a super-junction P column (4) whose sides are in contact with each other are arranged above the N-type field stop layer (3); and a trench gate structure and a trench emitter structure are arranged above the super-junction N column (5) and the super-junction P column (4) along the X-axis direction; The trench gate structure comprises a separation gate dielectric layer (7-1), a separation gate electrode (8) above the separation gate dielectric layer (7-1), a polysilicon gate structure trench dielectric (7-2) above the separation gate electrode (8), and a polysilicon gate electrode (9) within the polysilicon gate structure trench dielectric (7-2); The trench emitter structure comprises a separation gate dielectric layer (7-1), a split gate electrode (15) above the separation gate dielectric layer (7-1), an emitter structure trench dielectric layer (7-3) above the split gate electrode (15), and a polysilicon emitter electrode (13) in the emitter structure trench dielectric layer (7-3); A P-type doping region (6) is provided at the bottom of the trench gate structure and the trench emitter structure; an N-type charge storage layer (14) is provided above the super junction N column (5) and the super junction P column (4) and between the trench gate structure and the trench emitter structure; along the Z-axis direction, a P-type base region (12) is provided above the N-type charge storage layer (14); an N+ emitter region (10) and a P+ contact region (11) are provided above the P-type base region (12); an emitter metal (16) is provided above the N+ emitter region (10) and above the P+ contact region (11); the P-type doping region (6) is perpendicular to the super junction N column (5) and the super junction P column (4) along the Z-axis direction; and the P-type doping region (6) is in contact with the N-type charge storage layer (14) along the Z-axis direction; The super junction N column (5) and the super junction P column (4) are alternately arranged along the Y axis direction; the N+ emitter region (10) and the P+ contact region (11) are arranged in sequence along the X axis direction; the separated gate electrode (8), the polysilicon emitter electrode (13), the split gate electrode (15) and the emitter metal (16) have the same potential; The polysilicon gate electrode (9) is connected to an N-type charge storage layer (14), a P-type base region (12), an N+ emitter region (10), and a separation gate electrode (8) through a polysilicon gate structure trench dielectric layer (7-2); the polysilicon emitter electrode (13) is connected to an N-type charge storage layer (14), a P-type base region (12), and a P+ contact region (11) through an emitter structure trench dielectric layer (7-3); the separation gate electrode (8) and the split gate electrode (15) are connected to a P-type doping region (6) through a separation gate dielectric layer (7-1); the split gate electrode (15) is connected to a P-type doping region (6) through an emitter structure trench dielectric layer (7-3). The invention relates to a device for manufacturing a superjunction P-type doped region (6) and a superjunction P-column (4). The device comprises a plurality of layers of a plurality of layers of a plurality of layers of a plurality of layers of a plurality of layers of a plurality of layers. The plurality of layers of the plurality of layers of a plurality of layers of a plurality of layers are connected; the depth of the polysilicon gate electrode (9) exceeds the depth of the P-type base region (12); the depth of the polysilicon emitter electrode (13) exceeds the depth of the P-type base region (12); the depth of the trench gate structure and the trench emitter structure is greater than the junction depth of the N-type charge storage layer (14) and less than the junction depth of the P-type doped region (6); the thickness of the separation gate dielectric layer (7-1) is greater than the thickness of the trench dielectric layer (7-2) of the polysilicon gate structure and the trench dielectric layer (7-3) of the emitter structure; the doping concentration of the P-type doped region (6) is greater than or equal to the doping concentration of the superjunction P column (4); and the P-type doped region (6) cannot be completely exhausted before the device breaks down.

2. The super junction IGBT with a split gate structure according to claim 1, characterized in that: An N-drift region (17) is introduced between the super junction N column (5), the super junction P column (4) and the N-type field stop layer (3) in the Z direction, and the doping concentration of the N-drift region (17) is lower than the doping concentration of the super junction N column (5).

3. The super junction IGBT with a split gate structure according to claim 1, characterized in that: The polysilicon emitter electrode (13) is connected to the split gate electrode (15) through the emitter structure trench dielectric layer (7-3); the split gate electrode (15) is connected to the N-type charge storage layer (14) and the P-type buried layer (6) at the bottom of the right trench through the dielectric layer (7-1); the split gate electrode (15) is led out from the top of the device.

4. The super junction IGBT with a split gate structure according to claim 1, characterized in that: The extension depth of the N+ emitter region (10) at the top layer of the P-type base region (12) is less than the extension depth of the P+ contact region (11) at the top layer of the P-type base region (12); and the separation gate electrode (8) is led out from the top of the device.

5. The super junction IGBT with a split gate structure according to claim 1, characterized in that: A trench collector structure penetrating an N-type field stop layer (3) and a P-type collector (2) is introduced at the back of the device. The trench collector structure comprises a trench collector (20) and a trench collector dielectric layer (19) on its peripheral side. The trench collector (20) has the same potential as the collector metal (1). The trench collector (20) is isolated from the P-type collector (2), the N-type field stop layer (3), the super junction P column (4) and the super junction N column (5) by the trench collector dielectric layer (19).

6. The super junction IGBT with a split gate structure according to claim 3, characterized in that: The extension depth of the N+ emitter region (10) at the top layer of the P-type base region (12) is less than the extension depth of the P+ contact region (11) at the top layer of the P-type base region (12); and the separation gate electrode (8) is led out from the top of the device.

7. The super junction IGBT with a split gate structure according to claim 3, characterized in that: An N-drift region (17) is introduced between the super junction N column (5), the super junction P column (4) and the N-type field stop layer (3) in the Z direction, and the doping concentration of the N-drift region (17) is lower than the doping concentration of the super junction N column (5).

8. A super junction IGBT with a split gate structure, characterized in that: The three-dimensional direction of the device is defined in a three-dimensional rectangular coordinate system: the lateral direction of the device is defined as the X-axis direction, the vertical direction of the device is defined as the Z-axis direction, and the longitudinal direction of the device, i.e. the third dimension, is defined as the Y-axis direction; The cell structure comprises: a collector metal (1), a P-type collector (2), and an N-type field stop layer (3) which are stacked in sequence from bottom to top along the Z-axis direction; a super-junction N column (5) and a super-junction P column (4) whose sides are in contact with each other are arranged above the N-type field stop layer (3); and a trench gate structure and a trench emitter structure are arranged above the super-junction N column (5) and the super-junction P column (4) along the X-axis direction; The trench gate structure comprises a separation gate dielectric layer (7-1), a separation gate electrode (8) above the separation gate dielectric layer (7-1), a polysilicon gate structure trench dielectric (7-2) above the separation gate electrode (8), and a polysilicon gate electrode (9) within the polysilicon gate structure trench dielectric (7-2); The trench emitter structure comprises a separation gate dielectric layer (7-1) and a polysilicon trench emitter electrode (18) above the separation gate dielectric layer (7-1); A P-type doping region (6) is provided at the bottom of the trench gate structure and the trench emitter structure; an N-type charge storage layer (14) is provided above the super junction N column (5) and the super junction P column (4) and between the trench gate structure and the trench emitter structure; along the Z-axis direction, a P-type base region (12) is provided above the N-type charge storage layer (14); an N+ emitter region (10) and a P+ contact region (11) are provided above the P-type base region (12); an emitter metal (16) is provided above the N+ emitter region (10) and above the P+ contact region (11); the P-type doping region (6) is perpendicular to the super junction N column (5) and the super junction P column (4) along the Z-axis direction; and the P-type doping region (6) is in contact with the N-type charge storage layer (14) along the Z-axis direction; The super junction N column (5) and the super junction P column (4) are alternately arranged along the Y axis direction; the N+ emitter region (10) and the P+ contact region (11) are arranged in sequence along the X axis direction; the polysilicon trench emitter electrode (18), the separation gate electrode (8), the split gate electrode (15) and the emitter metal (16) have the same potential; The polysilicon gate electrode (9) is connected to an N-type charge storage layer (14), a P-type base region (12), an N+ emitter region (10), and a separation gate electrode (8) through a polysilicon gate structure trench dielectric layer (7-2); the polysilicon trench emitter electrode (18) is connected to a P+ contact region (11), a P-type base region (12), an N-type charge storage layer (14), and a P-type buried layer (6) at the bottom of the right trench through a dielectric layer (7-1); The depth of the polysilicon gate electrode (9) exceeds the depth of the P-type base region (12); the depth of the trench gate structure and the trench emitter structure is greater than the junction depth of the N-type charge storage layer (14) and less than the junction depth of the P-type doping region (6); the thickness of the separation gate dielectric layer (7-1) is greater than the thickness of the polysilicon gate structure trench dielectric layer (7-2); the doping concentration of the P-type doping region (6) is greater than or equal to the doping concentration of the super junction P column (4); and the P-type doping region (6) cannot be completely exhausted before the device breaks down.

9. The method for manufacturing a super junction IGBT with a split gate structure according to claim 1, characterized in that: The following steps are involved: Step 1: Use N-type doped single crystal silicon wafer as substrate; Step 2: epitaxially grow N-type doped silicon on a single crystal silicon wafer, and then reversely etch away excess silicon on the surface to form an N-type doped drift region; Step 3: deposit a protective layer on the surface of the silicon wafer, photolithography a window to perform trench silicon etching, and etch out a P column area trench; Step 4: epitaxially grow P-type doped silicon in the P-column region trench, fill the P-column trench, and then remove excess P-type silicon by chemical mechanical planarization; Step 5: epitaxially growing N-type silicon on the silicon wafer, and then reversely etching away excess silicon on the surface to form an N-type charge storage layer (14); Step 6: epitaxially grow P-type silicon on the silicon wafer, and then reversely etch away excess silicon on the surface to form a P-type base region (12); Step 7: deposit a protective layer on the surface of the silicon wafer, photolithography a window to perform trench silicon etching, and simultaneously etch out the gate electrode trench and the emitter trench; Step 8: growing a sacrificial oxide layer on the sidewall of the trench in an O2 atmosphere at 1050° C. to 1150° C., then removing the sacrificial oxide layer, and then growing a gate oxide layer on the sidewall of the trench in an O2 atmosphere at 1050° C. to 1150° C.; Step 9: depositing polysilicon on the dielectric layer at 750° C. to 950° C., and then reverse etching away excess polysilicon on the surface; Step 10: Etching the gate electrode trench and the emitter trench; Step 11: growing a gate oxide layer in the etched gate electrode trench and emitter trench in an O2 atmosphere at 1050° C. to 1150° C.; Step 12: depositing polysilicon on the dielectric layer in step 8 at 750° C. to 950° C., and then reverse etching away excess polysilicon on the surface; Step 13: Grow a pre-oxidation layer on the surface of the silicon wafer, and make a P buried layer by ion implantation of P-type impurities. The ion implantation energy is 100-200 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ; Step 14: grow a pre-oxidation layer on the surface of the silicon wafer, and produce an N+ emitter region (10) by ion implantation of N-type impurities, with an ion implantation energy of 60 to 100 keV and an ion implantation dose of 10 14 ~10 15 / cm 2 , ion implantation of P-type impurities to obtain a P+ contact region (11), the ion implantation energy is 50-100 keV, the ion implantation dose is 10 14 ~10 15 / cm 2 ; Step 15: Depositing metal on the front side of the device to make emitter metal (16); Step 16: Turn the silicon wafer over and ion-implant N-type impurities to obtain an N-type field stop layer (3). The ion implantation energy is 200-500 keV and the ion implantation dose is 10 12 ~10 14 / cm 2 , laser annealing is adopted; ion implantation of P-type impurities is performed to obtain a P+ collector (2), the ion implantation energy is 50-100 keV, the ion implantation dose is 10 12 ~10 15 / cm 2 ; Step 17: Deposit metal to make collector metal (1).

10. The method for manufacturing a super junction IGBT with a split gate structure according to claim 1, characterized in that: The following steps are involved: Step 1: Using N-type doped single crystal silicon wafer as substrate; Step 2: epitaxially grow N-type doped silicon on a single crystal silicon wafer, and then reversely etch away excess silicon on the surface to form an N-type doped drift region; Step 3: deposit a protective layer on the surface of the silicon wafer, photolithography a window to perform trench silicon etching, and etch out a P column area trench; Step 4: epitaxially grow P-type doped silicon in the P-column region trench, fill the P-column trench, and then remove excess P-type silicon by chemical mechanical planarization; Step 5: epitaxially growing N-type silicon on the silicon wafer, and then reversely etching away excess silicon on the surface to form an N-type charge storage layer (14); Step 6: epitaxially grow P-type silicon on the silicon wafer, and then reversely etch away excess silicon on the surface to form a P-type base region (12); Step 7: Grow a pre-oxidation layer on the surface of the silicon wafer, and make a P buried layer by ion implantation of P-type impurities. The ion implantation energy is 100-200 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ; Step 8: grow a pre-oxidation layer on the surface of the silicon wafer, and produce an N+ emitter region (10) by ion implantation of N-type impurities, with an ion implantation energy of 60-100 keV and an ion implantation dose of 10 14 ~10 15 / cm 2 , ion implantation of P-type impurities to obtain a P+ contact region (11), the ion implantation energy is 50-100 keV, the ion implantation dose is 10 14 ~10 15 / cm 2 ; Step 9: deposit a protective layer on the surface of the silicon wafer, photolithography a window to perform trench silicon etching, and simultaneously etch out the gate electrode trench and the emitter trench; Step 10: growing a sacrificial oxide layer on the sidewall of the trench in an O2 atmosphere at 1050° C. to 1150° C., then removing the sacrificial oxide layer, and then growing a gate oxide layer on the sidewall of the trench in an O2 atmosphere at 1050° C. to 1150° C.; Step 11: depositing polysilicon on the dielectric layer at 750° C. to 950° C., and then reverse etching away excess polysilicon on the surface; Step 12: Etching the gate electrode trench and the emitter trench; Step 13: growing a gate oxide layer in the etched gate electrode trench and emitter trench in an O2 atmosphere at 1050° C. to 1150° C.; Step 14: depositing polysilicon on the dielectric layer in step 9 at 750° C. to 950° C., and then reverse etching away excess polysilicon on the surface; Step 15: Deposit metal on the front side of the device to make emitter metal; Step 16: Turn the silicon wafer over and ion-implant N-type impurities to obtain an N-type field stop layer (3). The ion implantation energy is 200-500 keV and the ion implantation dose is 10 12 ~10 14 / cm 2 , laser annealing is adopted; ion implantation of P-type impurities is performed to obtain a P+ collector (2), the ion implantation energy is 50-100 keV, the ion implantation dose is 10 12 ~10 15 / cm 2 ; Step 17: Deposit metal to make collector metal (1).

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