Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, the semiconductor device comprises a semiconductor structure, a first trench gate structure, a second trench gate structure, a deep trench structure, a column region, a protection region, a source region, a first electrode, a second electrode and a gate, and the semiconductor structure comprises a substrate, an epitaxial layer and a body region which are stacked; the first trench gate structure and the second trench gate structure penetrate through the body region; the deep trench structure is at least embedded in the epitaxial layer at the bottom of the first trench gate structure; the column region wraps the side wall and the bottom surface of the deep groove structure and is communicated with the body region; the protection region is at least located at the bottom of the first trench gate structure; the source region is located on the upper surface layer of the body region between the first and second trench gate structures; the first and second electrodes and the gate are electrically connected to the corresponding regions, respectively. According to the invention, the deep trench structure at least located in the epitaxial layer below the first trench gate structure is arranged, and the column region is formed based on the deep trench, so that the manufacturing difficulty of the column region in the super junction structure is reduced, the on resistance of the device is reduced, and the voltage endurance capability of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a semiconductor device and a preparation method thereof. Background Art

[0002] Due to advantages such as a high critical breakdown electric field, high thermal conductivity, and high electron saturation velocity, the wide-bandgap semiconductor material silicon carbide (SiC) has become an ideal choice for high-voltage, high-temperature, and high-frequency high-power power electronic devices. The trench-gate SiC MOS device is widely used due to its high conductive channel density and low on-resistance. As Figure 1 shown, it is a schematic cross-sectional structure diagram of a trench-gate SiC MOS device, including a SiC substrate 01, a drift region 011, a body region 012, a source region 013, a source contact region 014, a shielding region 015, a gate trench 02, a gate oxide layer 021, a polysilicon gate 022, an interlayer dielectric layer 03, a source electrode 04, and a drain electrode 05. Since the overlapping area between the trench-gate structure and the substrate is large, the gate-drain parasitic capacitance of the device is too large, resulting in an increase in the switching loss of the device. At the same time, the bottom corner of the trench-gate structure usually also has a high electric field, affecting the reliability of the trench-gate device. In order to reduce the electric field at the bottom of the trench-gate structure, a corresponding shielding structure (shielding region) needs to be introduced for protection. However, when introducing the shielding structure, a JFET region is formed in the device, and then a JFET resistance is introduced, resulting in an increase in the on-resistance of the device. In order to reduce the on-resistance of the device, a superjunction structure is introduced into the epitaxial layer of the trench-gate SiC MOS device. As Figure 2 shown, it is a schematic cross-sectional structure diagram of a trench-gate superjunction MOS device, including a SiC substrate 01, a drift region 011, a body region 012, a source region 013, a source contact region 014, a shielding region 015, a column region 016, a gate trench 02, a gate oxide layer 021, a polysilicon gate 022, an interlayer dielectric layer 03, a source electrode 04, and a drain electrode 05. Although this structure reduces the on-resistance of the device to a certain extent, the P-columns in the device require multiple epitaxial growths and multiple high-temperature and high-energy implantations, resulting in a complex process, high implementation cost, and large process fluctuations and high reliability risks due to multiple epitaxial growths and multiple ion implantations, and it is difficult to accurately control the implantation dose each time. In addition, since the trench-gate structure is located between the P-columns (column regions) connected to the body region, it is difficult to reduce the cell size of the trench-gate superjunction MOS device, and then it is difficult to significantly reduce the specific on-resistance of the device.

[0003] Therefore, there is an urgent need to find a semiconductor device that can reduce the on-resistance of the device, reduce the cell size of the device, and simplify the device manufacturing process at the same time. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof, which are used to solve the problems of large on-resistance of trench-gate superjunction MOS devices in the prior art, difficulty in reducing the cell size of the device, and complex device manufacturing process.

[0005] To achieve the above object and other related objects, the present invention provides a semiconductor device, including:

[0006] A semiconductor structure, including a first-conductivity-type substrate, a first-conductivity-type epitaxial layer, and a second-conductivity-type body region stacked;

[0007] A first trench-gate structure and a second trench-gate structure alternately arranged at intervals along the X direction, both penetrating through the body region;

[0008] A deep trench structure, at least embedded in the epitaxial layer at the bottom of the first trench-gate structure, and the cross-sectional dimension of the deep trench structure in the direction perpendicular to the stacking direction of the substrate and the epitaxial layer is smaller than the cross-sectional dimension of the first trench-gate structure;

[0009] A second-conductivity-type column region, wrapping the side walls and the bottom surface of the deep trench structure and communicating with the body region;

[0010] A second-conductivity-type protection region, at least located at the bottom of the first trench-gate structure;

[0011] A first-conductivity-type source region, located on the upper surface layer of the body region between the first trench-gate structure and the second trench-gate structure, and the first trench-gate structure and the second trench-gate structure are respectively adjacent to the side walls of the adjacent source regions;

[0012] A first electrode, electrically connected to the source region;

[0013] A second electrode, electrically connected to the bottom of the semiconductor structure;

[0014] A gate electrode, electrically connected to the first trench-gate structure and the second trench-gate structure respectively.

[0015] Optionally, a first-conductivity-type current spreading layer is further provided in the semiconductor structure, the current spreading layer is located on the upper surface layer of the epitaxial layer and the upper surface is adjacent to the lower surface of the body region, and the first trench-gate structure and the second trench-gate structure both penetrate through the current spreading layer.

[0016] Optionally, the deep trench structure includes a deep trench and a dielectric layer, the deep trench is at least located in the epitaxial layer below the first trench-gate structure and the bottom surface is spaced from the upper surface of the substrate by a preset distance, and the dielectric layer at least covers the inner wall and the bottom surface of the deep trench.

[0017] Optionally, the dielectric layer fills the deep trench.

[0018] Optionally, the deep trench structure penetrates the first trench gate structure. The deep trench structure further includes a conductive filling layer of a second conductivity type. The conductive filling layer fills the deep trench. The dielectric layer wraps the sidewalls and the bottom surface of the conductive filling layer. The conductive filling layer is electrically connected to the first electrode.

[0019] Optionally, the thickness of the dielectric layer at the bottom of the deep trench is not less than 2 times the thickness of the dielectric layer covering the inner wall of the deep trench.

[0020] Optionally, the first trench gate structure includes a first gate trench, a first gate dielectric layer, and a first gate conductive layer of a first conductivity type. The first gate trench penetrates the body region. The first gate dielectric layer covers the inner wall of the first gate trench. The first gate conductive layer fills the first gate trench. The second trench gate structure includes a second gate trench, a second gate dielectric layer, and a second gate conductive layer of a first conductivity type. The second gate trench penetrates the body region. The second gate dielectric layer covers the inner wall of the second gate trench. The second gate conductive layer fills the second gate trench.

[0021] Optionally, the protection region is also located at the bottom of the second trench gate structure. The protection region at the bottom of the second trench gate structure wraps the bottom of the second trench gate structure.

[0022] Optionally, a collector region of a second conductivity type is further provided on the lower surface layer of the substrate. The second electrode is electrically connected to the collector region.

[0023] Optionally, the protection region is located at the top of the column region. The column region is communicated with the body region through the protection region at the bottom of the first trench gate structure.

[0024] The present invention further provides a method for manufacturing a semiconductor device, including the following steps:

[0025] Providing a semiconductor structure including a stacked first conductivity type substrate, a first conductivity type epitaxial layer, and a second conductivity type body region, forming deep trenches that penetrate the body region and whose bottom surfaces are spaced apart from the upper surface of the substrate by a preset distance. The deep trenches are arranged at intervals along the X direction;

[0026] Forming a second conductivity type column region in the epitaxial layer to wrap the sidewalls and the bottom surface of the deep trenches;

[0027] Form a first trench gate structure and a second trench gate structure that are alternately arranged in sequence along the X direction, a deep trench structure at least embedded in the epitaxial layer at the bottom of the first trench gate structure, and a second conductivity type protection region. The first trench gate structure and the second trench gate structure penetrate the body region. The cross-sectional dimension of the deep trench structure in the direction perpendicular to the stacking direction of the substrate and the epitaxial layer is smaller than the cross-sectional dimension of the first trench gate structure. The protection region is at least located at the bottom of the first trench gate structure, and the column region communicates with the body region;

[0028] Form a first conductivity type source region on the upper surface layer of the body region located between the first trench gate structure and the second trench gate structure. The first trench gate structure and the second trench gate structure are respectively adjacent to the side walls of the adjacent source regions;

[0029] Form a first electrode electrically connected to the source region, a second electrode electrically connected to the bottom of the semiconductor structure, and a gate electrode electrically connected to the first trench gate structure and the second trench gate structure respectively.

[0030] Optionally, after forming the column region and before forming the first trench gate structure, it further includes forming a dielectric layer covering at least the inner wall and the bottom surface of the deep trench.

[0031] Optionally, the dielectric layer fills the deep trench.

[0032] Optionally, after forming the dielectric layer that fills the deep trench and before forming the first trench gate structure, it further includes the steps of forming a first gate trench penetrating the body region in the top region of the deep trench, forming a first gate dielectric layer covering the inner wall and the bottom surface of the first gate trench, and forming a first gate conductive layer filling the first gate trench. When forming the first gate trench, the semiconductor structure around the top region of the deep trench and the dielectric layer on the top of the deep trench are removed to obtain the deep trench structure with the upper surface flush with the bottom surface of the first gate trench.

[0033] Optionally, after forming the dielectric layer and before forming the first trench gate structure, it further includes the following steps:

[0034] Form a conductive filling layer filling the deep trench, and form a first gate trench penetrating the body region in the top region of the deep trench and a second gate trench penetrating the body region and located between two adjacent first gate trenches. When forming the first gate trench, the semiconductor structure around the top region of the deep trench and the dielectric layer and the conductive filling layer on the top of the deep trench are removed;

[0035] Form the protection region at the bottom of the first gate trench;

[0036] A first gate dielectric layer covering the inner wall and bottom surface of the first gate trench and a second gate dielectric layer covering the inner wall and bottom surface of the second gate trench are formed, and a first gate conductive layer filling the first gate trench and a second gate conductive layer filling the second gate trench are formed. The first gate trench, the first gate dielectric layer, and the first gate conductive layer constitute the first trench gate structure, and the second gate trench, the second gate dielectric layer, and the second gate conductive layer constitute the second trench gate structure;

[0037] The first gate dielectric layer and the first gate conductive layer directly above the conductive filling layer remaining to fill the deep trench are removed to form the top of the deep trench again;

[0038] A dielectric layer covering the inner wall of the top of the deep trench and a conductive filling layer filling the top of the deep trench are formed. The dielectric layer, the conductive filling layer, and the deep trench in the deep trench constitute the deep trench structure.

[0039] Optionally, when forming the protection region at the bottom of the first gate trench, the protection region is also formed at the bottom of the second gate trench.

[0040] Optionally, the first electrode is electrically connected to the conductive filling layer.

[0041] As described above, the semiconductor device and its manufacturing method of the present invention improve the device structure, set a deep trench structure in the epitaxial layer of the device, synchronously form column regions through the deep trenches in the deep trench structure, reduce the manufacturing difficulty of the column regions connected to the body region, ensure the consistency of the column region manufacturing process, make the longitudinal electric field distribution in the epitaxial layer of the device more uniform, reduce the on-resistance of the device, and improve the breakdown voltage of the device. At the same time, since the column region is directly below the first trench gate structure, the cell size of the superjunction device can be reduced; by forming a second trench gate structure between two adjacent first trench gate structures, the density of the conductive channels in the device is increased, further reducing the on-resistance of the device and improving the power density of the device. In addition, by filling a conductive filling layer with a medium and low doping concentration electrically connected to the first electrode in the deep trench, the conductive filling layer is used to assist the column region in consuming the charges in the epitaxial layer, further optimizing the longitudinal electric field distribution in the epitaxial layer, reducing the on-resistance of the device, and improving the breakdown voltage performance of the device, which has high industrial utilization value. Description of the Drawings

[0042] Figure 1 It shows a schematic cross-sectional structure diagram of a trench gate SiC MOS device.

[0043] Figure 2 It shows a schematic cross-sectional structure diagram of a trench gate superstructure MOS device.

[0044] Figure 3 Shown is a schematic cross-sectional structure diagram of a semiconductor device of the present invention.

[0045] Figure 4 Shown is another schematic cross-sectional structure diagram of a semiconductor device of the present invention.

[0046] Figure 5 Shown is a third schematic cross-sectional structure diagram of a semiconductor device of the present invention.

[0047] Figure 6 Shown as Figure 1 the longitudinal electric field change trend diagram of the device in Figure 3 and the device in

[0048] Figure 7 Shown as Figure 2 the longitudinal electric field change trend diagram of the device in Figure 3 and the device in

[0049] Figure 8 Shown is a process flow diagram of a method for manufacturing a semiconductor device of the present invention.

[0050] Figure 9 Shown is a schematic cross-sectional structure diagram of a semiconductor structure of a method for manufacturing a semiconductor device of the present invention.

[0051] Figure 10 Shown is a schematic cross-sectional structure diagram after forming a deep trench in a method for manufacturing a semiconductor device of the present invention.

[0052] Figure 11 Shown is a schematic cross-sectional structure diagram after forming a column region in a method for manufacturing a semiconductor device of the present invention.

[0053] Figure 12 Shown is a schematic cross-sectional structure diagram after filling a conductive filling layer in a deep trench in a method for manufacturing a semiconductor device of the present invention.

[0054] Figure 13 Shown is a schematic cross-sectional structure diagram after forming a first gate trench and a second gate trench in a method for manufacturing a semiconductor device of the present invention.

[0055] Figure 14 Shown is a schematic cross-sectional structure diagram after forming a first gate dielectric layer and a second gate dielectric layer in a method for manufacturing a semiconductor device of the present invention.

[0056] Figure 15 Shown is a schematic cross-sectional structure diagram after forming a first gate conductive layer and a second gate conductive layer in a method for manufacturing a semiconductor device of the present invention.

[0057] Figure 16Schematic cross-sectional structure diagram after forming the top of the deep trench in the manufacturing method of the semiconductor device according to the present invention.

[0058] Figure 17 Schematic cross-sectional structure diagram after forming the deep trench structure in the manufacturing method of the semiconductor device according to the present invention.

[0059] Figure 18 Schematic cross-sectional structure diagram after forming the source region in the manufacturing method of the semiconductor device according to the present invention.

[0060] Description of the reference numerals in the drawings

[0061] 01 SiC substrate

[0062] 011 Drift region

[0063] 012 Body region

[0064] 013 Source region

[0065] 014 Source contact region

[0066] 015 Shielding region

[0067] 016 Column region

[0068] 02 Gate trench

[0069] 021 Gate oxide layer

[0070] 022 Polysilicon gate

[0071] 03 Interlayer dielectric layer

[0072] 04 Source

[0073] 05 Drain

[0074] 1 Semiconductor structure

[0075] 11 Substrate

[0076] 12 Epitaxial layer

[0077] 13 Current spreading layer

[0078] 14 Body region

[0079] 15 Column region

[0080] 16 Protection region

[0081] 17 Source region

[0082] 2 Deep trench structure

[0083] 21 Deep trench

[0084] 22 Dielectric layer

[0085] 23 Conductive filling layer

[0086] 24 First trench gate structure

[0087] 241 First gate trench

[0088] 242 First gate dielectric layer

[0089] 243 First gate conductive layer

[0090] 25 Second trench gate structure

[0091] 251 Second gate trench

[0092] 252 Second gate dielectric layer

[0093] 253 Second gate conductive layer

[0094] 3 Interlayer dielectric layer

[0095] 31 First contact hole

[0096] 4 First electrode

[0097] 5 Second electrode Detailed implementation manners

[0098] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0099] Please refer to Figures 3 to 18 . It should be noted that the drawings provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0100] Embodiment 1

[0101] This embodiment provides a semiconductor device, such as Figure 3 , Figure 4 and Figure 5As shown, they are respectively schematic diagrams of three cross-sectional structures of the semiconductor device, including a semiconductor structure 1, a first trench gate structure 24, a second trench gate structure 25, a deep trench structure 2, a second conductivity type column region 15, a second conductivity type protection region 16, a first conductivity type source region 17, a first electrode 4, a second electrode 5, and a gate electrode. Among them, the semiconductor structure 1 includes a stacked conductivity type substrate 11, a first conductivity type epitaxial layer 12, and a second conductivity type body region 14; the first trench gate structure 24 and the second trench gate structure 25 that are alternately arranged at intervals in the X direction both penetrate the body region 14; the deep trench structure 2 is at least embedded in the epitaxial layer 12 at the bottom of the first trench gate structure 24, and the cross-sectional dimension of the deep trench structure 2 in the direction perpendicular to the stacking direction of the substrate 11 and the epitaxial layer 12 is smaller than the cross-sectional dimension of the first trench gate structure 24; the column region 15 wraps the side wall and the bottom surface of the deep trench structure 2 and communicates with the body region 14; the protection region 16 is at least located at the bottom of the first trench gate structure 24; the source region 17 is located on the upper surface layer of the body region 14 between the first trench gate structure 24 and the second trench gate structure 25, and the first trench gate structure 24 and the second trench gate structure 25 are respectively adjacent to the side walls of the neighboring source regions 17; the first electrode 4 is electrically connected to the source region 17; the second electrode 5 is electrically connected to the bottom of the semiconductor structure 1; the gate electrode is electrically connected to the first trench gate structure 24 and the second trench gate structure 25 respectively.

[0102] Specifically, the first conductivity type includes one of N-type or P-type, the second conductivity type includes one of N-type or P-type, and the conductivity types of the first conductivity type and the second conductivity type are opposite. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0103] It should be noted that the substrate 11 is usually a process platform for forming the epitaxial layer 12 and is a heavily doped region. When the device is a MOS device, the substrate 11 is also used to form an ohmic contact with the drain of the device. When the device is an IGBT device, the substrate 11 serves as a field stop layer at the bottom of the device to cut off the longitudinal electric field in the device. Under the condition of ensuring the device performance, its thickness, size, shape, and doping concentration can be selected according to the actual situation.

[0104] Specifically, the material of the substrate 11 includes silicon, silicon germanium, silicon carbide, or other suitable semiconductor materials. Preferably, a silicon carbide wafer is used as the substrate 11.

[0105] It should be noted that usually the material of the epitaxial layer 12 is the same as that of the substrate 11, which will not be elaborated here.

[0106] Specifically, the epitaxial layer 12 is usually used to provide the breakdown voltage of the device and is a lightly doped region. Under the condition of ensuring the device performance, the thickness, size, shape, and doping concentration of the epitaxial layer 12 can be selected according to the actual situation.

[0107] As an example, a current spreading layer 13 of a first conductivity type is further provided in the semiconductor structure 1. The current spreading layer 13 is located on the upper surface of the epitaxial layer 12 and its upper surface is adjacent to the lower surface of the body region 14.

[0108] Specifically, the doping concentration of the current spreading layer 13 is greater than that of the epitaxial layer 12 to optimize the current flow path, reduce current crowding, lower the parasitic JFET resistance in the device, and enable the device to have a better FOM value.

[0109] Specifically, under the condition of ensuring the device performance, the thickness and doping concentration of the current spreading layer 13 can be selected according to the actual situation.

[0110] Specifically, usually the conductive channel of the device is formed in the body region 14. The doping concentration of the body region 14 is usually lightly doped or normally doped. Under the condition of ensuring the device performance, the thickness and doping concentration of the body region 14 can be selected according to the actual situation.

[0111] As an example, the first trench gate structure 24 includes a first gate trench 241, a first gate dielectric layer 242, and a first gate conductive layer 243 of a first conductivity type. The first gate trench 241 penetrates the body region 14. The first gate dielectric layer 242 covers the inner wall of the first gate trench 241. The first gate conductive layer 243 fills the first gate trench 241. The second trench gate structure 25 includes a second gate trench 251, a second gate dielectric layer 252, and a second gate conductive layer 253 of a first conductivity type. The second gate trench 251 penetrates the body region 14. The second gate dielectric layer 252 covers the inner wall of the second gate trench 251. The second gate conductive layer 253 fills the second gate trench 251.

[0112] Specifically, the first trench gate structure 24 and the second trench gate structure 25 are generally used to control the turn-off and turn-on of the conductive channel in the body region 14. Under the condition of ensuring device performance, the numbers of the first trench gate structure 24 and the second trench gate structure 25 can be selected according to actual situations; the opening size, opening shape, and depth of the first gate trench 241 can be selected according to actual situations; the opening size, opening shape, and depth of the second gate trench 251 can be selected according to actual situations; the thickness of the first gate dielectric layer 242 can be selected according to actual situations; the thickness of the second gate dielectric layer 252 can be selected according to actual situations; the distance between the first gate trench 241 and the second gate trench 251 can be selected according to actual situations. Here, the depth refers to the distance between the bottom surfaces of the first gate trench 241 and the second gate trench 251 and the upper surface of the body region 14, and the X direction refers to any direction parallel to the plane perpendicular to the stacking direction of the substrate 11 and the epitaxial layer 12. In this embodiment, the size of the first gate trench 241 in the X direction is greater than the size of the second gate trench 251 in the X direction, and the second trench gate structure 25 penetrates the body region 14 in the intermediate region between two adjacent first trench gate structures 24.

[0113] As an example, both the first trench gate structure 24 and the second trench gate structure 25 penetrate the current spreading layer 13, that is, the first gate trench 241 and the second gate trench 251 penetrate the body region 14 and also penetrate the current spreading layer 13.

[0114] Specifically, the material of the first gate dielectric layer 242 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the material of the second gate dielectric layer 252 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the material of the first gate conductive layer 243 includes polysilicon or other suitable conductive materials; the material of the second gate conductive layer 253 includes polysilicon or other suitable conductive materials. Preferably, N-type polysilicon is used as the first gate conductive layer 243 and the second gate conductive layer 253 respectively.

[0115] Specifically, the column region 15 is generally used to form a superjunction structure to increase the breakdown voltage capability of the device. It is usually a lightly doped or normally doped region, and the projection pattern of the column region 15 in the stacking direction of the substrate 11 and the epitaxial layer 12 falls within the projection pattern of the first trench gate structure 24 in this direction. Under the condition of ensuring device performance, the doping concentration and thickness of the column region 15 can be selected according to actual situations; the distance between the bottom surface of the column region 15 and the upper surface of the substrate 11 can be selected according to actual situations. Here, the thickness refers to the distance between the sidewalls of the column region 15 far from the deep trench structure 2 and the sidewalls of the deep trench structure 2.

[0116] As an example, the protection region 16 is also located at the bottom of the second trench gate structure 25. The protection region 16 located at the bottom of the second trench gate structure 25 wraps the bottom of the second trench gate structure 25, as Figure 3 shown.

[0117] Specifically, the protection region 16 is generally used to protect the first trench gate structure 24 and the second trench gate structure 25, and share the high electric field in the epitaxial layer 12, so as to reduce the electric field intensity at the bottom of the first trench gate structure 24 and the second trench gate structure 25, and avoid premature breakdown at the bottom corners of the first trench gate structure 24 and the second trench gate structure 25, which may affect the reliability of the device.

[0118] It should be noted that generally the protection region 16 is a heavily doped region. Under the condition of ensuring the device performance, the size, shape and doping concentration of the protection region 16 at the bottom of the first trench gate structure 24 and the second trench gate structure 25 can be selected according to the actual situation.

[0119] As an example, the protection region 16 is located at the top of the column region 15. The column region 15 is connected to the body region 14 through the protection region 16 located at the bottom of the first trench gate structure 24, so as to realize the connection between the column region 15 and the body region 14, and form a superjunction structure in the device. Subsequently, while enhancing the breakdown voltage of the device, the thickness of the epitaxial layer 12 can be relatively reduced, the doping concentration of the epitaxial layer 12 can be increased, and the on-resistance of the device can be reduced.

[0120] Specifically, since the protection region 16 is formed at the bottom of the first trench gate structure 24 and the second trench gate structure 25, a JFET region is formed below the conductive channel of the device, and then a JFET resistance is introduced into the device. By forming a current spreading layer 13 with a relatively high doping concentration between the body region 14 and the epitaxial layer 12, the JFET resistance of the device can be reduced, and the performance of the device can be improved.

[0121] As an example, the deep trench structure 2 includes a deep trench 21 and a dielectric layer 22. The deep trench 21 is at least located in the epitaxial layer 12 below the first trench gate structure 24, and the bottom surface is spaced a preset distance from the upper surface of the substrate 11. The dielectric layer 22 covers at least the inner wall and the bottom surface of the deep trench 21.

[0122] Specifically, under the condition of ensuring the device performance, the distance between the bottom surface of the deep trench 21 and the upper surface of the substrate 11, and the cross-sectional dimensions and cross-sectional shape perpendicular to the stacking direction of the substrate 11 and the epitaxial layer 12 can be selected according to the actual situation.

[0123] As an example, the dielectric layer 22 fills the deep trench 21, that is, the deep trench structure 2 only includes the deep trench 21 embedded in the epitaxial layer 12 and the dielectric layer 22 filling the deep trench 21, as Figure 5 shown.

[0124] Specifically, when the deep trench structure 2 only includes the deep trench 21 and the dielectric layer 22, the device forms a superjunction structure by using the column region 15 that wraps the sidewalls and the bottom surface of the deep trench 21 and is connected to the body region 14 through the protection region 16 at its top, thereby reducing the on-resistance of the device, while improving the breakdown voltage capability of the device and enhancing the power density of the device.

[0125] As an example, the deep trench structure 2 penetrates the first trench gate structure 24. The deep trench structure 2 further includes a conductive filling layer 23 of the second conductivity type. The conductive filling layer 23 fills the deep trench 21, the dielectric layer 22 wraps the sidewalls and the bottom surface of the conductive filling layer 23, and the conductive filling layer 23 is electrically connected to the first electrode 4, as Figure 3 and Figure 4 shown.

[0126] Specifically, a shield gate structure is formed by electrically connecting the conductive filling layer 23 to the first electrode 4. The conductive filling layer 23 of the second conductivity type is used to assist the column region 15 in depleting the epitaxial layer 12 (the drift region of the device), further optimizing the electric field distribution in the vertical direction of the device, reducing the electric field strength in the epitaxial layer 12 and the on-resistance of the device, so that before the device breaks down, the charges in the epitaxial layer 12 have been completely depleted, thereby preventing the first gate dielectric layer 242, the second gate dielectric layer 252, and the dielectric layer 22 from being broken down, improving the breakdown voltage capability of the device, and then ensuring the reliability of the device.

[0127] It should be noted that generally, the doping concentration of the conductive filling layer 23 is a medium-low doping concentration, and its doping concentration is less than 5×10 -17 cm -3 .

[0128] As an example, the thickness of the dielectric layer 22 at the bottom of the deep trench 21 is not less than 2 times the thickness of the dielectric layer 22 covering the inner wall of the deep trench 21.

[0129] Specifically, by making the dielectric layer 22 at the bottom of the deep trench 21 have a relatively thick thickness, the bottom of the deep trench 21 can withstand the impact of a high electric field, ensuring the reliability of the device.

[0130] It should be noted that generally, the thickness of the dielectric layer 22 is greater than the thicknesses of the first gate dielectric layer 242 and the second gate dielectric layer 252, so that the gate-source parasitic capacitance Cgs introduced by the conductive filling layer 23 electrically connected to the first electrode 4 is small, reducing the switching loss of the device, and its specific thickness can be selected according to the actual situation.

[0131] Specifically, the source region 17 is usually a heavily doped region to form an ohmic contact with the first electrode 4. Under the condition of ensuring the device performance, the size, shape, thickness, and doping concentration of the source region 17 can be selected according to the actual situation.

[0132] It should be noted that when the doping concentration of the body region 14 is relatively low and an ohmic contact cannot be formed with the first electrode 4, a heavily doped second-conductivity-type contact region needs to be formed in the body region 14 to form an ohmic contact between the first electrode 4 and the body region 14.

[0133] Specifically, on the premise of ensuring device performance, the thickness, size, shape, and doping concentration of the contact region can be selected according to the actual situation.

[0134] Specifically, an interlayer dielectric layer 3 covering the exposed upper surfaces of the source region 17, the body region 14, the first trench gate structure 24, and the second trench gate structure 25 is also provided in the device.

[0135] Specifically, the material of the interlayer dielectric layer 3 includes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), or other suitable dielectric materials.

[0136] It should be noted that generally, the interlayer dielectric layer 3 is used for electrical insulation between the first electrode 4 and the gate in the front structure of the device. On the premise of ensuring device performance, the thickness of the interlayer dielectric layer 3 can be selected according to the actual situation.

[0137] Specifically, a first contact hole 31 and a second contact hole are also provided in the interlayer dielectric layer 3. The first contact hole 31 penetrates the interlayer dielectric layer 3 and exposes the source region 17 and the body region 14 at the bottom. The bottom surface of the second contact hole directly above the first gate conductive layer 243 exposes the first gate conductive layer 243, and the bottom surface of the second contact hole directly above the second gate conductive layer 253 exposes the second gate conductive layer 253. The first electrode 4 fills the first contact hole 31 to achieve electrical connection with the source region 17 and the body region 14, and the gate fills the second contact hole to achieve electrical connection with the first gate conductive layer 243 and the second gate conductive layer 253.

[0138] It should be noted that when a contact region is provided in the body region 14, the contact region is also exposed at the bottom of the first contact hole 31, or the body region 14 exposed at the bottom of the first contact hole 31 is the contact region. In addition, when a conductive filling layer 23 is provided in the deep trench structure 2, a first contact hole 31 penetrating the interlayer dielectric layer 3 is also provided above the conductive filling layer 23, and the bottom surface of the first contact hole 31 exposes the conductive filling layer 23 to achieve electrical connection between the conductive filling layer 23 and the first electrode 4.

[0139] Specifically, on the premise of ensuring device performance, the opening size and opening shape of the first contact hole 31 can be selected according to the actual situation; the opening size and opening shape of the second contact hole can be selected according to the actual situation; the distance between the first contact hole 31 and the second contact hole can be selected according to the actual situation.

[0140] Specifically, the materials of the first electrode 4 and the gate are usually common electrode materials, which will not be elaborated here.

[0141] As an example, a collector region of the second conductivity type is further provided on the lower surface layer of the substrate 11, and the second electrode 5 is electrically connected to the collector region, that is, the device is an IGBT device.

[0142] It should be noted that when the collector region is not provided on the lower surface layer of the substrate 11, the device is a MOS device, and an ohmic contact is formed between the second electrode 5 and the lower surface of the substrate 11.

[0143] Specifically, when the device is an IGBT device, the doping concentration and thickness of the collector region can be selected according to the actual situation.

[0144] Specifically, as Figure 6 and Figure 7 shown, they are respectively the longitudinal electric field intensity change trend diagrams of the device in Figure 1 and the device in Figure 3 (the electric field intensity from the upper surface of the body region 14 to the bottom surface of the substrate 11, such as the AA cross-section in Figure 1 and the CC cross-section in Figure 3 ), and the longitudinal electric field intensity change trend diagrams of the device in Figure 2 and the device in Figure 3 (the electric field intensity from the upper surface of the body region 14 to the bottom surface of the substrate 11, such as the BB cross-section in Figure 2 and the CC cross-section in Figure 3 ). Among them, the parameters of the same parts of the device in Figure 1 and the device in Figure 3 are the same. Compared with the device in Figure 3 , the device in Figure 1 only adds a deep trench structure 2 with a conductive filling layer 23 and a column region 15 communicating with the body region 14. It can be seen from the figure that by the combined action of the conductive filling layer 23 and the column region 15, Figure 3 the triangular electric field in the drift region of the device in Figure 2 is flattened, the electric field in the drift region is uniformly distributed, the longitudinal electric field of the entire device is trapezoidally distributed, and then the breakdown voltage of the device can be improved and the on-resistance of the device can be reduced; The parameters of the same parts of the device in and Figure 3 are the same. The top of the column region 15 of the device in Figure 3 is provided with a first trench gate structure 24, and at the same time, a deep trench structure 2 penetrating through the first trench gate structure 24 is provided. And Figure 3 the column region 15 of the device in

[0145] Specifically, by alternately arranging the first trench gate structure 24 and the second trench gate structure 25, the distribution of the electric field in the device can be controlled more precisely. At the same time, the channel density in the device can be increased, the on-resistance of the device can be optimized, the switching control ability of the device can be enhanced, the switching speed of the device can be improved, the switching loss of the device can be reduced, and the power density of the device can be increased.

[0146] Specifically, by making the deep trench structure 2 at least directly below the first trench gate structure 24, and at the same time making the column region 15 wrap the side wall and bottom surface of the deep trench structure 2 in the epitaxial layer 12, the cell size of the superjunction device can be reduced, the on-resistance of the device can be further reduced, and the breakdown voltage of the device can be increased.

[0147] Specifically, by using the column region 15 to communicate with the body region 14 to form a superjunction structure in the device, and then expanding the depletion layer in the horizontal direction to form a lateral electric field, the breakdown voltage of the device can be increased, the on-resistance of the device can be reduced, and at the same time, the cell size of the superjunction device can be reduced.

[0148] Specifically, a conductive filling layer 23 with a medium and low doping concentration and electrically connected to the first electrode 4 is arranged in the deep trench structure 2. By using the conductive filling layer 23 to assist the column region 15 in consuming the charges in the epitaxial layer 12, the longitudinal electric field distribution in the epitaxial layer 12 can be further optimized, and then the breakdown voltage of the device and the on-resistance of the device can be further reduced, and the performance of the device can be improved.

[0149] Specifically, by arranging a protection region 16 at the bottom of the first trench gate structure 24 and a current spreading layer 13 with a higher doping concentration below the body region 14, while protecting the bottom of the first trench gate structure 24, the JFET resistance introduced by the protection region 16 can be reduced, and the performance of the device can be improved.

[0150] The semiconductor device of this embodiment forms a superjunction structure by improving the device structure. A deep trench structure 2 is disposed in the epitaxial layer 12 at least embedded under the first trench gate structure 24, and a column region 15 is disposed to wrap the sidewalls and bottom surface of the deep trench structure 2 and communicate with the body region 14, which can reduce the cell size of the superjunction device. The column region 15 is used to optimize the electric field distribution in the epitaxial layer 12 and reduce the on-resistance of the device. A protection region 16 is disposed at the bottom of the first trench gate structure 24 to protect the bottom of the first trench gate structure 24 and improve the reliability of the device. At the same time, a current spreading layer 13 is disposed under the body region 14 to reduce the JFET resistance introduced by the protection region 16 and improve the performance of the device. By disposing a second trench gate structure 25 between two adjacent first trench gate structures 24, the conductive channel density of the device can be increased, the on-resistance of the device can be further reduced, and the power density of the device can be improved. By disposing a conductive filling layer 23 with a medium and low doping concentration and electrically connected to the first electrode 4 in the deep trench structure 2, the column region 15 can be assisted to consume the charges in the epitaxial layer 12, further optimize the longitudinal electric field distribution in the epitaxial layer 12, reduce the on-resistance of the device, and improve the breakdown voltage performance of the device.

[0151] Embodiment 2

[0152] This embodiment also provides a method for manufacturing a semiconductor device. As Figure 8 shown, it is a process flow chart of the method for manufacturing the semiconductor device, including the following steps:

[0153] S1: Provide a semiconductor structure including a first-conductivity-type substrate, a first-conductivity-type epitaxial layer, and a second-conductivity-type body region stacked in sequence, form deep trenches penetrating the body region and having a bottom surface spaced from the upper surface of the substrate by a preset distance, and the deep trenches are arranged at intervals in the X direction;

[0154] S2: Form a second-conductivity-type column region in the epitaxial layer to wrap the sidewalls and bottom surface of the deep trenches;

[0155] S3: Form a first trench gate structure and a second trench gate structure arranged alternately in the X direction, a deep trench structure at least embedded in the epitaxial layer at the bottom of the first trench gate structure, and a second-conductivity-type protection region. The first trench gate structure and the second trench gate structure penetrate the body region. The cross-sectional dimension of the deep trench structure in a cross-section perpendicular to the stacking direction of the substrate and the epitaxial layer is smaller than the cross-sectional dimension of the first trench gate structure. The protection region is at least located at the bottom of the first trench gate structure, and the column region communicates with the body region;

[0156] S4: Form a source region of the first conductivity type on the upper surface layer of the body region between the first trench gate structure and the second trench gate structure, where the first trench gate structure and the second trench gate structure are respectively adjacent to the sidewalls of the adjacent source regions;

[0157] S5: Form a first electrode electrically connected to the source region, a second electrode electrically connected to the bottom of the semiconductor structure, and a gate electrode electrically connected to the first trench gate structure and the second trench gate structure respectively.

[0158] Please refer to Figures 9 to 17 , and perform steps S1, S2, and S3: Provide a semiconductor structure 1 including a first conductivity type substrate 11, a first conductivity type epitaxial layer 12, and a second conductivity type body region 14 stacked in sequence, form deep trenches 21 penetrating the body region 14 and having a bottom surface spaced from the upper surface of the substrate 11 by a preset distance, and the deep trenches 21 are arranged at intervals in the X direction; form a second conductivity type column region 15 in the epitaxial layer 12 to wrap the sidewalls and the bottom surface of the deep trenches 21; form a first trench gate structure 24 and a second trench gate structure 25 arranged alternately in sequence in the X direction, a deep trench structure 2 at least embedded in the epitaxial layer 12 at the bottom of the first trench gate structure 24, and a second conductivity type protection region 16. The first trench gate structure 24 and the second trench gate structure 25 penetrate the body region 14, the cross-sectional dimension of the deep trench structure 2 in the cross-section perpendicular to the stacking direction of the substrate 11 and the epitaxial layer 12 is smaller than the cross-sectional dimension of the first trench gate structure 24, the protection region 16 is at least located at the bottom of the first trench gate structure 24, and the column region 15 communicates with the body region 14.

[0159] Specifically, as Figure 9 shown, it is a schematic cross-sectional structure diagram of the semiconductor structure 1. A first conductivity type current spreading layer 13 is further provided in the semiconductor structure 1. The current spreading layer 13 is located on the upper surface layer of the epitaxial layer 12 below the body region 14 and its upper surface is adjacent to the bottom surface of the body region 14.

[0160] It should be noted that generally, the epitaxial layer 12 in the semiconductor structure 1 is epitaxially formed on the upper surface of the substrate 11. The current spreading layer 13 can be obtained by epitaxy on the upper surface of the epitaxial layer 12, or can be obtained by implanting corresponding ions into the upper surface layer of the epitaxial layer 12 through an ion implantation process. The body region 14 can be obtained by epitaxy on the upper surface of the current spreading layer 13, or can be obtained by implanting corresponding ions into the upper surface layer of the current spreading layer 13 through an ion implantation process. Preferably, corresponding ions are implanted into the upper surface layer of the epitaxial layer 12 through a high-temperature high-energy ion implantation process to form the current spreading layer 13, and annealing is performed after forming the current spreading layer 13. Then, after annealing, corresponding ions are implanted into the upper surface layer of the current spreading layer 13 through an ion implantation process to form the body region 14, and annealing is performed again.

[0161] Specifically, as Figure 10As shown, it is a schematic cross-sectional structure diagram after forming the deep trench 21. The formation of the deep trench 21 includes the following steps: forming a patterned masking layer on the upper surface of the semiconductor structure 1; forming the deep trench 21 based on the patterned masking layer.

[0162] It should be noted that the masking layer is usually a photoresist layer. The method of forming a patterned masking layer on the upper surface of the semiconductor structure 1 is the common photoresist spin coating, drying, and developing processes in the photolithography process, which will not be elaborated here.

[0163] Specifically, the method of forming the deep trench 21 based on the patterned masking layer includes dry etching, wet etching, or other suitable methods.

[0164] Specifically, as Figure 11 As shown, it is a schematic cross-sectional structure diagram after forming the pillar region 15. The method of forming the pillar region 15 includes ion implantation or other suitable methods. In this embodiment, after forming the deep trench 21, ion implantation is performed on the sidewalls and bottom of the deep trench 21 based on the masking layer to form the pillar region 15 that wraps the sidewalls and bottom of the deep trench 21 in the epitaxial layer 12.

[0165] It should be noted that after forming the pillar region 15 and before performing subsequent processes, it also includes the step of removing the masking layer, and the method of removing the masking layer is the common photoresist layer stripping process, which will not be elaborated here.

[0166] As an example, after forming the pillar region 15 and before forming the first trench gate structure 24, it also includes forming a dielectric layer 22 that at least covers the inner wall and bottom surface of the deep trench 21.

[0167] As an example, the dielectric layer 22 fills the deep trench 21, that is, the deep trench structure 2 only includes the deep trench 21 and the dielectric layer 22 that fills the deep trench 21.

[0168] As an example, after forming the dielectric layer 22 that fills the deep trench 21 and before forming the first trench gate structure 24, it also includes the steps of forming a first gate trench 241 that penetrates the body region 14 in the top region of the deep trench 21, forming a first gate dielectric layer 242 that covers the inner wall and bottom surface of the first gate trench, and forming a first conductive type first gate conductive layer 243 that fills the first gate trench 241. When forming the first gate trench 241, the semiconductor structure 1 around the top region of the deep trench 21 and the dielectric layer 22 on the top of the deep trench 21 are removed to obtain the deep trench structure 2 with the upper surface flush with the bottom surface of the first gate trench 241.

[0169] It should be noted that usually when the deep trench structure 2 only includes the deep trench 21 and the dielectric layer 22, the deep trench structure 2 is formed while the first gate trench 241 is formed, and a second gate trench 251 that penetrates the body region 14 between two adjacent first gate trenches 241 is also formed while the first gate trench 241 is formed. A second gate dielectric layer 242 that covers the second gate trench 251 is also formed while the first gate dielectric layer 242 is formed. A second gate conductive layer 253 of the first conductivity type that fills the second gate trench 251 is also formed while the first gate conductive layer 243 is formed. The first gate dielectric layer 242 wraps the sidewalls and the bottom surface of the first gate conductive layer 243, and the second gate dielectric layer 252 wraps the sidewalls and the bottom surface of the second gate conductive layer 253.

[0170] Specifically, the deep trench structure 2 may also include a conductive filling layer 23 of the second conductivity type. When the conductive filling layer 23 is provided in the deep trench structure 2, forming the first trench gate structure 24, the second trench gate structure 25, the protection region 16, and the deep trench structure 2 includes the following steps: After forming the dielectric layer 22 and before forming the first trench gate structure 24, a conductive filling layer 23 that fills the deep trench 21 is formed, and a first gate trench 241 that penetrates the body region 14 is formed in the top region of the deep trench 21, and a second gate trench 251 that is located between two adjacent first gate trenches 241 and penetrates the body region 14 is formed. When the first gate trench 241 is formed, the semiconductor structure 1 around the top region of the deep trench 21 and the dielectric layer 22 and the conductive filling layer 23 on the top of the deep trench 21 are removed; a protection region 16 located at the bottom of the first gate trench 241 is formed; a first gate dielectric layer 242 that covers the inner wall and the bottom surface of the first gate trench 241 and a second gate dielectric layer 252 that covers the inner wall and the bottom surface of the second gate trench 251 are formed, and a first gate conductive layer 243 that fills the first gate trench 241 and a second gate conductive layer 253 that fills the second gate trench 251 are formed. The first gate trench 241, the first gate dielectric layer 242, and the first gate conductive layer 243 constitute the first trench gate structure 24, and the second gate trench 251, the second gate dielectric layer 252, and the second gate conductive layer 253 constitute the second trench gate structure 25; the first gate dielectric layer 242 and the first gate conductive layer 243 directly above the remaining conductive filling layer 23 that fills the deep trench 21 are removed to form the top of the deep trench 21 again; a dielectric layer 22 that covers the inner wall of the top of the deep trench 21 and a conductive filling layer 23 that fills the top of the deep trench 21 are formed. The dielectric layer 22, the conductive filling layer 23, and the deep trench 21 in the deep trench 21 constitute the deep trench structure 2.

[0171] Specifically, the method for forming the dielectric layer 22 includes thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0172] Specifically, such as Figure 12As described above, it is a schematic cross-sectional structure diagram after forming the conductive filling layer 23 in the deep trench 21. The method for forming the conductive filling layer 23 includes chemical vapor deposition, physical vapor deposition or other suitable methods. In this embodiment, the LPCVD process is used to form the conductive filling layer 23 in the deep trench 21.

[0173] It should be noted that when the deep trench structure 2 includes the conductive filling layer 23, after forming the conductive filling layer 23 and before forming the first gate trench 241 and the second gate trench 251, a protective layer is further formed on the upper surface of the semiconductor structure 1 and the upper surface of the conductive filling layer 23, so as to remove the damage on the upper layer of the semiconductor structure 1 and provide good process conditions for the subsequent lithography process.

[0174] Specifically, as Figure 13 shown, it is a schematic cross-sectional structure diagram after forming the first gate trench 241 and the second gate trench 251. The method for forming the first gate trench 241 and the second gate trench 251 includes dry etching, wet etching or other suitable methods. Preferably, reactive ion etching (RIE) is used to simultaneously etch the conductive filling layer 23 and the semiconductor structure 1 to obtain the first gate trench 241 at the top of the deep trench 21 and the second gate trench 251 between two adjacent first gate trenches 241.

[0175] Specifically, the method for forming the protection region 16 includes ion implantation or other suitable methods. It should be noted that under the condition of ensuring the device performance, the ion implantation process can be carried out based on the masking film layer with the masking pattern for forming the protection region 16, or without the masking film layer with the masking pattern, and the doping ions can be directly implanted into the bottom of the first gate trench 241.

[0176] As an example, when forming the protection region 16 at the bottom of the first gate trench 241, the protection region 16 is also formed at the bottom of the second gate trench 251, that is, when the protection region 16 is also formed at the bottom of the second gate trench 251, the protection region 16 at the bottom of the first gate trench 241 and the protection region 16 at the bottom of the second gate trench 251 are formed synchronously.

[0177] Specifically, the column region 15 is connected to the body region 14 through the protection region 16 at the bottom of the first gate trench 241.

[0178] Specifically, as Figure 14 shown, it is a schematic cross-sectional structure diagram after forming the first gate dielectric layer 242 and the second gate dielectric layer 252. Usually, the first gate dielectric layer 242 and the second gate dielectric layer 252 are formed synchronously. The method for forming the first gate dielectric layer 242 and the second gate dielectric layer 252 includes chemical vapor deposition, physical vapor deposition, thermal oxidation or other suitable methods.

[0179] It should be noted that, in order to ensure the performance of the device, during the process of forming the first gate dielectric layer 242 and the second gate dielectric layer 252, it is usually necessary to adjust the process so that the thickness of the first gate dielectric layer 242 covering the bottom of the first gate trench 241 is greater than the thickness of the first gate dielectric layer 242 covering the inner wall of the first gate trench 241, and at the same time, the thickness of the second gate dielectric layer 252 covering the bottom of the second gate trench 251 is greater than the thickness of the second gate dielectric layer 252 covering the inner wall of the second gate trench 251, so as to improve the breakdown voltage capability of the device.

[0180] Specifically, as Figure 15 shown, it is a schematic cross-sectional structure diagram after forming the first gate conductive layer 243 and the second gate conductive layer 253. The first gate conductive layer 243 and the second gate conductive layer 253 are usually formed synchronously. The methods for synchronously forming the first gate conductive layer 243 and the second gate conductive layer 253 include chemical vapor deposition, physical vapor deposition or other suitable methods.

[0181] Specifically, as Figure 16 shown, it is a schematic cross-sectional structure diagram after forming the top of the deep trench 21. The methods for removing the first gate dielectric layer 242 and the first gate conductive layer 243 directly above the conductive filling layer 23 remaining in the deep trench 21 include dry etching, wet etching or other suitable methods. Preferably, the dry etching process is used to remove the first gate dielectric layer 242 and the first gate conductive layer 243 directly above the conductive filling layer 23 remaining in the deep trench 21.

[0182] It should be noted that generally, the size of the top of the deep trench 21 is the same as that of the lower part of the deep trench 21 under the first gate trench 241. Under the condition of ensuring the device performance and facilitating the electrical connection between the conductive filling layer 23 and the subsequent formed first electrode 4, the size of the upper part of the deep trench 21 can also be smaller than the size of the part of the deep trench 21 under the first gate trench 241, or larger than the size of the part of the deep trench 21 under the first gate trench 241. Here, the larger or smaller can be the size in any direction perpendicular to the plane where the substrate 11 and the epitaxial layer 12 are stacked. Preferably, the mask for manufacturing the deep trench 21 before forming the first gate trench 241 and the second gate trench 251 is used to manufacture the top of the deep trench 21 in the first gate conductive layer 243, which can reduce the number of masks and lower the manufacturing cost.

[0183] Specifically, as Figure 17As shown, it is a schematic cross-sectional structure diagram after forming the deep trench structure 2. The method for forming the dielectric layer 22 covering the first gate conductive layer 243 exposed on the inner wall of the top of the deep trench 21 includes chemical vapor deposition, physical vapor deposition, thermal oxidation or other suitable methods; the method for supplementing the conductive filling layer 23 below the top of the deep trench 21 includes chemical vapor deposition, physical vapor deposition or other suitable methods. Preferably, the dielectric layer 22 covering the first gate conductive layer 243 exposed on the inner wall of the top of the deep trench 21 is formed by a thermal oxidation process.

[0184] Please refer to Figure 18 , and perform step S4 and step S5: form a first-conductive-type source region 17 on the upper surface layer of the body region 14 located between the first trench gate structure 24 and the second trench gate structure 25, and the first trench gate structure 24 and the second trench gate structure 25 are respectively adjacent to the side walls of the adjacent source regions 17; form a first electrode 4 electrically connected to the source region 17, a second electrode 5 electrically connected to the bottom of the semiconductor structure 1, and a gate electrode electrically connected to the first trench gate structure 24 and the second trench gate structure 25 respectively.

[0185] Specifically, as Figure 18 shown, it is a schematic cross-sectional structure diagram after forming the source region 17. The method for forming the source region 17 includes ion implantation or other suitable methods.

[0186] It should be noted that generally, between the adjacent first trench gate structure 24 and the second trench gate structure 25, there is a preset distance between the source region 17 adjacent to the side wall of the first trench structure and the source region 17 adjacent to the side wall of the second trench gate structure 25. Under the condition of ensuring device performance, the source region 17 can also be located on the upper surface layer of the body region 14 between the entire adjacent first trench gate structure 24 and the second trench gate structure 25.

[0187] Specifically, after forming the source region 17 and before forming the first electrode 4 and the gate electrode, it further includes the step of forming an interlayer dielectric layer 3 covering the exposed upper surfaces of the first trench gate structure 24, the second trench gate structure 25, the source region 17, and the body region 14.

[0188] Specifically, the method for forming the interlayer dielectric layer 3 includes chemical vapor deposition, physical vapor deposition or other suitable methods. In this embodiment, after forming the source region 17 and before forming the first electrode 4, a silicon oxide layer and a borophosphosilicate glass (BPSG) layer are sequentially deposited as the interlayer dielectric layer 3.

[0189] It should be noted that when the doping concentration of the body region 14 is relatively low and it is difficult to form an ohmic contact with the subsequently fabricated first electrode 4, after forming the first trench gate structure 24, the second trench gate structure 25 and the deep trench structure 2, and before forming the interlayer dielectric layer 3, a second-conductivity-type contact region located in the body region 14 is formed through an ion implantation process. Under the condition of ensuring device performance, the contact region can also be formed before the subsequent fabrication of the first electrode 4.

[0190] Specifically, forming the first electrode 4 and the gate includes the following steps: forming a first contact hole 31 and a second contact hole (not shown) that penetrate the interlayer dielectric layer 3. The bottom surface of the first contact hole 31 exposes the source region 17. The second contact holes are respectively located directly above the first gate conductive layer 243 and the second gate conductive layer 253, and their bottom surfaces respectively expose the first gate conductive layer 243 and the second gate conductive layer 253; forming the first electrode 4 and the gate that respectively fill the first contact hole 31 and the second contact hole to achieve the electrical connection between the first electrode 4 and the source region 17 and the electrical connection between the first gate conductive layer 243 and the second gate conductive layer 253 and the gate respectively.

[0191] As an example, the first electrode 4 is electrically connected to the conductive filling layer 23, that is, when the conductive filling layer 23 is formed in the deep trench structure 2, the first electrode 4 is also electrically connected to the conductive filling layer 23.

[0192] Specifically, when the first electrode 4 is electrically connected to the conductive filling layer 23, a first contact hole 31 that penetrates the interlayer dielectric layer 3 is also formed directly above the conductive filling layer 23, and the bottom of the first contact hole 31 exposes the conductive filling layer 23 to achieve the electrical connection between the first electrode 4 filling the first contact hole 31 and the conductive filling layer 23.

[0193] It should be noted that generally, the thickness of the dielectric layer 22 covering the inner wall of the top of the deep trench 21 that exposes the first gate conductive layer 243 is greater than that of the first gate dielectric layer 242 and the second gate dielectric layer 252, so that the gate-source parasitic capacitance Cgs generated due to the electrical connection between the first electrode 4 and the conductive filling layer 23 is relatively small.

[0194] Specifically, the methods for forming the first contact hole 31 and the second contact hole include dry etching, wet etching, or other suitable methods.

[0195] It should be noted that when a contact region is formed in the body region 14, the bottom of the first contact hole 31 also exposes the contact region, so that an ohmic contact is formed between the first electrode 4 filling the first contact hole 31 and the body region 14.

[0196] Specifically, such as Figure 3As shown, it is a schematic cross-sectional structure diagram after forming the second electrode 5. The methods for forming the first electrode 4 filling the first contact hole 31, the gate filling the second contact hole, and the second electrode 5 are common electrode formation methods, which will not be elaborated here.

[0197] It should be noted that before forming the second electrode 5, a collector region of a second conductivity type with a preset thickness can also be formed on the lower surface layer of the substrate 11, and an ohmic contact is formed between the second electrode 5 and the collector region. That is, the device is an IGBT device. Among them, the heavily doped substrate 11 above the collector region serves as the field stop layer of the device.

[0198] Specifically, the method for forming the collector region includes ion implantation or other suitable methods.

[0199] Specifically, after forming the deep trench 21, a column region 15 is formed based on the deep trench 21, and the column region 15 is connected to the body region 14 and forms a superjunction structure with the epitaxial layer 12, reducing the difficulty and process complexity of fabricating the column region 15 of the superjunction device. At the same time, due to the synchronous formation of the column region 15, the consistency of the fabrication process of the column region 15 is ensured, making the longitudinal electric field distribution in the epitaxial layer 12 of the device more uniform and improving the performance of the device.

[0200] Specifically, by forming a conductive filling layer 23 with a medium-low doping concentration and electrically connected to the first electrode 4 in the deep trench structure 2, the column region 15 can be assisted to deplete the epitaxial layer 12, and then the electric field distribution in the epitaxial layer 12 can be further optimized, reducing the on-resistance of the device and improving the breakdown voltage capability of the device.

[0201] In the preparation method of the semiconductor device of this embodiment, after forming the deep trench 21, a column region 15 is formed based on the deep trench 21, and the column region 15 is connected to the body region 14 and forms a superjunction structure with the epitaxial layer 12, reducing the difficulty and process complexity of fabricating the column region 15 of the superjunction device. At the same time, due to the synchronous formation of the column region 15, the consistency of the fabrication process of the column region 15 is ensured, making the longitudinal electric field distribution in the epitaxial layer 12 of the device more uniform and improving the performance of the device.

[0202] In summary, in the semiconductor device and its manufacturing method of the present invention, by providing a deep trench structure in the epitaxial layer of the device and using the deep trench to form a column region, the manufacturing difficulty of the column region connected to the body region is reduced. At the same time, a column region with a superjunction structure can be formed synchronously, ensuring the consistency of the column region manufacturing process, making the longitudinal electric field distribution in the epitaxial layer of the device more uniform, reducing the on-resistance of the device, improving the breakdown voltage capability of the device, and at the same time realizing the reduction of the cell size of the superjunction device; by forming a second trench gate structure between two adjacent first trench gate structures, the density of the conductive channel in the device is increased, further reducing the on-resistance of the device and improving the power density of the device; by filling the deep trench with a conductive filling layer that is electrically connected to the first electrode and has a medium-low doping concentration, the conductive filling layer is used to assist the column region in consuming the charges in the epitaxial layer, further optimizing the longitudinal electric field distribution in the epitaxial layer, reducing the on-resistance of the device, and improving the breakdown voltage performance of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0203] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor structure comprising a stacked first conductivity type substrate, a first conductivity type epitaxial layer and a second conductivity type body region; The first trench gate structure and the second trench gate structure are alternately arranged in sequence along the X direction and both penetrate the body region; A deep trench structure, embedded at least in the epitaxial layer at the bottom of the first trench gate structure, and the cross-sectional dimension of the deep trench structure in a direction perpendicular to the stacking direction of the substrate and the epitaxial layer is smaller than the cross-sectional dimension of the first trench gate structure; A second conductive type column region wraps around the sidewall and bottom surface of the deep trench structure and is connected to the body region; A second conductive type protection zone is at least located at the bottom of the first trench gate structure; A first conductive type source region is located at an upper surface layer of the body region between the first trench gate structure and the second trench gate structure, wherein the first trench gate structure and the second trench gate structure are respectively adjacent to side walls of the adjacent source region; a first electrode, electrically connected to the source region; a second electrode electrically connected to the bottom of the semiconductor structure; The gate is electrically connected to the first trench gate structure and the second trench gate structure respectively.

2. The semiconductor device according to claim 1, wherein: The semiconductor structure is also provided with a first conductive type current spreading layer, which is located on the upper surface of the epitaxial layer and has an upper surface adjacent to the lower surface of the body region. Both the first trench gate structure and the second trench gate structure penetrate the current spreading layer.

3. The semiconductor device according to claim 1, wherein: The deep trench structure includes a deep trench and a dielectric layer. The deep trench is at least located in the epitaxial layer below the first trench gate structure and the bottom surface is spaced a preset distance from the upper surface of the substrate. The dielectric layer at least covers the inner wall and bottom surface of the deep trench.

4. The semiconductor device according to claim 3, wherein: The dielectric layer fills the deep trench.

5. The semiconductor device according to claim 3, wherein: The deep trench structure penetrates the first trench gate structure, and the deep trench structure also includes a second conductive type conductive filling layer, the conductive filling layer fills the deep trench, the dielectric layer wraps the sidewall and bottom surface of the conductive filling layer, and the conductive filling layer is electrically connected to the first electrode.

6. The semiconductor device according to claim 5, characterized in that: The thickness of the dielectric layer at the bottom of the deep trench is not less than twice the thickness of the dielectric layer covering the inner wall of the deep trench.

7. The semiconductor device according to claim 5, wherein: The first trench gate structure includes a first gate trench, a first gate dielectric layer and a first gate conductive layer of the first conductive type, the first gate trench passes through the body region, the first gate dielectric layer covers the inner wall of the first gate trench, and the first gate conductive layer fills the first gate trench; the second trench gate structure includes a second gate trench, a second gate dielectric layer and a second gate conductive layer of the first conductive type, the second gate trench passes through the body region, the second gate dielectric layer covers the inner wall of the second gate trench, and the second gate conductive layer fills the second gate trench.

8. The semiconductor device according to claim 1, wherein: The protection zone is also located at the bottom of the second trench gate structure, and the protection zone located at the bottom of the second trench gate structure wraps the bottom of the second trench gate structure.

9. The semiconductor device according to claim 1, wherein: The protection zone is located at the top of the column region, and the column region is connected with the body region through the protection zone located at the bottom of the first trench gate structure.

10. The semiconductor device according to claim 1, wherein: A second conductive type collector region is also provided on the lower surface layer of the substrate, and the second electrode is electrically connected to the collector region.

11. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a semiconductor structure including a stacked first conductive type substrate, a first conductive type epitaxial layer and a second conductive type body region, forming a deep trench penetrating the body region and having a bottom surface spaced a preset distance from an upper surface of the substrate, wherein the deep trenches are spaced apart along an X direction; Forming a second conductive type column region in the epitaxial layer to wrap around the sidewalls and bottom surface of the deep trench; Forming a first trench gate structure and a second trench gate structure alternately arranged in sequence along the X direction, a deep trench structure at least embedded in the epitaxial layer at the bottom of the first trench gate structure, and a second conductive type protection zone, wherein the first trench gate structure and the second trench gate structure penetrate the body region, the cross-sectional dimension of the deep trench structure in a direction perpendicular to the stacking direction of the substrate and the epitaxial layer is smaller than the cross-sectional dimension of the first trench gate structure, the protection zone is at least located at the bottom of the first trench gate structure, and the column region is connected to the body region; forming a first conductive type source region located on the upper surface of the body region between the first trench gate structure and the second trench gate structure, wherein the first trench gate structure and the second trench gate structure are respectively adjacent to the sidewalls of the adjacent source region; A first electrode electrically connected to the source region, a second electrode electrically connected to the bottom of the semiconductor structure, and a gate electrically connected to the first trench gate structure and the second trench gate structure are formed.

12. The method for preparing a semiconductor device according to claim 11, characterized in that: After forming the column region and before forming the first trench gate structure, the method further includes forming a dielectric layer that at least covers the inner wall and bottom surface of the deep trench.

13. The method for preparing a semiconductor device according to claim 12, wherein: The dielectric layer fills the deep trench.

14. The method for preparing a semiconductor device according to claim 13, wherein: After forming the dielectric layer filling the deep trench and before forming the first trench gate structure, the method also includes the steps of forming a first gate trench penetrating the body region in the top area of ​​the deep trench, forming a first gate dielectric layer covering the inner wall and bottom of the first gate trench, and forming a first gate conductive layer of the first conductive type filling the first gate trench. While forming the first gate trench, the semiconductor structure around the top area of ​​the deep trench and the dielectric layer at the top of the deep trench are removed to obtain the deep trench structure whose upper surface is flush with the bottom surface of the first gate trench.

15. The method for preparing a semiconductor device according to claim 12, characterized in that: After forming the dielectric layer and before forming the first trench gate structure, the method further includes the following steps: Forming a conductive filling layer filling the deep trench, and forming a first gate trench penetrating the body region and a second gate trench located between two adjacent first gate trenches and penetrating the body region at the top region of the deep trench, while removing the semiconductor structure around the top region of the deep trench and the dielectric layer and the conductive filling layer at the top of the deep trench; forming the protection zone at the bottom of the first gate trench; forming a first gate dielectric layer covering the inner wall and bottom surface of the first gate trench and a second gate dielectric layer covering the inner wall and bottom surface of the second gate trench, and forming a first gate conductive layer filling the first gate trench and a second gate conductive layer filling the second gate trench, wherein the first gate trench, the first gate dielectric layer and the first gate conductive layer constitute the first trench gate structure, and the second gate trench, the second gate dielectric layer and the second gate conductive layer constitute the second trench gate structure; Removing the first gate dielectric layer and the first gate conductive layer directly above the remaining conductive filling layer filling the deep trench, so as to form the top of the deep trench again; The dielectric layer covering the inner wall of the top of the deep trench and the conductive filling layer filling the top of the deep trench are formed, and the dielectric layer, the conductive filling layer and the deep trench in the deep trench constitute the deep trench structure.

16. The method for preparing a semiconductor device according to claim 15, characterized in that: Forming the protection zone at the bottom of the first gate trench also includes forming the protection zone at the bottom of the second gate trench.

17. The method for preparing a semiconductor device according to claim 15, characterized in that: The first electrode is electrically connected to the conductive filling layer.

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