A VDMOS switch element and its manufacturing method

Abstract

The present invention relates to the field of MOS semiconductor technology and discloses a VDMOS switching element and a method for manufacturing the same. The element comprises a metal drain, a metal source, a semiconductor epitaxial layer, and a gate. The semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P+ layer, a P well layer, and an N well layer. A connecting layer is provided between the metal source and the N well layer. The present invention significantly reduces the interface contact resistance by using TiSi₂, CoSi₂, or highly doped polysilicon as the material for the connecting layer between the metal source and the N well layer. These materials have excellent electrical conductivity and low interface barrier properties, enabling efficient ohmic contact and reducing carrier scattering and energy loss at the interface. This design directly suppresses Joule heat accumulation caused by poor contact, thereby effectively reducing leakage current and improving the device's conduction efficiency and thermal stability.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a VDMOS switch element and a manufacturing method thereof. Background Art

[0002] Vertical double-diffused metal oxide semiconductor (VDMOS) switching elements, as core components of power semiconductor devices, are widely used in power management, motor drives, and high-frequency switching. Traditional VDMOS devices typically consist of a metal drain, source, gate, and multi-layer semiconductor epitaxial structure. Their performance is limited by factors such as interface contact resistance, leakage current, and parasitic effects. Conventional uniformly doped structures are prone to forming parasitic bipolar transistor conduction paths, further exacerbating leakage current and latch-up risks. These issues not only limit device conduction efficiency and thermal stability, but also restrict their application in high-frequency, high-integration scenarios. Therefore, there is an urgent need to achieve efficient and reliable design of VDMOS switching elements through material optimization, structural innovation, and process improvements.

[0003] An existing patent discloses a vertical double-diffused metal-oxide-semiconductor field-effect transistor (DDMMOSFET) (publication number CN104112773A), which includes side insulating layers located on the sides of the drift region, extending longitudinally and having varying lateral widths along the extension direction. In this prior art, the metal source and N-well layers are often contacted using ordinary metal or polysilicon, resulting in a high interface barrier and high contact resistance, leading to Joule heat accumulation and increased leakage current. Furthermore, electric field concentration at the gate edge can easily lead to leakage, reducing the device's withstand voltage capability. Summary of the Invention

[0004] In order to solve the existing technical problems, the present invention provides a VDMOS switch element and a manufacturing method thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a VDMOS switching element includes a metal drain, a metal source, a semiconductor epitaxial layer and a gate, wherein the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a P+ layer, a P well layer and an N well layer, and a connecting layer is provided between the metal source and the N well layer; wherein the connecting layer is in ohmic contact with the metal source, and the connecting layer is in contact with the N well layer.

[0006] Furthermore, the material of the connection layer is one of TiSi2, CoSi2 or highly doped polysilicon.

[0007] Furthermore, a high-K dielectric layer is deposited on both the left and right sides of the gate, wherein the bottom cross-sectional height of the high-K dielectric layer is the same as the bottom cross-sectional height of the connection layer.

[0008] Furthermore, the connection layer further includes a doping-increasing layer, and the doping concentration inside the doping-increasing layer increases step by step from the outside to the inside.

[0009] Furthermore, polysilicon layers are deposited on both the left and right sides of the gate.

[0010] Furthermore, an N-doped layer is formed at the inner center of the P-well layer by ion implantation.

[0011] Furthermore, the connection layer includes an N+ layer and a P- layer, wherein the P- layer is located between the N+ layer and the gate.

[0012] A method for manufacturing a VDMOS switch element includes:

[0013] S1. Forming an N drift layer on the surface of the N substrate layer by epitaxial growth;

[0014] S2. Performing P-type impurity ion implantation on the surface of the N-drift layer to form a P+ layer, and forming a P-well layer on the P+ layer by photolithography and ion implantation, and implanting N-type impurities into the center region of the P-well layer to form an N-doped layer;

[0015] S3, performing N-type impurity ion implantation in the peripheral region of the P-well layer to form an N-well layer;

[0016] S4. Depositing a high-K dielectric layer on the semiconductor surface, and forming a symmetrical high-K dielectric layer on both sides of the gate region by photolithography and etching, controlling the bottom height thereof to be aligned with the subsequent connection layer;

[0017] S5, forming a connection layer between the metal source and the N-well layer by chemical vapor deposition;

[0018] S6. Gradual doping is performed on the connection layer to form a doping-increasing layer, and the doping concentration is gradually increased from the outside to the inside by multiple ion implantations;

[0019] S7, forming an N+ layer and a P- layer in the connection layer step by step, ensuring that the P- layer is located between the N+ layer and the gate;

[0020] S8. Prepare a metal source electrode on the surface of the connection layer, achieve ohmic contact through an annealing process, and prepare a metal drain electrode on the back side of the substrate.

[0021] The present invention provides a VDMOS switch element and a manufacturing method thereof. Compared with the prior art, the present method has the following effects:

[0022] 1. The present invention significantly reduces the interface contact resistance by using TiSi2, CoSi2 or highly doped polysilicon as the connecting layer material between the metal source and the N-well layer. These materials have excellent conductivity and low interface barrier characteristics, can achieve efficient ohmic contact, and reduce carrier scattering and energy loss at the interface. This design directly suppresses the accumulation of Joule heat caused by poor contact, thereby effectively reducing leakage current and improving the conduction efficiency and thermal stability of the device.

[0023] 2. This invention optimizes the electric field distribution in the gate region by symmetrically depositing high-K dielectric layers on both sides of the gate and precisely controlling their bottom height to align with the connection layer. The high dielectric constant of the high-K dielectric significantly enhances gate capacitance, reduces the peak electric field intensity at the gate edge, and mitigates the electric field concentration effect. This improvement not only reduces gate leakage current but also improves the device's withstand voltage and reliability, while enabling smaller device sizes and achieving high integration density.

[0024] 3. The present invention introduces a doping-increase layer into the connecting layer, forming a doping concentration gradient that increases from the outside to the inside through multiple ion implantations. This gradient design smoothes the carrier migration path from the metal source to the N-well layer, reducing carrier accumulation and recombination probability at the interface. Furthermore, the concentration gradient balances the conductivity distribution, avoiding the formation of localized high-resistance regions, further suppressing leakage current and improving current conduction uniformity.

[0025] 4. This invention expands the effective control range of the gate by depositing polysilicon layers on both sides of the gate. The polysilicon layer not only enhances the gate's ability to regulate the channel electric field, but also improves the uniformity of the electric field distribution, reducing the risk of leakage at the gate edge. This design reduces leakage current while enhancing the device's switching speed and dynamic response characteristics, making it particularly suitable for high-frequency applications.

[0026] 5. This invention creates a localized reverse doping structure by injecting N-type impurities into the central region of the P-well layer to form an N-doped layer. This structure effectively suppresses the turn-on effect of the parasitic bipolar transistor and blocks leakage current caused by parasitic paths. Furthermore, reverse doping optimizes the carrier distribution in the P-well region, improving the device's breakdown voltage and latch-up resistance, and enhancing overall reliability.

[0027] 6. The present invention forms an N+ layer and a P- layer in stages within the connecting layer, placing the P- layer between the N+ layer and the gate. The depletion region formed by the P- layer effectively blocks the lateral diffusion of leakage current, while the N+ layer provides a low-resistance conduction path. This composite structure suppresses leakage current while ensuring efficient carrier transport between the source and drift regions, achieving a synergistic optimization of low leakage and high conduction performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic structural diagram of Example 1 of the present invention;

[0029] Figure 2 This is a schematic structural diagram of Example 2 of the present invention;

[0030] Figure 3 This is a schematic structural diagram of Example 3 of the present invention;

[0031] Figure 4 This is a schematic structural diagram of Embodiment 4 of the present invention;

[0032] Figure 5 This is a structural diagram of Example 5 of the present invention;

[0033] Figure 6 This is a structural diagram of Example 6 of the present invention.

[0034] In the figure: 1. Metal drain; 2. Metal source; 3. Gate; 4. N substrate layer; 5. N drift layer; 6. P+ layer; 7. P well layer; 8. N well layer; 9. Connection layer; 10. High-K dielectric layer; 11. Polysilicon layer; 12. N doped layer; 91. Doping increase layer; 92. N+ layer; 93. P- layer. DETAILED DESCRIPTION

[0035] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] like Figure 1-6 According to one aspect of the present invention, a method for manufacturing a VDMOS switch element is provided, comprising:

[0037] Step 1: Form an N drift layer 5 on the surface of the N substrate layer 4 by epitaxial growth; Epitaxially grow the N drift layer 5 on the N substrate layer 4, and form a low-defect, highly uniform drift region by precisely controlling the epitaxial process, providing an ideal carrier migration channel for subsequent structures and reducing leakage current caused by lattice defects.

[0038] Step 2: P-type impurity ions are implanted on the surface of the N-drift layer 5 to form a P+ layer 6. A P-well layer 7 is formed on the P+ layer 6 through photolithography and ion implantation. N-type impurities are implanted in the center of the P-well layer 7 to form an N-doped layer 12. P-type impurities are implanted on the surface of the N-drift layer 5 to form the P+ layer 6 and the P-well layer 7. N-type impurities are implanted in the center of the P-well layer to form an N-doped layer 12. This operation weakens the conduction effect of the parasitic bipolar transistor through localized reverse doping (embedding an N-type region in the P-well), thereby suppressing leakage current caused by parasitic paths.

[0039] Step 3: N-type impurity ions are implanted in the peripheral area of ​​the P-well layer 7 to form an N-well layer 8; N-type impurities are implanted in the peripheral area of ​​the P-well layer 7 to form the N-well layer 8, which optimizes the connection between the source and the drift region, reduces the contact resistance, and balances the lateral electric field distribution of the device.

[0040] Step 4: Deposit a high-K dielectric layer 10 on the semiconductor surface. Using photolithography and etching, symmetrical high-K dielectric layers 10 are formed on both sides of the gate region 3, with their bottom heights aligned with the subsequent connection layer 9. Depositing high-K dielectric layers 10 on both sides of the gate 3 and precisely aligning their bottom heights with the connection layer 9 enhances gate capacitance, reduces electric field concentration at the gate edge, and thus reduces gate leakage current. The introduction of high-K dielectrics also improves device integration and reliability.

[0041] Step 5: Form a connection layer 9 between the metal source 2 and the N-well layer 8 by chemical vapor deposition; chemical vapor deposition of the connection layer 9 between the metal source 2 and the N-well layer 8 uses low-resistance materials such as TiSi2 to form an ohmic contact, significantly reducing the interface resistance and avoiding Joule heat and leakage caused by poor contact.

[0042] Step 6: Gradient doping is performed on the connection layer 9 to form a doping-increasing layer 91, and the doping concentration is gradually increased from the outside to the inside through multiple ion injections; Gradient doping is performed on the connection layer 9 to form a doping-increasing layer 91, and the concentration is gradually increased from the outside to the inside through multiple ion injections, which smoothes the carrier migration path, reduces the carrier accumulation and recombination at the interface, and further suppresses the leakage current.

[0043] Step 7: Form an N+ layer 92 and a P- layer 93 in the connection layer 9, ensuring that the P- layer 93 is located between the N+ layer 92 and the gate 3. Form an N+ layer 92 and a P- layer 93 in the connection layer 9, ensuring that the P- layer 93 is located between the N+ layer and the gate 3. The depletion region formed by the P- layer effectively blocks the lateral diffusion of leakage current, while the N+ layer provides a low-resistance conduction path, achieving both low leakage and high conduction performance.

[0044] Step 8: A metal source electrode 2 is formed on the surface of the connection layer 9 and annealed to achieve ohmic contact. A metal drain electrode 1 is then formed on the back of the substrate. This annealing process establishes ohmic contact between the metal source electrode 2 and the connection layer 9, and a metal drain electrode 1 is formed on the back of the substrate to ensure low-resistance connection and thermal stability of the overall structure, ultimately achieving efficient switching characteristics for the device.

[0045] Example 1

[0046] like Figure 1As shown, a VDMOS switch element includes a metal drain 1, a metal source 2, a semiconductor epitaxial layer, and a gate 3. The semiconductor epitaxial layer includes an N substrate layer 4, an N drift layer 5, a P+ layer 6, a P well layer 7, and an N well layer 8. The element is characterized by a connection layer 9 provided between the metal source 2 and the N well layer 8; the connection layer 9 is in ohmic contact with the metal source 2, and the connection layer 9 is in contact with the N well layer 8. The connection layer 9 is made of one of TiSi2, CoSi2, or highly doped polysilicon. The excellent conductivity and low interface barrier properties of TiSi2, CoSi2, or highly doped polysilicon enable efficient ohmic contact between the metal source 2 and the N well layer 8, significantly reducing contact resistance and thus suppressing leakage current.

[0047] Example 2

[0048] like Figure 2 As shown, high-K dielectric layers 10 are deposited on both sides of the gate 3. The bottom cross-sectional height of the high-K dielectric layer 10 is the same as the bottom cross-sectional height of the connection layer 9. The high-K dielectric layers 10 are deposited symmetrically on both sides of the gate 3, and their bottom heights are aligned with the connection layer 9 to optimize the electric field distribution in the gate region. The high dielectric constant of the high-K dielectric enhances gate capacitance, reduces the electric field concentration effect at the gate edge, and effectively reduces gate leakage current.

[0049] Example 3

[0050] like Figure 3 As shown, the connection layer 9 also includes a doping-increase layer 91, within which the doping concentration gradually increases from the outside to the inside. By introducing the doping-increase layer 91 into the connection layer 9, a doping concentration gradient that gradually increases from the outside to the inside is formed through multiple ion implantations. This gradient design smoothes the carrier migration path, reduces carrier accumulation and recombination at the interface, and further suppresses leakage current.

[0051] Example 4

[0052] like Figure 4 As shown, polysilicon layers 11 are deposited on both sides of the gate 3. Depositing polysilicon layers 11 on both sides of the gate 3 expands the effective control area of ​​the gate, improves the uniformity of the electric field distribution, and reduces the risk of leakage at the gate edge.

[0053] Example 5

[0054] like Figure 5 As shown, an N-doped layer 12 is formed at the center of the P-well layer 7 by ion implantation. By implanting N-type impurities into the center of the P-well layer 7 to form the N-doped layer 12, a localized reverse doping structure is constructed. This structure weakens the conduction effect of the parasitic bipolar transistor and avoids leakage current paths caused by parasitic effects.

[0055] Example 6

[0056] like Figure 6 As shown, the connection layer 9 includes an N+ layer 92 and a P- layer 93, wherein the P- layer 93 is located between the N+ layer 92 and the gate 3. The N+ layer 92 and the P- layer 93 are formed step by step in the connection layer 9, and the P- layer 93 is placed between the N+ layer 92 and the gate 3. This design blocks the lateral diffusion path of the leakage current through the depletion region formed by the P- layer, while the N+ layer provides a low-resistance connection, comprehensively optimizing the leakage and conduction performance.

[0057] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A VDMOS switch element, comprising a metal drain (1), a metal source (2), a semiconductor epitaxial layer and a gate (3), wherein the semiconductor epitaxial layer comprises an N substrate layer (4), an N drift layer (5), a P+ layer (6), a P well layer (7) and an N well layer (8), wherein the upper end of the P+ layer (6) contacts the metal source (2), the right end of the P+ layer (6) contacts the left end of the P well layer (7), and the upper end of the P well layer (7) extends to below the gate (3), and the N well layer (8) is located above between the P+ layer (6) and the P well layer (7), characterized in that: A connection layer (9) is provided between the metal source electrode (2) and the N-well layer (8); wherein the connection layer (9) is in ohmic contact with the metal source electrode (2), and the connection layer (9) is in contact with the N-well layer (8); An N-doped layer (12) is formed at the inner center of the P-well layer (7) by ion implantation.

2. The VDMOS switch element according to claim 1, wherein: The material of the connecting layer (9) is one of TiSi2, CoSi2 or highly doped polysilicon.

3. The VDMOS switch element according to claim 1, wherein: A high-K dielectric layer (10) is deposited on both the left and right sides of the gate (3), wherein the bottom cross-sectional height of the high-K dielectric layer (10) is the same as the bottom cross-sectional height of the connection layer (9).

4. The VDMOS switch element according to claim 1, wherein: The connection layer (9) further comprises a doping increasing layer (91), wherein the doping concentration inside the doping increasing layer (91) increases step by step from the outside to the inside.

5. The VDMOS switch element according to claim 1, wherein: Polysilicon layers (11) are deposited on both the left and right sides of the gate (3).

6. The VDMOS switch element according to claim 1, wherein: The connection layer (9) includes an N+ layer (92) and a P- layer (93), wherein the P- layer (93) is located between the N+ layer (92) and the gate (3).

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