Electronic device

Abstract

The invention provides an electronic device. The electronic device is provided with an active area and a peripheral area adjacent to the active area. The electronic device includes a substrate, a conductive layer disposed on the substrate, a first transistor disposed on the conductive layer and located in the active region, a second transistor disposed on the substrate and located in the peripheral region, and a first electrode disposed on the first transistor. And a lead electrically connected between the first transistor and the second transistor. In a plan view direction of the electronic device, the conductive layer includes an outer surrounding portion located within the peripheral region and between the first transistor and the second transistor, and the conductive wire spans the outer surrounding portion and is electrically insulated from the outer surrounding portion.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to an electronic device capable of improving the reliability of electronic units. Background Art

[0002] Active components (such as transistors, but not limited thereto) within an electronic device may be damaged by the polarization phenomenon of the substrate, the signal of a stylus, or other factors. For example, active components may be damaged by electrostatic discharge, thereby affecting the reliability of the electronic device. Therefore, how to improve the reliability of active components within an electronic device remains one of the important issues in this field. Summary of the Invention

[0003] An object of the present invention is to provide an electronic device capable of improving the reliability of electronic units.

[0004] The present invention provides an electronic device having an active area and a peripheral area adjacent to the active area. The electronic device includes a substrate, a conductive layer disposed on the substrate, a first transistor disposed on the conductive layer and within the active area, a second transistor disposed on the substrate and within the peripheral area, and a wire electrically connected between the first transistor and the second transistor. In a top view direction of the electronic device, the conductive layer includes an outer surrounding portion located within the peripheral area and between the first transistor and the second transistor, and the wire straddles the outer surrounding portion and is electrically insulated from the outer surrounding portion. Brief Description of the Drawings

[0005] Figure 1A Partial cross-sectional schematic diagram of the electronic device according to the first embodiment of the present invention.

[0006] Figure 1B Partial enlarged cross-sectional schematic diagram of the electronic device according to the first embodiment of the present invention.

[0007] Figure 2 Top view schematic diagram of the electronic device according to the first embodiment of the present invention.

[0008] Figure 3 Equivalent circuit schematic diagram of the driving unit according to the first embodiment of the present invention.

[0009] Figure 4 Top view schematic diagram of the electronic device according to the second embodiment of the present invention.

[0010] Figure 5 Top view schematic diagram of the electronic device according to the third embodiment of the present invention.

[0011] Figure 6 Partial top view schematic diagram of the electronic device according to the fourth embodiment of the present invention.

[0012] Figure 7 It is a partial top view schematic diagram of the electronic device according to the fifth embodiment of the present invention.

[0013] Figure 8 It is a top view schematic diagram of the electronic device according to the sixth embodiment of the present invention.

[0014] Figure 9 It is a partial cross-sectional schematic diagram of the electronic device according to the seventh embodiment of the present invention.

[0015] Figure 10 It is a cross-sectional schematic diagram of the electronic device according to the eighth embodiment of the present invention.

[0016] Explanation of the reference numerals: AD2, AD1, AD3-adhesion layer; AIT-anode initialization voltage; AR-active area; B1-first distance; B2-second distance; BER-bending sub-area; BM-black matrix layer; BM1, BM2-sub-black matrix layer; BP-bonding pad; BR-bonding sub-area; C1, C2-capacitor; CEL-conductive element; CL-circuit layer; CO-covering layer; COL1, COL2-sub-conductive layer; COM-common voltage; COR-corner; CP, CP1, CP2, CP3, CP2', CP2"-connecting part; CR1, CR-channel region; CT-center point; CUR-bending region; CW1, CW2, CW3, CW4, CW5, CW6, CW-conductor; D3, D4, D1, D2-distance; DOE1, DOE2, DOE-drain electrode; DR1, DR-drain region; DT-data voltage; DU-driving circuit; E1, E2-electrode; ED-electronic device; EM-emission management signal; ER-flat sub-area; EXL-extension line; FPC1, FPC2-printed circuit board; FR-foldable sub-area; G1-first gate signal; G2-second gate signal; G3-third gate signal; G4-fourth gate signal; GC-gate driving circuit; GE1, GE2, GE-gate electrode; GP, GP1, GP2, GP3-group; HC-hard coating layer; HD-heat dissipation layer; HL1, HL2-water Flat extension line; I11, I12, I13, I14, IL4, IL5, IL6, IL7, IL8, IL9, IL10, IL1, IL2, IL3, I3, I4, I5, INL, I6, I7, I8, I9, I1, I2, I10-insulating layer; IC1, IC2, IC3-electronic unit; LCL-optical layer; LEL-luminous layer; LR-straight area; LU-luminous unit; M5, M6, M7, M8, M9, M1, M2, M3, M4, COL-conductive layer; ME-electronic component; MEL-electronic component layer; OM-organic material; OP5, OP6, OP7, OP2, OP3, OP1, OP4-opening; OSP-external periphery Winding part; P3, P1, P2-point; PL-protective layer; PO-part; PP, PP1-pattern part; PR-peripheral area; PT1, PT2-pitch; R1-area; RC-minimum rectangle; S1-upper surface; S2-lower surface; SB, SB1, SB2-substrate; SEL-sensing layer; SM1, SM2, SM-semiconductor layer; SOE1, SOE2, SOE-source electrode; SP-support layer; SR1, SR-source region; SUP-support plate; T6, T7, T1, T2, TR1, TR2, TR3, TR4, TR5, TR6, TR7, T3, T4, T5-transistor; TAL-tangent; TS-touch structure; UA1-first unit area;UA2 - Second unit area; V1 - Perforation; VIT - Gate initialization voltage; VS - Power supply voltage; W3, W1, W2 - Width; Y1, Z1, X1 - Pattern sub - parts; θ1, θ2, θ3, θ4 - Acute - angle included angles; X, Y, Z - Directions; Detailed implementation

[0017] The present invention can be understood by referring to the following detailed description and simultaneously combining the accompanying drawings. It should be noted that, for the convenience of the reader's understanding and for the simplicity of the drawings, only a part of the device is shown in the multiple drawings of the present invention, and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the drawings are only for illustration and are not used to limit the scope of the present invention.

[0018] Throughout the specification and the appended claims of the present invention, certain terms are used to refer to specific elements. Those of ordinary skill in the art should understand that electronic device manufacturers may use different names to refer to the same element. This document does not intend to distinguish elements that have the same function but different names.

[0019] In the specification and claims of the present invention, words such as "comprising" and "including" are open - ended words, and thus should be interpreted as meaning "including but not limited to...".

[0020] It should be understood that when an element or a film layer is said to be "disposed on" another element or film layer or "connected to" another element or film layer, it can be directly on this other element or film layer or directly connected to this other element or film layer, or there are intervening elements or film layers between them (non - direct situation). On the contrary, when an element is said to be "directly" on another element or film layer or "directly connected to" another element or film layer, there are no intervening elements or film layers between them. When an element or a film layer is said to be "electrically connected to" another element or film layer, it can be interpreted as either directly electrically connected or non - directly electrically connected. The electrical connections or couplings described in the present invention can refer to either direct connections or indirect connections. In the case of direct connections, the endpoints of two components on the circuit are directly connected or connected to each other by a conductor segment. In the case of indirect connections, there are switches, diodes, capacitors, inductors, resistors, other suitable components, or combinations of the above components between the endpoints of two components on the circuit, but not limited to this.

[0021] Although terms such as "first", "second", "third",... can be used to describe various components, the components are not limited by these terms. These terms are only used to distinguish a single component in the specification from other components. The same terms may not be used in the claims, and instead, the components in the claims may be declared as first, second, third,... in the order of the claim. Therefore, in the following specification, the first component may be the second component in the claims.

[0022] In the present invention, the thickness, length, and width can be measured by using an optical microscope, and the thickness or width can be measured from a cross-sectional image in an electron microscope, but this is not limiting.

[0023] In addition, there may be a certain error between any two numerical values or directions to be compared. Terms such as "about", "equal to", "equivalent to" or "the same", "substantially" or "roughly" are generally interpreted as within a range of plus or minus 20% of the given value, or within a range of plus or minus 10%, plus or minus 5%, plus or minus 3%, plus or minus 2%, plus or minus 1%, or plus or minus 0.5% of the given value.

[0024] Furthermore, the phrase "a given range is from a first numerical value to a second numerical value", "a given range falls within the range from a first numerical value to a second numerical value" means that the given range includes the first numerical value, the second numerical value, and other numerical values therebetween.

[0025] If a first direction is perpendicular to a second direction, the angle between the first direction and the second direction can be between 80 degrees and 100 degrees; if a first direction is parallel to a second direction, the angle between the first direction and the second direction can be between 0 degrees and 10 degrees.

[0026] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the technical field to which the present invention pertains. It is understood that these terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning consistent with the relevant technology and the background or context of the present invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of the present invention.

[0027] It should be noted that, without departing from the spirit of the present invention, the technical features in several different embodiments can be replaced, recombined, and mixed to complete other embodiments in the following examples.

[0028] The electronic device of the present invention may include a display device, a sensing device, a backlight device, an antenna device, a splicing device, or other suitable electronic devices, but is not limited thereto. The electronic device may be a bendable, flexible, or stretchable electronic device. The display device may include a non-self-emitting display device or a self-emitting display device. The non-self-emitting display device includes, for example, a liquid crystal display device, but is not limited thereto. The self-emitting display device includes, for example, a light-emitting diode display device, but is not limited thereto. The display device may be applied to, for example, a laptop computer, a public display, a tiled display, a vehicle display, a touch display, a television, a monitor, a smart phone, a tablet computer, a light source module, a lighting device, or an electronic device applied to the above products, but is not limited thereto. The sensing device may include a biosensor, a touch sensor, a fingerprint sensor, other suitable sensors, or a combination of the above types of sensors. The antenna device may include, for example, a liquid crystal antenna device, but is not limited thereto. The splicing device may include, for example, a display splicing device or an antenna splicing device, but is not limited thereto. The shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may include an electronic unit, where the electronic unit may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, sensors, etc. The diode may include a light-emitting diode or a photodiode. The light-emitting diode may include, for example, an organic light-emitting diode (OLED) or an inorganic light-emitting diode. The inorganic light-emitting diode may include, for example, a mini light-emitting diode (mini LED), a micro light-emitting diode (micro LED), or a quantum dot light-emitting diode (quantum dot LED), but is not limited thereto. It should be noted that the electronic device of the present invention may be various combinations of the above devices, but is not limited thereto. The electronic device may have peripheral systems such as a driving system, a control system, a light source system, etc. to support the display device, the antenna device, a wearable device (such as including augmented reality or virtual reality), a vehicle-mounted device (such as including an automotive windshield), or a splicing device. Hereinafter, the content of the present invention will be described by taking the electronic device including a display device as an example, but the present invention is not limited thereto.

[0029] Please refer to Figure 1A 、 Figure 1B and Figure 2 , Figure 1A is a partial cross-sectional schematic diagram of the electronic device according to the first embodiment of the present invention, Figure 1B is a partially enlarged cross-sectional schematic diagram of the electronic device according to the first embodiment of the present invention, Figure 2 is a top view schematic diagram of the electronic device according to the first embodiment of the present invention. As Figure 1AAs shown, the electronic device ED may include a substrate SB, a circuit layer CL disposed on the substrate SB, and an electronic component layer MEL disposed on the circuit layer CL, but is not limited thereto. The electronic component layer MEL may include electronic components ME, such as Figure 1B as shown. Specifically, Figure 1A only a single film layer represents the circuit layer CL, the electronic component layer MEL, and the touch structure TS, and the detailed structure thereof can be referred to Figure 1B . Figure 1B For example, it is Figure 1A an enlarged cross-sectional view of a part PO of. The type of the electronic component ME may depend on the type or use of the electronic device ED. For example, the electronic device ED of this embodiment may include a display device, and the electronic component ME may include a light-emitting element, but is not limited thereto. In some embodiments, the electronic device ED may include a sensing device, and the electronic component ME may include any suitable sensing element, such as a light sensing element or a thermal sensing element. In some embodiments, the electronic component ME may include an electromagnetic wave transmitting / receiving element, such as an antenna element, but is not limited thereto.

[0030] The substrate SB can be used to support the components and film layers located thereon. The substrate SB may include a hard material or a flexible material. The hard material includes, for example, glass, quartz, sapphire, ceramic, other suitable materials, or a combination of the above materials. The flexible material includes, for example, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), other suitable materials, or a combination of the above materials. The substrate SB may at least partially include a flexible material such that the substrate SB is a flexible substrate, but is not limited thereto. It should be noted that in some embodiments, the substrate SB may include a multi-layer structure and is not limited to Figure 1A , Figure 1B as shown.

[0031] The circuit layer CL may include various wires, circuits, and electronic units applicable to the electronic device ED. The electronic unit may include any suitable active components and / or passive components. The circuit layer CL may include any suitable structure formed by stacking a conductive layer and an insulating layer, where the conductive layer may form the above-mentioned wires, circuits, or electronic units. The stacking direction of the conductive layer and the insulating layer in the circuit layer CL may be parallel to the top view direction or the normal direction (i.e., direction Z, which will not be elaborated hereinafter) of the electronic device ED. For example, as Figure 1B shown, the circuit layer CL may include a driving circuit DU, where the driving circuit DU may be electrically connected to any suitable electronic component in the electronic device ED. For example, one driving circuit DU may be electrically connected to one electronic component ME. The driving circuit DU may include transistors, such as Figure 1BThe transistor T1 shown. The transistor T1 can be a thin film transistor (TFT), but is not limited thereto. Specifically, the circuit layer CL can include a semiconductor layer SM, a conductive layer M1, and a conductive layer M2. The semiconductor layer SM can form a channel region CR, a source region SR, and a drain region DR of the transistor T1, and the conductive layer M1 can form a gate electrode GE of the transistor T1. The channel region CR can be defined as a part of the semiconductor layer SM that overlaps the gate electrode GE. The conductive layer M2 is located on the conductive layer M1 and can form a source electrode SOE and a drain electrode DOE that are electrically connected to the source region SR and the drain region DR, respectively. The semiconductor layer SM can include a semiconductor material. The semiconductor material can include silicon or a metal oxide, such as a low temperature polysilicon (LTPS) semiconductor, an amorphous silicon (a-Si) semiconductor, an indium gallium zinc oxide (IGZO) semiconductor, a low temperature polysilicon oxide (LTPO), or a combination of the above, but is not limited thereto. The conductive layer M1 and the conductive layer M2 can include any suitable conductive material, such as a metal material, but is not limited thereto. The circuit layer CL can further include an insulating layer I3 disposed between the semiconductor layer SM and the conductive layer M1, an insulating layer I4 disposed between the conductive layer M1 and the conductive layer M2, and an insulating layer I5 disposed on the insulating layer I4. The insulating layer I3, the insulating layer I4, and the insulating layer I5 can include any suitable insulating material, such as an organic insulating material or an inorganic insulating material. In some embodiments, the insulating layer I3 can be a gate insulating layer of the transistor T1. It should be noted that Figure 1B The structure of the circuit layer CL shown is only exemplary, and this embodiment is not limited thereto.

[0032] As Figure 2 shown, the electronic device ED can include a gate driving circuit GC disposed on a substrate SB. The gate driving circuit GC can include an amplifier, signal lines, a shift register, and / or other suitable components, but is not limited thereto. The gate driving circuit GC can include transistors (not shown in Figure 2 , and reference can be made to Figure 6 the transistor T2). Figure 2 Only exemplarily, the structure of the gate driving circuit GC is represented by a block. Specifically, Figure 2 the block shown represents the setting positions of the transistors of the gate driving circuit GC. That is, the transistors in the gate driving circuit GC can be arranged at intervals, but are not limited thereto. In some embodiments, Figure 2The square shown may represent a group of transistors composed of multiple transistors of the gate drive circuit GC, and multiple groups of transistors may be arranged at intervals. The transistors in the gate drive circuit GC can be electrically connected to the transistors in the drive circuit DU through a wire (not shown in Figure 2 , reference can be made to Figure 4 and Figure 6 the wire CW). It should be noted that, for the sake of simplicity of the drawing, Figure 1A the structure of the gate drive circuit GC is not shown.

[0033] Please refer to Figure 1B, the electronic component layer MEL includes electronic components ME. The electronic components ME in this embodiment may include light-emitting units LU, but are not limited thereto. The light-emitting unit LU may include a self-luminous element or a non-self-luminous element. The self-luminous element may include a light-emitting diode, but is not limited thereto. The light-emitting diode may include an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED or QDLED), an inorganic light-emitting diode (LED), any other suitable light-emitting element, or a combination of the above. The inorganic light-emitting diode may include, for example, a mini LED or a micro LED, but is not limited thereto. The non-self-luminous element includes, for example, a liquid crystal layer, but is not limited thereto. The light-emitting unit LU in this embodiment may include an organic light-emitting diode, but is not limited thereto. Specifically, the light-emitting unit DU may include an electrode E1, an electrode E2, and a light-emitting layer LEL disposed between the electrode E1 and the electrode E2. The electrode E1 may be disposed on the insulating layer I5 of the circuit layer CL, the light-emitting layer LEL may be disposed on the electrode E1, and the electrode E2 may be disposed on the light-emitting layer LEL. The electronic device ED may further include an insulating layer INL disposed on the insulating layer I5, wherein the insulating layer INL may partially cover the electrode E1 and may expose a part of the electrode E1. The insulating layer INL may include a plurality of openings OP2, and the light-emitting layer LEL may be disposed corresponding to the openings OP2, or in other words, the light-emitting layer LEL may be disposed in the openings OP2 of the insulating layer INL. Specifically, the openings OP2 may expose the electrode E1, and the light-emitting layer LEL may be disposed on the part of the electrode E1 exposed by the openings OP2. The insulating layer INL may serve as a pixel defining layer (PDL). The electrode E2 may be a continuous film layer conformally disposed on the light-emitting layer LEL and the insulating layer INL, that is, the electrodes E2 of different light-emitting units LU may be connected to each other, but are not limited thereto. The electrode E1 may be electrically connected to the driving circuit DU (for example, the drain electrode DOE of the transistor in the driving circuit DU), thereby electrically connecting the light-emitting unit LU to the driving circuit DU. The electronic device ED may further include an insulating layer I6 disposed on the electronic component ME (or the light-emitting unit LU), wherein the insulating layer I6 may be disposed on the electrode E2. The insulating layer I6 may serve as a packaging layer for packaging the components and film layers thereunder. In addition, the insulating layer I6 may provide a flat upper surface to facilitate the setting of other components and film layers thereon.

[0034] In this embodiment, a driving circuit DU may include a plurality of transistors, and Figure 1B the transistor T1 shown may be one of the transistors in the driving circuit DU. In other words, Figure 1BThe driving circuit DU is only represented by the transistor T1 for example. Please refer to Figure 3 , Figure 3 which is a schematic equivalent circuit diagram of the driving unit according to the first embodiment of the present invention. In this embodiment, a driving circuit DU may include transistors TR1, TR2, TR3, TR4, TR5, TR6, and TR7. In addition, the driving circuit DU may further include capacitors C1 and C2. Figure 1B The illustrated transistor T1 may be one of the transistors TR1, TR2, TR3, TR4, TR5, TR6, and TR7.

[0035] One end of the light-emitting unit LU (such as the electrode E1, but not limited thereto) may be electrically connected to the transistors TR6 and TR7. It should be noted that the "light-emitting unit LU is electrically connected to the transistors TR6 and TR7" here may include embodiments in which the light-emitting unit LU is electrically connected to the transistors TR6 and TR7 through other electronic components, and these electronic components may or may not be layer-turned. The other end of the light-emitting unit LU (such as the electrode E2, but not limited thereto) may be electrically connected to a common voltage COM. In other words, the above-mentioned "the electrode E1 of the light-emitting unit LU is electrically connected to the transistors in the driving circuit DU" may, for example, refer to being electrically connected to the transistors TR6 and TR7 in the driving circuit DU.

[0036] One end of the capacitor C1 may be electrically connected to the transistor TR1, and the other end of the capacitor C1 may be electrically connected to a power supply voltage VS. The capacitor C1 can be used to maintain the voltage of the gate of the transistor TR1 during the period when the first gate signal G1 is not received.

[0037] One end of the capacitor C2 may be electrically connected to the transistor TR3. The other end of the capacitor C2 may be electrically connected to the gate driving circuit GC (as Figure 2 shown) and can receive the first gate signal G1. The capacitor C2 can be used to compensate for the voltage drop of the gate of the transistor TR1.

[0038] The gate of the transistor TR1 may be electrically connected to one end of the capacitor C1, the source of the transistor TR1 may be electrically connected to the transistor TR2 and receive the data voltage DT, and the drain of the transistor TR1 may be electrically connected to the transistor TR6. The transistor TR1 can be used as a driving transistor.

[0039] The gate of transistor TR2 can receive a first gate signal G1. Specifically, the gate of transistor TR2 can be electrically connected to a scan line (not shown in the figure) to receive the first gate signal G1. The source of transistor TR2 can receive a data voltage DT. Specifically, the source of transistor TR2 can be electrically connected to a data line (not shown in the figure) to receive the data voltage DT. The drain of transistor TR2 can be electrically connected to the source of transistor TR1 to provide the data voltage DT to the source of transistor TR1 when transistor TR2 is turned on. Transistor TR2 can act as a switching transistor.

[0040] Transistor TR3 can be a dual-gate transistor and can include a gate and a bottom gate. The gate and the bottom gate of transistor TR3 can be electrically connected to a gate driving circuit GC and receive a second gate signal G2. The source of transistor TR3 can be electrically connected to the drain of transistor TR1, and the drain of transistor TR3 can be electrically connected to the gate of transistor TR1. Transistor TR3 can act as a compensating transistor to compensate for the threshold voltage of transistor TR1.

[0041] Transistor TR4 can be a dual-gate transistor and can include a gate and a bottom gate. The gate and the bottom gate of transistor TR4 can be electrically connected to a gate driving circuit GC and receive a third gate signal G3. The source of transistor TR4 can be electrically connected to the gate of transistor TR1, and the drain of transistor TR4 can receive a gate initialization voltage VIT. Transistor TR3 can act as a gate initialization transistor for initializing the gate of transistor TR1 to the gate initialization voltage VIT.

[0042] The gate of transistor TR5 can receive an emission management signal EM. The source of transistor TR5 can receive a power supply voltage VS. The drain of transistor TR5 can be electrically connected to transistor TR1. After transistor TR5 receives the emission management signal EM and is turned on, transistor TR5 can provide the power supply voltage VS to transistor TR1.

[0043] The gate of transistor TR6 can receive an emission management signal EM. The source of transistor TR6 can be electrically connected to transistor TR1. The drain of transistor TR6 can be electrically connected to a light emitting unit LU. After transistor TR6 receives the emission management signal EM and is turned on, transistor TR6 can provide a driving current to the light emitting unit LU.

[0044] The gate of transistor TR7 can receive a fourth gate signal G4. The source of transistor TR7 can be electrically connected to the light-emitting unit LU. The drain of transistor TR7 can receive an anode initialization voltage AIT. After transistor TR7 is turned on upon receiving the fourth gate signal G4, transistor TR7 can supply the anode initialization voltage AIT to the light-emitting unit LU, and initialize the electrode E1 of the light-emitting unit LU to the anode initialization voltage AIT. In other words, transistor TR7 can serve as an anode initialization transistor.

[0045] It should be noted that the number, type, and electrical connection design of the transistors included in the above driving circuit DU are only exemplary, and the present invention is not limited thereto.

[0046] As Figure 2 shown, the electronic device ED can include an active area AR and a peripheral area PR. The active area AR can be the area where the electronic components ME and the driving circuit DU (labeled in Figure 1B ) electrically connected to the electronic components ME are provided in the electronic device ED. In other words, the active area AR can be the area in the electronic device ED where the electronic components ME operate or can be operated by the user. In the top view direction of the electronic device ED, the active area AR can be defined as the smallest rectangle enclosed by the outermost edges of the outermost electronic components ME and the driving circuit DU, but not limited thereto. The above "outermost driving circuit DU" can refer to the outermost transistors in the driving circuit DU. In other words, the active area AR can be defined as the smallest rectangle enclosed by the outermost edges of the outermost components among the electronic components ME and the transistors of the driving circuit DU. After defining the active area AR, the other areas in the electronic device ED except the active area AR can be defined as the peripheral area PR. The electronic components ME and the driving circuit DU (or rather, the transistors in the driving circuit DU) are provided in the active area AR, while the gate driving circuit GC (or rather, the transistors in the gate driving circuit GC) is provided in the peripheral area PR.

[0047] In some embodiments, the electronic device ED may further include a touch structure TS disposed on the electronic component ME. The touch structure TS may include a structure formed by stacking a conductive layer and an insulating layer, but not limited thereto. For example, as Figure 1BAs shown, the electronic device ED may further include a conductive layer M3 disposed on the insulating layer I6, an insulating layer I7 disposed on the conductive layer M3, a conductive layer M4 disposed on the insulating layer I7, and an insulating layer I8 disposed on the conductive layer M4. The conductive layer M4 may be electrically connected to the conductive layer M3 through a via hole passing through the insulating layer I7. The conductive layer M3 and the conductive layer M4 may include any suitable conductive material, such as metal, but not limited thereto. In this embodiment, in the top view direction of the electronic device ED, the patterns of the conductive layers (such as the conductive layer M3 and the conductive layer M4) in the touch structure TS may not overlap with the light-emitting unit LU, or rather, do not overlap with the light-emitting region of the light-emitting layer LEL of the light-emitting unit LU. It should be noted that the setting position of the touch structure TS in the electronic device ED is not limited to Figure 1A , Figure 1B shown. In addition, Figure 1B the structure of the touch structure TS shown is only exemplary, and the present invention is not limited thereto. The touch structure TS may include a resistive touch structure, a capacitive touch structure, an infrared touch structure, an ultrasonic touch structure, other suitable touch structures, or a combination of the above touch structures.

[0048] In some embodiments, the electronic device ED may further include an optical layer LCL and a black matrix layer BM disposed on the light-emitting unit LU. The optical layer LCL may include elements or film layers that can provide any suitable optical function, depending on the design of the electronic device ED. For example, the optical layer LCL may include a light conversion layer, which may include any suitable material that can change the wavelength or color of the light passing through the light conversion layer. For example, the optical layer LCL may include a color filter, which may allow light of a specific wavelength to pass through, but not limited thereto. In some embodiments, the optical layer LCL may include quantum dots, fluorescent materials, phosphorescent materials, other suitable materials, or a combination of the above materials. In this embodiment, the electronic device ED may include a plurality of optical layers LCL, and the plurality of optical layers LCL may convert light into light having different wavelengths or colors. For example, the optical layer LCL may convert light into red light, green light, and blue light respectively, and may mix to produce white light, but not limited thereto. The optical layer LCL may be disposed corresponding to the light-emitting unit LU. The black matrix layer BM may be disposed between two adjacent optical layers LCL. Specifically, the black matrix layer BM may include a plurality of openings OP3, and the optical layer LCL may be disposed corresponding to the openings OP3 of the black matrix layer BM. As Figure 1A , Figure 1B shown, the electronic device ED may further include an insulating layer I9 disposed on the optical layer LCL and the black matrix layer BM. The insulating layer I9 may provide a flat upper surface to facilitate the setting of other elements and film layers thereon.

[0049] In some embodiments, the electronic device ED may further include a cover layer CO disposed on the light-emitting unit LU. Specifically, the cover layer CO may be attached to the insulating layer I9 through an adhesive layer AD2. It should be noted that although Figure 1A , Figure 1B the shown cover layer CO is a single-layer structure, the present invention is not limited thereto. In some embodiments, the cover layer CO may include a multi-layer structure, such as a multi-layer structure formed by stacking an inorganic layer, an organic layer, and an inorganic layer.

[0050] In some embodiments, the electronic device ED may further include a hardcoating layer HC disposed on the cover layer CO. For example, the hardcoating layer HC may be disposed on the side of the cover layer CO opposite to the optical layer LCL. The hardcoating layer HC may provide a protective effect for the elements and film layers located thereunder.

[0051] In some embodiments, the electronic device ED may further include a support plate SUP disposed under the substrate SB, on the side of the substrate SB opposite to the circuit layer CL. As Figure 1A shown, the support plate SUP may be attached to the substrate SB through an adhesive layer AD1, but not limited thereto. The support plate SUP may include any suitable flexible support material. In the present embodiment, the active area AR of the electronic device ED may include a foldable sub-area FR, where the part of the electronic device ED within the foldable sub-area FR may be folded, bent, curled, or deformed in other suitable ways. The part of the electronic device ED within the foldable sub-area FR may not be fixed or may be fixed during the use of the electronic device ED. In the present embodiment, the part of the support plate SUP corresponding to the foldable sub-area FR (shown in Figure 1A and Figure 2 ) may include at least one opening OP1. The opening OP1 may be formed by partially removing the part of the support plate SUP corresponding to the foldable sub-area FR. The opening OP1 may penetrate the support plate SUP and may expose the adhesive layer AD1, but not limited thereto. In some embodiments, the opening OP1 may not penetrate the support plate SUP. Thus, the flexibility of the support plate SUP can be improved. In some embodiments, the active area AR may include a plurality of foldable sub-areas FR, not limited to Figure 1A shown. In the present embodiment, the other areas within the active area AR except the foldable sub-area FR may be defined as a flat sub-area ER. Specifically, the part of the electronic device ED within the flat sub-area ER may not be bent or deformed in other ways. In addition, the part of the electronic device ED within the flat sub-area ER may be fixed during the use of the electronic device ED.

[0052] In some embodiments, the electronic device ED may further include a sensing layer SEL, a heat dissipation layer HD, and a support layer SP disposed under the substrate SB. As Figure 1AAs shown, the sensing layer SEL can be disposed on the side of the support plate SUP opposite to the substrate SB (or the back side of the substrate SB), the heat dissipation layer HD can be disposed on the side of the sensing layer SEL opposite to the substrate SB, and the support layer SP can be disposed on the side of the heat dissipation layer HD opposite to the sensing layer SEL. In other words, the heat dissipation layer HD is disposed between the sensing layer SEL and the support layer SP. The sensing layer SEL can include any suitable sensing element, such as a touch sensing element, a biosensing element, a distance sensing element, an electromagnetic wave sensing element (such as an antenna), other suitable sensing elements, or a combination of the above elements. In some embodiments, the sensing layer SEL can include any suitable element that can sense a finger, a stylus, or other suitable external object. The sensing layer SEL can be electrically connected to the printed circuit board FPC1 through the through hole V1 passing through the heat dissipation layer HD and the support layer SP. The printed circuit board FPC1 includes, for example, a flexible printed circuit board (FPCB), but is not limited thereto. The electronic device ED can further include an electronic unit IC1 electrically connected to the printed circuit board FPC1. The electronic unit IC1 can be used to drive / control the sensing layer SEL. The electronic unit IC1 includes, for example, a chip, other suitable electronic units, or a combination of the above. The heat dissipation layer HD can be used to dissipate the heat generated by components such as the sensing layer SEL, the printed circuit board FPC1, or the electronic unit IC1. The heat dissipation layer HD can include any suitable high thermal conductivity material, such as copper, but is not limited thereto. The support layer SP can provide a supporting effect for the heat dissipation layer HD, the sensing layer SEL, the printed circuit board FPC1, and the electronic unit IC1. In this embodiment, the sensing layer SEL can be disposed offset from the foldable sub-region FR in the active region AR. For example, the electronic device ED can include two sensing layers SEL, which are respectively disposed on both sides of the foldable sub-region FR and corresponding to the flat sub-region ER, but is not limited thereto. In this case, the electronic device ED can include two heat dissipation layers HD, two support layers SP, two printed circuit boards FPC1, and two electronic units IC1, which are respectively disposed corresponding to the two sensing layers SEL. Thus, the possibility of damage to the sensing layer SEL and the electronic unit IC1 during the flexing process of the electronic device ED can be reduced.

[0053] The electronic device ED may further include a flexible printed circuit board FPC2 disposed on the substrate SB, and electronic units IC2 and IC3 disposed on the flexible printed circuit board FPC2. The flexible printed circuit board FPC2 may include, for example, a flexible printed circuit board, but is not limited thereto. The driving circuit DU and the gate driving circuit GC may be electrically connected to the flexible printed circuit board FPC2, and thus electrically connected to the electronic unit IC2. In this way, the driving circuit DU and the gate driving circuit GC can be controlled by the electronic unit IC2. The electronic unit IC3 may be used to drive / control the touch structure TS, but is not limited thereto. In some embodiments, the electronic unit IC3 may be used to drive / control other electronic components in the electronic device ED. The electronic unit IC2 and the electronic unit IC3 include, for example, wafers, other suitable electronic units, or combinations thereof. In the present embodiment, a part of the substrate SB on which the flexible printed circuit board FPC2, the electronic unit IC2, and the electronic unit IC3 are disposed may be bent backward so that the flexible printed circuit board FPC2, the electronic unit IC2, and the electronic unit IC3 can be on the same side (the back side of the substrate SB) as the sensing layer SEL. Specifically, the peripheral region PR of the electronic device ED may further include a bending sub-region BER and a bonding sub-region BR. The bending sub-region BER may be connected between the bonding sub-region BR and the active region AR, but is not limited thereto. The bending sub-region BER may be defined as the region corresponding to the bending and fixing of the substrate SB of the electronic device ED during use. Specifically, the substrate SB of the electronic device ED may start to deviate from a horizontal extension line HL1 parallel to the extension direction of the outer surface of the substrate SB (e.g., direction X) at point P1, and may start to deviate from another horizontal extension line HL2 parallel to the extension direction of the outer surface of the substrate SB at point P2, and the bending sub-region BER may be defined as the region corresponding to the portion between point P1 and point P2 of the substrate SB. The bonding sub-region BR may be defined as the region of the substrate SB corresponding to the above components such as the flexible printed circuit board FPC2, the electronic unit IC2, and the electronic unit IC3. That is, the gate driving circuit GC and the driving circuit DU may be electrically connected to the flexible printed circuit board FPC2, the electronic unit IC2, and the electronic unit IC3 in the bonding sub-region BR. The electronic device ED may further include a protective layer PL, where the protective layer PL may be disposed corresponding to the peripheral region PR. Specifically, the protective layer PL may cover the portion of the electronic device ED in the peripheral region PR, thereby providing a protection effect for the electronic device ED. The protective layer PL may include any suitable protective material, such as a waterproof layer, but is not limited thereto.

[0054] According to the present invention, the electronic device ED may include a conductive layer COL disposed on the substrate SB. Specifically, in the top view direction of the electronic device ED, the conductive layer COL is disposed between the substrate SB and the driving circuit DU, or rather, the conductive layer COL is disposed between the substrate SB and the transistors of the driving circuit DU. For example, as Figure 1A ,Figure 1B As shown, the electronic device ED may include an insulating layer I1 disposed on a substrate SB, a conductive layer COL disposed on the insulating layer I1, and an insulating layer I2 disposed on the conductive layer COL, but is not limited thereto. The insulating layer I1 may be disposed between the substrate SB and the conductive layer COL. The insulating layer I2 may be disposed between the conductive layer COL and a driving circuit DU (such as a semiconductor layer SM of a transistor in the driving circuit DU). It should be noted that other elements and / or film layers may also be included between the substrate SB and the circuit layer CL.

[0055] The conductive layer COL may be a patterned film layer. Specifically, as Figure 2 shown, the conductive layer COL may include a plurality of pattern portions PP, a plurality of connection portions CP, and an outer surrounding portion OSP, but is not limited thereto. The pattern portions PP may have any suitable shape, such as a rectangle, but is not limited thereto. In a top view direction of the electronic device ED, the pattern portions PP may be arranged in a matrix, but is not limited thereto. In a top view direction of the electronic device ED, the outer surrounding portion OSP may surround the pattern portions PP of the conductive layer COL. For example, as Figure 2 shown, the outer surrounding portion OSP of the present embodiment may have an annular structure and surround the pattern portions PP, but is not limited thereto. It should be noted that the above "the outer surrounding portion OSP surrounds the pattern portions PP" may include a case where the outer surrounding portion OSP is disposed along at least one side of the plurality of pattern portions PP, that is, the outer surrounding portion OSP is not limited to including a closed pattern or an annular pattern. In some embodiments, the outer surrounding portion OSP may include two separate portions disposed along opposite sides of the plurality of pattern portions PP. The connection portions CP may connect between two adjacent pattern portions PP and between a pattern portion PP and the outer surrounding portion OSP. For example, the connection portions CP may include a connection portion CP1 connecting adjacent pattern portions PP and a connection portion CP2 connecting a pattern portion PP and the outer surrounding portion OSP, but is not limited thereto. The connection portions CP may be strip-shaped or similar to a strip shape, but is not limited thereto. For example, the connection portion CP1 may have a curved strip structure, and the connection portion CP2 may have a straight structure, but is not limited thereto. The shapes of the connection portion CP1 and the connection portion CP2 may be the same or different, and the present invention is not limited thereto. It should be noted that the connection portion CP may further include a part (not labeled) connecting the pattern portion PP to the connection portion CP2, but is not limited thereto. Figure 2 The pattern of the conductive layer COL shown is only exemplary, and the present embodiment is not limited thereto.

[0056] In the top-down direction of the electronic device ED, the patterned portion PP of the conductive layer COL may overlap the drive circuit DU, or rather, overlap the transistors in the drive circuit DU. Specifically, one patterned portion PP may overlap a transistor in one drive circuit DU, but not limited thereto. In this embodiment, the above-mentioned "patterned portion PP overlapping the transistor in the drive circuit DU" may mean that the patterned portion PP at least overlaps the largest-sized transistor among the transistors in the drive circuit DU. For example, in this embodiment, the drive circuit DU may include seven transistors (refer to the above and Figure 3 structure), where the transistor TR1 may be the largest-sized one among the seven transistors. In this case, one patterned portion PP may at least overlap the transistor TR1 in one drive circuit DU. The above-mentioned "size of the transistor" may refer to the length or width of the transistor. In other words, the transistor TR1 may be the transistor with the largest length or width among the seven transistors. In some embodiments, one patterned portion PP may simultaneously overlap multiple transistors in one drive circuit DU, and these transistors may include the transistor TR1. Figure 1B shows the structure where the patterned portion PP of the conductive layer COL overlaps the transistor of the drive circuit DU, and in this case, Figure 1B the shown transistor T1 may be Figure 3 the shown transistor TR1. It should be noted that the above-mentioned "patterned portion PP overlapping the transistor in the drive circuit DU" may include embodiments where the patterned portion PP at least partially overlaps the channel region CR of the semiconductor layer SM of the transistor in the drive circuit DU. In short, one patterned portion PP may at least partially overlap the channel region CR of the semiconductor layer SM of a transistor in the drive circuit DU. As mentioned above, the drive circuit DU may be disposed in the active region AR. Therefore, the patterned portion PP of the conductive layer COL overlapping the drive circuit DU is disposed in the active region AR. As Figure 2 shown, the range of the active region AR may cover the setting range of the patterned portion PP. In this case, in some embodiments, the active region AR may be defined as the smallest rectangle surrounded by the outermost components of the electronic component ME and the patterned portion PP, such as Figure 2 shown. In summary, the electronic device ED includes a plurality of first transistors disposed on the conductive layer COL and within the active region AR, where a plurality of patterned portions PP of the conductive layer COL respectively overlap these first transistors. The first transistors here are the transistors in the drive circuit DU, which are disposed in the active region AR and configured to drive the electronic unit (i.e., the electronic component ME) within the active region AR, such as Figure 1B the shown transistor T1.

[0057] According to this embodiment, an outer surrounding portion OSP is disposed within a peripheral region PR and between a driving circuit DU and a gate driving circuit GC. Specifically, the outer surrounding portion OSP is disposed between a transistor of the driving circuit DU and a transistor of the gate driving circuit GC. In this case, the outer surrounding portion OSP can surround an electronic component ME. A connection portion CP can be disposed within an active region AR and within the peripheral region PR. Specifically, a connection portion CP1 connecting adjacent pattern portions PP can be located within the active region AR, and a connection portion CP2 connecting the pattern portion PP and the outer surrounding portion OSP can extend from the active region AR to the peripheral region PR.

[0058] By disposing a conductive layer COL between the substrate SB and the transistor of the driving circuit DU and making the conductive layer have the above-mentioned pattern design, the possibility that the transistor of the driving circuit DU is damaged by the electrostatic discharge generated during the use of the sensing layer SEL or the polarization phenomenon of the substrate SB can be reduced, thereby improving the reliability of the electronic device ED.

[0059] In this embodiment, as Figure 1BAs shown, in the normal direction (i.e., the Z direction) of the electronic device ED, there may be a distance D1 between the conductive layer COL and the transistor of the driving circuit DU, and there may be a distance D2 between the conductive layer COL and the sensing layer SEL, where the distance D1 may be less than the distance D2. The "distance D1 between the conductive layer COL and the transistor of the driving circuit DU" here may be defined as the minimum distance (or may be the vertical distance) between the conductive layer COL and the channel region CR of the semiconductor layer SM of the transistor of the driving circuit DU, and the "distance D2 between the conductive layer COL and the sensing layer SEL" may be defined as the minimum distance (or may be the vertical distance) between the conductive layer COL and the sensing layer SEL. For example, the distance D1 may be the vertical distance from the upper surface S1 of the conductive layer COL to the lower surface (not labeled) of the semiconductor layer SM of the transistor of the driving circuit DU, and the distance D2 may be the vertical distance from the lower surface S2 of the conductive layer COL to the upper surface (not labeled) of the sensing layer SEL, but it is not limited thereto. In this embodiment, the ratio of the distance D2 to the distance D1 may be greater than or equal to 20 and less than or equal to 1000 (i.e., 20 ≤ D2 / D1 ≤ 1000), but it is not limited thereto. In some embodiments, the ratio of the distance D2 to the distance D1 may be greater than or equal to 30 and less than or equal to 900 (i.e., 30 ≤ D2 / D1 ≤ 900). In some embodiments, the ratio of the distance D2 to the distance D1 may be greater than or equal to 40 and less than or equal to 800 (i.e., 40 ≤ D2 / D1 ≤ 800). The range of the distance D1 may be from 0.5 micrometers (μm) to 5 μm (i.e., 0.5 μm ≤ D1 ≤ 5 μm), but it is not limited thereto. In some embodiments, the range of the distance D1 may be from 1 micrometer (μm) to 4 μm (i.e., 1 μm ≤ D1 ≤ 4 μm). In some embodiments, the range of the distance D1 may be from 1.5 micrometers (μm) to 3 μm (i.e., 1.5 μm ≤ D1 ≤ 3 μm). The range of the distance D2 may be from 100 micrometers to 500 μm (i.e., 100 μm ≤ D2 ≤ 500 μm), but it is not limited thereto. In some embodiments, the range of the distance D2 may be from 150 micrometers to 450 μm (i.e., 150 μm ≤ D2 ≤ 450 μm). In some embodiments, the range of the distance D2 may be from 200 micrometers to 400 μm (i.e., 200 μm ≤ D2 ≤ 400 μm). In summary, in the top view direction of the electronic device ED, there may be a distance D1 between the conductive layer COL and a first transistor, and there may be a distance D2 between the conductive layer COL and the sensing layer SEL, and the distance D1 is less than the distance D2, where the first transistor is a transistor in the driving circuit DU, which is disposed in the active region AR and configured to drive an electronic unit (i.e., the electronic component ME) in the active region AR. Through the above design, the possibility that the semiconductor layer SM of the transistor is damaged by electrostatic discharge can be reduced. The above design can be applied to various embodiments and variant embodiments of the present invention.

[0060] In this embodiment, the cross-sectional structure of the conductive layer COL may include a rounded corner structure or other suitable non-pointed structures. In other words, the cross-sectional structure of the conductive layer COL may include a curved edge or an arc-shaped edge. For example, in a cross-sectional view of the electronic device ED (such as Figure 1A , Figure 1B ), the cross-sectional shape of the pattern portion PP of the conductive layer COL may include an arc-shaped edge, but is not limited thereto. Through the above design, the possibility of electrostatic discharge can be reduced. It should be noted that the cross-sectional structures of the connection portion CP and the outer surrounding portion OSP of the conductive layer COL may also include a rounded corner structure or other suitable non-pointed structures. The pattern design of the cross-sectional structure of the conductive layer COL here can be applied to various embodiments and variant embodiments of the present invention.

[0061] In this embodiment, the connection portions CP2 for connecting the pattern portion PP and the outer surrounding portion OSP at different positions may have different widths. Specifically, as Figure 2 shown, the connection portion CP2 (i.e., connection portion CP2') connecting the pattern portion PP and a part of the outer surrounding portion OSP adjacent to the bonding region BR (i.e., one side of the outer surrounding portion OSP adjacent to the bonding region BR) may have a width W1, while the connection portion CP2 (i.e., connection portion CP2") connecting the pattern portion PP and another part of the outer surrounding portion OSP relative to the said part of the outer surrounding portion OSP adjacent to the bonding region BR (i.e., the other side of the outer surrounding portion OSP relative to the side adjacent to the bonding region BR, or the side farthest from the bonding region BR) may have a width W2, where the width W1 may be different from the width W2. In this embodiment, a part of the outer surrounding portion OSP adjacent to the bonding region BR and another part of the outer surrounding portion OSP relative to the said part of the outer surrounding portion OSP may be two parts corresponding to two opposite sides of the active region AR of the outer surrounding portion OSP respectively. The definition of the bonding region BR can be referred to above, so it will not be elaborated here. According to this embodiment, the width of the connection portion CP (i.e., width W1) connected to a part of the outer surrounding portion OSP adjacent to the bonding region BR may be greater than the width of the connection portion CP (i.e., width W2) connected to another part of the outer surrounding portion OSP relative to the said part of the outer surrounding portion OSP (i.e., W1>W2). The above "width of the connection portion CP2" may refer to the dimension of the connection portion CP2 in a direction perpendicular to its extending direction. For example, as Figure 2As shown, the connecting portion CP2' can extend in the direction X, and the width W1 of the connecting portion CP2' can be the dimension of the connecting portion CP2' in the direction Y perpendicular to the direction X. Through the above design of the width of the connecting portion CP2, the anti-static discharge effect of the conductive layer COL can be improved, and thus the reliability of the electronic device ED can be improved. In summary, in this embodiment, the conductive layer COL includes a first connecting portion (i.e., Figure 2 the connecting portion CP2') and a second connecting portion (i.e., Figure 2 the connecting portion CP2"), the first connecting portion is connected to a part of the outer surrounding portion OSP adjacent to the bonding region BR, the second connecting portion is connected to another part of the outer surrounding portion OSP relative to the first connecting portion, and the width of the first connecting portion (i.e., the width W1) can be greater than the width of the second connecting portion (i.e., the width W2). In some embodiments, the width of the connecting portion CP2 (i.e., the connecting portion CP2') connected to a part of the outer surrounding portion OSP adjacent to the bonding region BR can be greater than the width of the other connecting portions CP2 connected to the outer surrounding portion OSP. The width design of the connecting portion CP2 in this embodiment can be applied to various embodiments and variant embodiments of the present invention.

[0062] According to this embodiment, as Figure 2 shown, the conductive layer COL may further include a connecting portion CP3, wherein the connecting portion CP3 is connected to a part of the outer surrounding portion OSP adjacent to the bonding region BR. Specifically, the connecting portion CP3 of the conductive layer COL can be disposed in the peripheral region PR and extend from the outer surrounding portion OSP toward the bonding region BR, wherein the connecting portion CP3 can pass through the bending sub-region BER and extend to the bonding region BR to be electrically connected to the bonding pad BP disposed in the bonding region BR. As Figure 2 shown, the conductive layer COL can include a plurality of connecting portions CP3, and each connecting portion CP3 can be electrically connected to a bonding pad BP respectively, but not limited thereto. The connecting portion CP3 of the conductive layer COL can extend on the bending sub-region BER. Figure 1A An exemplary structure of the conductive layer COL extending in the bending sub-region BER is shown. That is, Figure 1A the part of the conductive layer COL extending in the bending sub-region BER shown can be the connecting portion CP3 ( Figure 1A(not shown), but not limited thereto. The bonding pad BP can be electrically connected to any suitable electronic component in the electronic device ED, such as the above-mentioned electronic unit IC2, but not limited thereto. Thus, the conductive layer COL can be electrically connected to the electronic unit IC2 through the connection portion CP3. Through the above design, an electrical signal can be transmitted from the electronic unit IC2 to the conductive layer COL. In other words, the connection portion CP3 of the conductive layer COL can be configured to transmit a signal from the electronic unit IC2. For example, a common voltage can be transmitted from the electronic unit IC2 to the conductive layer COL through the connection portion CP3, but not limited thereto. Thus, the instability of the conductive layer COL caused by floating can be reduced, thereby improving the reliability of the conductive layer COL. It should be noted that, in some embodiments, the conductive layer COL may not include the connection portion CP3, and the conductive layer COL may not be electrically connected to other electronic components.

[0063] As Figure 2 shown, in this embodiment, the portion of the connection portion CP3 overlapping the bent sub-region BER may include at least one opening OP4, but not limited thereto. In some embodiments, a connection portion CP3 may include an opening OP4, where the opening OP4 may have a strip structure and overlap the bent sub-region BER, as Figure 2 shown in the upper half. In some embodiments, a connection portion CP3 may include a plurality of openings OP4, where the plurality of openings OP4 may have a circular structure and be arranged corresponding to the bent sub-region BER, as Figure 2 shown in the lower half. It should be noted that the structure of the opening OP4 is not limited to Figure 2 shown. The above design can reduce the possibility of the connection portion CP3 breaking, thereby improving the flexibility of the connection portion CP3. The structural features of the connection portion CP3 can be applied to various embodiments and variant embodiments of the present invention.

[0064] It should be noted that the structure of the electronic device ED in this embodiment is not limited to the above figure, and may further include other suitable components or film layers. More embodiments of the present invention will be described below. For the sake of simplicity, the same film layers or components in the following embodiments will be denoted by the same reference numerals, and their features will not be described again, and the differences between the embodiments will be described in detail below. It should be noted that the features described in each embodiment can be applied to each other, and are not limited to the structure of that embodiment.

[0065] Please refer to Figure 4 , Figure 4 which is a top view schematic diagram of the electronic device according to the second embodiment of the present invention. For the sake of simplicity of the drawings, Figure 4 the bent sub-region BER and the bonding sub-region BR of the electronic device ED are not shown therein, and their structural features can be referred to the above. In addition, althoughFigure 4 Not shown, the active region AR of the electronic device ED may include a foldable sub-region FR. According to the present embodiment, the pattern portion PP of the conductive layer COL may overlap a plurality of transistors in a driving circuit DU. Specifically, as Figure 4 shown, the pattern portion PP of the conductive layer COL of the present embodiment may include pattern sub-portions X1, Y1, and Z1 connected to each other, where the pattern sub-portions X1, Y1, and Z1 may respectively overlap a transistor in a driving circuit DU. In other words, one pattern portion PP of the present embodiment may overlap three transistors in a driving circuit DU, but is not limited thereto. Among the three transistors overlapped by the pattern sub-portions X1, Y1, and Z1, there may be included the largest-sized transistor in the driving circuit DU, such as the transistor TR1 mentioned above. For example, as Figure 4 shown, the pattern sub-portions X1, Y1, and Z1 in one pattern portion PP may respectively overlap the transistor TR1, the transistor TR2, and the transistor TR3, but are not limited thereto. In some embodiments, the pattern sub-portions Y1 and Z1 may respectively overlap any two of the other transistors (i.e., the transistors TR2, TR3, TR4, TR5, TR6, and TR7) in the driving circuit DU except for the transistor TR1. In some embodiments, the transistor TR1 may overlap the pattern sub-portion Y1 or the pattern sub-portion Z1. In some embodiments, two of the pattern sub-portions X1, Y1, and Z1 may respectively overlap a switching element (or switching transistor, such as the transistor TR2) and a driving element (or driving transistor, such as the transistor TR1) in the driving circuit DU. The material of the semiconductor layer of the switching transistor (such as the transistor TR2) may include metal oxides, such as indium gallium zinc oxide (IGZO), but is not limited thereto. The material of the semiconductor layer of the driving transistor (such as the transistor TR1) may, for example, include low-temperature polycrystalline silicon (LTPS), but is not limited thereto. As described above, the pattern portion PP overlapping a transistor in the present invention may mean that the pattern portion PP at least partially overlaps the channel region CR of the semiconductor layer SM of the transistor. Therefore, Figure 4 the transistors TR1, TR2, and TR3 shown may, for example, respectively represent the channel regions CR of the semiconductor layers SM of the transistors TR1, TR2, and TR3, but are not limited thereto. It should be noted that, Figure 4The pattern of the pattern portion PP shown is only exemplary, and this embodiment is not limited thereto. In some embodiments, the pattern sub-portions X1, Y1, and Z1 may have other arrangements or connection manners to form a pattern portion PP having any suitable pattern. In some embodiments, the pattern portion PP of the conductive layer COL may include any suitable pattern and overlap two, four, or more transistors in the driving circuit DU. The pattern design of the pattern portion PP of this embodiment can be applied to various embodiments and variant embodiments of the present invention.

[0066] As described above, in the present invention, the transistors in the driving circuit DU can be electrically connected to the transistors in the gate driving circuit GC. Specifically, as Figure 4 shown, the electronic device ED may include a plurality of wires CW, and one of the wires CW can be electrically connected between the transistor of the driving circuit DU and the transistor of the gate driving circuit GC. It should be noted that Figure 4 only exemplary, the structure in which the wire CW is electrically connected to the transistor TR1 represents the feature that the wire CW is electrically connected between the transistor of the driving circuit DU and the transistor of the gate driving circuit GC, and the wire CW can be electrically connected to any suitable transistor in the driving circuit DU, depending on the design of the driving circuit DU. In addition, Figure 4 not all of the wires CW are shown. Furthermore, Figure 4The position of the transistor to which the wire CW is electrically connected as shown is only exemplary, and this embodiment is not limited thereto. According to this embodiment, in the top view direction of the electronic device ED, the wire CW can extend between the driving circuit DU and the gate driving circuit GC, and can cross the outer surrounding portion OSP located between the driving circuit DU and the gate driving circuit GC. In other words, in the top view direction of the electronic device ED, the wire CW can overlap the outer surrounding portion OSP, or it can be said that the wire CW can intersect the outer surrounding portion OSP. In addition, according to the present invention, the wire CW may not be electrically connected to the outer surrounding portion OSP of the conductive layer COL. Specifically, the wire CW and the outer surrounding portion OSP can be provided on different layers, or there can be at least one insulating layer (such as the insulating layer I2, but not limited thereto) between the wire CW and the outer surrounding portion OSP to electrically insulate the wire CW from the outer surrounding portion OSP. In summary, the electronic device ED of the present invention can include a conductive layer COL provided on a substrate SB, a first transistor provided on the conductive layer COL and within the active region AR, a second transistor provided on the substrate SB and within the peripheral region PR, and a wire CW electrically connected between the first transistor and the second transistor. In the top view direction of the electronic device ED, the wire CW crosses the outer surrounding portion OSP located within the peripheral region PR and between the first transistor and the second transistor, and is electrically insulated from the outer surrounding portion OSP. Here, the first transistor is the transistor included in the driving circuit DU, which is configured to drive the electronic unit (i.e., the electronic component ME) within the active region AR; the second transistor is a transistor included in the gate driving circuit GC, and the transistor of the gate driving circuit GC can be electrically connected to the first transistor in the driving circuit DU.

[0067] The wire CW can cross the outer surrounding portion OSP and have an included angle with the outer surrounding portion OSP. According to this embodiment, in the top view direction of the electronic device ED, the acute included angle between the wire CW and the outer surrounding portion OSP can be greater than 20 degrees. The above-mentioned "acute included angle between the wire CW and the outer surrounding portion OSP" can be defined as the acute included angle between the wire CW and the outer edge of the outer surrounding portion OSP, but not limited thereto. Specifically, as Figure 4As shown, there is an acute angle θ1 between the wire CW1 connecting a transistor of the driving circuit DU and a transistor of the gate driving circuit GC and the outer edge of the outer surrounding part OSP, and there is an acute angle θ2 between the wire CW2 connecting another transistor of the driving circuit DU and another transistor of the gate driving circuit GC and the outer surrounding part OSP. The acute angle θ1 and the acute angle θ2 can be greater than 20 degrees (i.e., θ1, θ2 > 20°), but not limited thereto. In some embodiments, the acute angle θ1 and the acute angle θ2 can be greater than 25 degrees (i.e., θ1, θ2 > 25°). In some embodiments, the acute angle θ1 and the acute angle θ2 can be greater than 30 degrees (i.e., θ1, θ2 > 30°). It should be noted that in some embodiments, when a wire CW (such as the wire CW1) intersects a part of the outer surrounding part OSP having an arc-shaped edge, the acute angle between the wire CW and the outer surrounding part OSP (such as the acute angle θ1) can be defined as the acute angle between the tangent line (such as the tangent line TAL) passing through the intersection point (such as the point P3) of the wire CW and the outer edge of the outer surrounding part OSP and the wire CW, but not limited thereto. In addition, Figure 4 Only the feature that the acute angle θ1 and the acute angle θ2 are greater than 20 degrees is shown exemplarily, but this embodiment is not limited thereto. Other wires CW in the electronic device ED can respectively have acute angles with the outer surrounding part OSP, and these acute angles can be greater than 20 degrees.

[0068] In some embodiments, the acute angles between different wires CW and the outer surrounding part OSP can be different from each other. Specifically, the electronic device ED can include a first transistor and another first transistor (the first transistors are the transistors in the driving circuit DU) arranged in the active region AR, a second transistor and another second transistor (the second transistors are the transistors in the gate driving circuit GC) arranged in the peripheral region PR, a wire CW electrically connected between the first transistor and the second transistor, and another wire CW electrically connected between the other first transistor and the other second transistor. The acute angle between the wire CW and the outer surrounding part OSP can be different from the acute angle between the other wire CW and the outer surrounding part OSP. For example, in Figure 4 the acute angle θ1 between the wire CW1 and the outer surrounding part OSP can be different from the acute angle θ2 between the wire CW2 and the outer surrounding part OSP. In addition, the acute angles between other wires CW and the outer surrounding part OSP can be different from the acute angle θ1 and the acute angle θ2.

[0069] Through the design of the acute angles between the above-mentioned wires CW and the outer surrounding part OSP, the coupling between the wire CW and the outer surrounding part OSP can be reduced, thereby improving the reliability of the electronic device ED.

[0070] In some embodiments, a plurality of the conductive wires CW may have the same acute angle with respect to the outer surrounding portion OSP, and another plurality of the conductive wires CW may have the same another acute angle with respect to the outer surrounding portion OSP, where the acute angle may be different from the another acute angle. In other words, the electronic device ED may include multiple groups of the conductive wires CW, where the acute angle between the conductive wires CW in each group and the outer surrounding portion OSP may be the same, and the acute angles between the conductive wires CW in different groups and the outer surrounding portion OSP may be different. For example, as Figure 4 shown, the conductive wire CW3 and the conductive wire CW4 may respectively have an acute angle θ3 with respect to the outer surrounding portion OSP, and the conductive wire CW5 and the conductive wire CW6 may respectively have an acute angle θ4 with respect to the outer surrounding portion OSP, where the acute angle θ3 may be different from the acute angle θ4, but not limited thereto. In some embodiments, the conductive wires CW in the same group may be parallel to each other. For example, the conductive wire CW3 may be parallel to the conductive wire CW4, and the conductive wire CW5 may be parallel to the conductive wire CW6, but not limited thereto. Through the above design, the manufacturing difficulty of the conductive wires CW can be reduced while making the acute angles between different conductive wires CW and the outer surrounding portion OSP different.

[0071] The above characteristics regarding the acute angle between the conductive wires CW and the outer surrounding portion OSP can be applied to various embodiments and variant embodiments of the present invention.

[0072] According to this embodiment, the gate driving circuit GC disposed in the peripheral region PR may be partially arranged in an arc shape, but not limited thereto. Specifically, a part of the plurality of transistors in the gate driving circuit GC may be arranged in an arc shape. In detail, as Figure 4As shown, the setting area of the gate driving circuit GC (or the transistors in the gate driving circuit GC) may include a straight region LR and curved regions CUR on both sides of the straight region LR. In other words, the straight region LR may be connected between the two curved regions CUR. The transistors of the gate driving circuit GC arranged in the straight region LR may be arranged linearly, while the transistors of the gate driving circuit GC arranged in the curved regions CUR may be arranged in an arc. In this embodiment, the gate driving circuit GC in the curved region CUR may be defined, for example, in the following manner. First, an extension line EXL passing through the outer edge of the gate driving circuit GC arranged in the straight region LR may be defined, and the part of the gate driving circuit GC whose outer edge deviates from the extension line EXL may be regarded as the gate driving circuit GC in the curved region CUR. According to this embodiment, the transistors of the gate driving circuit GC arranged in the curved region CUR may be arranged along the arc edge of the outer surrounding part OSP, but not limited thereto. In this case, the range of the curved region CUR may be determined according to the position of the arc edge of the outer surrounding part OSP. The curved region CUR may be closer to the corner COR of the substrate SB than the straight region LR. In other words, the part of the transistors in the gate driving circuit GC close to the corner COR of the substrate SB may be arranged in an arc. It should be noted that although not mentioned above, Figure 2 it is also shown that the design in which the gate driving circuit GC can be arranged along the arc edge of the outer surrounding part OSP. In addition, in this embodiment, as Figure 4 shown, in the gate driving circuit GC, a distance D3 may exist between two adjacent transistors arranged in the straight region LR, and a distance D4 may exist between two adjacent transistors arranged in the curved region CUR, where the distance D3 and the distance D4 may be different. For example, the distance D3 may be less than the distance D4, but not limited thereto. The distance D3 may be defined as the minimum distance between two adjacent transistors in the straight region LR, and the distance D4 may be defined as the minimum distance between two adjacent transistors in the curved region CUR, but not limited thereto. In other words, the density of the transistors in the gate driving circuit GC in the straight region LR may be greater than that in the curved region CUR. Through the above arrangement design and distance design of the gate driving circuit GC, the spatial configuration of the electronic device ED can be improved. The arrangement design and distance design of the gate driving circuit GC here can be applied to various embodiments and variant embodiments of the present invention.

[0073] Please refer to Figure 5 , Figure 5A top view schematic diagram of the electronic device according to the third embodiment of the present invention. In this embodiment, as described above, the sensing layer SEL may not be disposed corresponding to the foldable sub-region FR in the active region AR. Specifically, the electronic device ED may include two sensing layers SEL, which are respectively disposed on both sides of the foldable sub-region FR, but not limited thereto. In this case, in the top view direction of the electronic device ED, a part of the outer surrounding portion OSP may overlap the sensing layer SEL, and another part of the outer surrounding portion OSP may be outside the sensing layer SEL, or may not overlap the sensing layer SEL. Specifically, a part of the outer surrounding portion OSP corresponding to the foldable sub-region FR may be outside the sensing layer SEL.

[0074] In this embodiment, the conductive layer COL may span the foldable sub-region FR, or rather, a part of the conductive layer COL may be disposed corresponding to the foldable sub-region FR. Specifically, the outer surrounding portion OSP of the conductive layer COL may partially correspond to the foldable sub-region FR. For example, as Figure 5 shown. The outer surrounding portion OSP may extend in the flat sub-region ER and may span the foldable sub-region FR, but not limited thereto. The connection portion CP of the conductive layer COL may span the foldable sub-region FR. Specifically, as Figure 5 shown, the connection portion CP1 connecting between the pattern portions PP located on both sides of the foldable sub-region FR may span the foldable sub-region FR. In other words, the conductive layer COL may include a pattern portion PP overlapping a first transistor (i.e., the transistor of the driving circuit DU) on one side of the foldable sub-region FR, another pattern portion PP overlapping another first transistor (i.e., the transistor of the driving circuit DU) on the other side of the foldable sub-region FR, and a connection portion CP1 connecting the pattern portion PP and the other pattern portion PP, wherein the connection portion CP1 may span the foldable sub-region FR. In some embodiments, the connection portion CP2 connecting the pattern portion CP2 and the outer surrounding portion OSP may overlap the foldable sub-region FR. In some embodiments, the pattern portion PP may overlap the foldable sub-region FR.

[0075] According to this embodiment, the part of the conductive layer COL corresponding to the foldable sub-region FR may include openings. In detail, as Figure 5 shown, the part of the outer surrounding portion OSP of the conductive layer COL corresponding to the foldable sub-region FR may include at least one opening OP5, or rather, the outer surrounding portion OSP includes an opening OP5 spanning the foldable sub-region FR. Through the above design, the flexibility of the conductive layer COL can be improved. It should be noted that although Figure 5Not shown, in the top view direction of the electronic device, a connection part CP of the conductive layer COL that partially overlaps the foldable sub-region FR may include at least one opening within the foldable sub-region FR, or in other words, the connection part CP may include an opening corresponding to the foldable sub-region FR. In some embodiments, a pattern part PP that overlaps the foldable sub-region FR may include an opening corresponding to the foldable sub-region FR.

[0076] According to this embodiment, the thickness of the part of the conductive layer COL outside the foldable sub-region FR may be different from the thickness of the part of the conductive layer COL within the foldable sub-region FR. The above-mentioned "part of the conductive layer COL outside the foldable sub-region FR" may, for example, include the part of the conductive layer COL in the flat sub-region ER. Specifically, the thickness of the part of the conductive layer COL in the flat sub-region ER may be greater than the thickness of the part of the conductive layer COL in the foldable sub-region FR. For example, although Figure 5 Not shown, the thickness of the part of the outer surrounding part OSP in the flat sub-region ER may be greater than the thickness of the part of the outer surrounding part OSP in the foldable sub-region FR. In addition, the thickness of the part of the connection part CP that overlaps the foldable sub-region FR in the flat sub-region ER may be greater than the thickness of the part of the connection part CP in the foldable sub-region FR. In this embodiment, the ratio of the thickness of the part of the conductive layer COL in the flat sub-region ER to the thickness of the part of the conductive layer COL in the foldable sub-region FR may range from 1.1 to 2 (i.e., 1.1 ≤ ratio ≤ 2), but is not limited thereto. In some embodiments, the range of the above ratio may be from 1.2 to 1.9 (i.e., 1.2 ≤ ratio ≤ 1.9). In some embodiments, the range of the above ratio may be from 1.3 to 1.8 (i.e., 1.3 ≤ ratio ≤ 1.8). The design of having different thicknesses of the conductive layer COL in different regions may be achieved, for example, by forming grooves in the part of the conductive layer COL corresponding to the foldable sub-region FR, but is not limited thereto. The thickness design of the conductive layer COL may reduce the possibility of the conductive layer COL breaking when the electronic device ED is bent, thereby improving the flexibility of the conductive layer COL. The opening design and thickness design of the conductive layer COL may be applied to various embodiments and variant embodiments of the present invention.

[0077] According to this embodiment, in the top view direction of the electronic device ED, the setting range of the conductive layer COL can generally correspond to the setting range of the sensing layer SEL. The setting range of the conductive layer COL can be, for example, the range surrounded by the outer surrounding portion OSP. The setting range of the sensing layer SEL can be, for example, the range surrounded by the outer edge of the sensing layer SEL. Specifically, in the top view direction of the electronic device ED, the ratio of the area of the overlapping part of the setting range of the conductive layer COL to the area of the setting range of the sensing layer SEL can be greater than or equal to 0.8, but not limited thereto. In other words, the area of the region occupied by the setting range of the conductive layer COL in the setting range of the sensing layer SEL can be at least 80% of the area of the setting range of the sensing layer SEL. In some embodiments, the setting range of the conductive layer COL can be smaller than the setting range of the sensing layer SEL. For example, the setting range of the conductive layer COL can be located within the setting range of the sensing layer SEL, but not limited thereto. Through the above design, the possibility of electrostatic discharge caused by the sensing layer SEL can be reduced by the conductive layer COL.

[0078] According to this embodiment, in the conductive layer COL, the width of the outer surrounding portion OSP can be greater than the width of the connecting portion CP (i.e., connecting portion CP2) connected between the pattern portion PP and the outer surrounding portion OSP, but not limited thereto. For example, as Figure 5 shown, the outer surrounding portion OSP can have a width W3, where the width W3 can be greater than the width of the connecting portion CP2 connected between the pattern portion PP and the outer surrounding portion OSP, that is, the above-mentioned width W1 and width W2. In other words, the width W3 can be greater than the width W1, and the width W1 can be greater than the width W2. It should be noted that the width W3 can also be greater than the width of other connecting portions CP2 connected between the pattern portion PP and the outer surrounding portion OSP, and is not limited to the above widths. In some embodiments, the width W3 of the outer surrounding portion OSP can also be greater than the width of the connecting portion CP1 connected between the pattern portions PP. Through the above width design, the anti-electrostatic discharge effect of the conductive layer COL can be improved.

[0079] Please refer to Figure 6 , Figure 6 which is a partial top view schematic diagram of the electronic device according to the fourth embodiment of the present invention. Figure 6 It shows the top view structure of a part of the electronic device ED adjacent to the outer surrounding portion OSP of the conductive layer COL. In addition, Figure 6 the pattern design of the shown conductive layer COL can be different from the pattern design of the conductive layer COL in the above embodiment, and the patterns of the conductive layer COL in each embodiment can be applied to each other. According to this embodiment, as Figure 6As shown, the electronic device ED may include a transistor T3 disposed within the active region AR and adjacent to the outer surrounding portion OSP of the conductive layer COL, and a transistor T2 disposed within the peripheral region PR and adjacent to the outer surrounding portion OSP of the conductive layer COL, wherein the transistor T3 may be electrically connected to the transistor T2 (e.g., via a wire CW). The above-mentioned transistor T3 may be a transistor of the driving circuit DU, and the transistor T2 may be a transistor in the gate driving circuit GC that is electrically connected to the transistor T3. It should be noted that for simplicity of the drawings, Figure 6Details of the electrical connection relationship between some transistors of the gate driving circuit GC and some transistors of the driving circuit DU are not shown. In this embodiment, "the transistor T3 is adjacent to the outer surrounding part OSP" may mean that there are no other transistors of the driving circuit DU between the transistor T3 and the outer surrounding part OSP. Similarly, "the transistor T2 is adjacent to the outer surrounding part OSP" may mean that there are no other transistors of the gate driving circuit GC between the transistor T2 and the outer surrounding part OSP. For example, the transistor T3 may be the transistor closest to the outer surrounding part OSP in one driving circuit DU among a plurality of driving circuits DU adjacent to the outer surrounding part OSP, and the transistor T2 in the gate driving circuit GC may be electrically connected to the transistor T3 and may be adjacent to the outer surrounding part OSP. According to this embodiment, there may be a first distance B1 between the outer surrounding part OSP and the transistor T3, and there may be a second distance B2 between the outer surrounding part OSP and the transistor T2, where the ratio of the second distance B2 to the first distance B1 may be greater than or equal to 0.8 and less than or equal to 10 (i.e., 0.8 ≤ B2 / B1 ≤ 10). The above-mentioned first distance B1 may be defined as the minimum distance between the outer surrounding part OSP and the channel region (such as the above-mentioned channel region CR) of the transistor T3, and the above-mentioned second distance B2 may be defined as the minimum distance between the outer surrounding part OSP and the channel region of the transistor T2. For example, the first distance B1 may be the distance between the outer surrounding part OSP and the channel region of the transistor T3 in the direction X, and the second distance B2 may be the distance between the outer surrounding part OSP and the channel region of the transistor T2 in the same direction X, but not limited thereto. In some embodiments, the ratio of the second distance B2 to the first distance B1 may be greater than 1 and less than or equal to 5 (i.e., 1 < B2 / B1 ≤ 5). In this case, the first distance B1 may be less than the second distance B2, that is, the outer surrounding part OSP may be closer to the driving circuit DU than to the gate driving circuit GC. In other words, the above ratio can be used to describe the relationship between the distances of two transistors electrically connected to each other and located on both sides of the outer surrounding part OSP from the outer surrounding part OSP. In some embodiments, the above ratio can be used to describe the distance relationship between a transistor adjacent to the outer surrounding part OSP in the driving circuit DU and another transistor adjacent to the outer surrounding part OSP in the gate driving circuit GC, where the transistor may not be electrically connected to the other transistor. Through the above distance design, the anti-static discharge effect of the conductive layer COL can be improved.In summary, in this embodiment, the electronic device ED may include a first transistor (i.e., the transistor T3 described above) disposed in the active region AR and a second transistor (i.e., the transistor T2 described above) disposed in the peripheral region PR and electrically connected to the first transistor. The first transistor and the second transistor are disposed adjacent to the outer surrounding portion OSP, and the ratio of the second distance between the outer surrounding portion OSP and the second transistor to the first distance between the outer surrounding portion OSP and the first transistor may fall within the above range. It should be noted that the above range of the distance ratio can be applied to another first transistor adjacent to the outer surrounding portion OSP in the electronic device ED and another second transistor adjacent to the outer surrounding portion OSP and electrically connected to the other first transistor, and is not limited to Figure 6 the illustrated transistors T2 and T3. The above distance ratio relationship can be applied to various embodiments and variant embodiments of the present invention.

[0080] In addition, in this embodiment, the transistors in the gate driving circuit GC may be disposed in the peripheral region PR in a multi-row manner. For example, as Figure 6 illustrated, the transistors in the gate driving circuit GC may be disposed in the peripheral region PR in a two-row manner, but not limited thereto. In this embodiment, there may be a pitch PT1 between one row of the transistors in the gate driving circuit GC, and there may be a pitch PT2 between the other row of the transistors in the gate driving circuit GC, where the pitch PT1 may be different from the pitch PT2, but not limited thereto.

[0081] Please refer to Figure 7 , Figure 7 which is a partial top view schematic diagram of the electronic device according to the fifth embodiment of the present invention. Specifically, Figure 7 shows the top view structure of a part of the arc edge of the electronic device ED adjacent to the outer surrounding portion OSP. In this embodiment, the transistors (such as the transistor T4) of the gate driving circuit GC disposed in the peripheral region PR and adjacent to the arc edge of the outer surrounding portion OSP may be divided into a plurality of groups GP, such as group GP1, group GP2, and group GP3, where the plurality of groups GP may be arranged along the arc edge of the outer surrounding portion OSP. Specifically, among the transistors of the gate driving circuit GC adjacent to the arc edge of the outer surrounding portion OSP, a plurality of transistors arranged in the same direction may be regarded as the transistors in the same group GP. In other words, the transistors in each group GP may be arranged in a specific direction, but not limited thereto. In this embodiment, Figure 2 the illustrated square box representing the gate driving circuit GC may include at least one transistor. It should be noted that although Figure 7 not shown, the straight region LR (such as Figure 4The transistors of the gate driving circuit GC in the curved region CUR (as shown in FIG. 1 ) can be arranged in the same manner as above, but the present invention is not limited thereto. In the present embodiment, the number of transistors in each group GP can be the same or different, but the present invention is not limited thereto. Figure 4 The distance D4 between two adjacent transistors within the Figure 4 ) may be the minimum distance between two groups GP, but is not limited thereto. In other words, the distance D4 may be the minimum distance between two transistors that are in two adjacent groups GP and closest to each other. In some embodiments, the distance D4 may be the minimum distance between two adjacent transistors in the same group GP. It should be noted that, in some embodiments, the distance D3 may be the minimum distance between two groups GP disposed in the straight line region LR. In addition, in this embodiment, Figure 7 As shown, the conductive line CW connecting the pattern portion PP and the transistors in the group GP (e.g., transistor T5) at one end of the gate drive circuit GC may first extend substantially along the arc edge of the outer surrounding portion OSP, and then extend into the active region AR and be electrically connected to the transistors in the drive circuit DU. It should be noted that, in order to simplify the drawings, Figure 7 The details of the electrical connection relationship between all transistors of the gate driver circuit GC and all transistors of the driver circuit DU are not shown. Specifically, each transistor in the gate driver circuit GC can be electrically connected to at least one wire CW, and electrically connected to a transistor of the driver circuit DU through the wire CW. In other words, Figure 7 One group GP shown may, for example, be electrically connected to the same number of conductive lines CW as the number of transistors in the group GP.

[0082] Please refer to Figure 8 , Figure 8 FIG. 6 is a top view of an electronic device according to a sixth embodiment of the present invention. Figure 8 Only the substrate SB, the sensing layer SEL and the conductive layer COL disposed on the substrate SB are shown, and the other elements and film layers can refer to the contents of the above embodiment. Figure 5 According to this embodiment, the pattern portion PP of the conductive layer COL may have different sizes in different regions. Figure 8 As shown, the pattern portion PP (e.g., pattern portion PP1) disposed in a region R1 may have a smaller size than other pattern portions PP, but is not limited thereto. The size of the pattern portion PP mentioned above may refer to the width, length or area of ​​the pattern portion PP, but is not limited thereto. It should be noted that Figure 8The size and position of the shown region R1 are only exemplary, and this embodiment is not limited thereto. Specifically, the size and position of the region R1 can be determined according to the specific electronic components of the electronic device ED. In this embodiment, the region R1 can correspond to the setting region of the sensing element of the electronic device ED, but is not limited thereto. The sensing element can include a light sensing element or other suitable sensing elements. For example, the region R1 can correspond to the setting region of the light sensing element (such as a camera, but not limited thereto) of the electronic device ED, but is not limited thereto. The light sensing element can include any suitable element that can sense visible light or infrared light, but is not limited thereto. In other words, the size of the pattern portion PP corresponding to the setting region of the optical element can be smaller than the size of other pattern portions PP. In some embodiments, the region R1 can correspond to the setting region of any suitable element of the electronic device ED. Through the above design, the influence of the pattern portion PP of the conductive layer COL on the electronic components of the electronic device ED can be reduced, thereby improving the performance of the electronic device ED. In some embodiments, the pattern portion PP disposed within the region R1 can have a larger size compared to other pattern portions. In some embodiments, the pattern portion PP disposed within the region R1 and other pattern portions PP can have different shapes.

[0083] In addition, in this embodiment, the pattern portion PP disposed in the active region AR can have different densities in different regions. Specifically, the density of the pattern portion PP that is farther away from the peripheral region PR (or, in other words, farther away from the outer surrounding portion OSP) can be greater than the density of the pattern portion PP that is closer to the outer surrounding portion OSP. Specifically, as Figure 8As shown, the portion of the pattern part PP located within a first unit area UA1 may have a first density, and another portion of the pattern part PP located within a second unit area UA2 may have a second density. The first unit area UA1 is closer to the peripheral region PR than the second unit area UA2, and the first density may be less than the second density. The above-mentioned "the first unit area UA1 is closer to the peripheral region PR than the second unit area UA2" may mean that the minimum distance between the first unit area UA1 and the peripheral region PR is less than the minimum distance between the second unit area UA2 and the peripheral region PR, but is not limited thereto. The first unit area UA1 and the second unit area UA2 may have any suitable sizes, such as 30μm * 30μm, 50μm * 50μm, or 1 millimeter (mm) * 1mm, but are not limited thereto. The above-mentioned first density may be defined as the ratio of the total area of the portion of the pattern part PP within the first unit area UA1 to the first unit area UA1, that is, the area proportion of the pattern part PP within the first unit area UA1. The second density may be defined in the same manner, so it will not be elaborated here. In this embodiment, the pattern part PP having different densities in different regions may be achieved, for example, by not arranging the pattern part PP at a specific position, but is not limited thereto. Specifically, the density of the pattern part PP within the first unit area UA1 may be made smaller by not arranging the pattern part PP adjacent to the arcuate edge of the outer surrounding part OSP. For example, in this embodiment, in the top view direction of the electronic device ED, the portion of the pattern part PP adjacent to the peripheral region PR may be arranged in a stepped manner, but is not limited thereto.

[0084] It should be noted that the shapes and positions of the above-mentioned first unit area UA1 and second unit area UA2 are only exemplary, and the present invention is not limited thereto. In this embodiment, the second unit area UA2 can be defined as a unit area of any size or shape falling within the central region of the conductive layer COL, and the first unit area UA1 can be defined as a unit area of any size or shape falling within the edge region of the conductive layer COL. In other words, the density of the pattern portion PP provided in the central region of the conductive layer COL can be greater than the density of the pattern portion PP provided in the edge region of the conductive layer COL. Specifically, the minimum rectangle RC surrounding the conductive layer COL can be defined first. For example, the minimum rectangle RC can be the minimum rectangle surrounding the outer surrounding portion OSP of the conductive layer COL. Then, the center point CT where the two diagonal lines of the minimum rectangle RC intersect can be defined. Among them, a unit area whose range includes the center point CT can be regarded as a unit area falling within the central region of the conductive layer COL, that is, the second unit area UA2, and a unit area whose range does not include the center point CT can be regarded as a unit area falling within the edge region of the conductive layer COL, that is, the first unit area UA1. In other embodiments, the first unit area UA1 and the second unit area UA2 can be defined by other suitable means. In some embodiments, the density of the pattern portion PP can decrease as the distance between the pattern portion PP and the peripheral region PR becomes smaller, and it is not limited to Figure 8 the structure shown. Through the above design, the antistatic discharge effect of the conductive layer COL can be improved. The design of the above-mentioned pattern portion PP can be applied to various embodiments and variant embodiments of the present invention.

[0085] Please refer to Figure 9 , Figure 9 which is a partial cross-sectional schematic diagram of an electronic device according to the seventh embodiment of the present invention. In this embodiment, the electronic device ED can include a double-substrate structure. For example, as Figure 9 shown, the electronic device ED can include a substrate SB1, a substrate SB2, and an adhesive layer AD3 provided between the substrate SB1 and the substrate SB2, but it is not limited thereto. The materials of the substrate SB1 and the substrate SB2 can refer to the materials of the above-mentioned substrate SB, so they will not be described in detail. Specifically, the substrate SB1 can be attached to the substrate SB2 through the adhesive layer AD3, but it is not limited thereto. It should be noted that although Figure 9 not shown, the electronic device ED of this embodiment may further include components and film layers such as a sensing layer SEL, an electronic unit IC1, and an electronic unit IC2 provided under the substrate SB1, which can refer to Figure 1A the structure shown, but it is not limited thereto.

[0086] According to this embodiment, the conductive layer COL provided on the substrate SB1 and the substrate SB2 can include a multi-layer structure. For example, as Figure 9As shown, the conductive layer COL of this embodiment may include a sub-conductive layer COL1 disposed on the substrate SB2 and a sub-conductive layer COL2 disposed on the sub-conductive layer COL1, but is not limited thereto. Specifically, the electronic device ED may include an insulating layer I10 disposed on the substrate SB2, a sub-conductive layer COL1 disposed on the insulating layer I10, an insulating layer I11 disposed on the sub-conductive layer COL1, a sub-conductive layer COL2 disposed on the insulating layer I11, and an insulating layer I12 disposed on the sub-conductive layer COL2. The sub-conductive layer COL2 may be electrically connected to the sub-conductive layer COL1 through a via hole penetrating the insulating layer I11. In this embodiment, the sub-conductive layer COL1 may be disposed in the active region AR, and the sub-conductive layer COL2 may be disposed in the peripheral region PR, but is not limited thereto. In this case, when the conductive layer COL of this embodiment extends to the peripheral region PR, it may transfer from the sub-conductive layer COL1 to the sub-conductive layer COL2. It should be noted that the conductive layer COL of this embodiment may include more sub-conductive layers that are electrically connected to each other and is not limited to Figure 9 as shown. In this embodiment, the sub-conductive layer COL1 may form, for example, a pattern portion PP, a connection portion CP, and an outer surrounding portion OSP of the conductive layer COL, and the conductive layer COL may transfer to the sub-conductive layer COL2 in the bonding sub-region BR to be electrically connected to an electronic component (such as the above-mentioned electronic unit IC2). In this case, the sub-conductive layer COL2 may form, for example, Figure 2 the connection portion CP3 shown. In some embodiments, the sub-conductive layer COL1 may form the pattern portion PP and the connection portion CP of the conductive layer COL, and the sub-conductive layer COL2 may form the outer surrounding portion OSP of the conductive layer COL. In this case, the connection portion (i.e., the connection portion CP2) connecting the pattern portion PP and the outer surrounding portion OSP in the conductive layer COL may transfer from the sub-conductive layer COL1 to the sub-conductive layer COL2 to be electrically connected to the outer surrounding portion OSP in the sub-conductive layer COL2. As Figure 9 shown, the electronic device ED may further include an insulating layer I13 and an insulating layer I14 disposed between the insulating layer I12 and the driving circuit DU, but is not limited thereto. The design of the conductive layer COL of this embodiment can be applied to various embodiments and variant embodiments of the present invention.

[0087] Please refer to Figure 10 , Figure 10A cross-sectional schematic view of an electronic device according to an eighth embodiment of the present invention. According to this embodiment, the electronic device ED may include a double-substrate structure, for example, including the above-mentioned substrate SB1 and substrate SB2, and the conductive layer COL may be disposed between the substrate SB1 and the substrate SB2, but not limited thereto. In this case, since the conductive layer COL includes a patterned film layer, the substrate SB1 may be connected to the substrate SB2. In some embodiments, the substrate of the electronic device ED may include a multi-layer structure, and the conductive layer COL may be disposed between any two layers of the multi-layer structure of the substrate. The conductive layer COL may be electrically connected to other electronic components, such as the electronic unit IC2, through the conductive element CEL passing through the substrate SB1, but not limited thereto.

[0088] In addition, in this embodiment, a driving circuit DU of the electronic device ED may include a transistor T6 and a transistor T7 disposed on a substrate SB2, where the transistor T6 may be electrically connected to the transistor T7, and the transistor T7 may be electrically connected to an electronic component ME (such as a light-emitting unit LU). Specifically, the electronic device ED may include a semiconductor layer SM1 disposed on the substrate SB2, an insulating layer IL4 disposed on the semiconductor layer SM1, a conductive layer M5 disposed on the insulating layer IL4, an insulating layer IL5 disposed on the conductive layer M5, a conductive layer M6 disposed on the insulating layer IL5, an insulating layer IL6 disposed on the conductive layer M6, a conductive layer M7 disposed on the insulating layer IL6, an insulating layer IL7 disposed on the conductive layer M7, a semiconductor layer SM2 disposed on the insulating layer IL7, an insulating layer IL8 disposed on the semiconductor layer SM2, a conductive layer M8 disposed on the insulating layer IL8, an insulating layer IL9 disposed on the conductive layer M8, a conductive layer M9 disposed on the insulating layer IL9, and an insulating layer IL10 disposed on the conductive layer M9. The semiconductor layer SM1 includes a source region SR1, a channel region CR1, and a drain region DR1 of the transistor T6, the conductive layer M5 forms a gate electrode GE1 of the transistor T6, and the conductive layer M7 forms a source electrode SOE1 and a drain electrode DOE1 of the transistor T6 that are electrically connected to the source region SR1 and the drain region DR1, respectively. The transistor T7 includes the semiconductor layer SM2, the conductive layer M6 forms a gate electrode GE2 of the transistor T7, and the conductive layer M8 forms a source electrode SOE2 and a drain electrode DOE2 that are electrically connected to the semiconductor layer SM2 of the transistor T7. The drain electrode DOE1 of the transistor T6 may be electrically connected to the conductive layer M6, or rather, electrically connected to the gate electrode GE2 of the transistor T7. An electrode E1 of the electronic component ME may be electrically connected to the conductive layer M9 and electrically connected to the conductive layer M8 through the conductive layer M9, for example, electrically connected to the drain electrode DOE2 of the transistor T7. In other words, the transistor T6 may serve as a switching element, and the transistor T7 may serve as a driving element, but not limited thereto. The semiconductor layer SM1 may include low-temperature polycrystalline silicon (LTPS), and the semiconductor layer SM2 may include a metal oxide, such as indium gallium zinc oxide (IGZO), but not limited thereto. In this embodiment, a patterned portion PP of the conductive layer COL may overlap one of the transistor T6 and the transistor T7. Specifically, the patterned portion PP may overlap the transistor T6 and not overlap the transistor T7, but not limited thereto. It should be noted that the driving circuit DU may further include other transistors and is not limited to the above-mentioned transistors T6 and T7.

[0089] As Figure 10As shown, the electronic device ED of this embodiment may further include an insulating layer IL1, an insulating layer IL2, and an insulating layer IL3 disposed between the transistor T6 and the substrate SB2, but is not limited thereto. The insulating layer IL1, the insulating layer IL2, and the insulating layer IL3 include, for example, an inorganic insulating material, but are not limited thereto.

[0090] The features of the electronic component ME and the touch structure TS of the electronic device ED may be referred to Figure 1B and the above, so they will not be elaborated here. As Figure 10 shown, the electronic device ED of this embodiment may include a black matrix layer BM and an optical layer LCL disposed on the touch structure TS, wherein the black matrix layer BM may include a sub-black matrix layer BM1 and a sub-black matrix layer BM2 disposed on the sub-black matrix layer BM1. Specifically, the sub-black matrix layer BM1 is disposed on the insulating layer I8 of the touch structure TS and includes an opening (not labeled), the optical layer LCL is disposed in the opening of the sub-black matrix layer BM1, and the sub-black matrix layer BM2 is disposed between the optical layer LCLs. The electronic device ED may further include a cover layer CO and a hard coating layer HC disposed on the optical layer LCL, but is not limited thereto.

[0091] According to this embodiment, the electronic device ED may further include at least one opening penetrating at least one insulating layer in the electronic device ED. Specifically, the above opening may penetrate at least one inorganic insulating layer in the electronic device ED. For example, as Figure 10 shown, the electronic device ED may include an opening OP6 and an opening OP7, wherein the opening OP6 may pass through the insulating layer IL6, the insulating layer IL7, and the insulating layer IL8, and may expose the conductive layer M6; the opening OP7 may correspond to the opening OP6 and pass through the insulating layer IL5, the insulating layer IL4, the insulating layer IL3, the insulating layer IL2, the insulating layer IL1, and the substrate SB2, and expose the substrate SB1. In this case, the conductive layer M6 may be located between the opening OP6 and the opening OP7. The electronic device ED may further include an organic material OM filled in the opening OP6 and the opening OP7. In other words, a part of the above insulating layer may be removed first to form the opening OP6 and the opening OP7, and then the organic material OM may be filled in the opening OP6 and the opening OP7. In this embodiment, the opening OP6 and the opening OP7 may not be disposed corresponding to the conductive layer COL, and the opening OP7 may extend between the conductive layers COL. The above "the opening OP7 extends between the conductive layers COL" may mean that the opening OP7 extends at least to the surface on which the conductive layer COL is disposed, such as the surface of the substrate SB1. Specifically, the opening OP7 may at least penetrate the substrate SB2 and may be located between the pattern portions PP of the conductive layer COL. It should be noted that the structure of the opening penetrating the insulating layer in this embodiment is not limited to Figure 10As shown is limited. In some embodiments, the conductive layer COL can be disposed at any suitable position, and the electronic device ED can at least include an opening extending between the conductive layers COL, where the opening can be formed by removing a portion of at least one inorganic insulating layer, and the opening can be filled with an organic material OM. Through the above design, the possibility of damage to components and film layers (such as the conductive layer COL, transistor T6, transistor T7, etc.) in the electronic device ED can be reduced, thereby improving the reliability of the electronic device ED. The feature that the electronic device ED in this embodiment includes at least an opening extending between the conductive layers COL can be applied to the above embodiments and variant embodiments.

[0092] In summary, the present invention provides an electronic device, which includes a substrate, a conductive layer disposed on the substrate, and a transistor of a driving circuit disposed on the conductive layer and within an active region, where the conductive layer can reduce the possibility of damage to the transistor of the driving circuit due to electrostatic discharge, thereby improving the reliability of the electronic device.

[0093] The above are only embodiments of the present invention and are not used to limit the present invention. For those of ordinary skill in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An electronic device having an active region and a peripheral region adjacent to the active region, characterized in that, The electronic device includes: a substrate; a conductive layer disposed on the substrate; a first transistor disposed on the conductive layer and within the active region; a second transistor disposed on the substrate and within the peripheral region; and a wire electrically connecting between the first transistor and the second transistor; wherein, in a top view direction of the electronic device, the conductive layer includes an outer surrounding portion located within the peripheral region and between the first transistor and the second transistor, and the wire crosses over the outer surrounding portion and is electrically insulated from the outer surrounding portion.

2. The electronic device according to claim 1, wherein The first transistor and the second transistor are disposed adjacent to the outer surrounding portion. A first distance B1 exists between the outer surrounding portion and the first transistor, and a second distance B2 exists between the outer surrounding portion and the second transistor. The second distance B2 and the first distance B1 satisfy: 0.8 ≤ B2 / B1 ≤ 10.

3. The electronic device according to claim 2, wherein The first distance is less than the second distance.

4. The electronic device according to claim 1, characterized in that, In the top view direction of the electronic device, an acute angle between the wire and the outer surrounding portion is greater than 20 degrees.

5. The electronic device according to claim 1, wherein It further includes another first transistor disposed within the active region, another second transistor disposed within the peripheral region, and another wire electrically connecting between the another first transistor and the another second transistor, wherein the another wire crosses over the outer surrounding portion, and an acute angle between the wire and the outer surrounding portion is different from another acute angle between the another wire and the outer surrounding portion.

6. The electronic device according to claim 1, wherein The first transistor is included in a driving circuit and configured to drive an electronic unit within the active region, and the second transistor is included in a gate driving circuit.

7. The electronic device according to claim 1, characterized in that, The electronic device includes a plurality of second transistors disposed within the peripheral region, and the plurality of second transistors are arranged along an arc-shaped edge of the outer surrounding portion.

8. The electronic device according to claim 1, wherein The conductive layer includes a patterned portion and a connecting portion. The patterned portion overlaps the first transistor, the connecting portion connects the patterned portion and the outer surrounding portion, and a width of the outer surrounding portion is greater than a width of the connecting portion.

9. The electronic device according to claim 1, characterized in that, The peripheral region includes a bonding sub-region. The conductive layer includes a first connecting portion and a second connecting portion. The first connecting portion connects to a part of the outer surrounding portion adjacent to the bonding sub-region, the second connecting portion connects to another part of the outer surrounding portion relative to the first connecting portion, and a width of the first connecting portion is greater than a width of the second connecting portion.

10. The electronic device according to claim 1, wherein The peripheral region includes a bonding sub-region. The conductive layer includes a connecting portion that connects to a part of the outer surrounding portion adjacent to the bonding sub-region, and the connecting portion is configured to transmit a signal.

11. The electronic device according to claim 1, wherein The electronic device includes a plurality of first transistors disposed on the conductive layer and within the active region, wherein the conductive layer includes a plurality of pattern portions that respectively overlap the plurality of first transistors.

12. The electronic device according to claim 11, wherein A part of the plurality of pattern portions is located within a first unit area and has a first density, and another part of the plurality of pattern portions is located within a second unit area and has a second density. The first unit area is closer to the peripheral region than the second unit area, and the first density is less than the second density.

13. The electronic device according to claim 11, wherein In the top view direction of the electronic device, the plurality of pattern portions adjacent to the peripheral region are arranged in a stepped manner.

14. The electronic device according to claim 1, wherein The active region includes a foldable sub-region. The conductive layer includes a pattern portion overlapping the first transistor, another pattern portion overlapping another first transistor, and a connection portion connecting the pattern portion and the another pattern portion. In the top view direction of the electronic device, the connection portion straddles the foldable sub-region.

15. The electronic device according to claim 14, wherein The active region includes a flat sub-region adjacent to the foldable sub-region. The thickness of the connection portion in the foldable sub-region is less than the thickness of the connection portion in the flat sub-region.

16. The electronic device according to claim 14, wherein In the top view direction of the electronic device, the connection portion includes at least one opening within the foldable sub-region.

17. The electronic device according to claim 1, wherein It further includes a sensing layer disposed under the substrate. In the normal direction of the electronic device, there is a third distance D1 between the conductive layer and the first transistor, and a fourth distance D2 between the conductive layer and the sensing layer, and the third distance D1 is less than the fourth distance D2.

18. The electronic device according to claim 17, wherein The fourth distance D2 and the third distance D1 satisfy: 20 ≤ D2 / D1 ≤ 1000.

19. The electronic device according to claim 1, wherein It further includes a sensing layer disposed under the substrate. In the top view direction of the electronic device, a part of the outer surrounding portion overlaps the sensing layer, and another part of the outer surrounding portion is located outside the sensing layer.

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