Image sensor and manufacturing method thereof

Abstract

The embodiment of the invention provides an image sensor and a manufacturing method thereof. The image sensor achieves high pixel density by unloading a portion of the photodetector circuit to a device layer separate from the photodiode, thereby achieving high resolution. The photodetector uses a lateral overflow integrating capacitor and a dual conversion gain transistor to increase the dynamic range. The dynamic range is further increased by providing a high conversion gain mode in which the floating diffusion node is isolated from the second device layer and the wiring extending to the second device. This is accomplished by disposing a DCG transistor and a source follower in a first device layer having a photodiode, a pass gate, and a floating diffusion region. In a high conversion gain mode, isolating the floating diffusion node from wiring to the second device layer reduces the capacitance of the floating diffusion node in a high conversion amplifier mode, thereby increasing the dynamic range.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of semiconductors, and more particularly, to an image sensor and a method of manufacturing the same. Background Art

[0002] Many modern electronic devices (such as digital cameras, optical imaging devices, etc.) include image sensors. An image sensor includes an array of photosensitive regions, which serve as converters for converting light into charge. Examples of image sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. Compared with CCD image sensors, CMOS image sensors are favored for their low power consumption, small size, fast data processing speed, direct data output, and low manufacturing cost. Summary of the Invention

[0003] Embodiments of the present invention provide an image sensor, comprising: a first die, including a first semiconductor substrate and a first metal interconnect structure; a second die, including a second semiconductor substrate and a second metal interconnect structure, wherein the second die is bonded to the first die; and a photodetector, including a photosensitive region, a floating diffusion node, a transfer gate, a source follower, a row selection transistor, a first dual conversion gain transistor, and a reset transistor; wherein the photosensitive region, the transfer gate, the source follower, and the first dual conversion gain transistor are on the first die, and the row selection transistor is on the second die; and the source follower is connected to the row selection transistor through the first metal interconnect structure and the second metal interconnect structure.

[0004] Another embodiment of the present invention provides an image sensor, comprising: a first die, including a first substrate and a first metal interconnect structure; a second die, including a second substrate and a second metal interconnect structure, wherein the second die is bonded to the first die; and a photodetector, including a photosensitive region in the first substrate, a floating diffusion node, a transfer gate between the floating diffusion node and the photosensitive region, a first transistor on the first die, and a second transistor on the second die; wherein when the first transistor is open, the floating diffusion node is restricted within the first die.

[0005] Another embodiment of the present invention provides a method of manufacturing an image sensor, the method comprising: providing a first substrate; forming a photodiode and a floating diffusion region in the first substrate; forming a transfer gate, a source follower, and a first dual conversion gain transistor on the first substrate, wherein the transfer gate is configured to selectively couple the photodiode to the floating diffusion region; forming a first metal interconnect structure on the first substrate, wherein the first metal interconnect structure couples the floating diffusion region to the gate of the source follower and the source side of the first dual conversion gain transistor; providing a second substrate; forming a row selection transistor on the second substrate; forming a second metal interconnect structure above the second substrate; and bonding the first substrate to the second substrate, wherein the bonding couples the drain side of the row selection transistor to the source side of the source follower. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A three-layer device according to some embodiments is shown.

[0008] Figure 2 A circuit diagram of an image sensor according to a first embodiment is provided.

[0009] Figure 3 A plan view of a first device layer in an image sensor according to a first embodiment is shown.

[0010] Figure 4 A perspective view corresponding to FIG. 3 is provided.

[0011] Figure 5 A plan view of a second device layer in an image sensor according to a first embodiment is shown.

[0012] Figure 6 A perspective view corresponding to FIG. 5 is provided.

[0013] Figure 7 A perspective view depicting the first device layer and the second device layer according to a first embodiment is provided.

[0014] Figure 8 A circuit diagram of an image sensor according to a second embodiment is provided.

[0015] Figure 9 A plan view of a first device layer in an image sensor according to a second embodiment is shown.

[0016] Figure 10 Shows a plan view of a second device layer in an image sensor according to a second embodiment.

[0017] Figure 11 Provides a circuit diagram of an image sensor according to a third embodiment.

[0018] Figure 12 Shows a plan view of a first device layer in an image sensor according to a third embodiment.

[0019] Figure 13 Shows a plan view of a second device layer in an image sensor according to a third embodiment.

[0020] Figures 14 to 21 Provides a series of cross-sectional views showing an embodiment of a manufacturing process applied to the first device layer.

[0021] Figure 22 Provides a plan view corresponding to Figure 21 a relative one.

[0022] Figures 23 to 32 Provides a series of cross-sectional views showing an embodiment of a manufacturing process applied to the second device layer.

[0023] Figure 33 Provides a plan view corresponding to Figure 32 a relative one.

[0024] Figures 34A to 39 Provides a series of cross-sectional views showing the combination of the first, second, and third device layers according to an embodiment and further manufacturing applied to the first device layer.

[0025] Figure 40 Is a flowchart of a process according to some embodiments. Detailed Description

[0026] The present invention provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming the first component above or on the second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0027] Moreover, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component shown in the figures to another (or other) element or component. In addition to the orientation shown in the figures, the spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly as well.

[0028] A type of CMOS image sensor has a photodetector array, and each photodetector array includes at least one photosensitive region within a semiconductor substrate, a transfer gate, a floating diffusion node, a source follower, a row selection transistor, and a reset transistor. When the reset transistor is closed, the floating diffusion node is charged to a reference voltage. Light is converted to charge within the photosensitive region. The charge accumulates until the transfer gate is closed, allowing it to flow to the floating diffusion node. The charge changes the floating diffusion node voltage. The floating diffusion node is coupled to the gate electrode of the source follower. The source follower is connected in series with the row selection transistor. When the row selection transistor is closed, current flows through the source follower and the row selection transistor. The magnitude of this current depends on the floating diffusion node voltage applied to the gate electrode of the source follower. The current is detected and used to infer the amount of charge transferred to the floating diffusion node, which in turn reflects the amount of radiation incident on the photosensitive region during the sampling interval.

[0029] Conversion gain is an important parameter in the above type of CMOS image sensor. The conversion gain is related to the capacitance of the floating diffusion node. The capacitance of the floating diffusion node includes contributions from the floating diffusion region, which is the drain region of the transfer gate, the source region of the reset transistor, the gate electrode of the source follower, and the wiring connecting these structures. If the capacitance of the floating diffusion node is too low (conversion gain too high) for a given illumination condition and sampling rate, the photodetector will experience saturation, thus losing the variation of high-end light intensity. If the capacitance is too high (conversion gain too low), there will be too much noise in the voltage signal, and the variation of low-end light intensity will also be lost.

[0030] One way to expand the effective illumination condition range (increase the dynamic range) of a photodetector is to add a dual conversion gain (DCG) transistor to the photodetector circuit. The DCG transistor allows the photodetector to switch between a low conversion gain mode and a high conversion gain mode. In the low conversion gain mode, the DCG transistor is closed, enabling a capacitor (commonly referred to as a lateral overflow integration capacitor) to be coupled to the floating diffusion node through the DCG transistor. In the high conversion gain mode, the DCG transistor is open, isolating the lateral overflow integration capacitor (LOFIC) from the floating diffusion node.

[0031] Another important performance parameter of a CMOS image sensor is resolution. High resolution is achieved through high pixel density. The chip area occupied by transistors in the photodetector circuit limits the pixel density. A way to overcome this limitation is to use a two - or three - layer device layer approach, where the photodetector transistors (except for the transfer gates) and the LOFIC are disposed on a second die. The drawback of this method is that even in the high conversion gain mode, the wiring connecting the floating diffusion node to the second die increases the capacitance of the floating diffusion node. The additional capacitance reduces the conversion gain, thereby increasing noise and reducing the dynamic range.

[0032] According to the present disclosure, using a two - or three - layer device layer system solves the problem of providing high resolution and high dynamic range, where in the high conversion gain mode, the wiring of the floating diffusion node is isolated from the second die. This is achieved by arranging the DCG transistor and the source follower together with the photosensitive region, transfer gate, and floating diffusion region on a first die. Some or all of the remaining photodetector circuit components are disposed on the second die, thus still enabling high pixel density.

[0033] In some embodiments, the DCG transistor, source follower, and other photodetector circuit components are shared, so there is one DCG transistor and one source follower for every four transfer gates and photosensitive regions. This sharing method can increase the pixel density. The shared arrangement requires combining the floating diffusion regions corresponding to four transfer gates into one floating diffusion node. This seemingly increases the capacitance of the floating diffusion node. However, under very low light conditions, when high conversion gain is crucial, four photodetector pixels can operate as one large pixel. This operating mode increases the full well capacity and provides a higher dynamic range.

[0034] The conversion gain of the image sensor according to the present disclosure may have a very large difference between the low conversion gain mode and the high conversion gain mode. In some embodiments, the photodetector includes a second DCG transistor and a second LOFIC, such that an intermediate conversion gain mode may exist between the low conversion gain mode and the high conversion gain mode. The intermediate conversion gain mode can be used to provide a smoother transition from the low conversion gain mode to the high conversion gain mode. Alternatively, the intermediate conversion gain mode can replace the high conversion gain mode, and the high conversion gain module can become a very high conversion gain module, thereby further increasing the dynamic range.

[0035] In some embodiments, the source follower and the dual conversion gain transistor are arranged in a row. Four photosensitive regions sharing the source follower and the dual conversion gain transistor can be arranged two on each side of the row. In some embodiments, each pair of transmission gates shares a floating diffusion region, which is a substrate region on the drain side of the corresponding transmission gate. The DCG transistor and the source follower can be isolated from the floating diffusion region and the photosensitive region by a shallow trench isolation structure. The wiring associated with the floating diffusion node may be limited to four contact plugs and the interconnect wiring in the metallization layer closest to the substrate (M1 metallization layer). The four contact plugs can include contact plugs for each of the two floating diffusion regions, a contact plug for the gate electrode of the source follower, and a contact plug for the source region of the DCG transistor. All these contact plugs can be coupled to two short wiring segments in the M1 metallization layer. Wiring in the M2 and higher metallization layers can be avoided. This structure limits the wiring connected to the floating diffusion node in the high conversion gain mode, thereby increasing the dynamic range.

[0036] The first DCG and the second DCG can be connected in series, and the first LOFIC can be connected in parallel with the second DCG to the first DCG. Closing the first DCG adds the first LOFIC to the floating diffusion node. In addition to the first DCG, closing the second DCG brings the second LOFIC into the floating diffusion node. In some embodiments, the first LOFIC is located on the first die, and the second LOFIC is on the second die. This arrangement allows each of the first LOFIC and the second LOFIC to have a relatively large area. Both the first LOFIC and the second LOFIC can be three-dimensional metal-insulator-metal (3DMIM) capacitors.

[0037] In some embodiments, each photodetector includes two connectors between a first die and a second die. The first connector can be between a DCG transistor on the first die and a LOFIC or reset transistor on the second die. The second connector can be between a source follower on the first die and a row select transistor on the second die. In some embodiments, the first and second connectors form a first row, and each first row includes alternating first and second connectors extending across the photodetector array. The first and second connectors are formed by pads on the first die. In some embodiments, pseudo-contact pads are disposed in a second row staggered with the first row. The pseudo-contact pads facilitate fabrication. In some embodiments, Vdd rails extend between and parallel to the first rows. The positions of these Vdd rails avoid inductive coupling. In some embodiments, LOFIC capacitors are disposed directly below the Vdd rails.

[0038] In some embodiments, the second die has corresponding pads and rows of pseudo-contact pads. In some embodiments, the second die has Vdd rails that are flat and extend between and parallel to the first rows. In some embodiments, the second die has LOFIC capacitors disposed directly above the Vdd rails such that the LOFIC capacitors are located between the Vdd rails and the substrate of the second die.

[0039] In some embodiments, the image sensor includes a third die. The third die can be stacked with the first die and the second die. The third die can contain an application specific integrated circuit (ASIC). The ASIC uses data from the photodetector array and can include components such as memory cells, logic circuits, etc. Placing this additional circuitry on the third die preserves the image sensing area on the first die and leaves more area on the second die for the in-pixel circuitry.

[0040] Figure 1 A perspective view of an integrated circuit device 100 according to some embodiments is shown. The integrated circuit device 100 includes three device layers: a first wafer 101A including a first die 101, a second wafer 103A including a second die 103, and a third wafer 105A including a third die 105. The first die 101 and the second die 103 include photodetector assemblies. The third die 105 can provide an application specific integrated circuit (ASIC). After cutting along the scribe line 109 and subsequent packaging, the integrated circuit device 100 provides an image sensor 107, and each image sensor 107 includes the first die 101, the second die 102, and the third die 105.

[0041] Figure 2A circuit diagram 200 of a photodetector is provided, and the photodetector can be one of a photodetector array in an image sensor 107. The photodetector includes four photodiodes PD, four transmission gates TX, a DCG transistor, and a source follower SF on a first die 101. The four photodiodes PD are connected to a floating diffusion node FD through the four corresponding transmission gates TX. The gate of the source follower SF and the source side of the DCG transistor are also connected to the floating diffusion node FD.

[0042] The photodetector further includes a reset transistor RST, a row selection transistor RSL, and a LOFIC on a second die 103. The source side of the reset transistor RST is coupled to the drain side of the DCG transistor through a first connection structure 201A. Closing the DCG transistor adds the capacitance of the first connection structure 201A and the associated wiring and the capacitance of the LOFIC to the floating diffusion node FD. The drain side of the row selection transistor RSL is coupled to the source side of the source follower SF through a second connection structure 201B. The source side of the row selection transistor RSL can be coupled to an ASIC on a third die 105. The ASIC is not considered part of the photodetector.

[0043] Figure 3 A plan view 300 is provided. Figure 4 A perspective view 400 of a region of a portion of the first die 101 including a photodetector 351 is provided. The photodetector 351 corresponds to Figure 2 the circuit diagram 200. Referring to Figure 3 the plan view 300, the photodetector 351 includes photodiodes 311A to 311D in the first die 101. The photodiodes 311A to 311D are photosensitive regions in a semiconductor substrate 317, and the semiconductor substrate 317 is part of the first die 101. The photodiodes 311A and 311B are selectively coupled to a first floating diffusion region 315A through a first pair of transmission gates 319. The photodiodes 311C and 311D are selectively coupled to a second floating diffusion region 315B through a second pair of transmission gates 319. The first floating diffusion region 315A and the second floating diffusion region 315B are doped regions of the semiconductor substrate 317.

[0044] The DCG transistor 301 and the source follower 329 are arranged end to end in row 302. The photodiodes 311A and 311B are on one side of row 302, and the photodiodes 311C and 311D are on the opposite side of row 302. The DCG transistor 301 and the source follower 329 are isolated from each other by a section of the shallow trench isolation structure 333, isolated from the floating diffusion regions 315A to 315B, and isolated from the photodiodes 311A to 311D. The DCG transistor 301 includes a DCG source region 309, a DCG drain region 305, and a DCG gate electrode 307. The source follower 329 includes a source follower source region 325, a source follower drain region 321, and a source follower gate electrode 323.

[0045] The wiring in the first metallization layer on the semiconductor substrate 317 connects the first floating diffusion region 315A, the second floating diffusion region 315B, the source follower gate electrode 323, and the DCG source region 309 to provide a floating diffusion node 310. The wiring includes a straight line 331 connecting the first floating diffusion region 315A, the source follower gate electrode 323, and the second floating diffusion region 315B, and an L-shaped line 313 connecting the straight line 331 to the DCG source region 309.

[0046] Reference Figure 4 to the perspective view 400, the first metal pillar 303 connects the DCG drain region 305 to the contact pad 401A. The contact pad 401A is part of the first connection structure 201A (see Figure 2 ). The second metal pillar 327 connects the source follower source region 325 to the contact pad 401B, which is part of the second connection structure 201B.

[0047] Figure 4 The perspective view 400 is also a cross-sectional view, thus showing some structures inside the semiconductor substrate 317 and on the back side 406. These include the back-side deep trench isolation structure 413 that provides electrical isolation between adjacent photodiodes 311A to 311D. The back-side metal grid 411 increases the optical isolation between adjacent photodiodes 311A to 311D. The color filter 409 and the microlens 407 can also be provided on the back side 406.

[0048] Figure 5 A plan view 500 is provided, Figure 6 A perspective view 600 of the region on the second die 103 containing the second part of the photodetector 351 is provided. Refer to Figure 5For the plan view 500, the second die 103 includes a semiconductor substrate 517. A reset transistor 509 and a row select transistor 529 are formed on the semiconductor substrate 517 and are respectively surrounded by isolation structures 505 and 501. The reset transistor 509 includes a reset transistor source region 513, a reset transistor gate electrode 511, and a reset transistor drain region 507. The row select transistor 529 includes a row select transistor source region 521, a row select transistor gate electrode 525, and a row select transistor drain region 531. The LOFIC 515 is disposed on the semiconductor substrate 517, and the Vdd rail 503 is disposed on the LOFIC 515.

[0049] Reference Figure 6 For the perspective view 600, the first metal pillar 603A and the wire 519 connect the reset transistor source region 513 and the bottom electrode 607 of the LOFIC 515 to the contact pad 601A, which is part of the first connection structure 201A (see Figure 2 ). The second metal pillar 603B connects the row select transistor drain region 531 to the contact pad 601B, which is part of the second connection structure 201B.

[0050] Figure 7 A perspective view 700 is provided, showing how the first die 101 is connected to the second die 103. Specifically, the contact pad 401A abuts the contact pad 601A to form the first connection structure 201A, and the contact pad 401B abuts the contact pad 601B to form the second connection structure 201B. It can also be seen from the perspective view 700 that the first metal pillar 303, the second metal pillar 327, and the connection structures 201A and 201B can be electrically isolated from the floating diffusion node 310.

[0051] Figure 8 A circuit diagram 800 of another photodetector that can be used in the image sensor 107 is provided. The circuit diagram 800 is similar to Figure 2 the circuit diagram 200, except that in the circuit diagram 800, a second LOFIC (LOFIC2) is provided in the first die 101 and a second DCG transistor (DCG2) is provided in the second die 102. Closing the DCG1 transistor adds the second LOFIC to the floating diffusion node FD, and closing the DCG1 and DCG2 transistors adds the first LOFIC and the second LOFIC to the floating diffusion node FD.

[0052] Figure 9 A plan view 900 of a region on the first die 101 is provided, which region contains a portion of the photodetector 951 on the first die 102. The photodetector 951 is associated with Figure 8corresponds to the circuit diagram 800. The portion of the photodetector 951 on the first die 101 is similar to the portion of the photodetector 351 on the first die 101 (see Figure 3 ), except that the photodetector 951 includes a second LOFIC 905. A wire 901 connects the bottom electrode (not shown) of the second LOFIC 905 to the first metal pillar 303 and the DCG drain region 305. The top electrode 904 of the second LOFIC 905 is connected to the Vdd rail 903, and the Vdd rail is located above the second LOFC 905 in the metal interconnect structure of the first die 101. The Vdd rail 903 can be one of the Vdd rail arrays 903 staggered with the row 302.

[0053] Figure 10 A plan view 1000 of the region on the second die 103 is provided, and this region contains the portion of the photodetector 951 on the second die 103. The portion of the photodetector 951 on the second die 103 is similar to the portion of the photodetector 351 on the second die 103 (see Figure 5 ), except that the photodetector 951 includes a second DCG 1003 on the second die 103. The second DCG 1003 includes a drain region 1001, a source region 1007, and a gate electrode 1005. A wire 519 is connected to the first connection structure 201A through the second DCG 1003, rather than being directly coupled to the first connection structure 201A as in the photodetector 351 (see Figure 5 ).

[0054] Figure 11 A circuit diagram 1100 of a photodetector according to another embodiment is provided. The circuit diagram 1100 is similar to Figure 2 the circuit diagram 200, except that in the circuit diagram 1100, there is one less connection between the first die 101 and the second die 103, and the LOFIC and the reset transistor RST are located on the first die 101. Moving these components to the first die 101 leaves more area on the second die 103 for in-pixel circuitry. The additional area on the second die 103 can alternatively be used to implement an ASIC.

[0055] Figure 12 A plan view 1200 of the region on the first die 101 containing the portion of the photodetector 1251 is provided. The photodetector 1251 corresponds to Figure 11 the circuit diagram 1100. The portion of the photodetector 1251 on the first die 101 is similar to the portion of the photodetector 351 on the first die 101 (see Figure 3 ), except that the photodetector 125l includes a reset transistor 1203 and a LOFIC 1209. In addition, the photodetector 1251 lacks the metal pillar 303 (see Figure 3) Instead, it includes a wire 1207 that connects the DCG drain region 305 to the source region 1205 of the reset transistor 1203 and the bottom electrode of the LOFIC 1209. The top electrode of the LOFIC 1209 is connected to the Vdd rail (not shown).

[0056] Figure 13 A plan view 1300 of a region on the second die 103 that includes a second portion of the photodetector 1251 is provided. The portion of the photodetector 1251 on the second die 103 is similar to the portion of the photodetector 351 on the second die 103 (see Figure 5 ) except that the photodetector 951 lacks the reset transistor 509 and the LOFIC 515.

[0057] Figures 14 to 39 A series of views showing an image sensor according to the present disclosure at various manufacturing stages of a process according to the present disclosure is provided. The cross-sectional views in this series of views may correspond to the line A-A' in Figure 3 and Figure 5 . Although Figures 14 to 39 is described in terms of a series of steps, it is understood that, in some cases, the order of the steps may be changed and this series of steps is applicable to other structures besides the structures shown. In some embodiments, some of these steps may be omitted in whole or in part. Additionally, although Figures 14 to 39 is described in terms of a series of steps, it should be understood that Figures 14 to 39 the structure shown in

[0058] is not limited to the manufacturing method but can exist independently as a structure separate from the method. Figure 14 As shown in the cross-sectional view 1400 of

[0059] Figure 15 ​As shown in the cross-sectional view 1500, the method can continue to inject dopants to form photodiodes 311A to 311D. The dopants can be injected in a series of steps, including, for example, deep n-well injection, shallow p-well injection, etc. Some of these dopant injections can be performed with a mask, while others do not require a mask. Some of these dopant injections can be performed before forming the shallow trench isolation structure 333.

[0060] As Figure 16 As shown in the cross-sectional view 1600, a transistor gate including a gate dielectric 1601 and a gate electrode 1603 can be formed on the semiconductor substrate 317 to provide a transmission gate 319 and other transistors. The gate dielectric 1601 can be an oxide or some other suitable material. The gate electrode 1603 can be polysilicon or some other suitable material. These layers can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. or any other suitable process. The gate dielectric 1601 can be formed by oxidation. After deposition, these layers are patterned to define the respective gates. Spacers (not shown) are typically formed around the gates. The spacers can be formed by depositing spacer material and then performing anisotropic etching. The spacer material can include one or more layers of any suitable dielectric. The spacer material can be or include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), a high-k dielectric layer, etc. The spacer material can be deposited by ALD, CVD, PVD, etc. or any other suitable process.

[0061] As Figure 17 As shown in the cross-sectional view 1700, dopants can be injected to form floating diffusion regions 315A to 315B, a source follower source region 325, and other source / drain regions. A mask 1701 can be formed before injecting the dopants. The floating diffusion regions 315A to 315B can be aligned with the transmission gate 319 and the shallow trench isolation structure 333. Alternatively, the floating diffusion regions 315A to 315B can be spaced apart from the shallow trench isolation structure 333 to reduce leakage current.

[0062] As Figure 18 As shown in the cross-sectional view 1800, the process can continue to form a metal interconnect structure 371. The metal interconnect structure 371 includes a plurality of metallization layers, contact plugs 1801, vias 1809, and a plurality of metallization layers including wires 1803. The metallization layers include the M1 metallization layer closest to the semiconductor substrate 317, the M2 metallization layer, and the topmost M top metallization layer. A greater or lesser number of metallization layers can be included. The Vdd rail 373 can be disposed in the M top metallization layer or some other metallization layer.

[0063] The contact plug 1801 can be or include tungsten (W), cobalt (Co), cobalt silicide (CoSi2), nickel (Ni), nickel silicide (NiSi), their alloys, etc. or some other suitable materials. The wire 1803 and the via 1809 can be or include copper (Cu), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), conductive carbides, oxides, their alloys, etc. or any other suitable conductive material. The wire 1803 and the via 1809 can also include a diffusion barrier layer, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc. The metallization layer can be formed by a damascene or dual damascene process. The conductive material in the metal interconnect structure 371 can be deposited by electroplating, electroless plating, ALD, CVD, PVD, etc. or any other suitable process.

[0064] The interlayer dielectric 1807 surrounds the wire 1803 and the via 1809. Adjacent metallization layers can be separated by an etch stop layer 1805. The interlayer dielectric 1807 can include one or more layers of silicon dioxide (SiO2), a low dielectric or an extremely low dielectric. A low dielectric constant refers to a dielectric constant less than that of silicon dioxide (SiO2). The dielectric constant of silicon dioxide is approximately 3.9. Examples of low dielectrics include organosilicate glass (OSG), such as carbon-doped silicon dioxide, fluorine-doped silicon dioxide (also known as fluorinated silica glass (FSG)), organic polymer low dielectrics, and porous silicate glass. An extremely low dielectric constant refers to a material with a dielectric constant of about 2.1 or lower. Extremely low dielectric materials are usually low-k dielectric substances with a porous structure. The porosity reduces the effective dielectric constant. The etch stop layer 1805 can include one or more layers of silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SIOC), silicon oxynitride carbide (SiOCN), their combinations, etc. The interlayer dielectric 1807 and the etch stop layer 1805 can be deposited by ALD, CVD, PVD, etc. or any other suitable process.

[0065] As Figures 19 to 21 shown in cross-sectional views 1900 to 2100 of Figure 19 As shown in cross-sectional view 1900 of

[0066] As Figure 20As shown in the cross-sectional view 2000 of FIG. 1 , metal 2001 may be deposited to fill the openings 1905 and 1907. Metal 2001 may be or include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), indium (In), nickel (Ni), conductive carbides, oxides, alloys of these metals, etc., or any other suitable material. Metal 2001 may be deposited by electroplating, electroless plating, ALD, CVD, PVD, etc., or any other suitable process.

[0067] like Figure 21 As shown in the cross-sectional view 2100 of , a planarization process may be performed to remove metal 2001 deposited outside openings 1905 and 1907. Metal 2001 remaining in opening 1905 provides contact pad 401B, etc. Metal 2001 remaining in opening 1907 provides dummy contact pad 375. The planarization process may be chemical mechanical polishing (CMP), etc., or some other suitable process.

[0068] Figure 22 Provides Figure 21 2200. As shown in plan view 2200, dummy contact pads 375 form row 2201 between row 302 including contact pads 401A and 401B. Dummy contact pads 375 are combined with contact pads 401A and 401B to form a regular grid, such that dummy contact pads 375 are arranged in a row 2201 between row 302 including contact pads 401A and 401B. Figure 21 The cross-sectional view 2100 of the embodiment of the present invention prevents dishing during the CMP process. The plan view 2200 also shows that the Vdd rail 373 extends parallel to the rows 302 and is disposed between the rows 302. The extensive coverage of the Vdd rail 373 prevents voltage drops that may cause noise. The positioning of the Vdd rail 373 avoids noise associated with inductive coupling of the wires connected to the contact pads 401A and 401B.

[0069] Figures 23 to 32 The cross-sectional views 2300 to 3200 show the process for manufacturing the second wafer 103A. Figure 23 As shown in the cross-sectional view 2300 of FIG. 23, the process may begin by forming an isolation structure 501 in a semiconductor substrate 517. The semiconductor substrate 517 may have one of the compositions suitable for the semiconductor substrate 317 (see FIG. Figure 14 ). The transistor can be formed on the semiconductor substrate 517 as on the semiconductor substrate 317 (see Figure 16 and 17 ), although in Figures 23 to 32 Not shown in the cross-sectional views 2300 to 3200 .

[0070] like Figure 24As shown in the cross-sectional view 2400, the first set of metallization layers in the metal interconnect structure 575 can be formed on the semiconductor substrate 517. The composition of these layers and the method of forming them can be as described in connection with Figure 18 the metal interconnect structure 371.

[0071] Figures 23 to 32 The cross-sectional views 2500 to 3000 show an example process for forming the LOFIC 515 (see Figure 6 ). As Figure 25 shown in the cross-sectional view 2500, the process can start with the deposition of the etch stop layer 2501, the interlayer dielectric layer 2503, and the mask 2505. The mask 2505 is patterned and used to etch one or more trenches 2507. The wires 2509 for the bottom electrode contacts can be exposed through the trenches 2507

[0072] As Figure 26 shown in the cross-sectional view 2600, the bottom electrode layer 2603 can be deposited to line up the trenches 2507 and contact the wires 2509. The bottom electrode layer 2603 can be, for example, titanium nitride (TiN), tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), copper (Cu), silver (Ag), aluminum (Al), nickel (Ni), their conductive alloys, etc. In some embodiments, the bottom is titanium nitride (TiN), etc. Using titanium nitride (TiN) as the electrode metal layer helps to achieve a very low equivalent series resistance. In some embodiments, the bottom electrode layer 2603 is deposited to a thickness in the range of about 1 nm to about 20 nm. In some embodiments, the bottom electrode layer 2603 is deposited to a thickness in the range of about 20 nm to about 50 nm. A thinner electrode metal layer allows for more capacitor plates to be deposited in the trenches 2507 and can provide a higher capacitance. A thicker electrode metal layer can reduce the equivalent series resistance. The bottom electrode layer 2603 can be deposited by physical vapor deposition (PVD), chemical vapor deposition, atomic layer deposition (ALD), electroplating, electroless plating, etc. or any other suitable process.

[0073] The sacrificial layer 2601 can be deposited on the bottom electrode layer 2603 to fill the trenches 2507. The sacrificial layer 2601 can be a bottom antireflective coating (BARC) or any other suitable material. As Figure 27 shown in the cross-sectional view 2700, the sacrificial layer 2601 helps with the planarization process. The planarization process can be CMP, etc. and removes the portion of the bottom electrode layer 2603 deposited outside the trenches 2507. The remaining portion of the bottom electrode layer 2603 provides the bottom electrode 607. As Figure 28 shown in the cross-sectional view 2800, after planarization, the sacrificial layer 2601 can be removed.

[0074] As Figure 29As shown in the cross-sectional view 2900, the capacitor dielectric layer 606 and the top electrode 605 can be deposited on Figure 28 the structure shown in the cross-sectional view 2800. The capacitor dielectric layer 606 can be any suitable dielectric. In some embodiments, the capacitor dielectric layer 606 is a high-k dielectric. Examples of high-k dielectrics include but are not limited to hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride, hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), hafnium oxide-aluminum oxide (HfO2 - Al2O3), zirconium oxide (ZrO2), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), strontium titanate (SrTiO3), etc. The capacitor dielectric layer 606 can be deposited to any suitable thickness. In some embodiments, the capacitor dielectric layer 606 is deposited to have a thickness in the range of about 5 nm to about 20 nm. The capacitor dielectric layer 606 can be deposited by ALD, CVD, PVD, etc. or any suitable process. The top electrode 605 can have the composition and thickness as described for the bottom electrode 607.

[0075] The cross-sectional view 2900 shows that the trench 2507 is substantially filled with the top electrode 605. Alternatively, trench dimensions of any layer thickness can be selected so that additional dielectric layers and electrode layers can be deposited before filling the trench 2507, such that the resulting capacitor can have more plates than the number shown. As the trench 2507 is filled, inclusions 2901 can be formed within the trench 2507.

[0076] As Figure 30 shown in the cross-sectional view 3000, a mask 3001 can be formed and used to pattern the capacitor dielectric layer 606 and the top electrode 605 to complete the formation of the LOFIC 515. The LOFIC 515 is a trench capacitor, which can also be described as a 3D - MIM capacitor. More generally, the LOFIC 515 can be any suitable type of capacitor.

[0077] As Figure 31 shown in the cross-sectional view 3100, after the formation of the LOFIC 515, the formation of the metal interconnect structure 575 can be completed. The metal interconnect structure 575 can include the Vdd rail 503. In some embodiments, the Vdd rail 503 is directly located above the LOFIC 515.

[0078] As Figure 32 shown in the cross-sectional view 3200, a bonding layer 573 is formed on the metal interconnect structure 575. The bonding layer 573 includes contact pads 601B and dummy contact pads 571. The formation and composition of the bonding layer 573 can be as described for the bonding layer 377 in connection with Figures 19 to 21 the bonding layer 377.

[0079] Figure 33 provides a planar view 3300 corresponding to Figure 32 As shown in the planar view 3300, the pseudo-contact pads 571 form a row 3301 between the rows 3303 containing the contact pads 601A and 601B. The pseudo-contact pads 571 are combined with the contact pads 601A and 601B to form a regular grid, so that the pseudo-contact pads 571 prevent dents during CMP. As shown in the planar view 3300, the Vdd rail 503 extends parallel to the row 3303 and is disposed between the rows 3303. The positioning of the Vdd rail 503 avoids the noise related to the inductive coupling of the wires connected to the contact pads 601A and 601B.

[0080] As Figure 34A shown in the cross-sectional view 3400 of

[0081] As Figure 34B shown in the cross-sectional view 3410 of Figure 5 ), the semiconductor substrate 517 of the second wafer 103A can be thinned from the back side 3409. The semiconductor substrate 517 can be thinned by etching, mechanical grinding, CMP, etc. or any other suitable process. After thinning, a through-substrate via (TSV, not shown) can be formed. The TSV can connect the contact pads 3401 formed on the back side 3409 to the structures on the front side 3407, such as the metal interconnect structure 575 and the row selection transistor source region 521 (see

[0082] As Figure 34C shown in the cross-sectional view 3420 of

[0083] As Figure 35 shown in the cross-sectional view 3500 of Figure 3 ), thinning the semiconductor substrate 317 allows light to be more easily transmitted to the photodiodes 311A to 311D (see Figure 3)。The semiconductor substrate 317 can be thinned from the backside 406 by etching, mechanical polishing, CMP, etc. or any other suitable process. In some embodiments, the semiconductor substrate 317 is thinned to about 5 μm or less. In some embodiments, the semiconductor substrate 317 is thinned to about 3 μm or less.

[0084] As Figure 36 shown in the cross-sectional view 3600 of, a mask 3601 can be formed and used to etch trenches 3603 in the semiconductor substrate 317. The trenches 3603 form a grid using the sections between adjacent photodiodes 311A to 311D. The trenches 3603 have a high aspect ratio. In some embodiments, the trenches 3603 have an aspect ratio of 15:1 or greater. In some embodiments, the trenches 3603 have an aspect ratio of 20:1 or greater. In some embodiments, the trenches 3603 have an aspect ratio of 25:1 or greater. In some embodiments, the trenches 3603 abut the shallow trench isolation structure 333. In this example, a backside deep trench isolation structure is formed. Alternatively, a frontside deep trench isolation structure can be formed.

[0085] Continuing with this example, the trenches 3603 can be filled as Figure 37 shown in the cross-sectional view 3700 of to provide the DTI structure 413. In some embodiments, the trenches 3603 are filled with a dielectric. In other embodiments, the trenches 3603 are lined with a dielectric and then filled with a conductive material to provide a conductive core. The conductive core can be grounded or can be coupled to a bias voltage source.

[0086] The DTI structure 413 can include one or more dielectric layers. When these layers are deposited in the trenches 3603, they are also deposited on the backside 406. Depending on the conditions of the deposition process for forming these layers, some of these layers may be thicker on the backside 406.

[0087] In some embodiments, the trenches 3603 are lined with a high-k dielectric layer. The high-k dielectric layer passivates defects by forming an electric field that accumulates holes along the inner walls, thereby passivating charge carriers (such as electrons). The high-k dielectric layer can be or include, for example, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride, hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), hafnium oxide - aluminum oxide (HfO2 - Al2O3), zirconium oxide (ZrO2), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), strontium titanate (SrTiO3), etc., and can have a thickness, for example, in the range of 5 angstroms to 50 angstroms. The high-k dielectric layer can be deposited by ALD, CVD, PVD, etc. or any suitable process.

[0088] After the liner, trench 3603 can be filled with an oxide, such as silicon dioxide (SiO2), tantalum pentoxide (Ta2O5), etc. The filler can be deposited by ALD, CVD, PVD, etc. or any suitable process. In some embodiments, the oxide includes at least one layer of tantalum pentoxide, etc. The refractive index of tantalum pentoxide is between that of silicon (Si) and silicon dioxide. Thus, a layer of tantalum pentoxide can reduce reflection. The DTI structure 413 can be planarized on the backside 406. The planarization can be achieved by CMP, etc. or any other suitable process. The planarization provides a flat surface on which subsequent structures can be built.

[0089] As Figure 37 shown in cross-sectional view 3700 of, an additional dielectric layer and a backside metal grid 411 can be formed on the backside 406. The backside metal grid 411 can have any suitable composition and thickness. The backside metal grid 411 can include aluminum (Al), copper (Cu), tungsten (W), etc. or any other suitable material.

[0090] As Figure 39 shown in cross-sectional view 3900 of, then a color filter 409 and a microlens 407 can be formed. The color filter 409 can include red, green, and blue color filters. Other color combinations, such as cyan, yellow, and magenta, can also be used. The color filter 409 can be a Bayer pattern or some other pattern. The process may end with wafer dicing and packaging.

[0091] Figure 40 A flowchart of a process 4000 for forming an image sensor of the present disclosure is provided. Although process 4000 is shown and described below as a series of steps or events, it should be understood that the order of the steps or events shown should not be construed as restrictive. For example, some steps may occur in a different order and / or concurrently with other steps or events not shown and / or described herein. Additionally, not all of the steps shown are required to implement one or more aspects or embodiments described herein. Further, one or more of the steps described herein can be performed in one or more separate steps and / or phases.

[0092] Process 4000 begins with a set of steps 4001 performed on a first wafer and a set of steps 4021 performed on a second wafer. Steps 4001 can be performed before, after, or concurrently with the set of steps 4021.

[0093] Step 4003 forms an STI structure on the first wafer. Figure 14 Cross-sectional view 1400 of provides an example. Step 4005 implants dopants to form a photodiode. Figure 15Cross-sectional views 1500 provide examples. Forming a photodiode can include multiple dopant implants, some of which can be done earlier or later in the sequence of step 4001. For example, forming a photodiode can start with a deep n-well implant using high-energy ions without a mask.

[0094] Step 4007 forms transistors on the front side. These include transfer gates, DCG gates, and source followers. Figures 16 to 17 Cross-sectional views 1600 to 1700 provide examples. Steps 4009 to 4013 are the back-end-of-line (BEOL) processes for forming a metal interconnect structure on the front side of the first wafer. Figure 18 Cross-sectional view 1800 provides an example. Step 4011 is an optional step for forming LOFIC within the metal interconnect structure. Figures 25 to 30 Cross-sectional views 2500 to 3000 provide examples of how LOFIC is formed. Step 4015 forms a bonding layer. Figures 19 to 21 Cross-sectional views 1900 to 2100 and Figure 22 Planar view 2200 provides examples.

[0095] Step 4023 forms an STI structure on the second wafer. Figure 23 Cross-sectional view 2300 provides an example. Step 4025 forms transistors on the second wafer. The transistors on the second wafer include at least row select transistors. Step 4027 forms the lower part of the metal interconnect structure on the second wafer. Figure 24 Cross-sectional view 2400 provides an example. Step 4029 is an optional step for forming LOFIC within the metal interconnect structure. Figures 25 to 30 Cross-sectional views 2500 to 3000 and Figure 22 Planar view 2200 provide examples of how LOFIC is formed. Step 4031 forms the upper part of the metal interconnect structure on the second wafer. Figure 31 Cross-sectional view 3100 provides an example. Step 4033 is for forming a bonding layer. Figure 32 Cross-sectional view 3200 provides an example.

[0096] Step 4040 is to align the first and second wafers and bond them together through their respective bonding layers. Figure 34A Cross-sectional view 3400 provides an example.

[0097] Step 4041 thins the second wafer from the back side, forms TSVs through the substrate of the second wafer, and forms contact pads on the back side. Figure 34B Cross-sectional view 3410 provides an example. Step 4042 is to bond the second wafer to the third wafer such that the first, second, and third wafers are all bonded together. Figure 34C Cross-sectional view 3420 provides an example.

[0098] Step 4043 thins the first wafer from the back side. Figure 35 Cross-sectional view 3500 provides an example. Step 4045 etches deep trenches on the back side. Figure 36 Cross-sectional view 3600 provides an example. Step 4047 fills the trenches to provide a DTI structure. Figure 37 Cross-sectional view 3700 provides an example. The trenches can be lined with one or more high-k dielectric layers and then filled with another dielectric layer. Alternatively, the trenches can be filled with a conductive material after being lined with a dielectric layer. Another option is to form a front-side DTI structure instead of a back-side DTI structure.

[0099] Step 4049 forms a back-side metal grid. Figure 38 Cross-sectional view 3800. Step 4051 is additional processing to complete the formation of the image sensor. This may include forming color filters and microlenses. Figure 39 Cross-sectional view 3900 provides an example.

[0100] Some aspects of the present disclosure relate to an image sensor in which a photodetector includes a photosensitive region, a floating diffusion node, a transfer gate, a source follower, a row selection transistor, a first dual conversion gain transistor, and a reset transistor. The photosensitive region, the transfer gate, the source follower, and the first dual conversion gain transistor are located on a first die. The row selection transistor is located on a second die. The two dies are bonded together, and the source follower is connected to the row selection transistor through a metal interconnect structure of the two dies.

[0101] In some embodiments, opening the first dual conversion gain transistor electrically isolates the floating diffusion node from the second die. In some embodiments, the photodetector further includes a first LOFIC, which is located on the second die together with the reset transistor. In some embodiments, the photodetector further includes a second LOFIC and a second dual conversion gain transistor. The second LOFIC is located on the first die, and the second dual conversion gain transistor is located on the second die.

[0102] In some embodiments, the photodetector includes two contact pads on the first die that dock with two contact pads on the second die. In some embodiments, the two contact pads on the first die are in an array including active contact pads and dummy contact pads. The active contact pads are in the first row, the dummy contact pads are in the second row, and the first row and the second row are staggered.

[0103] In some embodiments, the first LOFIC is a three-dimensional metal-insulator-metal capacitor. In some embodiments, the first LOFIC is horizontally aligned with the Vdd rail in the second metal interconnect structure such that the first LOFIC is directly located between the Vdd rail and the second die.

[0104] In some embodiments, the photodetector further includes a LOFIC on the first die coupled to the floating diffusion node through a first dual-conversion gain transistor. In some embodiments, the photosensitive region is one of four photosensitive regions coupled to the floating diffusion node through four corresponding transmission gates. In some embodiments, the source follower and the first dual-conversion gain transistor are arranged in a row, with the first two of the four photosensitive regions on one side of the row and the last two of the four photosensitive regions on the opposite side of the row. In some embodiments, the shallow trench isolation structure has a section between the row and two corresponding ones of the four photosensitive regions on both sides of the row. In some embodiments, there is a Vdd rail on the first die extending parallel to the row. The Vdd rail is connected to the drain side of the source follower.

[0105] In some embodiments, the image sensor includes a backside deep trench isolation structure having a section surrounding the photosensitive region. In some embodiments, the floating diffusion node includes a wire in the first metallization layer on the first die, but the floating diffusion node is electrically isolated from the higher metallization layer when the first dual-conversion gain transistor is open.

[0106] Some aspects of the present disclosure relate to a photodetector including a photodiode in a first die, a floating diffusion node, a transmission gate between the floating diffusion node and the photodiode, and a plurality of additional transistors including a first transistor on the first die and a second transistor on a second die. When the first transistor is open, the floating diffusion node is confined within the first die. In some embodiments, the photodetector includes a LOFIC on the second die, and the floating diffusion node is coupled to the LOFIC through the first transistor.

[0107] Some aspects of the present disclosure relate to methods of fabricating an image sensor. The method includes forming a photodiode and a floating diffusion region on a first wafer. A transfer gate, a source follower, and a first dual conversion gain transistor are also formed on the first wafer. The transfer gate is configured to selectively couple the photodiode to the floating diffusion region. A first metal interconnect structure is formed on the first wafer. The first metal interconnect structure couples the floating diffusion region to the gate of the source follower and the source side of the first dual conversion gain transistor. The method further includes forming a row select transistor on a second wafer and forming a second metal interconnect structure on the second wafer. The first wafer and the second wafer are bonded such that the first metal interconnect structure and the second metal interconnect structure face each other. The bonding couples the drain side of the row select transistor to the source side of the source follower. The first wafer is thinned and a microlens is formed on the first wafer. In some embodiments, the method further includes forming a first 3D-MIM capacitor in the second metal interconnect structure. One or more transistors, including the first dual conversion gain transistor, selectively couple the first 3D-MIM to the floating diffusion region. In some embodiments, a second dual conversion gain transistor is formed on the second wafer, one or more transistors include the second dual conversion gain transistor, and a second 3D-MIM capacitor is formed in the first metal interconnect structure. The first dual conversion gain transistor selectively couples the second 3D-MIM capacitor to the floating diffusion region.

[0108] The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations therein without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor, comprising: a first die comprising a first semiconductor substrate and a first metal interconnect structure; a second die comprising a second semiconductor substrate and a second metal interconnect structure, wherein the second die is bonded to the first die; and a photodetector including a photosensitive region, a floating diffusion node, a transmission gate, a source follower, a row select transistor, a first dual conversion gain transistor, and a reset transistor; wherein the photosensitive region, the transmission gate, the source follower and the first dual conversion gain transistor are on the first die, and the row select transistor is on the second die; and The source follower is connected to the row select transistor through the first metal interconnect structure and the second metal interconnect structure.

2. The image sensor according to claim 1, wherein: The first dual conversion gain transistor is open-circuited to electrically isolate the floating diffusion node from the second die.

3. The image sensor according to claim 1, wherein: The photodetector further includes a first lateral overflow integration capacitor (LOFIC); and The first lateral overflow integrating capacitor and the reset transistor are located on the second die.

4. The image sensor according to claim 3, wherein: The photodetector further includes a second lateral overflow integrating capacitor and a second dual conversion gain transistor; and The second lateral overflow integrating capacitor is located on the first die and the second dual conversion gain transistor is located on the second die.

5. The image sensor according to claim 3, wherein: The photodetector includes two contact pads on the first die that interface with two contact pads on the second die.

6. The image sensor according to claim 5, wherein: The two contact pads on the first die are in an array including active contact pads and dummy contact pads, wherein the active contact pads are in a first row, the dummy contact pads are in a second row, and the first row is staggered with the second row.

7. The image sensor according to claim 3, wherein: The first lateral spillover integrating capacitor is a three-dimensional metal-insulator-metal capacitor.

8. An image sensor, comprising: A first die including a first substrate and a first metal interconnect structure; a second die comprising a second substrate and a second metal interconnect structure, wherein the second die is bonded to the first die; and a photodetector comprising a photosensitive region within the first substrate, a floating diffusion node, a transmission gate between the floating diffusion node and the photosensitive region, a first transistor on the first die, and a second transistor on the second die; Wherein, when the first transistor is open, the floating diffusion node is confined within the first die.

9. The image sensor according to claim 8, further comprising: A lateral overflow integrating capacitor is provided on the second die, wherein the floating diffusion node is coupled to the lateral overflow integrating capacitor through the first transistor, the first metal interconnect structure, and the second metal interconnect structure.

10. A method for manufacturing an image sensor, the method comprising: providing a first substrate; forming a photodiode and a floating diffusion region in the first substrate; forming a transmission gate, a source follower, and a first dual conversion gain transistor on the first substrate, wherein the transmission gate is configured to selectively couple the photodiode to the floating diffusion region; forming a first metal interconnect structure on the first substrate, wherein the first metal interconnect structure couples the floating diffusion region to a gate of the source follower and a source side of the first dual conversion gain transistor; providing a second substrate; forming a row selection transistor on the second substrate; forming a second metal interconnect structure over the second substrate; and The first substrate is bonded to the second substrate, wherein the bond couples a drain side of the row select transistor to a source side of the source follower.

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