Light-emitting panel, preparation method thereof and light-emitting device

Abstract

The embodiment of the invention provides a light-emitting panel, a preparation method thereof and a light-emitting device. The light-emitting panel includes: a driving back plate; the insulation bonding layer is located on one side of the driving backboard, the insulation bonding layer is provided with a first via hole, and the first via hole is at least partially overlapped with the corresponding control electrode; the light-emitting unit is located on the insulation bonding layer, the light-emitting unit and the first via hole are not overlapped, the light-emitting unit comprises a first electrode layer and a light-emitting body, the light-emitting body is located on the first electrode layer and comprises a first semiconductor layer, an active layer and a second semiconductor layer which are arranged in a laminated mode, and at least part, located outside the light-emitting body, of the first electrode layer forms a lap joint part; the connecting wires are located on the side, away from the driving backboard, of the first electrode layer and located outside the light-emitting body, and the connecting wires are coupled with the lap joint parts in a lap joint mode and coupled with the control electrodes through the first via holes. According to the technical scheme, the small interval between the adjacent LEDs can be kept, and the pixel density is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a light-emitting panel and a preparation method thereof, and a light-emitting device. Background Art

[0002] As an innovative display technology, light-emitting diode (LED) chips have better brightness, luminous efficiency and lower energy consumption than the current organic light-emitting diode (OLED) technology. These remarkable characteristics indicate that LED chips have broad application potential in micro-display devices, smart watches, smart phones, iPads and even TVs.

[0003] The efficient combination of LED and CMOS silicon substrate is currently a research hotspot. Summary of the invention

[0004] The embodiments of the present disclosure provide a light-emitting panel and a method for manufacturing the same, and a display device to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a light-emitting panel, including:

[0006] A driving backplane, including control electrodes;

[0007] An insulating bonding layer is located on one side of the driving backplane, the insulating bonding layer is provided with a first via hole, and an orthographic projection of the first via hole on the driving backplane at least partially overlaps with the corresponding control electrode;

[0008] A light-emitting unit is located on a side of the insulating bonding layer away from the driving backplane, the orthographic projection of the light-emitting unit on the driving backplane does not overlap with the orthographic projection of the first via hole on the driving backplane, the light-emitting unit includes a first electrode layer and a light-emitting body, the light-emitting body is located on a side of the first electrode layer away from the driving backplane, the light-emitting body includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, and at least a portion of the first electrode layer located outside the light-emitting body forms an overlap portion;

[0009] The connecting wire is located on a side of the first electrode layer away from the driving backplane and outside the light-emitting body. The connecting wire is overlapped and coupled with the overlapping portion and is coupled with the control electrode through the first via hole.

[0010] In some embodiments, the material of the insulating bonding layer includes silicon.

[0011] In some embodiments, the insulating bonding layer includes a first bonding material layer and a second bonding material layer which are stacked, the second bonding material layer is closer to the driving backplane than the first bonding material layer, and the first bonding material layer and the second bonding material layer are bonded to each other.

[0012] In some embodiments, it further includes:

[0013] A reflective layer, located on the side of the light-emitting unit and the connection trace away from the driving backplane. The reflective layer is provided with a second via hole, and the orthographic projection of the second via hole on the driving backplane is located within the orthographic projection of the second semiconductor layer on the driving backplane;

[0014] A second electrode, located on the side of the reflective layer away from the driving backplane. The second electrode is coupled to the second semiconductor layer through the second via hole.

[0015] In some embodiments, it further includes a passivation layer, which is located between the light-emitting unit and the reflective layer, and also between the connection trace and the reflective layer. The second via hole also penetrates through the passivation layer.

[0016] In some embodiments, the second electrodes corresponding to multiple light-emitting units are interconnected;

[0017] The light-emitting panel further includes multiple light extraction structures, which correspond to the multiple light-emitting bodies one by one. The light extraction structures are located on the side of the second electrode away from the driving backplane, and the orthographic projection of the light-emitting body on the driving backplane is located within the orthographic projection of the light extraction structure on the driving backplane.

[0018] In some embodiments, the light extraction structure includes a spherical light extraction body, and the ratio of the spherical diameter of the spherical light extraction body to the distance between two adjacent light-emitting bodies is 0.8 to 1.2.

[0019] As the second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a method for manufacturing a light-emitting panel, including:

[0020] Providing an epitaxial unit and a driving backplane. The epitaxial unit includes an epitaxial layer and a first bonding material layer sequentially arranged on a substrate; the driving backplane includes a control electrode, and a second bonding material layer is provided on the surface of the driving backplane provided with the control electrode;

[0021] Bonding and connecting the first bonding material layer and the second bonding material layer to form an insulating bonding layer;

[0022] Removing the substrate;

[0023] Performing a patterning process on the epitaxial layer to form multiple mutually separated light-emitting units. The light-emitting units include a first electrode layer and a light-emitting body arranged in a stacked manner. The light-emitting body is located on the side of the first electrode layer away from the driving backplane. The light-emitting body includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially arranged in a stacked manner. At least a part of the first electrode layer located outside the light-emitting body forms an overlapping part;

[0024] Forming a first via hole penetrating through the insulating bonding layer, and the orthographic projection of the first via hole on the driving backplane at least partially overlaps with the corresponding control electrode;

[0025] A connection trace is formed on a side of the first electrode layer facing away from the driving backplane. The connection trace is located outside the first semiconductor layer, and the connection trace is overlapped and coupled with the overlapping portion and is coupled with the control electrode through a first via hole.

[0026] In some embodiments, patterning the epitaxial layer includes:

[0027] Performing a first patterning process on the epitaxial layer to form a plurality of mutually separated initial light-emitting units. The initial light-emitting units include a first electrode layer, an initial first semiconductor layer, an initial active layer, and an initial second semiconductor layer which are sequentially stacked;

[0028] Performing a second patterning process on the initial first semiconductor layer, the initial active layer, and the initial second semiconductor layer to respectively form a first semiconductor layer, an active layer, and a second semiconductor layer.

[0029] In some embodiments, it further includes:

[0030] A passivation layer and a reflective layer are sequentially formed on a side of the light-emitting unit and the connection trace facing away from the driving backplane;

[0031] Performing a third patterning process on the reflective layer and the passivation layer to form a second via hole. A positive projection of the second via hole on the driving backplane is located within a positive projection of the second semiconductor layer on the driving backplane;

[0032] A second electrode is formed on a side of the reflective layer facing away from the driving backplane. The second electrode is coupled with the second semiconductor layer through the second via hole, and a plurality of second electrodes are connected to each other.

[0033] In some embodiments, it further includes:

[0034] A plurality of light extraction structures are formed on a side of the second electrode facing away from the driving backplane. The plurality of light extraction structures correspond to a plurality of light-emitting bodies one by one, and a positive projection of the light-emitting body on the driving backplane is located within a positive projection of the light extraction structure on the driving backplane.

[0035] In some embodiments, bonding the first bonding material layer and the second bonding material layer includes:

[0036] Bonding the first bonding material layer and the second bonding material layer by using an activation process.

[0037] In some embodiments, before patterning the epitaxial layer, the method further includes:

[0038] Filling an insulating material on a side of the driving backplane facing the epitaxial layer to form an insulating filling layer, and a surface of the insulating filling layer is flush with a surface of the epitaxial layer.

[0039] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a light-emitting device, including a light-emitting panel of any embodiment of the present disclosure.

[0040] In the technical solution of the embodiment of the present disclosure, the bonding layer between the light-emitting unit and the driving backplane is an insulating bonding layer. The insulating bonding layer is provided with a first via hole. The first electrode layer in the light-emitting unit is coupled to the control electrode at the position of the first via hole through a connecting trace. In such a light-emitting panel, the insulating bonding layer is used to connect the light-emitting unit and the driving backplane, instead of using a metal bonding layer. Thus, only the ICP etching process needs to be used to etch the epitaxial layer to form independent light-emitting units; and, since the material of the insulating bonding layer is non-metal, the ICP etching technology can be used to etch the insulating bonding layer to form the first via hole. The size of ICP etching is in the nanometer scale. Therefore, in the present disclosure, the interval between two adjacent light-emitting units is the basic nanometer size, which is much smaller than Figure 17 the interval D1 in the related art shown, which can keep a smaller interval between adjacent light-emitting units, is beneficial to improving the pixel density and achieving a higher PPI.

[0041] The above summary is only for the purpose of the specification and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will be readily apparent by reference to the drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In the drawings, unless otherwise specified, the same reference numerals throughout the several views denote the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments in accordance with the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0043] Figure 1 Schematic diagram of the front-end process flow in the preparation process of a light-emitting panel according to an embodiment of the present disclosure;

[0044] Figure 2 Cross-sectional view of an initial epitaxial wafer or an epitaxial unit according to an embodiment of the present disclosure;

[0045] Figure 3 Cross-sectional view of a driving mother board according to an embodiment of the present disclosure;

[0046] Figure 4A Planar view of an epitaxial unit bonded to a driving mother board according to an embodiment of the present disclosure;

[0047] Figure 4B For Figure 4A the cross-sectional view A-A in

[0048] Figure 5 Schematic diagram of the bonding principle of the first bonding material layer and the second bonding material layer according to an embodiment of the present disclosure;

[0049] Figure 6 Schematic plan view after filling an insulating material in a region outside the epitaxial unit on the driving mother board;

[0050] Figure 7 Is Figure 6 Schematic cross-sectional view taken along line A-A in ;

[0051] Figure 8 Schematic view after forming an initial light-emitting unit in the process of manufacturing a light-emitting panel according to an embodiment of the present disclosure;

[0052] Figure 9 Schematic view after forming a light-emitting unit in the process of manufacturing a light-emitting panel according to an embodiment of the present disclosure;

[0053] Figure 10 Schematic view after forming a first via hole in the process of manufacturing a light-emitting panel according to an embodiment of the present disclosure;

[0054] Figure 11 Schematic view after forming a connection trace in the process of manufacturing a light-emitting panel according to an embodiment of the present disclosure;

[0055] Figure 12 Schematic view after forming a passivation layer in the process of manufacturing a light-emitting panel according to an embodiment of the present disclosure;

[0056] Figure 13 Schematic view after forming a reflective layer in the process of manufacturing a light-emitting panel according to an embodiment of the present disclosure;

[0057] Figure 14 Schematic view after forming a second via hole in the process of manufacturing a light-emitting panel according to an embodiment of the present disclosure;

[0058] Figure 15 Schematic view after forming a second electrode in the process of manufacturing a light-emitting panel according to an embodiment of the present disclosure;

[0059] Figure 16 Schematic view after forming a light extraction structure in the process of manufacturing a light-emitting panel according to an embodiment of the present disclosure;

[0060] Figure 17 Schematic view of a process for manufacturing an LED light-emitting panel in the related art.

[0061] Description of reference numerals:

[0062] 100. Driving backplane / driving mother board; 10. Substrate; 11. Control electrode; 12. Second bonding material layer;

[0063] 200, epitaxial wafer; 20, light-emitting unit; 21, first semiconductor layer; 210, first semiconductor thin film; 22, second semiconductor layer; 220, second semiconductor thin film; 23, active layer; 230, active thin film; 24, first electrode layer; 240, first electrode thin film;. 25, first bonding material layer

[0064] 31, connecting trace; 32, passivation layer; 33, reflective layer; 34, second electrode Detailed implementation manners

[0065] In the following, only some exemplary embodiments are briefly described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure, and different embodiments can be arbitrarily combined without conflict. Therefore, the drawings and the description are considered to be exemplary in nature rather than restrictive

[0066] The light-emitting diode (LED) in the present disclosure can be a submillimeter light-emitting diode (Mini Light Emitting Diode, abbreviated as Mini LED), or can be a micro light-emitting diode (Micro Light Emitting Diode, abbreviated as Micro LED).

[0067] As Figure 17 As shown, in the related art, first, the epitaxial layer and the driving backplane 501 are bonded and connected through the bonding metal layer 502. The epitaxial layer includes a first gallium nitride layer P-GaN, a quantum well layer MQW, and a second gallium nitride layer N-GaN that are sequentially stacked. The bonding metal layer 502 includes at least one heavy metal such as gold (Au), platinum (Pt), and chromium (Cr). Then, the epitaxial layer is patterned. Specifically, first, the first gallium nitride layer P-GaN, the quantum well layer MQW, and the second gallium nitride layer N-GaN are patterned by ICP etching to form a plurality of light-emitting units 50. Then, the bonding metal layer 502 needs to be patterned to form a plurality of bonding metal pads 503 so that each light-emitting unit 50 is connected to the driving backplane 501 through the corresponding bonding metal pad 503. Then, a passivation layer 504 is formed on the side of the light-emitting unit 50 facing away from the driving backplane 501, and a common cathode layer 505 is formed on the passivation layer 504. The common cathode layer 505 is connected to the second gallium nitride layer N-GaN through a via hole penetrating the passivation layer 504

[0068] In the related art, an IBE etching process is required to etch the bonding metal layer 502. The thickness of the bonding metal layer 502 is about 1 μm. The IBE etching requires that the etching aspect ratio is less than 3:1. That is to say, when the thickness of the bonding metal layer 502 is 1 μm, the interval D1 between two adjacent light-emitting units 50 needs to be greater than 0.33 μm. This results in an excessive interval between adjacent light-emitting units, thereby restricting the improvement of the pixel density of the light-emitting units.

[0069] An embodiment of the present disclosure provides a method for manufacturing a light-emitting panel, including steps S11 to S16. It should be noted that during the manufacturing process, multiple epitaxial units are bonded to the same large-sized driving mother board. After the manufacturing is completed, the driving mother board is cut to obtain the light-emitting panel. The driving mother board in the light-emitting panel can be called the driving backplane. Therefore, in the related descriptions of the manufacturing method in this article, the driving mother board and the driving backplane can be understood in the same way.

[0070] In step S11, an epitaxial unit and a driving backplane / driving mother board are provided. Refer to Figure 2 , the epitaxial unit 200 includes an epitaxial layer 202 and a first bonding material layer 25 sequentially provided on a substrate 201. The shapes and sizes of the epitaxial layer 202 and the first bonding material layer 25 may be the same as those of the substrate 201. The epitaxial layer 202 may include a second semiconductor thin film 220, an active thin film 230, a first semiconductor thin film 210, and a first conductive thin film 240 sequentially stacked on the substrate 201. The material of the first bonding material layer 25 is an insulating material and may include silicon. Figure 3 is a cross-sectional schematic diagram of the driving mother board in an embodiment of the present disclosure. As Figure 3 shown, the driving mother board 100 includes a control electrode 11. A second bonding material layer 12 is provided on the surface of the driving mother board 100 where the control electrode 11 is provided. The material of the second bonding material layer 12 is an insulating material and may include silicon. The materials of the first bonding material layer 25 and the second bonding material layer 12 may be the same. It should be noted that the control electrode 11 is schematically shown in the driving mother board in the drawing, and the specific position and number of the control electrodes can be set as needed.

[0071] Exemplarily, the driving motherboard 100 may include a substrate 10 and a driving structure layer disposed on the substrate 10. The driving structure layer includes PMOS and / or NMOS. The driving structure layer further includes a control electrode 11, and the control electrode 11 is connected to the corresponding MOS transistor. The control electrode 11 may correspond to the LEDs one by one, and the control electrode 11 is coupled to the first semiconductor layer 21 of the LED to drive the LED to emit light. The control electrode 11 may be a columnar structure. For example, an opening may be provided at a corresponding position of the driving structure layer, and a metal material such as tungsten or copper may be filled in the opening to form the control electrode 11. Alternatively, the control electrode 11 may be a metal trace disposed on the surface of the driving structure layer facing away from the substrate 10. The second bonding material layer 12 may be located on the surface of the driving structure layer facing away from the substrate 10. The second bonding material layer 12 may cover the control electrode 11. The second bonding material layer 12 may be made of silicon dioxide (SIO2), silicon carbonitride (SiNC), SOG (Spin-On Glass) material, or BCB (high-performance benzocyclobutene silicone resin) material. When using SIO2 or SiNC, the second bonding material layer 12 may be formed on the surface of the driving structure layer by chemical vapor deposition process. When using SOG material or BCB material, the second bonding material layer 12 may be formed on the surface of the driving structure layer by coating process.

[0072] In step S12, refer to Figure 4B , bond the first bonding material layer 25 and the second bonding material layer 12 to form an insulating bonding layer 40.

[0073] In the present disclosure, after the first bonding material layer 25 and the second bonding material layer 12 are bonded, an insulating bonding layer 40 is formed. Here, the formed insulating bonding layer 40 is no longer a metal bonding layer composed of heavy metal materials such as gold (Au), platinum (Pt), and chromium (Cr).

[0074] In step S13, remove the substrate 201.

[0075] In step S14, refer to Figure 9 , perform patterning on the epitaxial layer 202 to form a plurality of mutually separated light-emitting units 20. The light-emitting unit 20 includes a first electrode layer 24 and a light-emitting body arranged in a stacked manner. The light-emitting body is located on the side of the first electrode layer 24 facing away from the driving motherboard 100. The light-emitting body includes a first semiconductor layer 21, an active layer 23, and a second semiconductor layer 22 arranged in a stacked manner in sequence. At least a part of the first electrode layer 24 located outside the light-emitting body forms a lapping portion.

[0076] When forming a plurality of mutually separated light-emitting units 20, only the epitaxial layer 202 needs to be patterned, and the epitaxial layer 202 can be etched by using an ICP etching process.

[0077] In step S15, refer toFigure 10 , a first via hole K1 penetrating through the insulating bonding layer 40 is formed, and the orthographic projection of the first via hole K1 on the driving motherboard 100 overlaps at least partially with the corresponding control electrode 11.

[0078] The material of the insulating bonding layer 40 is a non-heavy metal. Therefore, ICP etching technology can be used to etch the insulating bonding layer 40 to form the first via hole K1, and IBE etching is not required. The first via hole K1 can be located between two adjacent first electrode layers 24. The first via hole K1 penetrates through the insulating bonding layer 40, and the orthographic projection of the first via hole K1 on the driving motherboard 100 overlaps at least partially with the corresponding control electrode 11, so that at least part of the surface of the control electrode 11 is exposed through the first via hole K1.

[0079] In step S16, referring to Figure 11 , a connecting trace 31 is formed on the side of the first electrode layer 24 away from the driving motherboard 100. The connecting trace 31 is located outside the first semiconductor layer 21. The connecting trace 31 is lap-coupled with the overlapping portion and is coupled to the control electrode 11 through the first via hole K1.

[0080] The connecting trace 31 is located outside the first semiconductor layer 21, so that the connecting trace 31 can be prevented from being coupled to the second semiconductor layer 22. Since the control electrode 11 is exposed through the first via hole K1, the connecting trace 31 can be coupled to the control electrode 11 through the first via hole K1, realizing the connection between the first electrode layer 24 and the control electrode 11 through the connecting trace 31, and further realizing the control of LED light emission by the driving motherboard 100.

[0081] In the technical solution of the present disclosure, a plurality of light-emitting units 20 including LED light-emitting bodies are formed on one side of the driving motherboard 100. In the process of forming a plurality of mutually separated light-emitting units 20 by using a patterning process, only ICP etching technology needs to be used to etch the epitaxial layer 202 to form independent light-emitting units 2; moreover, the material of the insulating bonding layer 40 is a non-metal, so ICP etching technology can be used to etch the insulating bonding layer 40 to form the first via hole K1. The size of the hole or interval of ICP etching is in the nm order of magnitude. Therefore, the size of the first via hole K1 is much smaller than Figure 17 the D1 size in Figure 17 , and the interval D2 between two adjacent light-emitting units 20 is much smaller than

[0082] In one embodiment, patterning the epitaxial layer 202 includes: performing a first patterning process on the epitaxial layer 202 to form a plurality of separated light-emitting units 20, where the light-emitting unit 20 includes a first electrode layer 24, an initial first semiconductor layer 21', an initial active layer 23', and an initial second semiconductor layer 22' stacked in sequence; performing a second patterning process on the initial first semiconductor layer 21', the initial active layer 23', and the initial second semiconductor layer 22' to form a first semiconductor layer 21, an active layer 23, and a second semiconductor layer 22, respectively.

[0083] Here, the light-emitting unit 20 is formed through two patterning processes. During the first patterning process, a first etching process is used to simultaneously etch the first conductive thin film 240, the first semiconductor thin film 210, the active thin film 230, and the second semiconductor thin film 220 to form the first electrode layer 24, the initial first semiconductor layer 21', the initial active layer 23', and the initial second semiconductor layer 22', respectively. During the second patterning process, a second etching process is used to simultaneously etch the initial first semiconductor layer 21', the initial active layer 23', and the initial second semiconductor layer 22' to form the first semiconductor layer 21, the active layer 23, and the second semiconductor layer 22, respectively. The light-emitting body includes the first semiconductor layer 21, the active layer 23, and the second semiconductor layer 22. The first conductive thin film 240 can be made of a common metal material or a transparent conductive material. The first semiconductor layer 21, the active layer 23, and the second semiconductor layer 22 are all semiconductor materials. Therefore, neither of these two etching processes requires etching of heavy metal materials, and neither of the two etching processes requires IBE etching. The ICP etching technology can be used, thereby avoiding the problem of excessive spacing between adjacent light-emitting units required by IBE etching.

[0084] In one embodiment, the method for preparing the light-emitting panel may further include: sequentially forming a passivation layer 32 and a reflective layer 33 on a side of the light-emitting body and the connection trace 31 facing away from the driving motherboard 100; performing a third patterning process on the reflective layer 33 and the passivation layer 32 to form a second via hole K2, where a positive projection of the second via hole K2 on the driving motherboard 100 is located within a positive projection of the second semiconductor layer 22 on the driving motherboard 100, and at least a part of the surface of the second semiconductor layer 22 is exposed through the second via hole K2; forming a second electrode 34 on a side of the reflective layer 33 facing away from the driving motherboard 100, where the second electrode 34 is coupled to the second semiconductor layer 22 through the second via hole K2, and the plurality of second electrodes 34 are interconnected. The second electrode 34 can be called the cathode of the light-emitting diode, and the cathodes of the plurality of light-emitting diodes are interconnected.

[0085] In some embodiments, the method for preparing a light-emitting panel may further include: forming a plurality of light extraction structures 35 on a side of the second electrode 34 facing away from the driving mother board 100, where the plurality of light extraction structures 35 correspond to the plurality of light-emitting bodies one by one, and the orthographic projection of the light-emitting body on the driving mother board 100 is located within the orthographic projection of the light extraction structure 35 on the driving mother board 100. The light extraction structure 35 can extract the light emitted by the LED and improve the brightness.

[0086] In one embodiment, bonding the first bonding material layer 25 and the second bonding material layer 12 includes: bonding the first bonding material layer 25 and the second bonding material layer 12 by using an activation process.

[0087] In some embodiments, providing the epitaxial unit 200 includes: growing an epitaxial thin film on an initial substrate of a first size, where the epitaxial thin film includes a second semiconductor thin film, an active thin film, a first semiconductor thin film, and a first conductive thin film that are sequentially stacked; forming a first bonding material thin film on a side of the epitaxial thin film facing away from the initial substrate'; and cutting the initial epitaxial wafer of the first size into a plurality of epitaxial units 200, where the size of the epitaxial unit 200 is smaller than the first size.

[0088] In some embodiments, cutting the initial epitaxial wafer of the first size into a plurality of epitaxial units 200 includes: performing material modification on a preset cutting channel of the initial substrate by using a laser to form a modified layer, where the modified layer divides the initial epitaxial wafer into a plurality of epitaxial units 200; and using a dicing process to break the modified layer to separate a plurality of epitaxial units 200.

[0089] The technical solution of the embodiments of the present disclosure will be further described below through the preparation process of a light-emitting panel in an embodiment of the present disclosure. It can be understood that, as used herein, when the material to be patterned is an inorganic material or a metal, "patterning" includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping. When the material to be patterned is an organic material, "patterning" includes processes such as mask exposure and development. Evaporation, deposition, coating, and spin coating as used herein are all mature preparation processes in related technologies.

[0090] The preparation process of the light-emitting panel mainly includes two processes, namely the front-end process and the back-end process. The front-end process mainly includes providing the epitaxial unit 200 and bonding the epitaxial unit 200 to the driving mother board 100, and the back-end process mainly includes the process of pixelating the epitaxial layer 202.

[0091] Figure 1 FIG. is a schematic diagram of the front-end process flow in the preparation process of a light-emitting panel according to an embodiment of the present disclosure. The front-end process mainly includes:

[0092] 1. Growing an epitaxial thin film on an initial substrate having a first size to form an initial epitaxial wafer, asFigure 1 As shown, the planar shape of the initial substrate is circular, and the first dimension refers to the diameter of this planar shape. The first dimension can be 4 inches. Of course, it can also be other dimensions. The material of the initial substrate can be sapphire, silicon carbide, aluminum oxide, diamond, etc. The epitaxial film may include a second semiconductor film, an active film, a first semiconductor film, and a first conductive film that are sequentially stacked. For example, a second semiconductor film, an active film, a first semiconductor film, and a first conductive film are sequentially grown on the initial substrate to form an epitaxial film.

[0093] 2. A first bonding material film is formed on the side of the epitaxial film facing away from the initial substrate, such as Figure 1 As shown. In actual implementation, an initial epitaxial wafer with consistent wavelength uniformity and good surface roughness can be selected, and a first bonding material film is prepared on the surface of the epitaxial film. The bonding material can be silicon dioxide (SIO2), silicon carbonitride (SiNC), SOG material, or BCB material. When using SiO2 or SiNC, a chemical vapor deposition process can be used to form the first bonding material film on the surface of the epitaxial film. When using SOG material or BCB material, a coating process can be used to form the first bonding material film on the surface of the epitaxial film.

[0094] 3. The surface of the first bonding material film is subjected to chemical mechanical polishing (CMP) to improve the surface flatness of the bonding interface.

[0095] 4. A first temporary substrate 61 is formed on the surface of the first bonding material thin film. The initial substrate is subjected to material modification by laser along a preset cutting channel to form a modified layer, with the aim of subsequently dividing the initial epitaxial wafer with a first size into multiple epitaxial units 200. For example, the initial substrate is cut along the preset cutting channel by laser scribing. The substrate material of the preset cutting channel is modified after being irradiated by the laser and becomes a modified layer that is prone to brittle fracture. The preset cutting channel divides the initial epitaxial wafer into multiple epitaxial units 200 with preset sizes. The preset size of the epitaxial unit 200 can be determined according to the display area size of the display product. To facilitate the mutual bonding of the epitaxial unit 200 and the driving mother board 100, the size of the epitaxial unit 200 should be slightly larger than the display area size. Table 1 provides the display area sizes and bonding area sizes corresponding to four display product sizes. For example, when the display product size is 0.13 inch, the corresponding display area size is 2.5 mm * 2.5 mm. Correspondingly, the size of the epitaxial unit 200 can be 2.7 mm * 2.7 mm, that is, the size of the epitaxial unit leaves a margin of 200 μm compared to the display area size. When the product size is 0.26 inch, the display area size is 5.76 mm * 3.24 mm. Correspondingly, the size of the epitaxial unit 200 is 5.96 mm * 3.44 mm. The rest will not be elaborated. In order to make the epitaxial unit 200 meet the product requirements, when cutting the initial epitaxial wafer, the preset cutting channel can be set according to the size of the epitaxial unit to ensure that the subsequent obtained epitaxial unit 200 meets the product requirements.

[0096] Table 1

[0097] Product Dimensions (inch) Length and Width of Display Area (mm * mm) Length and Width of Epitaxial Unit (mm * mm) 0.13 2.5*2.5 2.7*2.7 0.26 5.76*3.24 5.96*3.44 0.39 8.64*4.86 8.84*5.06 0.52 11.52*6.48 11.72*6.68

[0098] 5. After the substrate material of the preset cutting channel forms a modified layer, the modified layer can be fractured by mechanical force to form multiple independent epitaxial units 200 with preset sizes. Specifically, a dicing machine can be used to achieve dicing. The sizes of the multiple epitaxial units 200 can be the same or different. It can be understood that the size of the epitaxial unit 200 is much smaller than the first size. The epitaxial unit 200 includes a substrate 201, and an epitaxial layer 202 and a first bonding material layer 25 sequentially arranged on the substrate 201, as Figure 2 shown, Figure 2 which is a cross-sectional schematic diagram of the initial epitaxial wafer or the epitaxial unit in an embodiment of the present disclosure.

[0099] In this article, for the initial epitaxial wafer (before cutting) and the epitaxial unit (after cutting), the epitaxial layer includes a second semiconductor thin film, an active thin film, a first semiconductor thin film, and a first conductive thin film.

[0100] 6. Attach the surfaces of the obtained multiple independent epitaxial units 200 that are away from the first temporary substrate to the second temporary substrate 62, and remove the first temporary substrate 61 so that the surface of the first bonding material layer 25 is exposed.

[0101] 7. Clean the surfaces of the first bonding material layers 25 of each epitaxial unit 200, and perform PL spectral detection on each epitaxial unit 200 to screen out the epitaxial units 200 with better PL spectral consistency.

[0102] 8. Remove the second temporary substrate 62. For example, the second temporary substrate 62 can be a UV film and can be removed by laser irradiation; provide a driving motherboard 100, on which a second bonding material layer 12 is provided, and bond the first bonding material layer 25 of the epitaxial unit 200 and the second bonding material layer 12 on the driving motherboard 100 to form an insulating bonding layer 40 (as Figure 4B shown).

[0103] Figure 4A is a schematic plan view of the epitaxial unit bonded to the driving motherboard in an embodiment of the present disclosure, Figure 4B is Figure 4A the schematic cross-sectional view taken along A-A in Figure 4B which shows two epitaxial units 200. After the first bonding material layer 25 of each epitaxial unit 200 is bonded to the second bonding material layer 12, each epitaxial unit 200 is bonded to the driving motherboard 100. As shown in Figure 4A and the figure, a gap is provided between two adjacent epitaxial units 200.

[0104] In actual implementation, multiple epitaxial units 200 are bonded to a driving motherboard 100 with a larger size at the same time, and the sizes of the multiple epitaxial units 200 bonded to the same driving motherboard 100 can be the same or different.

[0105] Since both the first bonding material layer 25 and the second bonding material layer 12 include silicon, in order to achieve the bonding connection between the two, an activation process can be used to bond the first bonding material layer 25 and the second bonding material layer 12. For example, the materials of the first bonding material layer 25 and the second bonding material layer 12 both include SiO2, and the bonding process of SiO2 and SiO2 is as shown in Figure 5 shown and is briefly described as follows: The surface of SiO2 can be bombarded with plasma of nitrogen N2 or oxygen O2 to break the O-Si-O bonds in SiO2 to form Si dangling bonds Si-; then it is rinsed with deionized water so that the -OH bonds in the water combine with the Si- bonds to form Si-OH bonds; the Si-OH bonds combine with each other to form a covalent bond Si-O-Si, that is, Si-OH + HO-Si → Si-O-Si + H2O, to achieve the bonding connection of SiO2 and SiO2.

[0106] After multiple epitaxial units 200 are bonded to the driving motherboard 100, the process enters the latter stage of the light-emitting panel preparation process, and the specific process of the latter stage will be described in detail below.

[0107] 1. Remove the substrate 201 of each epitaxial unit 200 by using a dissociation process. For example, a laser lift-off (LLO) process can be used to remove the substrate 201 on the epitaxial unit 200. After the substrate 201 is removed, the surface of the second semiconductor layer 22 is exposed. It can be understood that since the second semiconductor thin film 220 is in direct contact with the substrate 201, when the substrate 201 is removed by LLO, the laser will cause GaN to decompose into nitrogen gas and metallic Ga, and then metallic gallium (Ga) will remain on the exposed surface of the second semiconductor layer 22. Therefore, an acid cleaning process is required to remove the residual metallic Ga on the surface of the epitaxial layer 202, and then isopropyl alcohol and deionized water are used to rinse the surface of the epitaxial layer 202.

[0108] 2. Form an insulating filling layer 203 between each epitaxial unit 200 by using an insulating material. The surface of the insulating filling layer 203 away from the driving backplane is flush with the surface of each epitaxial unit 200 away from the driving backplane, as Figure 6 and Figure 7 shown, Figure 6 is a plan view after filling the insulating material in the area outside the epitaxial unit on the driving motherboard, Figure 7 is Figure 6 the cross-sectional view taken along line A-A in Figure 7 . The insulating material can be at least one of SiO2, SiNC, SOG materials, and BCB materials. As can be seen from

[0109] 3. Pixelate the epitaxial layer of the epitaxial unit. The specific process of pixelation can be described in detail in combination with Figures 8 - 16 and Figures 8 - 16 are all illustrated by the cross-sectional view taken along line B-B in Figure 6 . For an epitaxial unit, a part of the driving motherboard corresponding to it can be called a driving backplane.

[0110] Pattern the epitaxial layer 202 of all epitaxial units to form a plurality of mutually separated light-emitting units 20. In an embodiment of the present disclosure, the epitaxial layer 202 can be patterned by using two patterning processes, specifically including a first patterning process and a second patterning process.

[0111] First patterning process: Perform a first patterning process on the epitaxial layer 202 to form a plurality of mutually separated initial light-emitting units 20', as Figure 8 shown,Figure 8 This is a schematic diagram after the formation of initial light-emitting units in the preparation process of a light-emitting panel according to an embodiment of the present disclosure. Exemplarily, a photoresist can be coated on the epitaxial layer 202, and the photoresist is exposed and developed to form a photoresist mask. The area of the photoresist mask outside the initial light-emitting units 20 is a hollowed-out area; the epitaxial layer 202 in the hollowed-out area is etched, and the second semiconductor thin film 220, the active thin film 230, the first semiconductor thin film 210, and the first conductive thin film 240 in the hollowed-out area are etched through to form a plurality of separated initial light-emitting units 20'. The initial light-emitting units 20' include a first electrode layer 24, an initial first semiconductor layer 21', an initial active layer 23', and an initial second semiconductor layer 22' stacked in sequence. The shape of the orthographic projection of the initial light-emitting units 20' on the driving motherboard 100 can be a polygon, a circle, an ellipse, etc., and the specific shape can be set as needed. The cross-section of the initial light-emitting units 20' in a plane perpendicular to the driving motherboard 100 can be a regular trapezoid, as Figure 8 shown. The maximum size of the orthographic projection of the initial light-emitting units 20' on the driving motherboard 100 is 3 μm to 5 μm. The material of the first electrode layer 24 can be a conductive material, such as a conductive metal, or a transparent conductive material, such as ITO, IZO, etc.

[0112] Since the bonding metal layer composed of heavy metals is not etched in the first patterning process, but mainly the gallium nitride material and the transparent conductive material are etched, ICP etching can be used, and it is not necessary to use IBE to etch through the bonding metal layer. In this way, the problem of too large a gap between adjacent light-emitting units 20 caused by using IBE to etch through the bonding metal layer can be avoided, and thus a smaller gap between two adjacent light-emitting units 20 can be ensured, which is beneficial to improving the pixel density of the display area and the resolution.

[0113] Second patterning process: The initial first semiconductor layer 21', the initial active layer 23', and the initial second semiconductor layer 22' are subjected to a second patterning process to respectively form a first semiconductor layer 21, an active layer 23, and a second semiconductor layer 22. The stacked structure formed by the first semiconductor layer 21, the active layer 23, and the second semiconductor layer 22 can be called a light-emitting body. Since the second patterning is carried out on the basis of the first patterning, the light-emitting body etched out in the second patterning process is within the range of the first electrode layer 24, and there is an area of the first electrode layer 24 outside the light-emitting body. At least a part of the area of the first electrode layer 24 outside the first semiconductor layer 21 forms a lapping part, as Figure 9 shown, Figure 9This is a schematic diagram after forming a light-emitting unit in the preparation process of a light-emitting panel according to an embodiment of the present disclosure. In a specific implementation, during the second etching, the initial first semiconductor layer 21', the initial active layer 23', and the initial second semiconductor layer 22' located in the overlapping portion region can be etched away, so that the overlapping portion 241 of the first electrode layer 24 is exposed. The shape and size of the overlapping portion 241 can be set as needed. The overlapping portion 241 forms a step between the light-emitting body and the insulating bonding layer 40. In the second patterning process, the initial first semiconductor layer 21', the initial active layer 23', and the initial second semiconductor layer 22' can be etched by ICP etching.

[0114] A first via hole K1 penetrating the insulating bonding layer 40 is formed, and the orthographic projection of the first via hole K1 on the driving mother board 100 overlaps at least partially with the corresponding control electrode 11. The insulating bonding layer 40 is etched to form the first via hole K1. The first via hole K1 is located in a region outside the light-emitting unit 20, or in other words, the orthographic projection of the first via hole K1 on the driving mother board 100 does not overlap with the orthographic projection of the light-emitting unit 20 on the driving mother board 100. The orthographic projection of the first via hole K1 on the driving mother board 100 overlaps at least partially with the corresponding control electrode 11, so that at least part of the surface of the control electrode 11 is exposed through the first via hole K1, as Figure 10 shown Figure 10 This is a schematic diagram after forming the first via hole in the preparation process of a light-emitting panel according to an embodiment of the present disclosure. Since the material of the insulating bonding layer 40 is not a bonding metal layer composed of heavy metals, but an insulating material, when etching the first via hole K1, IBE etching does not need to be used, and the ICP etching process is used to etch out the first via hole K1.

[0115] In this embodiment, the patterning process of the epitaxial layer 202 includes a first patterning process and a second patterning process. In this case, the sequence of the second patterning process and the step of forming the first via hole K1 can be set as needed, that is, the initial first semiconductor layer 21, the initial active layer 23, and the initial second semiconductor layer 22 can be subjected to the second patterning process first, and then the first via hole K1 penetrating the insulating bonding layer 40 is formed; or, the first via hole K1 penetrating the insulating bonding layer 40 can be formed first, and then the initial first semiconductor layer 21, the initial active layer 23, and the initial second semiconductor layer 22 are subjected to the second patterning process.

[0116] In another embodiment, a gray-tone mask may be used to pattern the epitaxial layer 202 once to form the light-emitting units 20. For example, photoresist is coated on the epitaxial layer 202, and the gray-tone mask is used to expose and develop the photoresist to form a photoresist mask. The area of the photoresist mask outside the initial light-emitting units 20 is a hollowed-out area. The photoresist mask includes a first-thickness photoresist located in the light-emitting body area and a second-thickness photoresist located in the overlapping part area, and the first thickness is greater than the second thickness; the epitaxial layer 202 in the hollowed-out area is etched to etch away the second semiconductor thin film 220, the active thin film 230, the first semiconductor thin film 210, and the first conductive thin film 240 in the hollowed-out area, forming a plurality of initial light-emitting units 20' separated from each other; the photoresist is ashed, the second-thickness photoresist is removed, and the first-thickness photoresist is thinned to a third-thickness photoresist, and the initial first semiconductor layer 21', the initial active layer 23', and the initial second semiconductor layer 22' in the second-thickness photoresist area are etched away, and the exposed first electrode layer 24 forms the overlapping part 241.

[0117] After forming the first vias K1, a connection trace 31 is formed on the side of the first electrode layer 24 facing away from the driving motherboard 100. The connection trace 31 is located outside the first semiconductor layer 21. The connection trace 31 overlaps and is coupled to the overlapping part 241 and is coupled to the control electrode 11 through the first vias K1, as Figure 11 shown Figure 11 is a schematic diagram after forming the connection trace during the preparation process of a light-emitting panel according to an embodiment of the present disclosure. The connection trace 31 may be made of a conductive material. For example, the material of the connection trace 31 may be a conductive metal, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc. Alternatively, the material of the connection trace 31 may be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The number of connection traces 31 is multiple, and multiple control electrodes 11, multiple light-emitting units 20, multiple first vias K1, and multiple connection traces 31 are arranged in one-to-one correspondence. The connection trace 31 overlaps and is coupled to the corresponding overlapping part and is coupled to the corresponding control electrode 11 through the corresponding first vias K1.

[0118] In the related art, in order to connect the first electrode layer 24 to the control electrode 11, a first conductive column is provided in the first bonding material layer 25, and a second conductive column is provided in the second bonding material layer 12. The second conductive column is connected to the control electrode 11. When bonding the first bonding material layer 25 and the second bonding material layer 12, it is necessary to accurately align the first conductive column in the first bonding material layer 25 with the second conductive column in the second bonding material layer 12, and then anneal at a high temperature to connect the first conductive column and the second conductive column, so as to realize the connection between the first electrode layer 24 and the control electrode 11. In such a way, the requirement for alignment accuracy is relatively high, and a high-temperature annealing process is also required after the bonding process, which increases the preparation steps and process difficulty, and the production cost is relatively high. In the present disclosure, the first bonding material layer 25 and the second bonding material layer 12 do not need to be accurately aligned, and only bonding is required, which reduces the process difficulty; moreover, by forming the first via hole K1 and the connection trace 31, the first electrode layer 24 is connected to the control electrode 11 exposed by the first via hole K1 through the connection trace 31, which reduces the process difficulty of connecting the first electrode layer 24 and the control electrode 11 and reduces the cost.

[0119] A passivation layer 32 is formed on the side of the light-emitting unit 20 and the connection trace 31 facing away from the driving mother board 100, as Figure 12 shown. Figure 12 FIG. shows a schematic diagram after forming the passivation layer in the preparation process of a light-emitting panel according to an embodiment of the present disclosure. The orthographic projections of the light-emitting unit 20 and the connection trace 31 on the driving mother board 100 are both located within the orthographic projection of the passivation layer 32 on the driving mother board 100, or in other words, the light-emitting unit 20 and the connection trace 31 are both covered by the passivation layer 32. The passivation layer 32 can protect the light-emitting unit 20 and the connection trace 31.

[0120] A reflective layer 33 is formed on the side of the passivation layer 32 facing away from the driving mother board 100, as Figure 13 shown. Figure 13 FIG. shows a schematic diagram after forming the reflective layer in the preparation process of a light-emitting panel according to an embodiment of the present disclosure. The reflective layer 33 can reflect light and improve the light extraction efficiency of the light-emitting unit 20. The reflective layer 33 can be a specular reflective layer 33. For example, the material of the reflective layer 33 can be a metal with reflective properties such as aluminum, or the reflective layer 33 can be made of white glue. In another embodiment, the reflective layer 33 can be a distributed Bragg reflector (DBR).

[0121] A third patterning process is performed on the reflective layer 33 and the passivation layer 32 to form a second via hole K2. The orthographic projection of the second via hole K2 on the driving mother board 100 is located within the orthographic projection of the second semiconductor layer 22 on the driving mother board 100, so that a part of the surface of the second semiconductor layer 22 is exposed through the second via hole K2, as Figure 14 shown. Figure 14Schematic diagram after forming a second via hole in the preparation process of a light-emitting panel according to an embodiment of the present disclosure. Within the allowable range of process capabilities, the opening of the second via hole K2 is as large as possible to increase the light-emitting area of the light-emitting unit 20 and the aperture ratio. In one embodiment, during the process of forming the second via hole K2, the reflective layer 33 and the passivation layer 32 between adjacent light-emitting units 20 may also be etched to form isolation trenches between adjacent light-emitting units 20.

[0122] A second electrode 34 is formed on the side of the reflective layer 33 facing away from the driving motherboard 100. The second electrode 34 is coupled to the second semiconductor layer 22 through the second via hole K2, and a plurality of second electrodes 34 are connected to each other, as Figure 15 shown. Figure 15 Schematic diagram after forming the second electrode in the preparation process of a light-emitting panel according to an embodiment of the present disclosure. The material of the second electrode 34 includes a transparent conductive material, such as ITO or IZO, etc.

[0123] A plurality of light extraction structures 35 are formed on the side of the second electrode 34 facing away from the driving motherboard 100. The plurality of light extraction structures 35 correspond to a plurality of light-emitting bodies one by one, and the orthographic projection of the light-emitting body on the driving motherboard 100 is located within the orthographic projection of the light extraction structure 35 on the driving motherboard 100, as Figure 16 shown. Figure 16 Schematic diagram after forming the light extraction structure in the preparation process of a light-emitting panel according to an embodiment of the present disclosure. Exemplarily, a transparent material thin film may be formed on the side of the second electrode 34 facing away from the driving motherboard 100, and after processes such as etching, annealing, and remelting of the transparent material thin film, a spherical light extraction body is formed. The light extraction structure 35 is usually a part of the entire sphere. The ratio of the spherical diameter D of the spherical light extraction body to the pitch L between adjacent two light-emitting bodies is 0.8 to 1.2. For example, the ratio of D to L may be 0.8, 0.9, 1.0, 1.1, or 1.2. For example, the ratio of D to L may be less than or equal to 1, so that adjacent two light extraction structures 35 can be separated from each other and not connected, which can prevent light crosstalk between adjacent light-emitting units 20. The material of the light extraction structure 35 may be a transparent insulating material. For example, the light extraction structure 35 may include any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), or the material of the light extraction structure 35 may include an organic material, such as photoresist or polyimide (PI), etc.

[0124] When a plurality of epitaxial units 200 are bonded to the same driving motherboard 100, the subsequent process of the manufacturing method of the light-emitting panel may further include: cutting the driving motherboard 100 along a preset cutting line by a cutting process to obtain a plurality of discrete light-emitting panels, and each light-emitting panel corresponds to an epitaxial unit 200.

[0125] An embodiment of the present disclosure provides a light-emitting panel, asFigure 16 As shown, the light-emitting panel may include a driving backplane 300, an insulating bonding layer 40, a light-emitting unit 20, and a connection trace 31. The driving backplane 300 includes a control electrode 11. The insulating bonding layer 40 is located on one side of the driving backplane 300. The insulating bonding layer 40 is provided with a first via hole K1, and the orthographic projection of the first via hole K1 on the driving backplane 300 overlaps at least partially with the corresponding control electrode 11. At least part of the surface of the control electrode 11 is exposed through the first via hole K1.

[0126] The light-emitting unit 20 is located on the side of the insulating bonding layer 40 away from the driving backplane 300. The orthographic projection of the light-emitting unit 20 on the driving backplane 300 does not overlap with the orthographic projection of the first via hole K1 on the driving backplane 300. The light-emitting unit 20 includes a first electrode layer 24 and a light-emitting body. The light-emitting body is located on the side of the first electrode layer 24 away from the driving backplane 300, and the light-emitting body includes a first semiconductor layer 21, an active layer 23, and a second semiconductor layer 22 stacked in sequence. The orthographic projection of the light-emitting body on the driving backplane 300 is located within the orthographic projection of the first electrode layer 24 on the driving backplane 300, and at least part of the first electrode layer 24 located outside the light-emitting body forms a lapping portion.

[0127] The connection trace 31 is located on the side of the first electrode layer 24 away from the driving backplane 300 and outside the light-emitting body. The connection trace 31 is lapped and coupled with the lapping portion and is coupled with the control electrode 11 through the first via hole K1.

[0128] The numbers of the control electrode 11, the first via hole K1, the light-emitting unit 20, and the connection trace 31 may all be multiple. The multiple control electrodes 11, the multiple first via holes K1, the multiple light-emitting units 20, and the multiple connection traces 31 correspond one by one. The connection trace 31 connects the lapping portion of the corresponding first electrode layer 24 with the control electrode 11 to realize the connection between the light-emitting unit 20 and the driving backplane 300. Thus, the driving backplane 300 can control the light-emitting unit 20 to emit light.

[0129] In the related art, the light-emitting unit 20 and the driving backplane 300 are connected through a metal bonding layer. In order to form an independent bonding metal pad, IBE etching needs to be performed on the metal bonding layer, resulting in too large a spacing between adjacent LEDs.

[0130] In the light-emitting panel of the embodiment of the present disclosure, the light-emitting unit 20 and the driving backplane 300 are fixedly connected through the insulating bonding layer 40. The insulating bonding layer 40 is provided with a first via hole K1. The first electrode layer 24 in the light-emitting unit 20 is coupled with the control electrode 11 at the position of the first via hole K1 through the connection trace 31. Such a light-emitting panel does not need to realize electrical connection through a metal bonding layer. Thus, it is no longer necessary to Figure 17The steps of patterning the metal bonding layer by IBE as shown avoid the problem that a too large gap is required between adjacent light-emitting units when using IBE to etch the metal bonding layer, enabling a smaller gap to be maintained between adjacent LEDs, which is beneficial to increasing the pixel density and achieving a higher PPI.

[0131] The material of the first electrode layer 24 may include a transparent conductive material, such as ITO or IZO. The first electrode layer 24 may serve as the anode of the LED.

[0132] One of the first semiconductor layer 21 and the second semiconductor layer 22 may be a P-type doped semiconductor layer, and the other may be an N-type doped semiconductor layer. The P-type doped semiconductor layer may be a p-type nitride semiconductor layer containing In x Al y Ga 1-x-y N (0 ≤ x < 1, 0 ≤ y < 1, 0 ≤ x + y < 1), and the p-type impurity may be magnesium. For example, the material of the P-type doped semiconductor layer may include P-type doped gallium nitride (GaN). The N-type doped semiconductor layer may be an n-type nitride semiconductor layer containing In x Al y Ga 1-x-y N (0 ≤ x < 1, 0 ≤ y < 1, 0 ≤ x + y < 1), and the n-type impurity may be silicon. For example, the material of the N-type doped semiconductor layer may include N-type doped gallium nitride (GaN).

[0133] The second semiconductor layer 22 may be a single-layer structure, but in some exemplary embodiments, it may have a multi-layer structure containing different components. The active layer 23 may have a multi-quantum well (MQW) structure, in which the quantum well layer and the quantum barrier layer are stacked alternately with each other. For example, the quantum well layer and the quantum barrier layer may respectively include In x Al y Ga 1-x-y N (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1) with different components. In one example, the quantum well layer may include In x Ga 1-x N (0 < x ≤ 1), and the quantum barrier layer may include GaN or AlGaN. The active layer 23 is not limited to the MQW structure and may have a single quantum well (SQW) structure.

[0134] The control electrode 11 may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0135] In one embodiment, the material of the insulating bonding layer 40 may include silicon. The insulating bonding layer 40 includes a first bonding material layer 25 and a second bonding material layer 12 which are stacked. The second bonding material layer 12 is closer to the driving backplane 300 than the first bonding material layer 25, and the first bonding material layer 25 and the second bonding material layer 12 are bonded together.

[0136] The light-emitting panel may further include a reflective layer 33 and a second electrode 34. The reflective layer 33 is located on the side of the light-emitting unit 20 and the connection trace 31 facing away from the driving backplane 300. The reflective layer 33 is provided with a second via hole K2, and the orthographic projection of the second via hole K2 on the driving backplane 300 is located within the orthographic projection of the second semiconductor layer 22 on the driving backplane 300. The second electrode 34 is located on the side of the reflective layer 33 facing away from the driving backplane 300, and the second electrode 34 is coupled to the second semiconductor layer 22 through the second via hole K2. The second electrodes 34 corresponding to the plurality of light-emitting units 20 are connected to each other.

[0137] The light-emitting panel may further include a passivation layer 32. The passivation layer 32 is located between the light-emitting unit 20 and the reflective layer 33, and is also located between the connection trace 31 and the reflective layer 33. The second via hole K2 also penetrates through the passivation layer 32. In the case where the light-emitting panel does not have the passivation layer 32, the reflective layer 33 needs to be an insulating reflective layer 33. For example, white glue can be used to form the reflective layer 33, or the reflective layer 33 may include a DBR. The passivation layer 32 can play an insulating and protective role, and the passivation layer 32 can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer.

[0138] The light-emitting panel may further include a plurality of light extraction structures 35, and the plurality of light extraction structures 35 correspond to the plurality of light-emitting bodies one by one. The light extraction structure 35 is located on the side of the second electrode 34 facing away from the driving backplane 300, and the orthographic projection of the light-emitting body on the driving backplane 300 is located within the orthographic projection of the light extraction structure 35 on the driving backplane 300. Thus, the light emitted by the light-emitting body can enter the light extraction structure 35 and be extracted by the light extraction structure 35, improving the pixel light-emitting brightness.

[0139] The light extraction structure 35 includes a spherical light extraction body, and the ratio of the spherical diameter of the spherical light extraction body to the distance between two adjacent light-emitting bodies is 0.8 to 1.2.

[0140] Based on the inventive concept of the foregoing embodiment, the embodiments of the present disclosure further provide a light-emitting device, and the light-emitting device includes the light-emitting panel of the foregoing embodiment. The light-emitting device may include a display device.

[0141] The light-emitting panel in the embodiments of the present disclosure can be assembled as a display panel in a display device, or can be assembled as a light source in a display device. The display device can be: an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a wearable display device, or any product or component with a display function.

[0142] The light-emitting panel in the embodiments of the present disclosure can also be used as a light-emitting source in lighting products.

[0143] In the description of this specification, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present disclosure.

[0144] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present disclosure, "a plurality of" means two or more, unless otherwise specifically defined.

[0145] In the present disclosure, unless otherwise clearly specified and limited, the terms "mounted", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection, an electrical connection, or a communication connection; it can be directly connected, or indirectly connected through an intermediate medium, and can be the internal connection or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0146] In this disclosure, unless otherwise expressly specified and defined, a first feature being "on" or "under" a second feature may include direct contact between the first and second features, or may include contact between the first and second features through additional features therebetween rather than direct contact. Moreover, a first feature being "above", "over" and "on top of" a second feature includes the first feature being directly above and diagonally above the second feature, or merely indicating that the first feature has a higher level height than the second feature. A first feature being "under", "below" and "beneath" a second feature includes the first feature being directly below and diagonally below the second feature, or merely indicating that the first feature has a lower level height than the second feature.

[0147] The foregoing disclosure provides many different embodiments or examples for implementing different structures of the present disclosure. For the sake of simplifying the present disclosure, the components and settings of specific examples are described above. Of course, they are merely examples and are not intended to limit the present disclosure. In addition, the present disclosure may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and in itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0148] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of various changes or substitutions thereof. Different parts in different embodiments can be combined with each other without conflict, and all of these should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A light-emitting panel, characterized in that: include: A driving backplane, including control electrodes; an insulating bonding layer, located on one side of the driving backplane, the insulating bonding layer being provided with a first via hole, the orthographic projection of the first via hole on the driving backplane at least partially overlapping with the corresponding control electrode; a light-emitting unit, located on a side of the insulating bonding layer away from the driving backplane, wherein an orthographic projection of the light-emitting unit on the driving backplane does not overlap with an orthographic projection of the first via hole on the driving backplane, wherein the light-emitting unit comprises a first electrode layer and a light-emitting body, wherein the light-emitting body is located on a side of the first electrode layer away from the driving backplane, wherein the light-emitting body comprises a first semiconductor layer, an active layer, and a second semiconductor layer which are sequentially stacked, and wherein at least a portion of the first electrode layer located outside the light-emitting body forms an overlap portion; The connecting wire is located on a side of the first electrode layer away from the driving backplane and outside the light-emitting body. The connecting wire is overlapped and coupled with the overlapping portion and is coupled with the control electrode through the first via hole.

2. The light emitting panel according to claim 1, characterized in that: The material of the insulating bonding layer includes silicon.

3. The light emitting panel according to claim 1, characterized in that: The insulating bonding layer includes a first bonding material layer and a second bonding material layer which are stacked, the second bonding material layer is closer to the driving backplane relative to the first bonding material layer, and the first bonding material layer and the second bonding material layer are bonded to each other.

4. The light emitting panel according to claim 1, characterized in that: Also includes: a reflective layer, located on a side of the light-emitting unit and the connecting wire away from the driving backplane, the reflective layer being provided with a second via hole, and an orthographic projection of the second via hole on the driving backplane being located within an orthographic projection of the second semiconductor layer on the driving backplane; The second electrode is located at a side of the reflective layer away from the driving back plate, and the second electrode is coupled to the second semiconductor layer through the second via hole.

5. The light emitting panel according to claim 4, characterized in that: It also includes a passivation layer, which is located between the light-emitting unit and the reflective layer, and also between the connecting wire and the reflective layer. The second via hole also penetrates the passivation layer.

6. The light emitting panel according to claim 2, characterized in that: The second electrodes corresponding to the plurality of light-emitting units are connected to each other; The light-emitting panel also includes a plurality of light-collecting structures, which correspond one-to-one to the plurality of light-emitting bodies. The light-collecting structures are located on the side of the second electrode away from the driving backplane, and the orthographic projection of the light-emitting body on the driving backplane is located within the orthographic projection of the light-collecting structures on the driving backplane.

7. The light emitting panel according to claim 6, characterized in that: The light-collecting structure includes a spherical light-collecting body, and the ratio of the spherical diameter of the spherical light-collecting body to the distance between two adjacent light-emitting bodies is 0.8 to 1.

2.

8. A method for preparing a light-emitting panel, characterized in that: include: An epitaxial unit and a driving backplane are provided, wherein the epitaxial unit comprises an epitaxial layer and a first bonding material layer sequentially arranged on a substrate; the driving backplane comprises a control electrode, and a second bonding material layer is arranged on a surface of the driving backplane where the control electrode is arranged; Bonding the first bonding material layer and the second bonding material layer to form an insulating bonding layer; removing the substrate; The epitaxial layer is patterned to form a plurality of light-emitting units separated from each other, wherein the light-emitting unit comprises a first electrode layer and a light-emitting body which are stacked, wherein the light-emitting body is located on a side of the first electrode layer away from the driving backplane, and wherein the light-emitting body comprises a first semiconductor layer, an active layer, and a second semiconductor layer which are stacked in sequence, and wherein at least a portion of the first electrode layer located outside the light-emitting body forms an overlap portion; forming a first via hole penetrating the insulating bonding layer, wherein an orthographic projection of the first via hole on the driving backplane at least partially overlaps with the corresponding control electrode; A connecting wire is formed on a side of the first electrode layer away from the driving backplane. The connecting wire is located outside the first semiconductor layer. The connecting wire is overlapped and coupled with the overlapping portion and is coupled with the control electrode through the first via hole.

9. The method according to claim 8, characterized in that: The patterning of the epitaxial layer comprises: Performing a first patterning process on the epitaxial layer to form a plurality of initial light-emitting units separated from each other, wherein the initial light-emitting units include the first electrode layer, the initial first semiconductor layer, the initial active layer and the initial second semiconductor layer stacked in sequence; The initial first semiconductor layer, the initial active layer and the initial second semiconductor layer are subjected to a second patterning process to form the first semiconductor layer, the active layer and the second semiconductor layer respectively.

10. The method according to claim 8, characterized in that: Also includes: A passivation layer and a reflective layer are sequentially formed on a side of the light emitting unit and the connecting wiring away from the driving backplane; Performing a third patterning process on the reflective layer and the passivation layer to form a second via hole, wherein the orthographic projection of the second via hole on the driving backplane is located within the orthographic projection of the second semiconductor layer on the driving backplane; A second electrode is formed on a side of the reflective layer away from the driving backplane, the second electrode is coupled to the second semiconductor layer through the second via hole, and a plurality of the second electrodes are connected to each other.

11. The method according to claim 8, characterized in that Also includes: A plurality of light-collecting structures are formed on a side of the second electrode away from the driving backplane, the plurality of light-collecting structures correspond one-to-one to a plurality of light-emitting bodies, and the orthographic projections of the light-emitting bodies on the driving backplane are located within the orthographic projections of the light-collecting structures on the driving backplane.

12. The method according to any one of claims 8 to 11, characterized in that The step of bonding the first bonding material layer and the second bonding material layer together comprises: The first bonding material layer and the second bonding material layer are bonded and connected by using an activation process.

13. The method according to any one of claims 8 to 11, characterized in that: Before patterning the epitaxial layer, the method further includes: An insulating material is filled on a side of the driving back plate facing the epitaxial layer to form an insulating filling layer, and a surface of the insulating filling layer is flush with a surface of the epitaxial layer.

14. A light emitting device, characterized in that: A light-emitting panel comprising any one of claims 1-7.

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