Display panel and display device

Abstract

Provided are a display panel and a display device. The display panel comprises a base substrate (SBT), a driving layer (DRL) and a pixel layer (PIXL) which are sequentially stacked; the display panel comprises circuit regions (PA) distributed in an array, and one pixel driving circuit for driving sub-pixels is provided in one circuit region (PA); the driving layer (DRL) is provided with data signal wires (DL), and each pixel driving circuit is provided with a data write transistor (T4) electrically connected to the corresponding data signal wire (DL); the orthographic projection of a channel region (T4A) of the data write transistor on the base substrate (SBT) at least partially overlaps the orthographic projection of the data signal wire (DL) on the base substrate (SBT). The display panel and the display device using the display panel can improve pixel density.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, the demand for high PPI (pixel density) LTPO (low-temperature polycrystalline silicon semiconductor + metal oxide semiconductor) technology is becoming increasingly urgent. In order to further improve the display quality of display panels, the COE (color film process) solution can be simultaneously equipped on the basis of LTPO technology. To this end, a high sensor aperture ratio must be ensured, so pixel compression is urgently needed to meet the compatibility of the two.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a display panel and a display device.

[0006] According to a first aspect of the present disclosure, a display panel is provided, comprising a base substrate, a driving layer, and a pixel layer stacked in sequence; the display panel has circuit areas distributed in an array, each circuit area having a pixel driving circuit for driving a sub-pixel;

[0007] The driving layer is provided with a data signal line and the pixel driving circuit has a data writing transistor electrically connected to the data signal line; the orthographic projection of the channel region of the data writing transistor on the base substrate at least partially overlaps with the orthographic projection of the data signal line on the base substrate.

[0008] According to an embodiment of the present disclosure, in two circuit areas adjacent to each other along the first direction, thin film transistors of two pixel driving circuits are symmetrically arranged;

[0009] The driving layer includes a transistor layer and a first source-drain metal layer stacked in sequence, and the thin film transistor is arranged in the transistor layer;

[0010] The driving layer has a multiplexing via hole that spans a boundary line between two adjacent circuit areas, and the first source-drain metal layer is simultaneously connected to the thin film transistors of the two pixel driving circuits through the multiplexing via hole.

[0011] According to an embodiment of the present disclosure, the display panel includes a first circuit area group distributed in an array, and the first circuit area group includes two circuit areas adjacent to each other along a first direction;

[0012] The pixel driving circuit includes a first light emitting transistor for being electrically connected to a power supply voltage terminal; the transistor layer is provided with a first polysilicon conductive structure serving as a first electrode of two first light emitting transistors in the first circuit area group;

[0013] The multiplexing via includes a first multiplexing via located in the first circuit area group, the first multiplexing via exposing the first polysilicon conductive structure;

[0014] In the first circuit area group, the first source-drain metal layer includes a power supply voltage metal structure capable of loading a power supply voltage;

[0015] The power voltage metal structure is electrically connected to the first polysilicon conductive structure through the first multiplexing via.

[0016] According to an embodiment of the present disclosure, the display panel includes a first circuit area group distributed in an array, and the first circuit area group includes two circuit areas adjacent to each other along a first direction;

[0017] The pixel driving circuit further includes a second reset transistor, wherein the second electrode of the second reset transistor is electrically connected to the second electrode of the first light emitting transistor; and the first electrode of the second reset transistor is electrically connected to the third initialization voltage terminal;

[0018] The transistor layer is provided with a second polysilicon conductive structure in the first circuit area group, which serves as the first electrode of the two second reset transistors;

[0019] The multiplexing via includes a second multiplexing via located in the first circuit area group, the second multiplexing via exposing the second polysilicon conductive structure;

[0020] In the first circuit area group, the first source-drain metal layer includes a third initialization metal structure capable of applying a third initialization voltage;

[0021] The third initialization metal structure is electrically connected to the second polysilicon conductive structure through the second multiplexing via.

[0022] According to an embodiment of the present disclosure, the display panel includes a second circuit area group distributed in an array, and the second circuit area group includes two circuit areas adjacent to each other along a first direction;

[0023] The pixel driving circuit includes a driving transistor and a first reset transistor electrically connected to a first initialization voltage terminal; a first electrode of the driving transistor is electrically connected to a second electrode of the data writing transistor, and a second electrode of the driving transistor is electrically connected to a second electrode of the first reset transistor;

[0024] The transistor layer is provided with a third polysilicon conductive structure in the second circuit area group, which serves as the first electrode of the two first reset transistors;

[0025] The multiplexing via includes a third multiplexing via located in the second circuit area group, wherein the third multiplexing via exposes the third polysilicon conductive structure;

[0026] In the second circuit area group, the first source-drain metal layer includes a first initialization metal structure capable of applying a first initialization voltage;

[0027] The first initialization metal structure is electrically connected to the third polysilicon conductive structure through the third multiplexing via.

[0028] According to an embodiment of the present disclosure, the driving layer includes a low-temperature polysilicon semiconductor layer, a metal oxide semiconductor layer, and a first source-drain metal layer stacked in sequence;

[0029] The pixel driving circuit further includes a first reset transistor, a threshold compensation transistor, a driving transistor, and a second light-emitting transistor; a first electrode of the first reset transistor is electrically connected to a first initialization voltage terminal, a second electrode of the first reset transistor, a first electrode of the threshold compensation transistor, a second electrode of the driving transistor, and a first electrode of the second light-emitting transistor are electrically connected, and a second electrode of the second light-emitting transistor is electrically connected to a pixel electrode; a second electrode of the threshold compensation transistor is electrically connected to a gate electrode of the driving transistor;

[0030] The channel region of the first reset transistor, the channel region of the drive transistor and the channel region of the second light emitting transistor are located in the low-temperature polysilicon semiconductor layer; the channel region of the threshold compensation transistor is provided in the metal oxide semiconductor layer;

[0031] The channel region of the first reset transistor, the channel region of the threshold compensation transistor, and the channel region of the second light emitting transistor are arranged in a straight line along a second direction.

[0032] According to an embodiment of the present disclosure, the transistor layer includes a low-temperature polysilicon semiconductor layer and a metal oxide semiconductor layer stacked together;

[0033] The pixel driving circuit further includes a first reset transistor, a threshold compensation transistor, a driving transistor, and a second light-emitting transistor; a first electrode of the first reset transistor is electrically connected to a first initialization voltage terminal, a second electrode of the first reset transistor, a first electrode of the threshold compensation transistor, a second electrode of the driving transistor, and a first electrode of the second light-emitting transistor are electrically connected, and a second electrode of the second light-emitting transistor is electrically connected to a pixel electrode; a second electrode of the threshold compensation transistor is electrically connected to a gate electrode of the driving transistor;

[0034] The channel region of the first reset transistor, the channel region of the drive transistor, and the channel region of the second light emitting transistor are located in the low-temperature polysilicon semiconductor layer; the channel region of the threshold compensation transistor is provided in the metal oxide semiconductor layer;

[0035] Along the first direction, the channel region of the first reset transistor and the channel region of the threshold compensation transistor are alternately arranged.

[0036] According to an embodiment of the present disclosure, in the circuit region, the metal oxide semiconductor layer includes a first metal oxide structure arranged along a first direction and a second metal oxide structure arranged along a second direction;

[0037] One end of the first metal oxide structure close to the data writing transistor and one end of the second metal oxide structure close to the driving transistor are connected to each other; the channel region of the threshold compensation transistor is located in the second metal oxide structure.

[0038] According to an embodiment of the present disclosure, the first source-drain metal layer includes a first metal structure and a second metal structure;

[0039] The second metal structure is electrically connected to the second electrode of the first reset transistor, the second electrode of the driving transistor, and the first electrode of the threshold compensation transistor through a via;

[0040] The first metal structure is electrically connected to the second electrode of the threshold compensation transistor and the gate of the driving transistor through a via;

[0041] A dimension of the second metal structure along the second direction is smaller than a dimension of the first metal structure along the second direction.

[0042] According to an embodiment of the present disclosure, the driving layer includes a low-temperature polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer, a first source-drain metal layer, and a second source-drain metal layer, which are stacked in sequence;

[0043] The first gate layer is provided with a gate of the data writing transistor, and the display panel is provided with a second scanning signal line electrically connected to the gate of the data writing transistor;

[0044] In the circuit area, the second scan signal routing line includes a first sub-scan routing line located in the first source / drain metal layer and a second sub-scan routing line located in the second source / drain metal layer;

[0045] The first sub-scanning line is electrically connected to the gate of the data writing transistor through a via hole, and the second sub-scanning line is electrically connected to the first sub-scanning line through a via hole.

[0046] According to an embodiment of the present disclosure, in the circuit area, the metal oxide semiconductor layer includes a second metal oxide structure arranged along the second direction; an end of the second metal oxide structure away from the channel region of the driving transistor is electrically connected to the gate of the driving transistor through the first metal structure located in the first source-drain metal layer;

[0047] In the circuit area, the first metal structure and the second sub-scanning trace are overlapped.

[0048] According to an embodiment of the present disclosure, the driving layer includes a low-temperature polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer and a first source-drain metal layer stacked in sequence;

[0049] The first gate layer is provided with a gate of the data writing transistor, and the display panel is provided with a first sub-scanning line electrically connected to the gate of the data writing transistor;

[0050] The first sub-scanning wiring is located in the first source-drain metal layer and is electrically connected to the gate of the data writing transistor through a via hole.

[0051] According to one embodiment of the present disclosure, in the circuit area, the metal oxide semiconductor layer includes a first metal oxide structure, a second metal oxide structure, and a third metal oxide structure connected in sequence, wherein the first metal oxide structure and the third metal oxide structure are arranged in parallel along the second direction; the second metal oxide structure is arranged along the first direction, and an end of the first metal oxide structure away from the driving transistor and an end of the third metal oxide structure away from the driving transistor are electrically connected to each other;

[0052] One end of the third metal oxide structure close to the driving transistor is electrically connected to the gate of the driving transistor through the first metal structure located in the first source-drain metal layer; one end of the first metal oxide structure close to the driving transistor is electrically connected to the second electrode of the driving transistor through the second metal structure located in the first source-drain metal layer;

[0053] The pixel driving circuit has a threshold compensation transistor, which includes two sub-transistors. Channel regions of the two sub-transistors are respectively located on the first metal oxide structure and the third metal oxide structure.

[0054] According to an embodiment of the present disclosure, the driving layer includes a low-temperature polysilicon semiconductor layer, a first source-drain metal layer, and a second source-drain metal layer stacked in sequence;

[0055] The low-temperature polysilicon semiconductor layer includes a fourth polysilicon conductive structure, and the fourth polysilicon conductive structure serves as the second electrode of the first reset transistor;

[0056] One end of the fourth polysilicon conductive structure close to the channel region of the driving transistor is electrically connected to the second electrode of the driving transistor through the second metal structure located in the first source-drain metal layer.

[0057] According to an embodiment of the present disclosure, the driving layer includes a low-temperature polysilicon semiconductor layer, a first source-drain metal layer, and a second source-drain metal layer stacked in sequence;

[0058] The low-temperature polysilicon semiconductor layer includes a fourth polysilicon conductive structure and a fifth polysilicon conductive structure, the fourth polysilicon conductive structure serving as the second electrode of the first reset transistor; the fifth polysilicon conductive structure is interconnected with the drain electrode of the driving transistor;

[0059] One end of the fourth polysilicon conductive structure close to the channel region of the driving transistor is connected to the fifth polysilicon conductive structure.

[0060] According to an embodiment of the present disclosure, the driving layer includes a low-temperature polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer and a first source-drain metal layer stacked in sequence;

[0061] The pixel driving circuit further includes a second reset transistor and a first light emitting transistor, wherein the second electrode of the second reset transistor is electrically connected to the second electrode of the first light emitting transistor; the first electrode of the second reset transistor is electrically connected to the third initialization voltage terminal; and the first light emitting transistor is electrically connected to the power supply voltage terminal;

[0062] The driving layer has a third initialization voltage wiring for loading a third initialization voltage and an enable signal wiring for loading an enable signal;

[0063] The third initialization voltage line is located in the third gate layer and extends along the first direction. The enable signal line is located in the first gate layer and extends along the first direction. The enable signal line and the third initialization voltage line are overlapped.

[0064] According to a second aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0065] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The accompanying drawings are incorporated into and constitute a part of this specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure. It is apparent that the drawings described below are merely some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0067] FIG1 is a schematic diagram of an array arrangement of circuit areas in one embodiment of the present disclosure.

[0068] FIG2 is an equivalent circuit diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0069] FIG3 is a schematic diagram of a film layer structure of a display panel in one embodiment of the present disclosure.

[0070] FIG4 is a schematic diagram of a low-temperature polysilicon semiconductor layer in one embodiment of the present disclosure.

[0071] FIG5 is a schematic diagram of a first gate layer in one embodiment of the present disclosure.

[0072] FIG6 is a schematic diagram of a second gate layer in one embodiment of the present disclosure.

[0073] FIG7 is a schematic diagram of a metal oxide semiconductor layer in one embodiment of the present disclosure.

[0074] FIG8 is a schematic diagram of a third gate layer in one embodiment of the present disclosure.

[0075] FIG9 is a schematic diagram of a first source / drain metal layer in one embodiment of the present disclosure.

[0076] FIG10 is a schematic diagram of a second source / drain metal layer in one embodiment of the present disclosure.

[0077] FIG11 is a schematic diagram of a third source / drain metal layer in one embodiment of the present disclosure.

[0078] FIG12 is a schematic diagram of a low-temperature polysilicon semiconductor layer in one embodiment of the present disclosure.

[0079] FIG13 is a schematic diagram of a first gate layer in one embodiment of the present disclosure.

[0080] FIG14 is a schematic diagram of a second gate layer in one embodiment of the present disclosure.

[0081] FIG15 is a schematic diagram of a metal oxide semiconductor layer in one embodiment of the present disclosure.

[0082] FIG16 is a schematic diagram of a third gate layer in one embodiment of the present disclosure.

[0083] FIG17 is a schematic diagram of a first source-drain metal layer in one embodiment of the present disclosure.

[0084] FIG18 is a schematic diagram of a second source-drain metal layer in one embodiment of the present disclosure.

[0085] FIG19 is a schematic diagram of a low-temperature polysilicon semiconductor layer in one embodiment of the present disclosure.

[0086] FIG20 is a schematic diagram of a first gate layer in one embodiment of the present disclosure.

[0087] FIG21 is a schematic diagram of a second gate layer in one embodiment of the present disclosure.

[0088] FIG22 is a schematic diagram of a metal oxide semiconductor layer in one embodiment of the present disclosure.

[0089] FIG23 is a schematic diagram of a third gate layer in one embodiment of the present disclosure.

[0090] FIG24 is a schematic diagram of a first source-drain metal layer in one embodiment of the present disclosure.

[0091] FIG25 is a schematic diagram of a low-temperature polysilicon semiconductor layer in one embodiment of the present disclosure.

[0092] FIG26 is a schematic diagram of a first gate layer in one embodiment of the present disclosure.

[0093] FIG27 is a schematic diagram of a second gate layer in one embodiment of the present disclosure.

[0094] FIG28 is a schematic diagram of a metal oxide semiconductor layer in one embodiment of the present disclosure.

[0095] FIG29 is a schematic diagram of a third gate layer in one embodiment of the present disclosure.

[0096] FIG30 is a schematic diagram of a first source-drain metal layer in one embodiment of the present disclosure.

[0097] FIG31 is a schematic diagram showing an overlapping portion between a data signal line and a channel region of a data writing transistor in one embodiment of the present disclosure.

[0098] Description of reference numerals:

[0099] T1, first reset transistor; T2, threshold compensation transistor; T3, drive transistor; T4, data write transistor; T5, first light-emitting transistor; T6, second light-emitting transistor; T7, electrode reset transistor; T8, second reset transistor; Cst, storage capacitor; CP1, first electrode; CP2, second electrode; Vinit1, first initialization voltage; Vinit2, second initialization voltage; Vinit3, third initialization voltage; N1, first node; N2, second node; N3, third node; N4, fourth node; ResetH, first capacitor reset control signal; ResetP, second capacitor reset control signal; EM, enable signal; GN, first scan signal; Dat a, data signal; GP, second scanning signal; VDD, power supply voltage; VSS, reference voltage; T1A, channel region of the first reset transistor; T2A, channel region of the threshold compensation transistor; T3A, channel region of the drive transistor; T4A, channel region of the data write transistor; T5A, channel region of the first light-emitting transistor; T6A, channel region of the second light-emitting transistor; T7A, channel region of the electrode reset transistor; T8A, channel region of the second reset transistor; HB1, first upper via region; HB2, second upper via region; HB3, third upper via region; HB4, fourth upper via region; HB5, fifth upper via region; HB6, sixth upper via region; HB7, seventh upper via region; HB8, eighth upper via region HB9, the ninth upper via area; HB10, the tenth upper via area; HB11, the eleventh upper via area; HB12, the twelfth upper via area; HB13, the thirteenth upper via area; HB14, the fourteenth upper via area; HB15, the fifteenth upper via area; HB16, the sixteenth upper via area; HB17, the seventeenth upper via area; HA1, the first lower via area; HA2, the second lower via area; HA3, the third lower via area; HA4, the fourth lower via area; HA5, the fifth lower via area; HA6, the sixth lower via area; HA7, the seventh lower via area; HA8, the eighth lower via area; HA9, the ninth lower via area; HA10, the tenth lower via area; HA11, the eleventh lower via area; HA12, the tenth The second lower via area; HA13, the thirteenth lower via area; HA14, the fourteenth lower via area; HA15, the fifteenth lower via area; HA16, the sixteenth lower via area; HA17, the seventeenth lower via area; HA18, the eighteenth lower via area; HB18, the eighteenth upper via area; HA19, the nineteenth lower via area; HB19, the nineteenth upper via area; HA20, the twentieth lower via area; HB20, the twentieth upper via area; HA21, the twenty-first lower via area; HB21, the twenty-first upper via area; HA22, the twenty-second lower via area; HB22, the twenty-second upper via area; HA23, the twenty-third lower via area; HB23, the twenty-third upper via area; HA24, the twenty-fourth lower via area;HB24, the 24th upper via area; HA25, the 25th lower via area; HB25, the 25th upper via area; HA26, the 26th lower via area; HB26, the 26th upper via area; HA27, the 27th lower via area; HB27, the 27th upper via area; HA28, the 28th lower via area; HB28, the 28th upper via area; HA29, the 29th lower via area; HB29, the 29th upper via area; RL1, the first capacitor reset control signal line; RL2, the second capacitor reset control signal line; EML, the enable signal line; GNLA, the first scan signal first line; GNLB, the second scan signal second line; GPL, the second scan signal line; G PL1, first sub-scanning line; GPL2, second sub-scanning line; H1, first direction; H2, second direction; VLT1, first initialization voltage line; VLT2, second initialization voltage line; VLT3, third initialization voltage line; SBT, substrate; DRL, drive layer; TL, transistor layer; LSCL, low-temperature polysilicon semiconductor layer; Buff1, first buffer layer; Buff2, second buffer layer; GI1, first gate insulating layer; GI2, second gate insulating layer; GT1, first gate layer; GT2, second gate layer; GT3, third gate layer; ILD, interlayer dielectric layer; SD1, first source and drain metal layer; SD2, second source and drain metal layer; SD3, The third source-drain metal layer; PLN1, the first planarization layer; PLN2, the second planarization layer; OSCL, the metal oxide semiconductor layer; PLN3, the third planarization layer; PDL, the pixel definition layer; PEL, the pixel electrode layer; COML, the common electrode layer; EL, the light-emitting functional layer; PIX, the sub-pixel; TFE, the thin film encapsulation layer; MA1, the first bridge portion; MA2, the second bridge portion; MA3, the third bridge portion; MA4, the fourth bridge portion; MA5, the fifth bridge portion; MA6, the sixth bridge portion; MA7, the seventh bridge portion; MA9, the ninth bridge portion; MA10, the tenth bridge portion; MB1, the first conductive portion; MB2, the second conductive portion; MB3, the third conductive portion; MB4, Fourth conductive portion; MC1, first metal portion; MH, multiplexing via; MHA, first multiplexing via; MHB, second multiplexing via; MHC, third multiplexing via; PLA, first polysilicon conductive structure; PLB, second polysilicon conductive structure; PLC, third polysilicon conductive structure; PLD, fourth polysilicon conductive structure; PLE, fifth polysilicon conductive structure; MS1, first metal structure; MS2, second metal structure; OLA, first metal oxide structure; OLB, second metal oxide structure; OLC, third metal oxide structure; SWL, spare signal trace; DL, data signal trace; PA, circuit area; PAS1, first circuit area group; PAS2, second circuit area group. DETAILED DESCRIPTION

[0100] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0101] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0102] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0103] Structural layer A is located on the side of structural layer B facing away from the base substrate. This means that structural layer A is formed on the side of structural layer B facing away from the base substrate. When structural layer B is a patterned structure, part of structural layer A may also be located at the same physical height as structural layer B or lower than the physical height of structural layer B, with the base substrate serving as a height reference.

[0104] In an embodiment of the present disclosure, a thin film transistor includes an active layer, a gate insulating layer and a gate that are stacked. The active layer is located in the semiconductor layer, and the active layer includes a channel region and a source and a drain located on both sides of the channel region. The channel region maintains semiconductor properties, and the source and the drain are both conductive. In an embodiment of the present disclosure, when using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged, that is, the "source" and the "drain" can be interchanged. In an embodiment of the present disclosure, for any transistor, one of the "source" and the "drain" is referred to as the first electrode of the transistor, and the other is referred to as the second electrode of the transistor.

[0105] With the rapid development of the display industry, people are pursuing higher and higher picture quality for display panels, and at the same time, the demand for high-PPI LTPO technology is becoming increasingly strong. In order to further improve the picture quality of display panels, the COE solution will be installed on the LTPO technology at the same time. Therefore, it is necessary to ensure a higher sensor aperture rate, so pixel compression is urgently needed to meet the compatibility of the two.

[0106] Based on this, an embodiment of the present disclosure provides a display panel. FIG3 is a schematic diagram of the film layer structure of a display panel in an exemplary embodiment of the present disclosure. Referring to FIG3 , the display panel includes a base substrate SBT, a drive layer DRL, and a pixel layer PIXL stacked in sequence. The display panel has an array of circuit areas PA, each of which has a pixel drive circuit for driving sub-pixels. The drive layer DRL is provided with a data signal line DL, and the pixel drive circuit has a data write transistor T4 electrically connected to the data signal line DL. The orthographic projection of the channel region T4A of the data write transistor on the base substrate SBT at least partially overlaps with the orthographic projection of the data signal line DL on the base substrate SBT (see FIG31 ).

[0107] In the embodiment of the present disclosure, the orthographic projection of the data signal line DL on the substrate SBT overlaps with the orthographic projection of the channel region T4A of the data writing transistor on the substrate SBT, thereby achieving compression of the pixel driving circuit, effectively reducing the size of a single pixel driving circuit, and thereby helping to improve the pixel density of the display panel.

[0108] See Figure 2, which shows an equivalent circuit diagram of a pixel driving circuit in an exemplary embodiment of the present disclosure. The pixel driving circuit may include a first reset transistor T1, a threshold compensation transistor T2, a drive transistor T3, a data write transistor T4, a first light-emitting transistor T5, a second light-emitting transistor T6, an electrode reset transistor T7, a second reset transistor T8, and a storage capacitor Cst. The first reset transistor T1 and the threshold compensation transistor T2 are N-type thin-film transistors, such as metal oxide thin-film transistors; the remaining thin-film transistors are P-type thin-film transistors, such as low-temperature polysilicon thin-film transistors.

[0109] 2 , a first electrode of the first reset transistor T1 is configured to apply a first initialization voltage Vinit1, a gate electrode is configured to apply a first capacitor reset control signal ResetP, and a second electrode of the first reset transistor T1 is connected to a third node N3. The first reset transistor T1 is configured to apply the first initialization voltage Vinit1 to the third node N3 in response to the first capacitor reset control signal ResetP.

[0110] A first electrode of the threshold compensation transistor T2 is electrically connected to the third node N3, a second electrode of the threshold compensation transistor T2 is electrically connected to the first node N1, and a gate of the threshold compensation transistor T2 is used to load the first scan signal GN; the threshold compensation transistor T2 is used to be turned on in response to the first scan signal GN to write the first initialization voltage Vinit1 of the first reset transistor T1 into the first node N1.

[0111] A first electrode of the driving transistor T3 is connected to the second node N2 , a second electrode of the driving transistor T3 is connected to the third node N3 , and a gate of the driving transistor T3 is connected to the first node N1 . The driving transistor T3 is configured to be turned on or off under the control of the first node N1 .

[0112] The first electrode of the data write transistor T4 is used to load the data signal Data, the second electrode of the data write transistor T4 is electrically connected to the second node N2, and the gate of the data write transistor T4 is used to load the second scan signal GP. The data write transistor T4 is used to be turned on in response to the second scan signal GP and load the data signal Data to the second node N2.

[0113] A first electrode of the first light emitting transistor T5 is used to load the power supply voltage VDD, a second electrode of the first light emitting transistor T5 is connected to the second node N2, and a gate of the first light emitting transistor T5 is used to load the enable signal EM.

[0114] The first electrode of the second light emitting transistor T6 is connected to the third node N3, the second electrode is connected to the fourth node, and the gate is used to load the enable signal EM. The first light emitting transistor T5 and the second light emitting transistor T6 are used to be turned on in response to the enable signal EM.

[0115] The first electrode of the electrode reset transistor T7 is used to load the second initialization voltage Vinit2, the gate of the electrode reset transistor T7 is used to load the second capacitor reset control signal ResetH, the second electrode of the electrode reset transistor T7 is connected to the fourth node N4, and the electrode reset transistor T7 is used to load the second initialization voltage Vinit2 to the fourth node N4 in response to the second capacitor reset control signal ResetH.

[0116] The first electrode of the second reset transistor T8 is used to load the third initialization voltage Vinit3, the gate of the second reset transistor T8 is used to load the second capacitor reset control signal ResetH, the second electrode of the second reset transistor T8 is connected to the second node N2, and the second reset transistor T8 is used to load the third initialization voltage Vinit3 to the second node N2 in response to the second capacitor reset control signal ResetH.

[0117] The pixel electrode of the light-emitting element is electrically connected to the pixel driving circuit (the connection between the light-emitting element and the pixel electrode is not specifically shown in this figure), the common electrode is used to load the reference voltage VSS, one end of the storage capacitor Cst is connected to the first node N1, and the other end is used to load the power supply voltage VDD.

[0118] Optionally, the substrate substrate SBT can be a substrate substrate SBT of an inorganic material, or a substrate substrate SBT of an organic material; of course, it can also be a composite substrate formed by stacking a substrate substrate SBT of an inorganic material and a substrate substrate SBT of an organic material. For example, in some embodiments of the present disclosure, the material of the substrate substrate SBT can be a glass material such as soda-lime glass, quartz glass, sapphire glass, etc. In some other embodiments of the present disclosure, the material of the substrate substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate or a combination thereof. In some other embodiments of the present disclosure, the substrate substrate SBT can also be a flexible substrate substrate SBT, for example, the material of the substrate substrate SBT can include polyimide.

[0119] Optionally, in the driving layer DRL, any pixel driving circuit may include a thin film transistor and a storage capacitor Cst (not specifically shown in the drawings of this application). Furthermore, the thin film transistor may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low-temperature polycrystalline silicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material, or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

[0120] It is understandable that, among the transistors in the pixel driving circuit, the types of any two transistors may be the same or different. For example, in some embodiments, in a pixel driving circuit, some transistors may be N-type transistors and some transistors may be P-type transistors. Again for example, in other embodiments, in a pixel driving circuit, the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistors are low-temperature polysilicon transistors. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors, and some thin film transistors are metal oxide transistors.

[0121] Optionally, referring to FIG3 , the driving layer DRL may include a semiconductor layer (see FIG3 , such as a low-temperature polysilicon semiconductor layer LSCL and a metal oxide semiconductor layer OSCL) stacked between the substrate SBT and the pixel layer PIXL, a gate insulating layer (see FIG3 , such as a first gate insulating layer GI1, a second gate insulating layer GI2, and a third gate insulating layer GI3), a gate layer (see FIG3 , such as a first gate layer GT1, a second gate layer GT2, and a third gate layer GT3), an interlayer dielectric layer ILD, a source-drain metal layer (see FIG3 , such as a first source-drain metal layer SD1, a second source-drain metal layer SD2, and a third source-drain metal layer SD3), a planarization layer (see FIG3 , such as a first planarization layer PLN1, a second planarization layer PLN2, and a third planarization layer PLN3), etc. Each thin film transistor and storage capacitor Cst (not shown in the drawings) may be formed by film layers such as a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer ILD, a source-drain metal layer, and the like; of course, other film layers may also be used. Among them, the positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. Furthermore, the semiconductor layer can be used to form the channel region of the transistor (as part of the active layer), and when necessary, it can also be formed by conductorization to form part of the wiring or conductive structure. The gate layer can be used to form one or more of the gate layer wirings such as the scan wiring, the reset control wiring, the light emitting control wiring, etc., and can also be used to form the gate of the transistor, and can also be used to form part or all of the electrode plates of the storage capacitor Cst. The source and drain metal layer can be used to form source and drain metal layer wirings such as the data wiring and the driving power supply voltage wiring VDDL, and can also be used to form part of the electrode plates of the storage capacitor Cst. Of course, in other embodiments of the present disclosure, the drive layer DRL can also include other film layers as needed, for example, it can also include a light shielding layer located between the semiconductor layer and the substrate SBT. As needed, any of the above-mentioned semiconductor layers, gate layers, source / drain metal layers and other film layers can also be multi-layered. For example, the driving layer DRL can include two different semiconductor layers, or two or three source / drain metal layers, or two or three gate layers; accordingly, the insulating film layers in the driving layer DRL (such as the gate insulating layer, the interlayer dielectric layer ILD, the planarization layer, etc.) can be adaptively increased or decreased, or new insulating film layers can be added as needed.

[0122] As an example, the driving layer DRL may also include a low-temperature polycrystalline silicon semiconductor layer LSCL, a first gate layer GT1, a second gate layer GT2, a metal oxide semiconductor layer OSCL, a third gate layer GT3, a first source-drain metal layer SD1, a second source-drain metal layer SD2, and a third source-drain metal layer SD3 stacked between the substrate SBT and the pixel layer PIXL.

[0123] Optionally, referring to FIG3 , the pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer EL, and a common electrode layer COML stacked in sequence. The pixel electrode layer PEL includes a plurality of pixel electrodes PE in the display area of ​​the display panel. The pixel definition layer PDL includes a plurality of through pixel openings corresponding one-to-one to the plurality of pixel electrodes PE, with any one of the pixel openings exposing at least a portion of the corresponding pixel electrode PE. For example, the pixel definition layer PDL covers the edge of the pixel electrode PE and exposes at least a portion of the inner region of the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode (the area directly connected to the light-emitting functional layer EL), thereby defining the light-emitting region and light-emitting area of ​​the sub-pixel. The common electrode layer COML serves as a common electrode and covers the light-emitting functional layer EL. The pixel electrode and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EL, so that the light-emitting functional layer EL emits light. The portion of the light-emitting functional layer EL located between the pixel electrode and the common electrode layer COML can serve as a light-emitting functional unit of the sub-pixel. The pixel electrode PE, the common electrode layer COML, and the light-emitting functional unit form a light-emitting element serving as a sub-pixel. One of the pixel electrode and the common electrode layer COML serves as an anode of the sub-pixel, and the other serves as a cathode of the sub-pixel.

[0124] In this example, the display panel is an OLED (organic light-emitting diode) display substrate. The light-emitting functional layer EL may include an organic light-emitting layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Furthermore, the organic light-emitting layer may include a light-emitting layer host material and a light-emitting layer guest material. The light-emitting layer guest material may be a fluorescent dopant or a phosphorescent dopant, and in particular, may be a thermally activated delayed fluorescent material.

[0125] It is understandable that the display panel can also be other types of display panels, such as QLED (electroluminescent quantum dots) display panel, QD-OLED (combination of electroluminescent quantum dots and organic light-emitting diodes) display panel or other types of display panels.

[0126] In some embodiments of the present disclosure, as shown in FIG1 , the thin-film transistors (TFTs) of two pixel driver circuits are symmetrically arranged in two adjacent circuit areas PA along a first direction. The drive layer DRL includes a transistor layer TL and a first source / drain metal layer SD1 stacked in sequence, with the TFTs disposed in the transistor layer TL. The drive layer DRL includes a multiplexing via MH that straddles the boundary between the two adjacent circuit areas PA. The first source / drain metal layer SD1 is connected to the TFTs of both pixel driver circuits through the multiplexing via MH. This reduces the number of vias in adjacent circuit areas PA, achieving lateral compression of the adjacent circuit areas and thereby helping to improve the PPI of the display panel.

[0127] In an example of this embodiment, referring to FIG1 , the display panel includes an array-distributed first circuit area group PAS1, the first circuit area group PAS1 including two circuit areas PA adjacent to each other along a first direction; the pixel driving circuit includes a first light-emitting transistor T5 for being electrically connected to a power supply voltage terminal; the transistor layer TL is provided with a first polysilicon conductive structure PLA (see FIG4 ) serving as the first pole of two first light-emitting transistors T5 at the same time in the first circuit area group PAS1; the multiplexing via MH includes a first multiplexing via MHA located in the first circuit area group PAS1, the first multiplexing via MHA exposing the first polysilicon conductive structure PLA; in the first circuit area group PAS1, the first source-drain metal layer SD1 includes a power supply voltage metal structure capable of loading a power supply voltage VDD; the power supply voltage metal structure is electrically connected to the first polysilicon conductive structure PLA through the first multiplexing via MHA. In this way, when the first source-drain metal layer SD1 is loaded with the power supply voltage VDD, the power supply voltage VDD passes through the power supply voltage metal structure, and the power supply voltage metal structure is electrically connected to the first polysilicon conductive structure PLA in the adjacent circuit area PA through the first multiplexing via MHA, thereby achieving the purpose of simultaneously loading the power supply voltage VDD to the first electrode of the first light-emitting transistor T5 in the adjacent circuit, thereby compressing the pixel circuit laterally and reducing the size of the pixel driving circuit in the adjacent circuit area PA.

[0128] In an example of this embodiment, referring to Figures 1, 2, 3, and 4, the display panel includes a first circuit area group PAS1 distributed in an array, and the first circuit area group PAS1 includes two circuit areas PA adjacent to each other along a first direction; the pixel driving circuit also includes a second reset transistor T8, and the second electrode of the second reset transistor T8 is electrically connected to the second electrode of the data write transistor T4; the first electrode of the second reset transistor T8 is electrically connected to the third initialization voltage Vinit3 end; the transistor layer TL is provided with a second polysilicon conductive structure PLB in the first circuit area group PAS1 that serves as the first electrode of two second reset transistors T8 at the same time; the reuse via MH includes a second reuse via MHB located in the first circuit area group PAS1, and the second reuse via MHB exposes the second polysilicon conductive structure PLB; in the first circuit area group PAS1, the first source and drain metal layer SD1 includes a third initialization metal structure capable of loading the third initialization voltage Vinit3; the third initialization metal structure is electrically connected to the second polysilicon conductive structure PLB through the second reuse via MHB. In this way, when the first source-drain metal layer SD1 is loaded with the third initialization voltage Vinit3, the third initialization voltage Vinit3 passes through the third initialization metal structure, and the third initialization metal structure is electrically connected to the second polysilicon conductive structure PLB in the adjacent circuit area PA through the second reuse via MHB, thereby achieving the purpose of simultaneously loading the third initialization voltage Vinit3 to the first electrode of the second reset transistor T8 in the adjacent circuit, thereby compressing the pixel circuit laterally and reducing the size of the pixel driving circuit in the adjacent circuit area PA.

[0129] In an example of this embodiment, the display panel includes a second circuit area group PAS2 distributed in an array, and the second circuit area group PAS2 includes two circuit areas PA adjacent to each other along a first direction; the pixel driving circuit includes a driving transistor T3 and a first reset transistor T1 electrically connected to the first initialization voltage Vinit1 end; the first electrode of the driving transistor T3 is electrically connected to the second electrode of the data writing transistor T4, and the second electrode of the driving transistor T3 is electrically connected to the second electrode of the first reset transistor T1; the transistor layer TL is provided with a third polysilicon conductive structure PLC (see Figure 4) in the second circuit area group PAS2, which serves as the first electrode of two first reset transistors T1 at the same time; the reuse via includes a third reuse via MHC located in the second circuit area group PAS2, and the third reuse via MHC exposes the third polysilicon conductive structure PLC; in the second circuit area group PAS2, the first source and drain metal layer SD1 includes a first initialization metal structure capable of loading the first initialization voltage Vinit1; the first initialization metal structure is electrically connected to the third polysilicon conductive structure PLC through the third reuse via MHC. In this way, when the first source-drain metal layer SD1 is loaded with the first initialization voltage Vinit1, the first initialization voltage Vinit1 passes through the first initialization metal structure, and the first initialization metal structure is electrically connected to the third polysilicon conductive structure PLC of the adjacent circuit area PA through the third multiplexing via MHC, thereby achieving the purpose of simultaneously loading the first initialization voltage Vinit1 to the first electrode of the first reset transistor T1 of the adjacent circuit area PA, thereby compressing the pixel circuit laterally and reducing the size of the pixel driving circuit of the adjacent circuit area PA.

[0130] In some embodiments of the present disclosure, the driving layer DRL includes a low-temperature polycrystalline silicon semiconductor layer LSCL, a metal oxide semiconductor layer OSCL, and a first source-drain metal layer SD1 stacked in sequence; the pixel driving circuit also includes a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, and a second light-emitting transistor T6; the first electrode of the first reset transistor T1 is electrically connected to the first initialization voltage Vinit1, the second electrode of the first reset transistor T1, the first electrode of the threshold compensation transistor T2, the second electrode of the driving transistor T3, and the first electrode of the second light-emitting transistor T6 are electrically connected, and the second electrode of the second light-emitting transistor T6 is electrically connected to the pixel electrode PE; the second electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3; the channel region T1A of the first reset transistor, the channel region T3A of the driving transistor, and the channel region T6A of the second light-emitting transistor are located in the low-temperature polycrystalline silicon semiconductor layer LSCL; the channel region T2A of the threshold compensation transistor is set in the metal oxide semiconductor layer OSCL; the channel region T1A of the first reset transistor, the channel region T2A of the threshold compensation transistor, and the channel region T6A of the second light-emitting transistor are arranged in a straight line along the second direction.

[0131] In some embodiments of the present disclosure, the transistor layer TL includes a stacked low-temperature polycrystalline silicon semiconductor layer LSCL and a metal oxide semiconductor layer OSCL; the pixel driving circuit also includes a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, and a second light-emitting transistor T6; the first electrode of the first reset transistor T1 is electrically connected to the first initialization voltage Vinit1 terminal, the second electrode of the first reset transistor T1, the first electrode of the threshold compensation transistor T2, the second electrode d of the driving transistor T3, and the first electrode of the second light-emitting transistor T6 are electrically connected, and the second electrode of the second light-emitting transistor T6 is electrically connected to the pixel electrode; the second electrode d of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3; the channel region of the first reset transistor T1, the channel region of the driving transistor T3, and the channel region of the second light-emitting transistor T6 are located in the low-temperature polycrystalline silicon semiconductor layer LSCL; the channel region of the threshold compensation transistor T2 is set in the metal oxide semiconductor layer OSCL; along the first direction, the channel region of the first reset transistor T1 and the channel region of the threshold compensation transistor T2 are alternately arranged.

[0132] In some embodiments of the present disclosure, referring to FIG. 28 , in the circuit area PA, the metal oxide semiconductor layer OSCL includes a first metal oxide structure OLA arranged along a first direction and a second metal oxide structure OLB arranged along a second direction; an end of the first metal oxide structure OLA close to the data writing transistor T4 and an end of the second metal oxide structure OLB close to the driving transistor T3 are connected to each other; and a channel region of the threshold compensation transistor T2 is located in the second metal oxide structure OLB.

[0133] In some embodiments of the present disclosure, referring to FIG17 , the first source-drain metal layer SD1 includes a first metal structure MS1 and a second metal structure MS2; the second metal structure MS2 is electrically connected to the second electrode of the first reset transistor T1, the second electrode of the driving transistor T3, and the first electrode of the threshold compensation transistor T2 through a via; the first metal structure MS1 is electrically connected to the second electrode of the threshold compensation transistor T2 and the gate of the driving transistor T3 through a via; the dimension of the second metal structure MS2 along the second direction is smaller than the dimension of the first metal structure MS1 along the second direction.

[0134] In some embodiments of the present disclosure, referring to Figures 3, 17 and 18, the driving layer DRL includes a low-temperature polycrystalline silicon semiconductor layer LSCL, a first gate layer GT1, a second gate layer GT2, a metal oxide semiconductor layer OSCL, a third gate layer GT3, a first source-drain metal layer SD1 and a second source-drain metal layer SD2, which are stacked in sequence; wherein the first gate layer GT1 is provided with a gate of the data write transistor T4, and the display panel is provided with a second scan signal line GPL electrically connected to the gate of the data write transistor T4; in the circuit area PA, the second scan signal line GPL includes a first sub-scan line GPL1 located in the first source-drain metal layer SD1 and a second sub-scan line GPL2 located in the second source-drain metal layer SD2; the first sub-scan line GPL1 is electrically connected to the gate of the data write transistor T4 through a via, and the second sub-scan line GPL2 is electrically connected to the first sub-scan line GPL1 through a via.

[0135] In some embodiments of the present disclosure, referring to FIG. 15 , in the circuit area PA, the metal oxide semiconductor layer OSCL includes a second metal oxide structure OLB arranged along the second direction; an end of the second metal oxide structure OLB away from the channel region of the driving transistor T3 is electrically connected to the gate of the driving transistor T3 through a first metal structure MS1 located in the first source / drain metal layer SD1; in the circuit area PA, the first metal structure MS1 is arranged to overlap with the second sub-scanning line GPL2.

[0136] In some embodiments of the present disclosure, the driving layer DRL includes a low-temperature polycrystalline silicon semiconductor layer LSCL, a first gate layer GT1, a second gate layer GT2, a metal oxide semiconductor layer OSCL, a third gate layer GT3 and a first source-drain metal layer SD1 stacked in sequence; wherein the first gate layer GT1 is provided with a gate of the data write transistor T4, and the display panel is provided with a first sub-scanning line GPL1 electrically connected to the gate of the data write transistor T4; the first sub-scanning line GPL1 is located in the first source-drain metal layer SD1, and is electrically connected to the gate of the data write transistor T4 through a via.

[0137] In some embodiments of the present disclosure, referring to FIG. 22 , in the circuit area PA, the metal oxide semiconductor layer OSCL includes a first metal oxide structure OLA, a second metal oxide structure OLB, and a third metal oxide structure OLC connected in sequence, and the first metal oxide structure OLA and the third metal oxide structure OLC are arranged in parallel along the second direction; the second metal oxide structure OLB is arranged along the first direction, and an end of the first metal oxide structure OLA away from the driving transistor T3 and an end of the third metal oxide structure OLC away from the driving transistor T3 are electrically connected to each other; an end of the third metal oxide structure OLC close to the driving transistor T3 is electrically connected to the gate of the driving transistor T3 through the first metal structure located in the first source / drain metal layer SD1.

[0138] In some embodiments of the present disclosure, referring to FIG. 19 , the low-temperature polysilicon semiconductor layer LSCL includes a fourth polysilicon conductive structure PLD, which serves as the second electrode of the first reset transistor T1; an end of the fourth polysilicon conductive structure PLD close to the channel region of the driving transistor T3 is electrically connected to the second electrode of the driving transistor T3 through a second metal structure located in the first source-drain metal layer SD1.

[0139] In some embodiments of the present disclosure, referring to FIG. 19 , the low-temperature polycrystalline silicon semiconductor layer LSCL includes a fourth polycrystalline silicon conductive structure PLD and a fifth polycrystalline silicon conductive structure PLE, wherein one end of the fourth polycrystalline silicon conductive structure PLD close to the channel region of the driving transistor T3 is interconnected with the fifth polycrystalline silicon conductive structure PLE, and the fifth polycrystalline silicon conductive structure PLE is interconnected with the second electrode of the driving transistor T3.

[0140] In one embodiment of the present disclosure, the drive layer DRL includes a third initialization voltage trace VL3 for applying a third initialization voltage Vinit3 and an enable signal line EML for applying an enable signal EM. The third initialization voltage trace VL3 is located on the third gate layer GT3 and extends along the first direction, while the enable signal line EML is located on the first gate layer GT1 and extends along the first direction. The enable signal line EML and the third initialization voltage trace VL3 are arranged to overlap. This further reduces the size of the pixel drive circuit in the second direction.

[0141] The following is a further introduction to the film layer structure of the first exemplary driving circuit.

[0142] Figure 4 is a schematic diagram of a low-temperature polycrystalline silicon semiconductor layer LSCL in one example. Referring to Figures 2, 3, and 4, the low-temperature polycrystalline silicon semiconductor layer LSCL includes first electrodes, second electrodes, and channel regions of transistors such as a first reset transistor T1, a driver transistor T3, a data write transistor T4, a first light-emitting transistor T5, a second light-emitting transistor T6, an electrode reset transistor T7, and a second reset transistor T8. The channel region T4A of the data write transistor and the channel region T5A of the first light-emitting transistor are arranged along a second direction H2, while the channel regions T5A of the first light-emitting transistor and T6A of the second light-emitting transistor are arranged along a first direction H1. Along the first direction H1, the channel region T3A of the driver transistor is located between the channel regions T5A of the first light-emitting transistor and T6A of the second light-emitting transistor. Along the second direction H2, the channel regions T7A of the electrode reset transistor and the channel region T3A of the driver transistor are located on either side of the channel region T5A of the first light-emitting transistor. The second electrode of the data write transistor T4, the second electrode of the first light-emitting transistor T5, and the first electrode of the drive transistor T3 are connected to each other. The second electrode of the drive transistor T3 and the first electrode of the second light-emitting transistor T6 are electrically connected to each other. The second electrode of the electrode reset transistor T7 and the second electrode of the second light-emitting transistor T6 are electrically connected to each other. In two adjacent rows of drive circuits, the channel region T7A of the electrode reset transistor of the upper row drive circuit is adjacent to the channel region T4A of the data write transistor of the lower row drive circuit. The second electrode of the second reset transistor T8 is electrically connected to the second electrode of the first light-emitting transistor T5.

[0143] 4 , the low-temperature polycrystalline silicon semiconductor layer LSCL may be provided with a first lower via area HA1 to a tenth lower via area HA10, the first lower via area HA1 being located at the first electrode of the first reset transistor T1, the second lower via area HA2 being located at the second electrode of the first reset transistor T1, the third lower via area HA3 being located at the first electrode of the data write transistor T4, the fourth lower via area HA4 being located at the second electrode of the data write transistor T4, the fifth lower via area HA5 being located at the first electrode of the second light-emitting transistor T6, the sixth lower via area HA6 being located at the second electrode of the second light-emitting transistor T6, the seventh lower via area HA7 being located at the second electrode of the electrode reset transistor T7, the eighth lower via area HA8 being located at the second electrode of the second reset transistor T8, the ninth lower via area HA9 being located at the first electrode of the second reset transistor T8, and the tenth lower via area HA10 being located at the second electrode of the second light-emitting transistor T5.

[0144] The low-temperature poly-silicon semiconductor layer LSCL may further include a first poly-silicon conductive structure PLA, a second poly-silicon conductive structure PLB, and a third poly-silicon conductive structure PLC.

[0145] Figure 5 is a schematic diagram of the first gate layer GT1 in one example. Referring to Figure 5 , the first gate layer GT1 is formed with a first capacitor reset control signal line RL1, a second capacitor reset control signal line RL2, a second scan signal line GPL, an enable signal line EML, and a first electrode CP1 of the storage capacitor Cst, extending along a first direction. The first capacitor reset control signal line RL1 extends along a first direction H1 and is used to apply a first capacitor reset control signal ResetP to the first reset transistor T1. The second capacitor reset control signal line RL2 extends along the first direction H1 and is used to apply a second capacitor reset control signal ResetH to the second reset transistor T8. The enable signal line EML extends along the first direction H1 and overlaps with the channel region T5A of the first light-emitting transistor and the channel region T6A of the second light-emitting transistor, serving as the gate of the first light-emitting transistor T5 and the gate of the second light-emitting transistor T6. The enable signal line EML can be used to apply the enable signal EM. The second scan signal line GPL extends along the first direction H1 and can overlap with the channel region T4A of the data write transistor. The overlapping portion serves as the gate of the data write transistor T4. The first electrode CP1 of the storage capacitor Cst overlaps with the channel region T3A of the drive transistor and serves as the gate of the drive transistor T3. The first electrode CP1 located on the first gate layer GT1 has an eleventh lower via area HA11.

[0146] Figure 6 is a schematic diagram of the second gate layer GT2 in one example. Referring to Figure 6 , the second gate layer GT2 is provided with the second electrode CP2 of the storage capacitor Cst and the second first scan signal trace GNLB. The second electrode CP2 of the storage capacitor Cst overlaps with the first electrode CP1 of the storage capacitor Cst, and a clearance hole is provided to partially expose the first electrode CP1 of the storage capacitor Cst. The second first scan signal trace GNLB extends along the first direction H1. The second electrode CP2 located in the second gate layer GT2 may have a twentieth lower via area HA20.

[0147] Figure 7 is a schematic diagram of a metal oxide semiconductor layer (OSCL) in one example. Referring to Figure 7, the metal oxide semiconductor layer (OSCL) includes a second electrode, a first electrode, and a channel region of a threshold compensation transistor (T2). Along the second direction (H2), the channel region (T1A) of the first reset transistor (TS1) is located on the side of the channel region (T2A) of the threshold compensation transistor (TS2) away from the channel region (T3A) of the drive transistor. The channel region (T2A) of the threshold compensation transistor (TS2) and the channel region (T5A) of the first light-emitting transistor (TS5) are located on either side of the channel region (T3A) of the drive transistor (TS3). Along the first direction (H1), the channel region (T4A) of the data write transistor (TS4A) of the next row of drive circuits and the channel region (T1A) of the first reset transistor (TS1) are located on either side of the channel region (T7A) of the reset transistor (TS7A) of the previous row of drive circuits. The second electrode of the first reset transistor (TS1) and the first electrode of the threshold compensation transistor (TS2) are interconnected. Furthermore, along the first direction, the channel region (T1A) of the first reset transistor (TS1) and the channel region (T2A) of the threshold compensation transistor (TS2) are interlaced. The metal oxide semiconductor layer (OSCL) includes a twelfth lower via region (HA12) and a thirteenth lower via region (HA12).

[0148] It should be noted that the metal oxide semiconductor layer OSCL in this exemplary embodiment includes a first metal oxide structure OLA arranged along a first direction and a second metal oxide structure OLB arranged along a second direction; an end of the first metal oxide structure OLA close to the data writing transistor T4 and an end of the second metal oxide structure OLB close to the driving transistor T3 are interconnected; and the channel region T2A of the threshold compensation transistor T2 is located in the second metal oxide structure OLB.

[0149] FIG8 is a schematic diagram of the third gate layer GT3 in one example. Referring to FIG8 , the third gate layer GT3 is provided with a first initialization voltage line VTL1, a second initialization voltage line VTL2, a third initialization voltage line VTL3, and a first scan signal line GNLA. The first initialization voltage line VTL1 extends in a first direction H1 and can be used to load Vinit1. The second initialization voltage line VTL2 extends along the first direction H1 and can be used to load the second initialization voltage Vinit2. The third initialization voltage line VTL3 extends along the first direction H1 and can be used to load the third initialization voltage Vinit3. The first scan signal line GNLA overlaps with the channel region T2A of the threshold compensation transistor, and the overlapping portion thereof is multiplexed into the second gate of the threshold compensation transistor T2. The first scan signal line GNLA overlaps with the second scan signal line GNLB, and the overlapping portion thereof is multiplexed into the upper and lower gates of the threshold compensation transistor T2.

[0150] The third gate layer GT3 may further have a fourteenth lower via area HA14 located at the first initialization voltage trace VTL1, a fifteenth lower via area HA15 located at the third initialization voltage trace VTL3, a sixteenth lower via area HA16, a seventeenth lower via area HA17 and an eighteenth lower via area HA18 located at the second initialization voltage trace VTL2.

[0151] FIG9 is a schematic diagram of the first source-drain metal layer SD1 in an example. Referring to FIG9 , the first source-drain metal layer SD1 is further provided with a first bridge portion MA1 to a tenth bridge portion MA10;

[0152] The first bridge MA1 includes a first upper via region HB1 and a fourteenth upper via region HB14. The first upper via region HB1 overlaps with the first lower via region HA1 and is connected via a via. The fourteenth upper via region HB14 overlaps with the fourteenth lower via region HA14 and is connected via a via. Thus, the first initialization voltage line VTL1 is electrically connected to the first electrode of the first reset transistor T1 via the first bridge MA1.

[0153] The second bridge portion MA2 has a fifteenth upper via area HB15 and a twenty-seventh lower via area HA27. The fifteenth upper via area HB15 and the fifteenth lower via area HA15 overlap and are connected by a via, and the twenty-seventh lower via area HA27 and the twenty-seventh upper via area HB27 overlap and are connected by a via. Thus, the signal is applied to the third initialization voltage trace VTL3 via the second bridge portion MA2.

[0154] The third bridge portion MA3 has an eleventh upper via area HB11 and a twelfth upper via area HB12, wherein the eleventh upper via area HB11 overlaps with the eleventh lower via area HA11 and is connected through a via, and the twelfth upper via area HB12 overlaps with the twelfth lower via area HA12 and is connected through a via, so that the second electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 through the third bridge portion MA3.

[0155] The fourth bridge portion MA4 has a third upper via area HB3 and a twenty-sixth lower via area HA26, wherein the third upper via area HB3 overlaps with the third lower via area HA3 and is connected through a via, and the twenty-sixth lower via area HA26 is connected to the twenty-sixth upper via area HB26 and is connected through a via, so that it is electrically connected to the first electrode of the data writing transistor T4 through the second bridge portion MA2.

[0156] The fifth bridge portion MA5 has a twenty-first lower via area HA21, a twentieth upper via area HB20, and a tenth upper via area HB10, wherein the twenty-first lower via area HA21 overlaps with the twenty-first upper via area HB21 and is connected through vias, the twentieth upper via area HB20 overlaps with the twentieth lower via area HA20 and is connected through vias, and the tenth upper via area HB10 is connected to the tenth lower via area HA10 and is connected through vias, so that the power supply voltage VDD is connected to the first electrode of the first light-emitting transistor T5 through the fifth bridge portion MA5.

[0157] The sixth bridge portion MA6 includes a twenty-third lower via area HA23 and a sixth upper via area HB6. The twenty-third lower via area HA23 overlaps with the twenty-third upper via area HB23 and is connected via a via. The sixth upper via area HB6 overlaps with the sixth lower via area HA6 and is connected via a via. Thus, the second initialization voltage trace VTL2 is electrically connected to the first electrode of the electrode reset transistor T7 via the first bridge portion MA6.

[0158] The seventh bridge portion MA7 has a seventh upper via area HB7 and an eighteenth upper via area HB18, wherein the seventh upper via area HB7 overlaps with the seventh lower via area HA7 and is connected through a via, and the eighteenth upper via area HB18 overlaps with the eighteenth lower via area HA18 and is connected through a via, so that the second initialization voltage line VTL2 is electrically connected to the second electrode of the electrode reset transistor T7 through the seventh bridge portion MA7.

[0159] The eighth bridge portion MA8 has a fourth upper via area HB4 and a ninth upper via area HB9, wherein the fourth upper via area HB4 overlaps with the fourth lower via area HA4 and is connected through a via, and the ninth upper via area HB9 overlaps with the ninth lower via area HA9 and is connected through a via, so that the second electrode of the data write transistor T4 is electrically connected to the second electrode of the second reset transistor T8 through the first bridge portion MA8.

[0160] The ninth bridge portion MA9 has a second upper via area HB2, a fifth upper via area HB5 and a thirteenth upper via area HB13, wherein the second upper via area HB2 overlaps with the second lower via area HA2 and is connected through a via, the fifth upper via area HB5 overlaps with the fifth lower via area HA5 and is connected through a via, the thirteenth upper via area HB13 overlaps with the thirteenth lower via area HA113 and is connected through a via, so that the second electrode of the first reset transistor T1, the first electrode of the second light-emitting transistor T6 and the first electrode of the threshold compensation transistor T2 are connected through the ninth bridge portion MA9.

[0161] The tenth bridge portion MA10 includes a sixteenth upper via region HB16 and an eighth upper via region HB8. The sixteenth upper via region HB16 and the sixteenth lower via region HA16 overlap and are connected via a via, and the eighth upper via region HB8 and the eighth lower via region HA8 overlap and are connected via a via. Thus, the third initialization voltage trace VLT3 is electrically connected to the first electrode of the second reset transistor T8 via the tenth bridge portion MA10.

[0162] 10 , the second source-drain metal layer SD2 is further provided with first to fourth conductive portions MB1 to MB4 ;

[0163] The first conductive part MB1 has a twenty-fifth lower via area HA25 and a twenty-sixth upper via area HB26, wherein the twenty-fifth lower via area HA25 overlaps with the twenty-fifth upper via area HB25 and is connected through a via, and the twenty-sixth upper via area HB26 overlaps with the twenty-sixth lower via area HA26 and is connected through a via, so that the signal is loaded onto the fourth bridging part MA4 through the first conductive part MB1.

[0164] The second conductive part MB2 has a twenty-seventh upper via area HB27 and a twenty-second lower via area HA22, wherein the twenty-seventh lower via area HA27 overlaps with the twenty-seventh upper via area HB27 and is connected through a via, and the twenty-second lower via area HA22 overlaps with the twenty-second upper via area HB22 and is connected through a via, so that the standby signal on the third source-drain metal layer SD3 is loaded onto the second bridging part MA2 through the second conductive part MB2.

[0165] The third conductive part MB3 has a nineteenth lower via area HA19 and a twenty-first upper via area HB21, wherein the twenty-first upper via area HB21 and the twenty-first lower via area HA21 overlap and are connected through vias, and the nineteenth lower via area HA19 and the nineteenth upper via area HB19 overlap and are connected through vias, so that the power supply voltage VDD is loaded onto the fifth bridge part MA5 through the third conductive part MB3.

[0166] The fourth conductive part MB4 has a twenty-fourth lower via area HA24 and a twenty-third upper via area HB23, wherein the twenty-fourth lower via area HA24 and the twenty-fourth upper via area HB24 overlap and are connected through vias, and the twenty-third upper via area HB23 overlaps with the twenty-third lower via area HA23 and is connected through vias, so that the signal of the third source-drain metal layer SD3 is loaded onto the sixth bridge part MA6 through the fourth conductive part MB4.

[0167] 11 , the third source / drain metal layer SD3 is further provided with a power supply voltage line VDDL, a standby signal line SWL, a data signal line DL and a first metal portion MC1 ;

[0168] A nineteenth upper via area HB19 is provided on the power voltage line VDDL, wherein the nineteenth upper via area HB19 overlaps with the nineteenth lower via area HA19 and is connected through a via, so that the power voltage VDD is applied to the third conductive portion MB3 through the power voltage line VDDL.

[0169] A twenty-second upper via area HB22 is provided on the standby signal line SWL; wherein the twenty-second upper via area HB22 overlaps with the twenty-second lower via area HA22 and is connected through vias, thereby enabling the standby signal to be loaded onto the second conductive portion MB2.

[0170] A twenty-fifth upper via area HB25 is provided on the data signal line DL. The twenty-fifth upper via area HB25 overlaps with the twenty-fifth lower via area HA25 and is connected through vias, thereby loading the data signal Data on the first conductive portion MB1 through the data signal line DL.

[0171] A twenty-fourth upper via region HB24 is provided on the first metal portion MC1 ; the twenty-fourth upper via region HB24 overlaps with the twenty-fourth lower via HA24 and is connected through a via hole, thereby achieving electrical connection with the pixel electrode PE through the first metal portion MC1 .

[0172] The following is a further introduction to the film layer structure of the second exemplary driving circuit.

[0173] Referring to Figures 2, 3, and 12, the low-temperature polycrystalline silicon semiconductor layer LSCL is provided with first electrodes, second electrodes, and channel regions of transistors such as a first reset transistor T1, a drive transistor T3, a data write transistor T4, a first light-emitting transistor T5, a second light-emitting transistor T6, an electrode reset transistor T7, and a second reset transistor T8. The channel region T4A of the data write transistor and the channel region T5A of the first light-emitting transistor are arranged along the second direction H2, while the channel region T5A of the first light-emitting transistor and the channel region T6A of the second light-emitting transistor are arranged along the first direction H1. Along the first direction H1, the channel region T3A of the drive transistor is located between the channel region T5A of the first light-emitting transistor and the channel region T6A of the second light-emitting transistor. Along the second direction H2, the channel region T7A of the electrode reset transistor and the channel region T3A of the drive transistor are located on either side of the channel region T5A of the first light-emitting transistor. The second electrode of the data write transistor T4, the second electrode of the first light-emitting transistor T5, and the first electrode of the drive transistor T3 are connected to each other. The second electrode of the drive transistor T3 and the first electrode of the second light-emitting transistor T6 are electrically connected to each other. The second electrode of the electrode reset transistor T7 and the second electrode of the second light-emitting transistor T6 are electrically connected to each other. In two adjacent rows of drive circuits, the channel region T7A of the electrode reset transistor of the upper row drive circuit is adjacent to the channel region T4A of the data write transistor of the lower row drive circuit. The second electrode of the second reset transistor T8 is electrically connected to the second electrode of the first light-emitting transistor T5.

[0174] The low-temperature polycrystalline silicon semiconductor layer LSCL may be provided with a first lower via area HA1 to a tenth lower via area HA10, and the first lower via area HA1 is located at the first electrode of the first reset transistor T1. It should be noted that, in the embodiment of the present disclosure, the low-temperature polycrystalline silicon semiconductor layer LSCL includes a fourth polycrystalline silicon conductive structure PLD and a fifth polycrystalline silicon conductive structure PLE, and the channel area T1A of the first reset transistor is located in the fourth polycrystalline silicon conductive structure PLD; one end of the fourth polycrystalline silicon conductive structure PLD close to the channel area T3A of the driving transistor is interconnected with the fifth polycrystalline silicon conductive structure PLE, and the fifth polycrystalline silicon conductive structure PLE is interconnected with the second electrode of the driving transistor T3. Since the fourth polycrystalline silicon conductive structure PLD and the fifth polycrystalline silicon conductive structure PLE are interconnected, the first reset transistor T1 and the driving transistor T3 do not need to be connected through a metal structure. Therefore, in this embodiment, the low-temperature polycrystalline silicon semiconductor layer LSCL is not provided with a second lower via area HA2. The third lower via area HA3 is located at the first electrode of the data writing transistor T4, the fourth lower via area HA4 is located at the second electrode of the data writing transistor T4, the fifth lower via area HA5 is located at the first electrode of the second light-emitting transistor T6, the sixth lower via area HA6 is located at the second electrode of the second light-emitting transistor T6, the seventh lower via area HA7 is located at the second electrode of the electrode reset transistor T7, the eighth lower via area HA8 is located at the second electrode of the second reset transistor T8, the ninth lower via area HA9 is located at the first electrode of the second reset transistor T8, and the tenth lower via area HA10 is located at the second electrode of the second light-emitting transistor T5.

[0175] Figure 13 is a schematic diagram of the first gate layer GT1 in one example. Referring to Figure 13 , the first gate layer GT1 is formed with a first capacitor reset control signal line RL1, a second capacitor reset control signal line RL2, a second scan signal line GPL, an enable signal line EML, and a first electrode CP1 of the storage capacitor Cst, extending along a first direction. The first capacitor reset control signal line RL1 extends along a first direction H1 and is used to apply a first capacitor reset control signal ResetP to the first reset transistor T1. The second capacitor reset control signal line RL2 extends along the first direction H1 and is used to apply a second capacitor reset control signal ResetH to the second reset transistor T8. The enable signal line EML extends along the first direction H1 and overlaps with the channel region T5A of the first light-emitting transistor and the channel region T6A of the second light-emitting transistor, serving as the gate of the first light-emitting transistor T5 and the gate of the second light-emitting transistor T6. The enable signal line EML can be used to apply the enable signal EM. The second scan signal line GPL extends along the first direction H1. The second scan signal line GPL can overlap with the channel region T4A of the data write transistor, with the overlapping portion being reused as the gate of the data write transistor T4. The first electrode CP1 of the storage capacitor Cst overlaps with the channel region T3A of the drive transistor to be reused as the gate of the drive transistor T3. The first electrode CP1 located on the first gate layer GT1 can be provided with an eleventh lower via region HA11. The second scan signal line GPL has a twenty-eighth lower via region. The twenty-eighth lower via region HA28 overlaps with the twenty-eighth upper via region HB28 and is connected via a via. This transfers the data signal Data via the second source / drain metal layer SD2 to the second scan signal line GPL located on the first source / drain metal layer SD1, thereby reducing the length of the second scan signal line GPL and achieving pixel circuit compression.

[0176] Figure 14 is a schematic diagram of the second gate layer GT2 in one example. Referring to Figure 14 , the second gate layer GT2 is provided with a second electrode CP2 of the storage capacitor Cst and a second first scan signal trace GNLB. The second electrode CP2 of the storage capacitor Cst overlaps with the first electrode CP1 of the storage capacitor Cst, and a clearance hole is provided to partially expose the first electrode CP1 of the storage capacitor Cst. The second first scan signal trace GNLB extends along a first direction H1 and is used to carry the first scan signal GN. The second electrode CP2 located in the second gate layer GT2 may be provided with a twentieth lower via area HA20.

[0177] Figure 15 is a schematic diagram of a metal oxide semiconductor layer (OSCL) in one example. Referring to Figure 15 , the metal oxide semiconductor layer (OSCL) includes a second electrode, a first electrode, and a channel region of a threshold compensation transistor (T2). Along the second direction (H2), the channel region (T1A) of the first reset transistor (T1A) is located on the side of the channel region (T2A) of the threshold compensation transistor (T2A) away from the channel region (T3A) of the drive transistor. The channel region (T2A) of the threshold compensation transistor (T2A) and the channel region (T5A) of the first light-emitting transistor (T5A) are located on either side of the channel region (T3A) of the drive transistor (T3A). Along the first direction (H1), the channel region (T4A) of the data write transistor (T1A) of the next row of drive circuits and the channel region (T7A) of the first reset transistor (T1) are located on either side of the channel region (T7A) of the reset transistor (T7A) of the previous row of drive circuits. The second electrode of the first reset transistor (T1) and the second electrode of the threshold compensation transistor (T2) are interconnected. Furthermore, along the first direction, the channel regions (T1A) of the first reset transistor (T1A) and the channel regions (T2A) of the threshold compensation transistor (T2A) are interlaced. The metal oxide semiconductor layer OSCL is further provided with a twelfth lower via area HA12 and a thirteenth lower via area HA13 .

[0178] It should be noted that, in the embodiment of the present disclosure, the metal oxide semiconductor layer OSCL includes a second metal oxide structure OLB arranged along the second direction; the end of the second metal oxide structure OLB away from the channel region T3A of the driving transistor is electrically connected to the gate of the driving transistor T3 through the first metal structure MS1 located in the first source and drain metal layer SD1.

[0179] FIG16 is a schematic diagram of the third gate layer GT3 in one example. Referring to FIG16 , the third gate layer GT3 is provided with a first initialization voltage trace VTL1, a second initialization voltage trace VTL2, a third initialization voltage trace VTL3, and a first scan signal trace GNLA. The first initialization voltage trace VTL1 extends in a first direction H1 and can be used to apply Vinit1. The second initialization voltage trace VTL2 extends along the first direction H1 and can be used to apply the second initialization voltage Vinit2. The third initialization voltage trace VTL3 extends along the first direction H1 and can be used to apply the third initialization voltage Vinit3. The first scan signal trace GNLA overlaps with the channel region T2A of the threshold compensation transistor, and the overlapping portion thereof serves as the second gate of the threshold compensation transistor T2. The first scan signal trace GNLA overlaps with the channel region T8A of the second reset transistor, and the overlapping portion thereof serves as the second gate of the threshold compensation transistor T2. The third gate layer GT3 also has a fourteenth lower via area HA14 located at the first initialization voltage trace VTL1, a fifteenth lower via area HA15 located at the third initialization voltage trace VTL3, a sixteenth lower via area HA16, a seventeenth lower via area HA17 and an eighteenth lower via area HA18 located at the second initialization voltage trace VTL2.

[0180] FIG17 is a schematic diagram of the first source-drain metal layer SD1 in an example. Referring to FIG17 , the first source-drain metal layer SD1 is further provided with a first bridge portion MA1 to a tenth bridge portion MA10 and a fifteenth bridge portion MA15;

[0181] The first bridge MA1 includes a first upper via region HB1 and a fourteenth upper via region HB14. The first upper via region HB1 overlaps with the first lower via region HA1 and is connected via a via. The fourteenth upper via region HB14 overlaps with the fourteenth lower via region HA14. Thus, the first initialization voltage line VTL1 is electrically connected to the first electrode of the first reset transistor T1 via the first bridge MA1.

[0182] The second bridge portion MA2 has a fifteenth upper via area HB15 , wherein the fifteenth upper via area HB15 overlaps with the fifteenth lower via area HA15 and is connected through vias, thereby enabling the signal of the standby signal line SWL to be loaded onto the second initialization voltage line VTL2 .

[0183] The third bridge portion MA3 has an eleventh upper via area HB11 and a twelfth upper via area HB12, wherein the eleventh upper via area HB11 overlaps with the eleventh lower via area HA11 and is connected through a via, and the twelfth upper via area HB12 overlaps with the twelfth lower via area HA12 and is connected through a via, so that the second electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 through the third bridge portion MA3.

[0184] The fourth bridge portion MA4 has a third upper via area HB3 and a twenty-sixth lower via area HA26, wherein the third upper via area HB3 overlaps with the third lower via area HA3 and is connected through a via, and the twenty-sixth lower via area HA26 is connected to the twenty-sixth upper via area HB26 and is connected through a via, so that the data signal Data is electrically connected to the first electrode of the data write transistor T4 via the third upper via area HB3.

[0185] The fifth bridge portion MA5 has a 21st lower via area HA21, a 20th upper via area HB20 and a tenth upper via area HB10, wherein the 21st lower via area HA21 overlaps with the 21st upper via area HB21 and is connected through vias, the 20th upper via area HB20 overlaps with the 20th lower via area HA20 and is connected through vias, and the tenth upper via area HB10 is connected to the tenth lower via area HA10 and is connected through vias, so that the power supply voltage VDD is connected to the first electrode of the first light-emitting transistor T5 through MA5.

[0186] The sixth bridge portion MA6 has a sixth upper via region HB6 , which overlaps with the sixth lower via region HA6 and is connected via a via hole. Thus, the second initialization voltage trace VTL2 is electrically connected to the first electrode of the electrode reset transistor T7 through the sixth bridge portion MA6 .

[0187] The seventh bridge portion MA7 has a seventh upper via area HB7 and an eighteenth upper via area HB18, wherein the seventh upper via area HB7 overlaps with the seventh lower via area HA7 and is connected through a via, and the eighteenth upper via area HB18 overlaps with the eighteenth lower via area HA18 and is connected through a via, so that the second initialization voltage line VTL2 is electrically connected to the second electrode of the electrode reset transistor T7 through the seventh bridge portion MA7.

[0188] The eighth bridge portion MA8 has a fourth upper via area HB4 and a ninth upper via area HB9, wherein the fourth upper via area HB4 overlaps with the fourth lower via area HA4 and is connected through a via, and the ninth upper via area HB9 overlaps with the ninth lower via area HA9 and is connected through a via, so that the second electrode of the data write transistor T4 is electrically connected to the second electrode of the second reset transistor T8 through the first bridge portion MA 8.

[0189] The ninth bridge portion MA9 has a second upper via area HB2, a fifth upper via area HB5 and a thirteenth upper via area HB13, wherein the second upper via area HB2 overlaps with the second lower via area HA2 and is connected through a via, the fifth upper via area HB5 overlaps with the fifth lower via area HA5 and is connected through a via, the thirteenth upper via area HB13 overlaps with the thirteenth lower via area HA113 and is connected through a via, so that the second electrode of the first reset transistor T1, the first electrode of the second light-emitting transistor T6 and the first electrode of the threshold compensation transistor T2 are connected through the ninth bridge portion MA9.

[0190] The tenth bridge portion MA10 includes a sixteenth upper via region HB16 and an eighth upper via region HB8. The sixteenth upper via region HB16 and the sixteenth lower via region HA16 overlap and are connected via a via, and the eighth upper via region HB8 and the eighth lower via region HA8 overlap and are connected via a via. Thus, the third initialization voltage trace VLT3 is electrically connected to the first electrode of the second reset transistor T8 via the tenth bridge portion MA10.

[0191] The fifteenth bridge portion MA15 includes a twenty-eighth upper via region HB28 and a twenty-ninth lower via region HA29. The twenty-eighth upper via region HB28 overlaps with the twenty-eighth lower via region HA28 and is connected via a via. The twenty-ninth lower via region HA29 overlaps with the twenty-ninth upper via region HB29 and is connected via a via. Thus, the second scan signal GP is applied to the gate of the data write transistor T4 via the fifteenth bridge portion MA15.

[0192] FIG18 is a schematic diagram of the second source / drain metal layer SD2 in an example. Referring to FIG18 , the second source / drain metal layer SD2 is further provided with a first conductive portion MB1 to a fourth conductive portion MB4;

[0193] The first conductive part MB1 has a twenty-fifth lower via area HA25 and a twenty-sixth upper via area HB26, wherein the twenty-fifth lower via area HA25 overlaps with the twenty-fifth upper via area HB25 and is connected through a via, and the twenty-sixth upper via area HB26 overlaps with the twenty-sixth lower via area HA26 and is connected through a via, so that the data signal Data is loaded onto the fourth bridge part MA4 through the first conductive part MB1.

[0194] The second conductive part MB2 has a twenty-seventh lower via area HA27 and a twenty-second lower via area HA22, wherein the twenty-seventh lower via area HA27 overlaps with the twenty-seventh upper via area HB27 and is connected through a via, and the twenty-second lower via area HA22 overlaps with the twenty-second upper via area HB22 and is connected through a via, so that the standby signal on the third source-drain metal layer SD3 is loaded onto the second bridging part MA2.

[0195] The third conductive portion MB3 has a twenty-first upper via region HB21 , wherein the twenty-first upper via region HB21 overlaps with the twenty-first lower via region HA21 and is connected through a via, so that the power supply voltage VDD is applied to the fifth bridge portion MA5 .

[0196] The fourth conductive part MB4 has a twenty-fourth lower via area HA24 and a twenty-third upper via area HA24; wherein, the twenty-fourth lower via area HA24 and the twenty-fourth upper via area HB24 overlap and are connected through vias, wherein, the twenty-third lower via area HA23 and the twenty-third upper via area HB23 overlap and are connected through vias, so that the fourth conductive part MB4 loads the signal onto the sixth bridging part MA6.

[0197] The following is a further introduction to the film layer structure of the third exemplary driving circuit.

[0198] 2 , 3 and 19 , the low-temperature polysilicon semiconductor layer LSCL may be provided with a first lower via area HA1 to a tenth lower via area HA10 , and the first lower via area HA1 is located at the first electrode of the first reset transistor T1. It should be noted that, in the embodiment of the present disclosure, the low-temperature polysilicon semiconductor layer LSCL includes a fourth polysilicon conductive structure PLD and a fifth polysilicon conductive structure PLE, and the channel area T1A of the first reset transistor is located at the fourth polysilicon conductive structure PLD; an end of the fourth polysilicon conductive structure PLD close to the channel area T3A of the driving transistor is interconnected with the fifth polysilicon conductive structure PLE, and the fifth polysilicon conductive structure PLE is interconnected with the second electrode of the driving transistor T3. Since the fourth polysilicon conductive structure PLD and the fifth polysilicon conductive structure PLE are interconnected, the first reset transistor T1 and the driving transistor T3 do not need to be connected through a metal structure. Therefore, in this embodiment, the low-temperature polysilicon semiconductor layer LSCL is not provided with a second lower via area HA2. The third lower via area HA3 is located at the first electrode of the data writing transistor T4, the fourth lower via area HA4 is located at the second electrode of the data writing transistor T4, the fifth lower via area HA5 is located at the first electrode of the second light-emitting transistor T6, the sixth lower via area HA6 is located at the second electrode of the second light-emitting transistor T6, the seventh lower via area HA7 is located at the second electrode of the electrode reset transistor T7, the eighth lower via area HA8 is located at the second electrode of the second reset transistor T8, the ninth lower via area HA9 is located at the first electrode of the second reset transistor T8, and the tenth lower via area HA10 is located at the second electrode of the second light-emitting transistor T5.

[0199] Figure 20 is a schematic diagram of the first gate layer GT1 in one example. Referring to Figure 20 , the first gate layer GT1 is formed with a first capacitor reset control signal line RL1, a second capacitor reset control signal line RL2, a second scan signal line GPL, an enable signal line EML, and a first electrode CP1 of the storage capacitor Cst, extending along a first direction. The first capacitor reset control signal line RL1 extends along a first direction H1 and is used to apply a first capacitor reset control signal ResetP to the first reset transistor T1. The second capacitor reset control signal line RL2 extends along the first direction H1 and is used to apply a second capacitor reset control signal ResetH to the second reset transistor T8. The enable signal line EML extends along the first direction H1 and overlaps with the channel region T5A of the first light-emitting transistor and the channel region T6A of the second light-emitting transistor, serving as the gate of the first light-emitting transistor T5 and the gate of the second light-emitting transistor T6. The enable signal line EML can be used to apply the enable signal EM. The first electrode CP1 of the storage capacitor Cst overlaps with the channel region T3A of the drive transistor, serving as the gate of the drive transistor T3. The second scan signal line GPL extends along the first direction H1 and may overlap with the channel region T4A of the data write transistor, with the overlapping portion serving as the gate of the data write transistor T4. The first electrode CP1 of the storage capacitor Cst overlaps with the channel region T3A of the drive transistor, serving as the gate of the drive transistor T3. The first electrode CP1 located on the first gate layer GT1 may be provided with an eleventh lower via region HA11. The second scan signal line GPL has a twenty-eighth lower via region, which overlaps with the twenty-eighth upper via region HB28 and is connected via a via. This transfers the data signal Data via the second source / drain metal layer SD2 to the first source / drain metal layer SD1 and is then applied to the second scan signal line GPL, thereby reducing the length of the second scan signal line GPL and achieving pixel circuit compression.

[0200] Figure 21 is a schematic diagram of the second gate layer GT2 in one example. Referring to Figure 21 , the second gate layer GT2 is provided with a second electrode CP2 of the storage capacitor Cst and a second first scan signal trace GNLB. The second electrode CP2 of the storage capacitor Cst overlaps with the first electrode CP1 of the storage capacitor Cst, and a clearance hole is provided to partially expose the first electrode CP1 of the storage capacitor Cst. The second first scan signal trace GNLB extends along a first direction H1 and is used to carry the second scan signal. The second electrode CP2 located in the second gate layer GT2 may be provided with a twentieth lower via area HA20.

[0201] Figure 22 is a schematic diagram of a metal oxide semiconductor layer (OSCL) in one example. Referring to Figure 22 , the metal oxide semiconductor layer (OSCL) includes a second electrode, a first electrode, and a channel region of a threshold compensation transistor (T2). Along the second direction (H2), the channel region (T1A) of the first reset transistor (T1A) is located on the side of the channel region (T2A) of the threshold compensation transistor (T2A) away from the channel region (T3A) of the drive transistor. The channel region (T2A) of the threshold compensation transistor (T2A) and the channel region (T5A) of the first light-emitting transistor (T5A) are located on either side of the channel region (T3A) of the drive transistor (T3A). Along the first direction (H1), the channel region (T4A) of the data write transistor (T1A) of the next row of drive circuits and the channel region (T7A) of the first reset transistor (T1) are located on either side of the channel region (T7A) of the reset transistor (T7A) of the previous row of drive circuits. The second electrode of the first reset transistor (T1) and the second electrode of the threshold compensation transistor (T2) are interconnected. Furthermore, along the first direction, the channel regions (T1A) of the first reset transistor (T1A) and the channel regions (T2A) of the threshold compensation transistor (T2A) are interlaced. The metal oxide semiconductor layer OSCL is further provided with a twelfth lower via area HA12 and a thirteenth lower via area HA13 .

[0202] It should be noted that, in the embodiment of the present disclosure, the metal oxide semiconductor layer OSCL includes a first metal oxide structure OLA, a second metal oxide structure OLB, and a third metal oxide structure OLC connected in sequence, and the first metal oxide structure OLA and the third metal oxide structure OLC are arranged in parallel along the second direction; the second metal oxide structure OLB is arranged along the first direction, and an end of the first metal oxide structure OLA away from the driving transistor T3 and an end of the third metal oxide structure OLC away from the driving transistor T3 are electrically connected to each other; an end of the third metal oxide structure OLC close to the driving transistor T3 is electrically connected to the gate of the driving transistor T3 through the first metal structure MS1 located in the first source and drain metal layer SD1.

[0203] FIG23 is a schematic diagram of the third gate layer GT3 in one example. Referring to FIG23 , the third gate layer GT3 is provided with a first initialization voltage line VTL1, a second initialization voltage line VTL2, a third initialization voltage line VTL3, and a first scan signal line GNLA. The first initialization voltage line VTL1 extends in a first direction H1 and can be used to apply Vinit1. The second initialization voltage line VTL2 extends along the first direction H1 and can be used to apply the second initialization voltage Vinit2. The third initialization voltage line VTL3 extends along the first direction H1 and can be used to apply the third initialization voltage Vinit3. The first scan signal line GNLA overlaps with the channel region T2A of the threshold compensation transistor, and the overlapping portion thereof is multiplexed into the second gate of the threshold compensation transistor T2. The first scan signal line GNLA overlaps with the second scan signal line GNLB, and the overlapping portion thereof is multiplexed into the upper and lower gates of the threshold compensation transistor T2.

[0204] The third gate layer GT3 may also be provided with a fourteenth lower via area HA14 located at the first initialization voltage trace VTL1, a fifteenth lower via area HA15 located at the third initialization voltage trace VTL3, a sixteenth lower via area HA16, a seventeenth lower via area HA17 and an eighteenth lower via area HA18 located at the second initialization voltage trace VTL2.

[0205] Figure 24 is a schematic diagram of the first source / drain metal layer SD1 in one example. Referring to Figure 24 , the first source / drain metal layer SD1 further comprises a first bridge MA1, a tenth bridge MA10, and a fifteenth bridge MA15. The first bridge MA1 includes a first upper via region HB1 and a fourteenth upper via region HB14. The first upper via region HB1 overlaps with the first lower via region HA1 and is connected via a via, while the fourteenth upper via region HB14 overlaps with the fourteenth lower via region HA14. Thus, the first initialization voltage line VTL1 is electrically connected to the first electrode of the first reset transistor T1 via the first bridge MA1.

[0206] The second bridge portion MA2 has a fifteenth upper via area HB15, wherein the fifteenth upper via area HB15 overlaps with the fifteenth lower via area HA15 and is connected through vias, so that the signal is loaded onto the third initialization voltage trace VTL3 through the second bridge portion MA2.

[0207] The third bridge portion MA3 has an eleventh upper via area HB11 and a twelfth upper via area HB12, wherein the eleventh upper via area HB11 overlaps with the eleventh lower via area HA11 and is connected through a via, and the twelfth upper via area HB12 overlaps with the twelfth lower via area HA12 and is connected through a via, so that the second electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T2 through the third bridge portion MA3.

[0208] The fourth bridge portion MA4 has a third upper via area HB3 and a twenty-sixth lower via area HA26, wherein the third upper via area HB3 overlaps with the third lower via area HA3 and is connected through a via, and the twenty-sixth lower via area HA26 is connected to the twenty-sixth upper via area HB26 and is connected through a via, so that the data signal Data is electrically connected to the first electrode of the data write transistor T4 via the third upper via area HB3.

[0209] The fifth bridge portion MA5 has a 21st lower via area HA21, a 20th upper via area HB20 and a tenth upper via area HB10, wherein the 21st lower via area HA21 overlaps with the 21st upper via area HB21 and is connected through vias, the 20th upper via area HB20 overlaps with the 20th lower via area HA20 and is connected through vias, and the tenth upper via area HB10 is connected to the tenth lower via area HA10 and is connected through vias, so that the power supply voltage VDD is connected to the first electrode of the first light-emitting transistor T5 through MA5.

[0210] The sixth bridge portion MA6 has a sixth upper via area HB6 , wherein the sixth upper via area HB6 overlaps with the sixth lower via area HA6 and is connected through a via, so that the second initialization voltage trace VTL2 is electrically connected to the first electrode of the electrode reset transistor T7 through the sixth bridge portion MA6 .

[0211] The seventh bridge portion MA7 has a seventh upper via area HB7 and an eighteenth upper via area HB18, wherein the seventh upper via area HB7 overlaps with the seventh lower via area HA7 and is connected through a via, and the eighteenth upper via area HB18 overlaps with the eighteenth lower via area HA18 and is connected through a via, so that the second initialization voltage line VTL2 is electrically connected to the second electrode of the electrode reset transistor T7 through the seventh bridge portion MA7.

[0212] The eighth bridge portion MA8 has a fourth upper via area HB4 and a ninth upper via area HB9, wherein the fourth upper via area HB4 overlaps with the fourth lower via area HA4 and is connected through a via, and the ninth upper via area HB9 overlaps with the ninth lower via area HA9 and is connected through a via, so that the second electrode of the data write transistor T4 is electrically connected to the second electrode of the second reset transistor T8 through the first bridge portion MA 8.

[0213] The ninth bridge portion MA9 includes a second upper via area HB2, a fifth upper via area HB5, and a thirteenth upper via area HB13. The second upper via area HB2 overlaps with the second lower via area HA2 and is connected via a via. The fifth upper via area HB5 overlaps with the fifth lower via area HA5 and is connected via a via. The thirteenth upper via area HB13 overlaps with the thirteenth lower via area HA113 and is connected via a via. Thus, the ninth bridge portion MA9 connects the second electrode of the first reset transistor T1, the first electrode of the second light-emitting transistor T6, and the first electrode of the threshold compensation transistor T2.

[0214] The tenth bridge portion MA10 has a sixteenth upper via area HB16 and an eighth upper via area HB8, wherein the sixteenth upper via area HB16 and the sixteenth lower via area HA16 overlap and are connected through vias, and the eighth upper via area HB8 and the eighth lower via area HA8 overlap and are connected through vias, so that the third initialization voltage trace VLT3 is electrically connected to the first electrode of the second reset transistor T8 through the tenth bridge portion MA10.

[0215] The fifteenth bridge portion MA15 has a twenty-eighth upper via region, which overlaps with the twenty-eighth lower via region and is connected through a via, so that one end of the second metal oxide structure OLB away from the channel region of the driving transistor T3 is electrically connected to the gate of the driving transistor T3 through the fifteenth bridge portion MA15.

[0216] The following is a further introduction to the film layer structure of the fourth exemplary driving circuit.

[0217] 2 , 3 and 25 , the low-temperature polycrystalline silicon semiconductor layer LSCL may be provided with a first lower via area HA1 to a tenth lower via area HA10, the first lower via area HA1 being located at the first electrode of the first reset transistor T1, the second lower via area HA2 being located at the second electrode of the first reset transistor T1, the third lower via area HA3 being located at the first electrode of the data write transistor T4, the fourth lower via area HA4 being located at the second electrode of the data write transistor T4, the fifth lower via area HA5 being located at the first electrode of the second light-emitting transistor T6, the sixth lower via area HA6 being located at the second electrode of the second light-emitting transistor T6, the seventh lower via area HA7 being located at the second electrode of the electrode reset transistor T7, the eighth lower via area HA8 being located at the second electrode of the second reset transistor T8, the ninth lower via area HA9 being located at the first electrode of the second reset transistor T8, and the tenth lower via area HA10 being located at the second electrode of the second light-emitting transistor T5.

[0218] Figure 26 is a schematic diagram of the first gate layer GT1 in one example. Referring to Figure 26 , the first gate layer GT1 is formed with a first capacitor reset control signal line RL1, a second capacitor reset control signal line RL2, a second scan signal line GPL, an enable signal line EML, and a first electrode CP1 of the storage capacitor Cst, extending along a first direction. The first capacitor reset control signal line RL1 extends along the first direction H1 and is used to apply the first capacitor reset control signal ResetP to the first reset transistor T1. The second capacitor reset control signal line RL2 extends along the first direction H1 and is used to apply the second capacitor reset control signal ResetH to the second reset transistor T8. The enable signal line EML extends along the first direction H1 and overlaps with the channel region T5A of the first light-emitting transistor and the channel region T6A of the second light-emitting transistor, serving as the gate of the first light-emitting transistor T5 and the gate of the second light-emitting transistor T6. The enable signal line EML can be used to apply the enable signal EM. The first electrode CP1 of the storage capacitor Cst overlaps with the channel region T3A of the driving transistor to be multiplexed as the gate of the driving transistor T3; the second scan signal line GPL extends along the first direction H1, and the second scan signal line GPL can overlap with the channel region T4A of the data write transistor, and the overlapping part is multiplexed as the gate of the data write transistor T4; the first electrode CP1 of the storage capacitor Cst overlaps with the channel region T3A of the driving transistor to be multiplexed as the gate of the driving transistor T3.

[0219] Figure 27 is a schematic diagram of the second gate layer GT2 in one example. Referring to Figure 27 , the second gate layer GT2 is provided with the second electrode CP2 of the storage capacitor Cst and the second first scan signal trace GNLB. The second electrode CP2 of the storage capacitor Cst overlaps with the first electrode CP1 of the storage capacitor Cst, and a clearance hole is provided to partially expose the first electrode CP1 of the storage capacitor Cst. The second first scan signal trace GNLB extends along the first direction H1 and is used to carry the second scan signal. The second electrode CP2 located in the second gate layer GT2 may be provided with a twentieth lower via area HA20.

[0220] Figure 28 is a schematic diagram of a metal oxide semiconductor layer (OSCL) in one example. Referring to Figure 28 , the metal oxide semiconductor layer (OSCL) includes a second electrode, a first electrode, and a channel region of a threshold compensation transistor (T2). Along the second direction (H2), the channel region (T1A) of the first reset transistor (T1A) is located on the side of the channel region (T2A) of the threshold compensation transistor (T2A) away from the channel region (T3A) of the drive transistor. The channel region (T2A) of the threshold compensation transistor (T2A) and the channel region (T5A) of the first light-emitting transistor (T5A) are located on either side of the channel region (T3A) of the drive transistor (T3A). Along the first direction (H1), the channel region (T4A) of the data write transistor (T4A) of the next row of drive circuits and the channel region (T1A) of the first reset transistor (T1A) are located on either side of the channel region (T7A) of the reset transistor (T7A) of the previous row of drive circuits. The second electrode of the first reset transistor (T1) and the second electrode of the threshold compensation transistor (T2) are interconnected. Furthermore, along the first direction, the channel regions (T1A) of the first reset transistor (T1A) and the channel regions (T2A) of the threshold compensation transistor (T2A) are interlaced. The metal oxide semiconductor layer OSCL is further provided with a twelfth lower via area HA12 and a thirteenth lower via area HA13 .

[0221] It should be noted that, in the embodiment of the present disclosure, the channel region T1A of the first reset transistor, the channel region T3A of the driving transistor, and the channel region T6A of the second light-emitting transistor are located in the low-temperature polycrystalline silicon semiconductor layer LSCL; the channel region T2A of the threshold compensation transistor is set in the metal oxide semiconductor layer OSCL; and the channel region T1A of the first reset transistor, the channel region T2A of the threshold compensation transistor, and the channel region T6A of the second light-emitting transistor are arranged in a straight line along the second direction.

[0222] FIG29 is a schematic diagram of the third gate layer GT3 in one example. Referring to FIG29 , the third gate layer GT3 is provided with a first initialization voltage line VTL1, a second initialization voltage line VTL2, a third initialization voltage line VTL3, and a first scan signal line GNLA. The first initialization voltage line VTL1 extends in a first direction H1 and can be used to apply Vinit1. The second initialization voltage line VTL2 extends along the first direction H1 and can be used to apply the second initialization voltage Vinit2. The third initialization voltage line VTL3 extends along the first direction H1 and can be used to apply the third initialization voltage Vinit3. The first scan signal line GNLA overlaps with the channel region T2A of the threshold compensation transistor, and the overlapping portion thereof is multiplexed into the second gate of the threshold compensation transistor T2. The first scan signal line GNLA overlaps with the second scan signal line GNLB, and the overlapping portion thereof is multiplexed into the upper and lower gates of the threshold compensation transistor T2.

[0223] The third gate layer GT3 may also be provided with a fourteenth lower via area HA14 located at the first initialization voltage trace VTL1, a fifteenth lower via area HA15 located at the third initialization voltage trace VTL3, a sixteenth lower via area HA16, a seventeenth lower via area HA17 and an eighteenth lower via area HA18 located at the second initialization voltage trace VTL2.

[0224] FIG30 is a schematic diagram of the first source-drain metal layer SD1 in an example. Referring to FIG30 , the first source-drain metal layer SD1 is further provided with a first bridge portion MA1 to a tenth bridge portion MA10;

[0225] The first bridge MA1 includes a first upper via region HB1 and a fourteenth upper via region HB14. The first upper via region HB1 overlaps with the first lower via region HA1 and is connected via a via. The fourteenth upper via region HB14 overlaps with the fourteenth lower via region HA14. Thus, the first initialization voltage line VTL1 is electrically connected to the first electrode of the first reset transistor T1 via the first bridge MA1.

[0226] The second bridge portion MA2 has a fifteenth upper via area HB15 and a twenty-seventh lower via area HA27. The fifteenth upper via area HB15 and the fifteenth lower via area HA15 overlap and are connected by a via. The twenty-seventh lower via area HA27 and the twenty-seventh upper via area HB27 overlap and are connected by a via. Thus, a signal is applied to the third initialization voltage trace VTL3 via the second bridge portion MA2.

[0227] The third bridge portion MA3 has an eleventh upper via area HB11 and a twelfth upper via area HB12, wherein the eleventh upper via area HB11 overlaps with the eleventh lower via area HA11 and is connected through a via, and the twelfth upper via area HB12 overlaps with the twelfth lower via area HA12 and is connected through a via, so that the second electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 through the third bridge portion MA3.

[0228] The fourth bridge portion MA4 has a third upper via area HB3 and a twenty-sixth lower via area HA26, wherein the third upper via area HB3 overlaps with the third lower via area HA3 and is connected through a via, and the twenty-sixth lower via area HA26 is connected to the twenty-sixth upper via area HB26 and is connected through a via, so that the signal is loaded onto the third initialization voltage trace VTL3 through the second bridge portion MA2.

[0229] The fifth bridge portion MA5 has a 21st lower via area HA21, a 20th upper via area HB20 and a tenth upper via area HB10, wherein the 21st lower via area HA21 overlaps with the 21st upper via area HB21 and is connected through vias, the 20th upper via area HB20 overlaps with the 20th lower via area HA20 and is connected through vias, and the tenth upper via area HB10 is connected to the tenth lower via area HA10 and is connected through vias, so that the power supply voltage VDD is connected to the first electrode of the first light-emitting transistor T5 through MA5.

[0230] The sixth bridge portion MA6 has a twenty-third lower via area HA23 and a sixth upper via area HB6, wherein the twenty-third lower via area HA23 overlaps with the twenty-third upper via area HB23 and is connected through a via, and the sixth upper via area HB6 overlaps with the sixth lower via area HA6 and is connected through a via, so that the second initialization voltage line VTL2 is electrically connected to the first electrode of the electrode reset transistor T7 through the first bridge portion MA6.

[0231] The seventh bridge portion MA7 has a seventh upper via area HB7 and an eighteenth upper via area HB18, wherein the seventh upper via area HB7 overlaps with the seventh lower via area HA7 and is connected through a via, and the eighteenth upper via area HB18 overlaps with the eighteenth lower via area HA18 and is connected through a via, so that the second initialization voltage line VTL2 is electrically connected to the second electrode of the electrode reset transistor T7 through the seventh bridge portion MA7.

[0232] The eighth bridge portion MA8 has a fourth upper via area HB4 and a ninth upper via area HB9, wherein the fourth upper via area HB4 overlaps with the fourth lower via area HA4 and is connected through a via, and the ninth upper via area HB9 overlaps with the ninth lower via area HA9 and is connected through a via, so that the second electrode of the data write transistor T4 is electrically connected to the second electrode of the second reset transistor T8 through the first bridge portion MA8.

[0233] The ninth bridge portion MA9 has a second upper via area HB2, a fifth upper via area HB5 and a thirteenth upper via area HB13, wherein the second upper via area HB2 overlaps with the second lower via area HA2 and is connected through a via, the fifth upper via area HB5 overlaps with the fifth lower via area HA5 and is connected through a via, the thirteenth upper via area HB13 overlaps with the thirteenth lower via area HA113 and is connected through a via, so that the second electrode of the first reset transistor T1, the first electrode of the second light-emitting transistor T6 and the first electrode of the threshold compensation transistor T2 are connected through the ninth bridge portion MA9.

[0234] The tenth bridge portion MA10 includes a sixteenth upper via region HB16 and an eighth upper via region HB8. The sixteenth upper via region HB16 and the sixteenth lower via region HA16 overlap and are connected via a via, and the eighth upper via region HB8 and the eighth lower via region HA8 overlap and are connected via a via. Thus, the third initialization voltage trace VLT3 is electrically connected to the first electrode of the second reset transistor T8 via the tenth bridge portion MA10.

[0235] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel comprising a base substrate, a driving layer, and a pixel layer stacked in sequence; the display panel having an array of circuit areas, each of the circuit areas having a pixel driving circuit for driving a sub-pixel; The driving layer is provided with a data signal line and the pixel driving circuit has a data writing transistor electrically connected to the data signal line; the orthographic projection of the channel region of the data writing transistor on the base substrate at least partially overlaps with the orthographic projection of the data signal line on the base substrate.

2. The display panel according to claim 1, wherein In two circuit areas adjacent to each other along the first direction, the thin film transistors of the two pixel driving circuits are symmetrically arranged; The driving layer includes a transistor layer and a first source-drain metal layer stacked in sequence, and the thin film transistor is arranged in the transistor layer; The driving layer has a multiplexing via hole that spans a boundary line between two adjacent circuit areas, and the first source-drain metal layer is simultaneously connected to the thin film transistors of the two pixel driving circuits through the multiplexing via hole.

3. The display panel according to claim 2, wherein: The display panel includes a first circuit area group distributed in an array, and the first circuit area group includes two circuit areas adjacent to each other along a first direction; The pixel driving circuit includes a first light emitting transistor for being electrically connected to a power supply voltage terminal; the transistor layer is provided with a first polysilicon conductive structure serving as a first electrode of two first light emitting transistors in the first circuit area group; The multiplexing via includes a first multiplexing via located in the first circuit area group, the first multiplexing via exposing the first polysilicon conductive structure; In the first circuit area group, the first source-drain metal layer includes a power supply voltage metal structure capable of loading a power supply voltage; The power voltage metal structure is electrically connected to the first polysilicon conductive structure through the first multiplexing via.

4. The display panel according to claim 3, wherein: The display panel includes a first circuit area group distributed in an array, and the first circuit area group includes two circuit areas adjacent to each other along a first direction; The pixel driving circuit further includes a second reset transistor, wherein the second electrode of the second reset transistor is electrically connected to the second electrode of the first light emitting transistor; and the first electrode of the second reset transistor is electrically connected to the third initialization voltage terminal; The transistor layer is provided with a second polysilicon conductive structure in the first circuit area group, which serves as the first electrode of the two second reset transistors; The multiplexing via includes a second multiplexing via located in the first circuit area group, the second multiplexing via exposing the second polysilicon conductive structure; In the first circuit area group, the first source-drain metal layer includes a third initialization metal structure capable of applying a third initialization voltage; The third initialization metal structure is electrically connected to the second polysilicon conductive structure through the second multiplexing via.

5. The display panel according to claim 2, wherein: The display panel includes a second circuit area group distributed in an array, and the second circuit area group includes two circuit areas adjacent to each other along a first direction; The pixel driving circuit includes a driving transistor and a first reset transistor electrically connected to a first initialization voltage terminal; a first electrode of the driving transistor is electrically connected to a second electrode of the data writing transistor, and a second electrode of the driving transistor is electrically connected to a second electrode of the first reset transistor; The transistor layer is provided with a third polysilicon conductive structure in the second circuit area group, which serves as the first electrode of the two first reset transistors; The multiplexing via includes a third multiplexing via located in the second circuit area group, wherein the third multiplexing via exposes the third polysilicon conductive structure; In the second circuit area group, the first source-drain metal layer includes a first initialization metal structure capable of applying a first initialization voltage; The first initialization metal structure is electrically connected to the third polysilicon conductive structure through the third multiplexing via. The display panel according to claim 1 , wherein: The driving layer includes a low-temperature polysilicon semiconductor layer, a metal oxide semiconductor layer, and a first source-drain metal layer stacked in sequence; The pixel driving circuit further includes a first reset transistor, a threshold compensation transistor, a driving transistor and a second light emitting transistor; a first electrode of the first reset transistor and a first initialization transistor The voltage end is electrically connected, the second electrode of the first reset transistor, the first electrode of the threshold compensation transistor, the second electrode of the driving transistor and the first electrode of the second light emitting transistor are electrically connected, and the second electrode of the second light emitting transistor is electrically connected to the pixel electrode; The second electrode of the threshold compensation transistor is electrically connected to the gate of the driving transistor; The channel region of the first reset transistor, the channel region of the driving transistor and the channel region of the second light emitting transistor are located in the low-temperature polysilicon semiconductor layer; the channel region of the threshold compensation transistor is provided in the metal oxide semiconductor layer; The channel region of the first reset transistor, the channel region of the threshold compensation transistor, and the channel region of the second light emitting transistor are arranged in a straight line along a second direction.

7. The display panel according to claim 2, wherein: The transistor layer includes a low-temperature polysilicon semiconductor layer and a metal oxide semiconductor layer stacked; The pixel driving circuit further includes a first reset transistor, a threshold compensation transistor, a driving transistor, and a second light-emitting transistor; a first electrode of the first reset transistor is electrically connected to the first initialization voltage terminal, a second electrode of the first reset transistor, a first electrode of the threshold compensation transistor, a second electrode of the driving transistor, and a first electrode of the second light-emitting transistor are electrically connected, and a second electrode of the second light-emitting transistor is electrically connected to the pixel electrode; The second electrode of the threshold compensation transistor is electrically connected to the gate of the driving transistor; The channel region of the first reset transistor, the channel region of the drive transistor, and the channel region of the second light emitting transistor are located in the low-temperature polysilicon semiconductor layer; the channel region of the threshold compensation transistor is provided in the metal oxide semiconductor layer; Along the first direction, the channel region of the first reset transistor and the channel region of the threshold compensation transistor are alternately arranged.

8. The display panel according to claim 7, wherein: In the circuit area, the metal oxide semiconductor layer includes a first metal oxide structure arranged along a first direction and a second metal oxide structure arranged along a second direction; One end of the first metal oxide structure close to the data writing transistor and one end of the second metal oxide structure close to the driving transistor are connected to each other; the channel region of the threshold compensation transistor is located in the second metal oxide structure.

9. The display panel according to claim 2, wherein: The first source-drain metal layer includes a first metal structure and a second metal structure; The second metal structure is electrically connected to the second electrode of the first reset transistor, the second electrode of the driving transistor, and the first electrode of the threshold compensation transistor through a via; The first metal structure is electrically connected to the second electrode of the threshold compensation transistor and the gate of the driving transistor through a via; A dimension of the second metal structure along the second direction is smaller than a dimension of the first metal structure along the second direction.

10. The display panel according to claim 9, wherein: The driving layer includes a low-temperature polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer, a first source-drain metal layer, and a second source-drain metal layer, which are stacked in sequence; The first gate layer is provided with a gate of the data writing transistor, and the display panel is provided with a second scanning signal line electrically connected to the gate of the data writing transistor; In the circuit area, the second scan signal routing line includes a first sub-scan routing line located in the first source / drain metal layer and a second sub-scan routing line located in the second source / drain metal layer; The first sub-scanning line is electrically connected to the gate of the data writing transistor through a via hole, and the second sub-scanning line is electrically connected to the first sub-scanning line through a via hole.

11. The display panel according to claim 10, wherein: In the circuit area, the metal oxide semiconductor layer includes a second metal oxide structure arranged along a second direction; an end of the second metal oxide structure away from the channel region of the driving transistor is electrically connected to the gate of the driving transistor through the first metal structure located in the first source-drain metal layer; In the circuit area, the first metal structure and the second sub-scanning trace are overlapped.

12. The display panel according to claim 1, wherein: The driving layer includes a low-temperature polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer and a first source-drain metal layer stacked in sequence; The first gate layer is provided with a gate of the data writing transistor, and the display panel is provided with a first sub-scanning line electrically connected to the gate of the data writing transistor; The first sub-scanning wiring is located in the first source-drain metal layer and is electrically connected to the gate of the data writing transistor through a via hole.

13. The display panel according to claim 7, wherein: In the circuit region, the metal oxide semiconductor layer includes a first metal oxide structure, a second metal oxide structure, and a third metal oxide structure connected in sequence, wherein the first metal oxide structure and the third metal oxide structure are arranged in parallel along the second direction; the second metal oxide structure is arranged along the first direction, and an end of the first metal oxide structure away from the driving transistor and an end of the third metal oxide structure away from the driving transistor are electrically connected to each other; One end of the third metal oxide structure close to the driving transistor is electrically connected to the gate of the driving transistor through the first metal structure located in the first source-drain metal layer; one end of the first metal oxide structure close to the driving transistor is electrically connected to the second electrode of the driving transistor through the second metal structure located in the first source-drain metal layer; The pixel driving circuit has a threshold compensation transistor, which includes two sub-transistors. Channel regions of the two sub-transistors are respectively located on the first metal oxide structure and the third metal oxide structure.

14. The display panel according to claim 9, wherein: The driving layer includes a low-temperature polysilicon semiconductor layer, a first source-drain metal layer, and a second source-drain metal layer stacked in sequence; The low-temperature polysilicon semiconductor layer includes a fourth polysilicon conductive structure, and the fourth polysilicon conductive structure serves as the second electrode of the first reset transistor; One end of the fourth polysilicon conductive structure close to the channel region of the driving transistor is electrically connected to the second electrode of the driving transistor through the second metal structure located in the first source-drain metal layer.

15. The display panel according to claim 5, wherein: The driving layer includes a low-temperature polysilicon semiconductor layer, a first source-drain metal layer, and a second source-drain metal layer stacked in sequence; The low-temperature polysilicon semiconductor layer includes a fourth polysilicon conductive structure and a fifth polysilicon conductive structure, the fourth polysilicon conductive structure serving as the second electrode of the first reset transistor; the fifth polysilicon conductive structure is interconnected with the drain electrode of the driving transistor; One end of the fourth polysilicon conductive structure close to the channel region of the driving transistor is connected to the fifth polysilicon conductive structure.

16. The display panel according to claim 1, wherein The driving layer includes a low-temperature polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer and a first source-drain metal layer stacked in sequence; The pixel driving circuit further includes a second reset transistor and a first light emitting transistor, wherein the second electrode of the second reset transistor is electrically connected to the second electrode of the first light emitting transistor; second The first electrode of the reset transistor is electrically connected to the third initialization voltage terminal; the first light emitting transistor is electrically connected to the power supply voltage terminal; The driving layer has a third initialization voltage wiring for loading a third initialization voltage and an enable signal wiring for loading an enable signal; The third initialization voltage line is located in the third gate layer and extends along the first direction. The enable signal line is located in the first gate layer and extends along the first direction. The enable signal line and the third initialization voltage line are overlapped.

17. A display device comprising the display panel according to any one of claims 1 to 16.

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