Capacitor and preparation method thereof

Abstract

The invention relates to a capacitor and a preparation method thereof. The capacitor includes: a substrate; the capacitor structure is located in the substrate and on the substrate; the capacitor structure at least comprises a first electrode layer, a first dielectric layer and a second electrode layer which are sequentially stacked from bottom to top; the electrode opening is at least located in the capacitor structure and exposes at least one of the first electrode layer and the second electrode layer; the etching barrier layer at least covers the bottom of the electrode opening and the side wall of the electrode opening; the electrode contact structure is located in the electrode opening and at least makes contact with at least one of the first electrode layer and the second electrode layer. According to the capacitor, the etching barrier layers are at least formed at the bottoms of the electrode openings and the side walls of the electrode openings, in the process of forming the electrode contact structures, the first electrode layer and the second electrode layer can be prevented from being over-etched, leakage current is reduced, and therefore a manufacturing process window is expanded, and manufacturing process stability and the product yield are improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technologies, and particularly to a capacitor and a method for manufacturing the same. Background Art

[0002] Deep Trench Capacitors (DTCs) can effectively improve the impedance of the Power Delivery Network (PDN) and the logic voltage drop, and are currently widely used in fields such as power supplies.

[0003] When forming electrode contact holes connecting to the electrode layer, deep trench capacitors are prone to over-etching the electrode layer, and even etching through the electrode layer. When forming electrode contact structures in the electrode contact holes, it is easy to cause excessive leakage current, thus affecting the product yield and other issues. Summary of the Invention

[0004] Based on this, to address the problems in the above background art, it is necessary to provide a capacitor and a method for manufacturing the same, which have the advantages of preventing over-etching of the electrode layer, reducing leakage current, and thus improving the product yield.

[0005] To solve the above technical problems and other problems, in a first aspect, this application provides a capacitor, which includes:

[0006] A substrate;

[0007] A capacitive structure located within and on the substrate; the capacitive structure at least includes a first electrode layer, a first dielectric layer, and a second electrode layer stacked in sequence from bottom to top;

[0008] An electrode opening, at least located within the capacitive structure and exposing at least one of the first electrode layer and the second electrode layer;

[0009] An etch stop layer covering at least the bottom and the sidewalls of the electrode opening;

[0010] An electrode contact structure located within the electrode opening and in contact with at least one of the first electrode layer and the second electrode layer.

[0011] In some embodiments, trenches are formed within the substrate, and the capacitive structure is located within the trenches and on the substrate.

[0012] In some embodiments, the capacitive structure includes a trench capacitor and a planar capacitor, and the trench capacitor and the planar capacitor are integrally connected; the trench capacitor is located within the trench, and the planar capacitor is located on the substrate.

[0013] In some embodiments, the electrode opening includes a first electrode opening and a second electrode opening; the first electrode opening exposes the second electrode layer, and the second electrode opening exposes the first electrode layer;

[0014] The electrode contact structure includes a first electrode contact structure and a second electrode contact structure; the first electrode contact structure is located within a first electrode opening and is in contact with the second electrode layer; the second electrode contact structure is located within a second electrode opening and is in contact with the first electrode layer.

[0015] In some embodiments, the electrode structure further includes: a second dielectric layer and a third electrode layer; the second dielectric layer is located on the upper surface of the second electrode layer; the third electrode layer is located on the upper surface of the second dielectric layer;

[0016] The electrode contact structure further includes a third electrode contact structure that is in contact with the third electrode layer.

[0017] In some embodiments, the third electrode layer includes a first sub-electrode layer and a second sub-electrode layer; the first sub-electrode layer is located on the upper surface of the second dielectric layer; the second sub-electrode layer is located on the upper surface of the first sub-electrode layer.

[0018] In some embodiments, the capacitor further includes:

[0019] A bottom insulating layer, located between the substrate and the capacitor structure;

[0020] A filling dielectric layer, located on the upper surface of the capacitor structure; the electrode opening is also located within the filling dielectric layer and penetrates through the filling dielectric layer in the thickness direction; an etching stop layer is also located on the upper surface of the filling dielectric layer;

[0021] A support layer, located on the upper surface of the etching stop layer and filling the electrode opening.

[0022] In a second aspect, the present application further provides a method for manufacturing a capacitor, the method for manufacturing a capacitor including:

[0023] Providing a substrate;

[0024] Forming a capacitor structure within and on the substrate; the capacitor structure at least includes a first electrode layer, a first dielectric layer, and a second electrode layer stacked in sequence from bottom to top;

[0025] Forming an electrode opening within the capacitor structure; the electrode opening exposes at least one of the first electrode layer and the second electrode layer;

[0026] Forming an etching stop layer that at least covers the bottom and the sidewalls of the electrode opening;

[0027] Forming an electrode contact structure that is located within the electrode opening and is in contact with at least one of the first electrode layer and the second electrode layer.

[0028] In some embodiments, forming a capacitor structure within and on the substrate includes:

[0029] Form a trench in the substrate;

[0030] Form a capacitor structure in the trench and on the substrate.

[0031] In some embodiments, before forming the capacitor structure in the trench and on the substrate, it further includes: forming a bottom insulating layer in the trench and on the substrate; the capacitor structure is formed on the upper surface of the bottom insulating layer;

[0032] After forming the capacitor structure in and on the substrate and before forming an electrode opening in the capacitor structure, it further includes: forming a filling dielectric layer on the upper surface of the capacitor structure; the electrode opening is also located in the filling dielectric layer and penetrates the filling dielectric layer in the thickness direction;

[0033] The etching barrier layer is also located on the upper surface of the filling dielectric layer; after forming the etching barrier layer and before forming the electrode contact structure, it further includes: forming a support layer on the upper surface of the etching barrier layer, the support layer fills the electrode opening; the etching selectivity ratio of the support layer to the etching barrier layer is greater than 1.

[0034] In the capacitor of the above embodiment, by forming an etching barrier layer at least at the bottom and on the sidewalls of the electrode opening, during the formation of the electrode contact structure, over-etching of the first electrode layer and the second electrode layer can be avoided, leakage current can be reduced, thereby expanding the process window, improving process stability and product yield.

[0035] In the method for manufacturing the capacitor of the above embodiment, by forming an etching barrier layer at the bottom and on the sidewalls of the electrode opening before forming the electrode contact structure, during the formation of the electrode contact structure, over-etching of the first electrode layer and the second electrode layer can be avoided, leakage current can be reduced, thereby expanding the process window, improving process stability and product yield. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0037] Figure 1 It is a flowchart of the method for manufacturing the capacitor provided by the present application;

[0038] Figure 2 It is a cross-sectional structure schematic diagram of the structure obtained in step S11 of the method for manufacturing the capacitor provided by the present application;

[0039] Figure 3Schematic cross-sectional structure diagram of the structure obtained after forming the bottom insulating layer in and on the substrate in the method for preparing a capacitor provided by the present application;

[0040] Figure 4 Schematic cross-sectional structure diagram of the structure obtained in step S12 of the method for preparing a capacitor provided by the present application;

[0041] Figure 5 Schematic cross-sectional structure diagram of the structure obtained after forming the filling dielectric layer on the upper surface of the capacitor structure in the method for preparing a capacitor provided by the present application;

[0042] Figure 6 Schematic cross-sectional structure diagram of the structure obtained in step S13 of the method for preparing a capacitor provided by the present application;

[0043] Figure 7 Schematic cross-sectional structure diagram of the structure obtained in step S14 of the method for preparing a capacitor provided by the present application;

[0044] Figure 8 Schematic cross-sectional structure diagram of the structure obtained after forming the isolation groove in the method for preparing a capacitor provided by the present application;

[0045] Figure 9 Schematic cross-sectional structure diagram of the structure obtained after forming the support layer in the method for preparing a capacitor provided by the present application;

[0046] Figure 10 Schematic cross-sectional structure diagram of the structure obtained in step S151 of the method for preparing a capacitor provided by the present application;

[0047] Figure 11 Schematic cross-sectional structure diagram of the structure obtained in step S152 of the method for preparing a capacitor provided by the present application.

[0048] Explanation of reference numerals:

[0049] 10. Substrate; 11. Groove; 12. Capacitor structure; 121. Groove capacitor; 122. Planar capacitor; 123. First electrode layer; 124. First dielectric layer; 125. Second electrode layer; 126. Second dielectric layer; 127. Third electrode layer; 1271. First sub-electrode layer; 1272. Second sub-electrode layer; 131. First electrode opening; 132. Second electrode opening; 14. Etching barrier layer; 15. Bottom insulating layer; 16. Filling dielectric layer; 17. Support layer; 181. First electrode contact hole; 182. Second electrode contact hole; 183. Third electrode contact hole; 191. First electrode contact structure; 192. Second electrode contact structure; 193. Third electrode contact structure; 20. Isolation groove; 21. Isolation structure. Detailed description of the invention

[0050] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0052] In the case of using "including", "having", and "comprising" described herein, unless explicit limiting terms are used, such as "only", "consisting of", etc., another component can also be added. Unless otherwise mentioned, terms in the singular form can include the plural form and should not be understood as having a quantity of one.

[0053] It should be understood that although terms such as "first" and "second" can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, the first element can be called the second element, and similarly, the second element can be called the first element.

[0054] In this application, unless otherwise clearly specified and defined, terms such as "connected" and "coupled" should be understood in a broad sense. For example, it can be directly connected or indirectly connected through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0055] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present disclosure schematically. Although only the components related to the present disclosure are shown in the diagrams and are not drawn according to the number, shape, and size of the components in actual implementation, the types, numbers, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0056] Deep trench capacitors can effectively improve the impedance of the power distribution network and the logic voltage drop, and are currently widely used in fields such as power supplies.

[0057] The deep trench capacitor will include multiple electrode layers stacked at intervals from bottom to top in sequence. When forming multiple electrode contact holes respectively connected to different electrode layers simultaneously by means of a single photolithography and etching process, the process requirements are relatively high; and since the depths of the respective electrode contact holes are different, the above process is prone to over-etching the electrode layer in the middle layer and the electrode layer in the bottom layer, and even etching through the electrode layer, and when forming an electrode contact structure in the electrode contact hole, it is likely to cause excessive leakage current, thus affecting the product yield and other problems.

[0058] Forming each electrode contact hole by etching one by one can solve the above problems, but this method requires multiple etching processes and multiple photomasks, which will make the process technology relatively complex, the process expensive, and the cost relatively high.

[0059] The above problems can be solved by increasing the thickness of the electrode layer, but the increase in the thickness of the electrode layer will sacrifice the space of the trench, thus sacrificing the surface area and sacrificing part of the capacitance, resulting in a decline in electrical performance.

[0060] In one embodiment, please refer to Figure 1 , the present application provides a method for manufacturing a capacitor, and the method for manufacturing a capacitor may include the following steps:

[0061] S11: Provide a substrate;

[0062] S12: Form a capacitor structure in and on the substrate; the capacitor structure at least includes a first electrode layer, a first dielectric layer, and a second electrode layer stacked in sequence from bottom to top;

[0063] S13: Form an electrode opening in the capacitor structure; the electrode opening exposes at least one of the first electrode layer and the second electrode layer;

[0064] S14: Form an etch stop layer, and the etch stop layer at least covers the bottom and the sidewalls of the electrode opening;

[0065] S15: Form an electrode contact structure, and the electrode contact structure is located in the electrode opening and is in contact with at least one of the first electrode layer and the second electrode layer at least.

[0066] In the method for manufacturing a capacitor in the above embodiment, an etch stop layer is formed on the bottom and the sidewalls of the electrode opening before forming the electrode contact structure. During the process of forming the electrode contact structure, over-etching of the first electrode layer and the second electrode layer can be avoided, the leakage current can be reduced, thereby expanding the process window and improving the process stability and product yield.

[0067] In step S11, please refer to Figure 1 the S11 step in Figure 2 , and provide the substrate 10.

[0068] As an example, the substrate 10 may include, but is not limited to, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, a germanium substrate, a silicon germanium substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a gallium arsenide substrate, etc., and even a glass substrate, a ceramic substrate, and even a printed circuit board, an insulating dielectric layer substrate, etc.; in this embodiment, the substrate 10 is a silicon substrate.

[0069] In step S12, please refer to Figure 1 step S12 in Figures 3 to 4 and form a capacitor structure 12 in and on the substrate 10; the capacitor structure 12 at least includes a first electrode layer 123, a first dielectric layer 124, and a second electrode layer 125 stacked in sequence from bottom to top.

[0070] As an example, in step S12, forming the capacitor structure 12 in and on the substrate 10 may include the following steps:

[0071] S121: Form a trench 11 in the substrate 10, as Figure 3 shown;

[0072] S122: Form the capacitor structure 12 in the trench 11 and on the substrate 10, as Figure 4 shown.

[0073] As an example, in step S121, the trench 11 may be formed by, but is not limited to, photolithography and dry etching processes; the depth of the trench 11 is less than the thickness of the substrate 10; the longitudinal cross-section of the trench 11 may be formed to include, but is not limited to, a U shape, an inverted trapezoid, or a rectangle, etc., and the cross-section of the trench 11 may be formed to include, but is not limited to, a round hole, a square hole, and holes of other shapes, or a long strip groove, a square groove, a wavy groove, and combinations thereof, etc.; in this embodiment, the longitudinal cross-section shape of the trench 11 is a U shape, and the cross-section shape is a round hole or a long strip groove.

[0074] As an example, please continue to refer to Figure 3 and before forming the capacitor structure 12 in the trench 11 and on the substrate 10, that is, before step S122, the following steps may further be included: forming a bottom insulating layer 15 in the trench 11 and on the substrate 10.

[0075] Specifically, a silicon oxide layer may be formed as the bottom insulating layer 15 on the surface of the trench 11 and the upper surface of the substrate 10 by, but is not limited to, a thermal oxidation process.

[0076] As an example, in step S122, the first electrode layer 123, the first dielectric layer 124, and the second electrode layer 125 may be deposited in sequence by, but is not limited to, physical vapor deposition processes, chemical vapor deposition processes, or atomic layer deposition processes, etc.

[0077] As an example, please continue to refer to Figure 4, the electrode structure 12 may further include: a second dielectric layer 126 and a third electrode layer 127; the second dielectric layer 126 is located on the upper surface of the second electrode layer 125; the third electrode layer 127 is located on the upper surface of the second dielectric layer 126. Specifically, the second dielectric layer 126 and the third electrode layer 127 may be formed in sequence by, but not limited to, physical vapor deposition process, chemical vapor deposition process, atomic layer deposition process, etc.

[0078] As an example (not shown in the figure), the electrode structure 12 may further include: a third dielectric layer and a fourth electrode layer, and / or a fourth dielectric layer and a fifth electrode layer, where the third dielectric layer is located on the upper surface of the third electrode layer, and the fourth electrode layer is located on the upper surface of the third dielectric layer; the fourth dielectric layer is located on the upper surface of the fourth electrode layer, and the fifth electrode layer is located on the upper surface of the fourth dielectric layer, forming a capacitor structure with multiple dielectric layers and electrode layers stacked in sequence. The embodiments of the present disclosure only show examples of a capacitor structure with one dielectric layer and two electrode layers, or two dielectric layers and three electrode layers, which are not limited herein. Those of ordinary skill in the art can set the capacitor stack structure according to specific circumstances.

[0079] As an example, the third electrode layer 127 may include a first sub - electrode layer 1271 and a second sub - electrode layer 1272; the first sub - electrode layer 1271 is located on the upper surface of the second dielectric layer 126; a groove is formed on the upper surface of the first sub - electrode layer 1271, and the second sub - electrode layer 1272 is located in the groove on the upper surface of the first sub - electrode layer 1271.

[0080] As an example, the capacitor structure 12 may include a trench capacitor 121 and a planar capacitor 122, and the trench capacitor 121 is integrally connected to the planar capacitor 122; the trench capacitor 121 is located in the trench 11, and the planar capacitor 122 is located on the substrate 10.

[0081] As an example, the materials of the first dielectric layer 124 and the second dielectric layer 126 may both be high - k dielectric layers; the materials of the first dielectric layer 124 and the second dielectric layer 126 may also be different; in this embodiment, the materials of the first dielectric layer 124 and the second dielectric layer 126 are the same. The materials of the first dielectric layer 124 and the second dielectric layer 126 may include, but not limited to, one of the oxides of metals such as aluminum, zirconium, hafnium, niobium, etc. and their combinations, including laminated combinations or mixture combinations. The materials of the first dielectric layer 124 and the second dielectric layer 126 may include, but not limited to, silicon oxide layer, silicon nitride layer or silicon oxynitride layer, etc.

[0082] In one example, the materials of the first electrode layer 123, the second electrode layer 125, and the first sub-electrode layer 1271 can be the same. For example, the materials of the first electrode layer 123, the second electrode layer 125, and the first sub-electrode layer 1271 can all be titanium nitride. Of course, in other examples, the materials of the first electrode layer 123, the second electrode layer 125, and the first sub-electrode layer 1271 can also be metal silicide, copper, tungsten, or copper-tungsten alloy, etc.

[0083] As an example, the second sub-electrode layer 1272 can be a conductive layer. For example, the second sub-electrode layer 1272 can include, but is not limited to, doped polysilicon or a metal layer, etc.

[0084] As an example, the thickness of the bottom insulating layer 15, the first electrode layer 123, the first dielectric layer 124, the second electrode layer 125, the second dielectric layer 126, the first sub-electrode layer 1271, and the second sub-electrode layer 1272 can be set according to actual needs and will not be specifically limited here.

[0085] As an example, please refer to Figure 5 , after step S12, the following steps can also be included: there is a groove on the upper surface of the second sub-electrode layer 1272 of the capacitor structure 12. After forming the second sub-electrode layer 1272, a dielectric layer 16 is filled in the groove.

[0086] As an example, in step S12, there is no groove on the upper surface of the second sub-electrode layer 1272 of the capacitor structure 12. When forming the second sub-electrode layer 1272, the second sub-electrode layer 1272 completely fills the groove formed on the upper surface of the first sub-electrode layer 1271 of the capacitor structure 12.

[0087] As an example, the filling dielectric layer 16 can be formed by, but is not limited to, physical vapor deposition process, chemical vapor deposition process, or atomic layer deposition process; the filling dielectric layer 16 can include, but is not limited to, a silicon oxide layer.

[0088] As an example, the thickness of the filling dielectric layer 16 can be set according to actual needs and will not be specifically limited here. However, it should be noted that after forming the filling dielectric layer 16, the bottom insulating layer 15, the first electrode layer 123, the first dielectric layer 124, the second electrode layer 125, the second dielectric layer 126, the third electrode layer 127, and the filling dielectric layer 16 together completely fill the trench 11.

[0089] In step S13, please refer to Figure 1 the S13 step in Figure 6 , and an electrode opening is formed in the capacitor structure 12; the electrode opening exposes at least one of the first electrode layer 123 and the second electrode layer 125.

[0090] As an example, the electrode opening may include a first electrode opening 131 and a second electrode opening 132; the first electrode opening 131 exposes the second electrode layer 125, and the second electrode opening 132 exposes the first electrode layer 123. Of course, in other examples, the electrode opening may also be a single opening. In this case, the electrode opening may expose only the first electrode layer 123 or only the second electrode layer 125.

[0091] As an example, in step S13, when the filled dielectric layer 16 is formed and when the electrode opening may include the first electrode opening 131 and the second electrode opening 132, forming the electrode opening in the capacitor structure 12 may include the following steps:

[0092] S131: Form a first patterned mask layer (not shown) on the upper surface of the filled dielectric layer 16, and the first patterned mask layer defines the shape and position of the first electrode opening 131;

[0093] S132: Etch the filled dielectric layer 16 and the capacitor structure 12 based on the first patterned mask layer to form the first electrode opening 131;

[0094] S133: Remove the first patterned mask layer;

[0095] S134: Form a second patterned mask layer (not shown) on the upper surface of the filled dielectric layer 16, and the second patterned mask layer defines the shape and position of the second electrode opening 132;

[0096] S135: Etch the filled dielectric layer 16 and the capacitor structure 12 based on the second patterned mask layer to form the second electrode opening 132;

[0097] S136: Remove the second patterned mask layer.

[0098] When forming the first electrode opening 131 and the second electrode opening 132 in the capacitor structure 12 as described above, the first electrode opening 131 and the second electrode opening 132 are respectively etched based on different patterned mask layers, so that the depth of the first electrode opening 131 and the depth of the second electrode opening 132 can be precisely controlled, thereby avoiding etching or over-etching the second electrode layer 125 when forming the first electrode opening 131, and avoiding etching or over-etching the first electrode layer 123 when forming the second electrode opening 132.

[0099] As an example, in step S131, the first patterned mask layer may include, but is not limited to, a patterned hard mask layer or a patterned photoresist layer; when the first patterned mask layer is a patterned hard mask layer, the first patterned mask layer may include, but is not limited to, at least one of a spin-on carbon layer, a silicon nitride layer, or a silicon oxide layer. The hard mask layer can be patterned by lithography and dry etching processes to obtain the first patterned mask layer; when the first patterned mask layer is a patterned photoresist layer, the photoresist layer can be patterned by exposure and development processes to obtain the first patterned mask layer.

[0100] As an example, in step S132, a dry etching process can be used to etch the fill dielectric layer 16 and the capacitor structure 12 based on the first patterned mask layer to form the first electrode opening 131. The first electrode opening 131 can penetrate through the fill dielectric layer 16, the third electrode layer 127, and the second dielectric layer 126 in the thickness direction to expose the second electrode layer 125.

[0101] As an example, in step S133, when the first patterned mask layer is a patterned hard mask layer, the first patterned mask layer can be removed by, but is not limited to, an etching process or a chemical mechanical polishing process; when the first patterned mask layer is a patterned photoresist layer, the first patterned mask layer can be removed by, but is not limited to, an ashing process.

[0102] As an example, in step S134, the second patterned mask layer may include, but is not limited to, a patterned hard mask layer or a patterned photoresist layer; when the second patterned mask layer is a patterned hard mask layer, the second patterned mask layer may include, but is not limited to, at least one of a spin-on carbon layer, a silicon nitride layer, or a silicon oxide layer. The hard mask layer can be patterned by lithography and dry etching processes to obtain the second patterned mask layer; when the second patterned mask layer is a patterned photoresist layer, the photoresist layer can be patterned by exposure and development processes to obtain the second patterned mask layer.

[0103] As an example, in step S135, a dry etching process can be used to etch the fill dielectric layer 16 and the capacitor structure 12 based on the second patterned mask layer to form the second electrode opening 132. The second electrode opening 132 can penetrate through the fill dielectric layer 16, the third electrode layer 127, the second dielectric layer 126, the second electrode layer 125, and the first dielectric layer 124 in the thickness direction to expose the first electrode layer 123.

[0104] As an example, in step S136, when the second patterned mask layer is a patterned hard mask layer, the second patterned mask layer can be removed by, but is not limited to, an etching process or a chemical mechanical polishing process; when the second patterned mask layer is a patterned photoresist layer, the second patterned mask layer can be removed by, but is not limited to, an ashing process.

[0105] In step S14, refer to Figure 1 step S14 in Figure 7 and form an etch stop layer 14, where the etch stop layer 14 covers at least the bottom of the electrode opening and the sidewalls of the electrode opening.

[0106] As an example, the etch stop layer 14 may also cover the upper surface of the filling dielectric layer 16.

[0107] As an example, the etch stop layer 14 may be formed by, but not limited to, physical vapor deposition process, chemical vapor deposition process or atomic layer deposition process.

[0108] In one example, refer to Figure 8 and after step S14, it may further include:

[0109] Etch the etch stop layer 14, the filling dielectric layer 16, the capacitor structure 12 and the bottom insulating layer 15 to form an isolation trench 20; the isolation trench 20 penetrates at least the filling dielectric layer 16, the third electrode layer 127, the second dielectric layer 126, the second electrode layer 125, the first dielectric layer 124 and the first electrode layer 123 in the thickness direction.

[0110] As an example, the etch stop layer 14, the filling dielectric layer 16, the capacitor structure 12 and the bottom insulating layer 15 may be etched by, but not limited to, dry etching process to form the isolation trench 20.

[0111] As an example, the isolation trench 20 may also penetrate the bottom insulating layer 15.

[0112] As an example, refer to Figure 9 and after forming the etch stop layer 14 and before forming the electrode contact structure, it further includes: forming a support layer 17 on the upper surface of the etch stop layer 14, where the support layer 17 fills the electrode opening; the etch selectivity of the support layer 17 to the etch stop layer 14 is greater than 1.

[0113] As an example, the support layer 17 fills the first electrode opening 131 and the second electrode opening 132 and extends to the upper surface of the etch stop layer 14.

[0114] As an example, the support layer 17 may be formed by, but not limited to, physical vapor deposition process, chemical vapor deposition process or atomic layer deposition process.

[0115] As an example, the etch selectivity of the support layer 17 to the etch stop layer 14 may be greater than or equal to 50. For example, the etch selectivity of the support layer 17 to the etch stop layer 14 may be 50, 60, 70, 80, 90 or 100, etc.

[0116] As an example, the support layer 17 may include a polysilicon layer or a silicon oxide layer; in this embodiment, the support layer 17 may be a silicon oxide layer. The etch stop layer 14 may include, but is not limited to, a silicon nitride layer, a silicon carbonitride layer.

[0117] As an example, the support layer 17 also fills the isolation trench 20, and the support layer 17 located in the isolation trench 20 constitutes an isolation structure 21. A trench electrode 121 and a flat electrode 122 located around it may constitute an electrode structure 12. The capacitor in this embodiment may include a plurality of electrode structures 12. The isolation structure 12 is located between adjacent electrode structures 12, and the isolation structure 21 is used to insulate and isolate adjacent two electrode structures 12.

[0118] In step S15, please refer to Figure 1 step S15 in Figures 10 to 11 , and form an electrode contact structure. The electrode contact structure is located in the electrode opening and is in contact with at least one of the first electrode layer 123 and the second electrode layer 125.

[0119] As an example, when the electrode structure 12 only includes a first electrode layer 123, a first dielectric layer 124, and a second electrode layer 125 stacked in sequence from bottom to top, the electrode contact structure may include a first electrode contact structure 191 and a second electrode contact structure 192; the first electrode contact structure 191 is located in the first electrode opening 131 and is in contact with the second electrode layer 125; the second electrode contact structure 192 is located in the second electrode opening 132 and is in contact with the first electrode layer 123.

[0120] As an example, when the electrode structure 12 includes a first electrode layer 123, a first dielectric layer 124, a second electrode layer 125, a second dielectric layer 126, and a third electrode layer 127 stacked in sequence from bottom to top, the electrode contact structure may include a first electrode contact structure 191, a second electrode contact structure 192, and a third electrode contact structure 193; the first electrode contact structure 191 is located in the first electrode opening 131 and is in contact with the second electrode layer 125; the second electrode contact structure 192 is located in the second electrode opening 132 and is in contact with the first electrode layer 123; the third electrode contact structure 192 is in contact with the third electrode layer 127. Specifically, the third electrode contact structure 192 may be in contact with the second sub-electrode layer 1272, as Figure 11 shown; of course, in other embodiments, the third electrode contact structure 193 may also be in contact with the first sub-electrode layer 1271.

[0121] Taking the electrode contact structure that may include a first electrode contact structure 191, a second electrode contact structure 192, and a third electrode contact structure 193 as an example, in step S15, forming the electrode contact structure may include the following steps:

[0122] S151: Form a first electrode contact hole 181, a second electrode contact hole 182, and a third electrode contact hole 183. The first electrode contact hole 181 is located within the first electrode opening 131 and exposes the second electrode layer 125. The second electrode contact hole 182 is located within the second electrode opening 132 and exposes the first electrode layer 123. The third electrode contact hole 183 is located between the first electrode contact hole 181 and the second electrode contact hole 182 and exposes the second sub - electrode layer 1272, as Figure 10 shown;

[0123] S152: Form a first electrode contact structure 191 within the first electrode contact hole 181, a second electrode contact structure 192 within the second electrode contact hole 182, and a third electrode contact structure 193 within the third electrode contact hole 183.

[0124] As an example, in step S151, an integrated etching process can be used to form the first electrode contact hole 181, the second electrode contact hole 182, and the third electrode contact hole 183. Using the integrated etching process to form the first electrode contact hole 181, the second electrode contact hole 182, and the third electrode contact hole 183 only requires one photomask, which can reduce the use of photomasks and thus save costs.

[0125] Specifically, in step S151, forming the first electrode contact hole 181, the second electrode contact hole 182, and the third electrode contact hole 183 may include the following steps:

[0126] S1511: Form a third patterned mask layer (not shown) on the upper surface of the support layer 17. The third patterned mask layer simultaneously defines the shape and position of the first electrode contact hole 181, the shape and position of the second electrode contact hole 182, and the shape and position of the third electrode contact hole 183.

[0127] S1512: Etch the support layer 17, the etch stop layer 14, the filling dielectric layer 16, and the capacitor structure 12 based on the third patterned mask layer to form the first electrode contact hole 181, the second electrode contact hole 182, and the third electrode contact hole 183.

[0128] As an example, in step S1511, the third patterned mask layer may include, but is not limited to, a patterned hard mask layer or a patterned photoresist layer; when the third patterned mask layer is a patterned hard mask layer, the third patterned mask layer may include, but is not limited to, at least one of a spin-on carbon layer, a silicon nitride layer, or a silicon oxide layer. The hard mask layer can be patterned by lithography and dry etching processes to obtain the third patterned mask layer; when the third patterned mask layer is a patterned photoresist layer, the photoresist layer can be patterned by an exposure and development process to obtain the third patterned mask layer.

[0129] As an example, in step S1512, a dry etching process can be used to etch the support layer 17, the etch stop layer 14, the fill dielectric layer 16, and the capacitor structure 12 based on the third patterned mask layer to form a first electrode contact hole 181, a second electrode contact hole 182, and a third electrode contact hole 183.

[0130] As an example, after step S1512, the following steps may further be included:

[0131] S1513: Remove the third patterned mask layer.

[0132] Specifically, in step S1513, when the third patterned mask layer is a patterned hard mask layer, the third patterned mask layer can be removed by, but is not limited to, an etching process or a chemical mechanical polishing process; when the third patterned mask layer is a patterned photoresist layer, the third patterned mask layer can be removed by, but is not limited to, an ashing process.

[0133] As an example, in step S152, forming a first electrode contact structure 191 in the first electrode contact hole 181, forming a second electrode contact structure 192 in the second electrode contact hole 182, and forming a third electrode contact structure 193 in the third electrode contact hole 183 may include the following steps:

[0134] S1521: Form a contact material layer (not shown). The contact material layer fills the first electrode contact hole 181, the second electrode contact hole 182, and the third electrode contact hole 183 and covers the upper surface of the support layer 17;

[0135] S1522: Remove the contact material layer located on the upper surface of the support layer 17, and retain the contact material layers in the first electrode contact hole 181, the second electrode contact hole 182, and the third electrode contact hole 183 as the first electrode contact structure 191, the second electrode contact structure 192, and the third electrode contact structure 193, respectively. The first electrode contact structure 191 is in contact with the second electrode layer 125, the second electrode contact structure 192 is in contact with the first electrode layer 123, and the third electrode contact structure 193 is in contact with the second sub-electrode layer 1272.

[0136] As an example, a contact material layer may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

[0137] In one example, the contact material layer may include a single-layer structure. In this case, the contact material layer may include, but not limited to, a metal layer, such as a copper layer, a nickel layer, an aluminum layer, or a gold layer, etc. Of course, in other examples, the contact material layer may also be a laminated structure. In this case, the contact material layer may include a metal barrier layer and a metal layer; the metal barrier layer may include, but not limited to, a titanium nitride layer, tantalum, tantalum nitride, etc., and the metal layer may include, but not limited to, a copper layer, a nickel layer, an aluminum layer, or a gold layer and metal alloys, etc.

[0138] In the method for preparing a capacitor of the above embodiment, before forming the first electrode contact hole, the second electrode contact hole, and the third electrode contact hole, an etch stop layer is first formed in the first electrode opening and the second electrode opening. During the process of forming the first electrode contact hole, the second electrode contact hole, and the third electrode contact hole, over-etching of the second electrode layer and the first electrode layer can be avoided, leakage current can be reduced, thereby expanding the process window, improving process stability and product yield; at the same time, due to the protection of the etch stop layer, the first electrode contact hole, the second electrode contact hole, and the third electrode contact hole can be formed simultaneously by an all-in-one etching process, reducing the use of photomasks, thereby saving costs.

[0139] In another embodiment, please continue to refer to Figures 1 to 11 , the present application also provides a capacitor, which may include: a substrate 10; a capacitor structure 12, the capacitor structure 12 being located within and on the substrate 10; the capacitor structure 12 including a first electrode layer 123, a first dielectric layer 124, and a second electrode layer 125 stacked in sequence from bottom to top; an electrode opening, the electrode opening being at least located within the capacitor structure 12 and exposing at least one of the first electrode layer 123 and the second electrode layer 125; an etch stop layer 14, the etch stop layer 14 covering at least the bottom and the sidewalls of the electrode opening; an electrode contact structure, the electrode contact structure being located within the electrode opening and the electrode contact structure being in contact with at least one of the first electrode layer 123 and the second electrode layer 125 at least.

[0140] In the capacitor of the above embodiment, an etch stop layer 14 is formed at the bottom and the sidewalls of the electrode opening. During the process of forming the electrode contact structure, over-etching of the first electrode layer 123 and the second electrode layer 125 can be avoided, leakage current can be reduced, thereby expanding the process window, improving process stability and product yield.

[0141] As an example, the capacitor in this embodiment may be, but not limited to, prepared by using the method for preparing a capacitor corresponding to the above as Figures 1 to 11 obtained.

[0142] As an example, the substrate 10 may include, but is not limited to, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, a germanium substrate, a silicon germanium substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a gallium arsenide substrate, etc.; in this embodiment, the substrate 10 is a silicon substrate.

[0143] As an example, as Figure 3 shown, a trench 11 is formed in the substrate 10, and the capacitor structure 12 is located in the trench 11 and on the upper surface of the substrate 10.

[0144] As an example, the longitudinal cross-section of the trench 11 may be formed to include, but is not limited to, a U-shape, an inverted trapezoid, a rectangle, etc.; in this embodiment, the longitudinal cross-sectional shape of the trench 11 is a U-shape.

[0145] As an example, the capacitor structure 12 may include a trench capacitor 121 and a planar capacitor 122, and the trench capacitor 121 and the planar capacitor 122 are integrally connected; the trench capacitor 121 is located in the trench 11, and the planar capacitor 122 is located on the substrate 10.

[0146] As an example, the electrode openings include a first electrode opening 131 and a second electrode opening 132; the first electrode opening 131 exposes the second electrode layer 125, and the second electrode opening 132 exposes the first electrode layer 123; the electrode contact structures include a first electrode contact structure 191 and a second electrode contact structure 192; the first electrode contact structure 191 is located in the first electrode opening 131 and is in contact with the second electrode layer 125; the second electrode contact structure 192 is located in the second electrode opening 132 and is in contact with the first electrode layer 123.

[0147] As an example, the electrode structure 12 may further include: a second dielectric layer 126 and a third electrode layer 127; the second dielectric layer 126 is located on the upper surface of the second electrode layer 125; the third electrode layer 127 is located on the upper surface of the second dielectric layer 126; the electrode contact structure further includes a third electrode contact structure 193, and the third electrode contact structure 193 is in contact with the third electrode layer 127.

[0148] As an example, the third electrode layer 127 may include a first sub-electrode layer 1271 and a second sub-electrode layer 1272; the first sub-electrode layer 1271 is located on the upper surface of the second dielectric layer 126; the second sub-electrode layer 1272 is located on the upper surface of the first sub-electrode layer 1271; the third electrode contact structure 193 is in contact with the second sub-electrode layer 1272; of course, in other embodiments, the third electrode contact structure 193 may also be in contact with the first sub-electrode layer 1271.

[0149] As an example, the capacitor may further include: a bottom insulating layer 15, which is located between the substrate 10 and the capacitive structure 12. Specifically, the bottom insulating layer 15 covers the sidewalls of the trench 11, the bottom of the trench 11, and the upper surface of the substrate 10, as Figure 3 shown.

[0150] As an example, the capacitor may further include a filling dielectric layer 16, which is located on the upper surface of the capacitive structure 12; the electrode opening is also located within the filling dielectric layer 16 and penetrates the filling dielectric layer 16 in the thickness direction; the etching stop layer 14 is also located on the upper surface of the filling dielectric layer 16; a support layer 17, which is located on the upper surface of the etching stop layer 14 and fills the electrode opening.

[0151] As an example, the bottom insulating layer 15 may include, but is not limited to, a silicon oxide layer.

[0152] As an example, the materials of the first dielectric layer 124 and the second dielectric layer 126 may both be high-k dielectric layers; the materials of the first dielectric layer 124 and the second dielectric layer 126 may also be different; in this embodiment, the materials of the first dielectric layer 124 and the second dielectric layer 126 are the same, and the materials of the first dielectric layer 124 and the second dielectric layer 126 may include, but are not limited to, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, etc.

[0153] In one example, the materials of the first electrode layer 123, the second electrode layer 125, and the first sub-electrode layer 1271 may all be the same. For example, the materials of the first electrode layer 123, the second electrode layer 125, and the first sub-electrode layer 1271 may all be titanium nitride; of course, in other examples, the materials of the first electrode layer 123, the second electrode layer 125, and the first sub-electrode layer 1271 may also all be metal silicide, copper, tungsten, or a copper-tungsten alloy, etc.

[0154] As an example, the second sub-electrode layer 1272 may be a conductive layer. For example, the second sub-electrode layer 1272 may include, but is not limited to, doped polysilicon or a metal layer, etc.

[0155] As an example, the thickness of the bottom insulating layer 15, the thickness of the first electrode layer 123, the thickness of the first dielectric layer 124, the thickness of the second electrode layer 125, the thickness of the second dielectric layer 126, the thickness of the first sub-electrode layer 1271, and the thickness of the second sub-electrode layer 1272 may be set according to actual needs and are not specifically limited herein.

[0156] As an example, the filling dielectric layer 16 may include, but is not limited to, a silicon oxide layer.

[0157] As an example, the thickness of the filling dielectric layer 16 can be set according to actual needs and will not be specifically limited here. However, it should be noted that after the filling dielectric layer 16 is formed, the bottom insulating layer 15, the first electrode layer 123, the first dielectric layer 124, the second electrode layer 125, the second dielectric layer 126, the third electrode layer 127, and the filling dielectric layer 16 together fill the trench 11.

[0158] As an example, the etching stop layer 14 can also cover the upper surface of the filling dielectric layer 16.

[0159] As an example, the capacitor can also include an isolation trench 20, and the isolation trench 20 can penetrate through the etching stop layer 14, the filling dielectric layer 16, the capacitor structure 12, and the bottom insulating layer 15 in the thickness direction.

[0160] As an example, the support layer 17 fills the first electrode opening 131 and the second electrode opening 132 and extends to the upper surface of the etching stop layer 14.

[0161] As an example, the etching selectivity ratio of the support layer 17 to the etching stop layer 14 can be greater than or equal to 50. For example, the etching selectivity ratio of the support layer 17 to the etching stop layer 14 can be 50, 60, 70, 80, 90, or 100, etc.

[0162] As an example, the support layer 17 can include a polysilicon layer or a silicon oxide layer; in this embodiment, the support layer 17 can be a silicon oxide layer. The etching stop layer 14 can include, but is not limited to, a silicon nitride layer.

[0163] As an example, the support layer 17 also fills the isolation trench 20, and the support layer 17 located in the isolation trench 20 forms an isolation structure 21. A trench electrode 121 and a planar electrode 122 located around it can form an electrode structure 12. The capacitor in this embodiment can include multiple electrode structures 12, and the isolation structure 12 is located between adjacent electrode structures 12. The isolation structure 21 is used to insulate and isolate adjacent two electrode structures 12.

[0164] In one example, the first electrode contact structure 191, the second electrode contact structure 192, and the third electrode contact structure 193 may all include a single-layer structure. In this case, the first electrode contact structure 191, the second electrode contact structure 192, and the third electrode contact structure 193 may all include, but are not limited to, a metal layer. For example, a copper layer, a nickel layer, an aluminum layer, a gold layer, and so on. Of course, in other examples, the first electrode contact structure 191, the second electrode contact structure 192, and the third electrode contact structure 193 may all be laminated structures. In this case, the first electrode contact structure 191, the second electrode contact structure 192, and the third electrode contact structure 193 may all include a metal barrier layer and a metal layer. The metal barrier layer may include, but is not limited to, a titanium nitride layer, and the metal layer may include, but is not limited to, a copper layer, a nickel layer, an aluminum layer, a gold layer, and so on.

[0165] Note that the above embodiments are for illustrative purposes only and do not imply a limitation on the present disclosure.

[0166] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference may be made to each other.

[0167] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0168] The above-described embodiments only represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A capacitor, characterized in that, Comprising: A substrate; A capacitor structure located within and on the substrate; the capacitor structure at least includes a first electrode layer, a first dielectric layer, and a second electrode layer stacked in sequence from bottom to top; An electrode opening at least located within the capacitor structure and exposing at least one of the first electrode layer and the second electrode layer; An etch stop layer at least covering the bottom and the sidewalls of the electrode opening; An electrode contact structure located within the electrode opening and at least contacting at least one of the first electrode layer and the second electrode layer.

2. The capacitor according to claim 1, characterized in that, A trench is formed within the substrate, and the capacitor structure is located within the trench and on the substrate.

3. The capacitor according to claim 2, characterized in that, The capacitor structure includes a trench capacitor and a planar capacitor, and the trench capacitor is integrally connected to the planar capacitor; the trench capacitor is located within the trench, and the planar capacitor is located on the substrate.

4. The capacitor according to claim 1, wherein The electrode opening includes a first electrode opening and a second electrode opening; The first electrode opening exposes the second electrode layer, and the second electrode opening exposes the first electrode layer; The electrode contact structure includes a first electrode contact structure and a second electrode contact structure; the first electrode contact structure is located within the first electrode opening and contacts the second electrode layer; the second electrode contact structure is located within the second electrode opening and contacts the first electrode layer.

5. The capacitor according to claim 1, wherein The electrode structure further includes: a second dielectric layer and a third electrode layer; the second dielectric layer is located on the upper surface of the second electrode layer; the third electrode layer is located on the upper surface of the second dielectric layer; The electrode contact structure further includes a third electrode contact structure, and the third electrode contact structure contacts the third electrode layer.

6. The capacitor according to claim 5, characterized in that, The third electrode layer includes a first sub-electrode layer and a second sub-electrode layer; the first sub-electrode layer is located on the upper surface of the second dielectric layer; the second sub-electrode layer is located on the upper surface of the first sub-electrode layer.

7. The capacitor according to any one of claims 1 to 6, characterized in that, The capacitor further includes: A bottom insulating layer located between the substrate and the capacitor structure; A filling dielectric layer located on the upper surface of the capacitor structure; the electrode opening is also located within the filling dielectric layer and penetrates through the filling dielectric layer in the thickness direction; the etch stop layer is also located on the upper surface of the filling dielectric layer; A support layer located on the upper surface of the etch stop layer and filling the electrode opening.

8. A method for preparing a capacitor, characterized in that, Comprising: Providing a substrate; Forming a capacitor structure within and on the substrate; The capacitor structure at least includes a first electrode layer, a first dielectric layer, and a second electrode layer stacked in sequence from bottom to top; Forming an electrode opening within the capacitor structure; the electrode opening exposes at least one of the first electrode layer and the second electrode layer; Forming an etch stop layer that at least covers the bottom and the sidewalls of the electrode opening; Forming an electrode contact structure that is located within the electrode opening and at least contacts at least one of the first electrode layer and the second electrode layer.

9. The method for preparing a capacitor according to claim 8, characterized in that, The forming the capacitor structure within and on the substrate includes: Forming a trench within the substrate; Form the capacitor structure within the trench and on the substrate.

10. The method for manufacturing a capacitor according to claim 9, wherein before forming the capacitor structure within the trench and on the substrate, further comprising: forming a bottom insulating layer within the trench and on the substrate; the capacitor structure is formed on the upper surface of the bottom insulating layer; after forming the capacitor structure within the substrate and on the substrate and before forming an electrode opening within the capacitor structure, further comprising: forming a filling dielectric layer on the upper surface of the capacitor structure; the electrode opening is also located within the filling dielectric layer and penetrates through the filling dielectric layer in the thickness direction; the etching barrier layer is also located on the upper surface of the filling dielectric layer; after forming the etching barrier layer and before forming an electrode contact structure, further comprising: forming a support layer on the upper surface of the etching barrier layer, the support layer filling the electrode opening; the etching selectivity ratio of the support layer to the etching barrier layer is greater than 1.

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