Test vector generation method and system and computer readable storage medium

Abstract

The test vector generation method provided by the invention comprises the following steps: acquiring a chip function test instruction, and analyzing task content and task input parameters contained in the function test instruction; selecting a corresponding instruction template based on the task content, calling the instruction template, assigning an instruction register value, and obtaining a TDI data sequence and TDO data according to a corresponding address parameter and write / read data in task input parameters; the instruction template is created based on a jtag protocol, an ADI protocol and a data transmission protocol of a chip test circuit, and the instruction template is associated with a jtag test driving function; calling the jtag test driving function according to the instruction register value, the TDI sequence and the TDO data, and outputting the content of the function test instruction as the combination of the TDI data, the TCK signal, the TMS signal and the TDO signal at different moments. The invention further provides a test vector generation system and a computer readable storage medium.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip testing, and particularly relates to a test vector generation method, system and computer-readable storage medium. Background Art

[0002] When a chip performs a functional test on an ATE (Automatic Test Equipment), a corresponding function pattern (functional test vector) is required. Usually, the verification department develops a test platform (testbench) and test cases, and then simulates to obtain a waveform file (such as a Value Change Dump file, also known as a vcd file, which is a standard waveform file). Then, the waveform file generated by the simulation is converted into a wgl file (wgl: Wave Generation Language, a format used to describe the functional test mode in automatic test equipment) or a stil format file (stil: Standard Test Interface Language). However, the waveform file also records glitches. At the same time, in ATE testing, if you want to temporarily modify the content of the function pattern, you need to modify the test cases again and generate a waveform file, which takes a relatively long time.

[0003] ARM (Advanced RISC Machine) is a family of processors designed based on the principle of Reduced Instruction Set Computing (RISC). The SoC chip (System on Chip) with the ARM architecture is a solution that integrates the core functions of a computer onto a single chip. Such chips are widely used in smartphones, tablets, embedded systems, and other electronic devices that require a balance between high performance and low power consumption.

[0004] The ARM debugging system consists of components such as a debug interface, DAP (Debug Access Port), CTI (Cross Trigger Interface), ETM (Embedded Trace Macrocell), Trace Funnel (a component in the CoreSight architecture used to manage and merge trace data streams from multiple sources), TPIU (Trace Port Interface Unit), etc., as well as ARM and DSP processors (Digital Signal Processing). The debugger is connected to the target system through a JTAG (Joint Test Action Group, an international standard test protocol) interface, and then sends debug commands to the DAP through the JTAG interface.

[0005] In order to simplify the process of generating functional test vectors for SoC chips with the ARM architecture and facilitate the modification of functional test vectors, a method for quickly generating functional test vectors based on the ARM debugging system needs to be designed. Summary of the Invention

[0006] The present invention provides a method and system for generating test vectors, which directly convert chip functional test instructions into functional test vectors based on the JTAG protocol.

[0007] The present invention also provides a computer-readable storage medium for executing the test vector generation method.

[0008] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0009] To achieve one or part or all of the above objects or other objects, a method for generating test vectors provided by a technical solution of the present invention includes: obtaining chip functional test instructions, and parsing out the task content and task input parameters included in the functional test instructions; selecting a corresponding instruction template based on the task content, calling the instruction template, assigning values to the instruction register, and obtaining a TDI data (input data) sequence and TDO data (output data) according to the corresponding address parameters and write / read data in the task input parameters; the instruction template is created based on the JTAG protocol, the ADI protocol (ARM Debug Interface, a standardized debug interface protocol defined by ARM, provides hardware-level debug support for the processor, usually implemented through the JTAG or SWD protocol, and is a bridge between the debug tool and the processor core), and the data transfer protocol of the chip test circuit, and the instruction template is associated with a JTAG test driver function; calling the JTAG test driver function according to the instruction register value, the TDI sequence, and the TDO data, and outputting the content of the functional test instruction as a combination of TDI data, TCK signal (clock signal), TMS signal (mode selection signal), and TDO signal at different times.

[0010] According to the basic tasks that need to be executed when testing the chip to be tested based on the test protocol, multiple basic instruction templates are created, and each basic instruction template executes an instruction task, and multiple different basic instruction templates are combined to implement different test functions of the chip.

[0011] The basic instruction template at least includes a write instruction to the DP port (Debug Port), a read instruction to the DP port, a write instruction to the AP port (Access Port), and a read instruction to the AP port.

[0012] The basic instruction template includes a write instruction for the AP port on the AHB bus (one of the AMBA bus protocols), a read instruction for the AP port on the AHB bus; a write instruction for the DP port on the AHB bus, and a read instruction for the DP port on the AHB bus; the write instruction for the AP port on the AHB bus and the read instruction for the AP port on the AHB bus are further converted into read / write instructions for the AP port, and the write instruction for the DP port on the AHB bus and the read instruction for the DP port on the AHB bus are further converted into read / write instructions for the DP port.

[0013] Based on the task content included in the functional test instruction, select the corresponding basic instruction template, and convert the functional test instruction into read / write instructions for the AP port and DP port on the chip according to the basic instruction template; the read / write instructions for the AP port and DP port on the chip after conversion are further associated with the jtag test driver function Lian .

[0014] Assign the value of the instruction register according to the instruction task executed based on the basic instruction template; set intermediate variables according to the JTAG protocol, ADI protocol, and the data transmission protocol of the chip test circuit, and assign the intermediate variables to the TDI data sequence or TDO data; the intermediate variables are related to the address parameters and the data to be written / read required for the created read / write instructions for the AP port and DP port.

[0015] The jtag test driver function inputs the TMS value, controls the state machine to enter the IR register scan state, the Capture-IR state (the system captures or loads a predefined fixed value into the instruction register), and the Shift-IR state (the system shifts new instructions into the instruction register bit by bit through the TDI pin, and removes the old data bit by bit through the TDO pin) in sequence, and operates the IR register jointly through the input TMS value and the TCK clock signal. In the Shift-IR state, fill the assigned value of the instruction register bit by bit in the TDI data sequence format starting from the low bit to output the TDI data, and obtain the combinations of the TDI data, TMS signal, TCK signal, and TDO signal at different times.

[0016] The instruction template outputs the data expected to be read in the functional test instruction plus a tail identifier as the TDO data, and the jtag test driver function simply fills and outputs the TDO data generated by the instruction template.

[0017] When the basic instruction template is used to execute the task of accessing the DP port, the instruction register is assigned the value 0b1010; when the basic instruction template is used to execute the task of accessing the AP port, the instruction register is assigned the value 0b1011; the jtag test driver function obtains the value of the instruction register assigned by the instruction template, and fills the assigned value of the instruction register bit by bit in the TDI data sequence format starting from the low bit to output the TDI data.

[0018] The data transmission protocol of the chip test circuit includes the AMBA bus protocol (Advanced Microcontroller Bus Architecture, the on-chip system bus architecture specification for connecting and managing the communication between different functional modules in an embedded system), and the DAP debugger accesses the system resources on the chip based on the AMBA bus protocol.

[0019] A test vector generation system provided by another technical solution of the present invention includes: a test instruction parsing module that parses the input functional test instruction and outputs the task content and task input parameters included in the functional test instruction; a test vector generation module that selects a corresponding instruction template based on the task content, calls the instruction template, assigns a value to the instruction register, and obtains the TDI data sequence and TDO data according to the corresponding address parameter and write / read data in the task input parameters; the instruction template is created based on the jtag protocol, the ADI protocol, and the data transmission protocol of the chip test circuit, and the instruction template is associated with the jtag test driver function; the jtag test driver function is called according to the instruction register value, the TDI sequence, and the TDO data, and the functional test instruction content is output as a combination of the TDI data, the TCK signal, the TMS signal, and the TDO signal at different times.

[0020] A computer-readable storage medium provided by another technical solution of the present invention stores a computer program thereon, and when the computer program is executed by a processor, it implements the steps of the test vector generation method described above.

[0021] Compared with the prior art, the beneficial effects of the present invention mainly include: by parsing the task content and write / read data included in the functional test instruction, the present invention obtains the instruction register value, the TDI sequence, and the TDO data, and calls the jtag test driver function in the instruction template according to the instruction register value, the TDI sequence, and the TDO data, and uses the instruction template to convert the functional test instruction into a test vector for output. The present invention does not need to simulate and generate a waveform file and then convert it into a test vector, and has the advantage of high test vector generation efficiency. At the same time, it also solves the problem that the acquisition clock is inaccurate during the generation of the vcd of the simulation file, which affects the output of the test vector when the simulation file generates the test vector.

[0022] To make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following specifically presents preferred embodiments and, in conjunction with the accompanying drawings, provides a detailed description as follows. Description of the Drawings

[0023] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the following-described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] Figure 1 It is a flowchart of the test vector generation method of the present invention.

[0025] Figure 2 It is a schematic diagram of the debugger of the present invention for realizing system debugging and control on hardware.

[0026] Figure 3 It is a schematic diagram of the connection between the JTAG-DP of the present invention and an external debugger on hardware.

[0027] Figure 4 It is an architecture diagram of an arm debugging system of the present invention.

[0028] Figure 5 It is a schematic diagram of the working state of the DBGTAPSM state machine of the present invention.

[0029] Figure 6 It is a schematic diagram of the call relationship of the created instruction templates. Detailed Description of the Specific Embodiments

[0030] Regarding the foregoing and other technical contents, features, and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front, or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0031] Embodiment 1 Embodiment 1 provides a test vector generation method, which includes: obtaining chip functional test instructions, and parsing out the task content and task input parameters included in the functional test instructions; selecting a corresponding instruction template based on the task content, calling the instruction template, assigning values to the instruction register, and obtaining a TDI data sequence and TDO data according to the corresponding address parameter and write / read data in the task input parameters; the instruction template is created based on the jtag protocol, the ADI protocol, and the data transmission protocol of the chip test circuit, and the instruction template is associated with a jtag test driver function; calling the jtag test driver function according to the instruction register value, the TDI sequence, and the TDO data, and outputting the functional test instruction content as a combination of TDI data, TCK signal, TMS signal, and TDO signal at different times.

[0032] Among them, the obtained functional test instructions (also called functional test outputs) are developed by technical developers based on the functions to be implemented by the chip. The functional test instructions drive the chip under test to perform specific operations and output corresponding instruction execution results to verify whether the functions of the chip meet the requirements.

[0033] The following will explain in detail a test vector generation method according to Embodiment 1 with reference to the accompanying drawings.

[0034] The test vector generation method of the present invention is used for outputting functional test vectors of an SoC chip with an ARM architecture. According to the jtag protocol within the ARM debug system architecture, the functional test instructions are output as external interface test vectors of the jtag interface.

[0035] Specifically, as Figure 1 shown, it includes the following steps: Step 1: Create an instruction template based on the jtag protocol, the ADI protocol, and the data transmission protocol of the chip test circuit.

[0036] See Figure 4An architecture diagram of an ARM debugging system. The ARM debugging system includes debug interfaces (JTAG port), DAP debugger, CTI (Cross Trigger Interface), ETM (Embedded Trace Macrocell), Trance Funnel (which merges or distributes trace data from multiple sources), TPIU (Trace Port Interface Unit, responsible for outputting trace data from the chip interior to external devices), and other coresight components (on-chip debugging and tracing systems developed by ARM). The debugger is connected to the target board through the JTAG interface and then sends debug commands to the DAP through this interface. After receiving the commands, the DAP processes them differently depending on whether they are DP commands or AP commands: 1) If it is a DP command, the DAP directly processes and returns the result. For example, it can be used to obtain DAP information, set the AP address, terminate transaction access, etc. 2) If it is an AP command, the command is sent to the specified AP access port (memory access port MEM-AP or JTAG access port JTAG-AP). Taking the AP access port MEM-AP as an example, according to the AMBA bus protocol, it accesses the corresponding debug bus or system bus, and then realizes operations on relevant registers of coresight components, CPU, etc., or operations such as reading and writing memory values. Taking Figure 4 as an example, Figure 4 the DAP debugger accesses the coresight components through the Debug APB protocol. The Debug APB protocol belongs to the bus protocol for debugging in the ARM architecture and is part of the ARM AMBA (Advanced Microcontroller Bus Architecture) bus family. It is mainly used to communicate with the debugging logic inside the processor (such as debugging registers, debug interfaces, etc.) and is one of the core components of the ARM processor's debugging function).

[0037] In actual chip design, the data transfer protocol can also be other bus protocols, such as the Ahb protocol.

[0038] The above functions are achieved through a series of components and specifications, specifically including: 1) The connection port between the debugger and the chip uses the jtag protocol or the SWD protocol (Serial Wire Debug); 2) The ADI specification (ARM Debug Interface) stipulates how the debugger accesses the DP layer and the AP layer. See Figure 2Schematic diagram of the debugger implementing system debugging and control on hardware, including a DP, multiple APs connected to the DP, and system resources connected to the APs. The debugger is connected to the DP through a physical interface (usually a JTAG interface or an SWD interface), can directly access DP information, or select a certain AP connected to it through the DP register, and then access its corresponding system resources through the AP.

[0039] In the first embodiment, the debugger is connected to the DP through jtag on hardware. Refer to Figure 3 , the debugger of the ARM architecture debugging system is connected to the target board through the jtag interface, and debugging commands are sent to the debugger through this jtag interface. After receiving the command, the debugger will process it according to whether it is a command sent to the DP (Debug port, the main entry point for communication between the debugger and the target hardware, responsible for managing the debug connection, and providing a mechanism to reset the system, control execution, and communicate with one or more Access ports. The DP can be implemented through the jtag physical interface) port or a command sent to the AP (Access port, which allows the debugger to access different components on the chip, such as system memory, peripherals, etc.) port: If it is a DP command, the debugger will directly process it and return the result. If it is an AP command, the command will be sent to the JTAG-DP and then sent to the AP through the JTAG-DP.

[0040] The ADI protocol defines a hierarchical system composed of the following levels: Ⅰ. The jtag or SWD physical layer; Ⅱ. The jtag protocol or SWD protocol layer, which is used to manage the state machine of jtag or SWD; Ⅲ. The jtag or SWD data link layer, which is used to perform DP register and AP register access; Ⅳ. The AP layer, which is used to access one or more subsystems in the SOC.

[0041] 3) The coresight component contains the definitions of various on-chip debugging components, such as DP, APB-AP (accessing the AP port through the APB protocol), AXI-AP (accessing the AP port through the AXI protocol), etc.

[0042] 4) The CPU architecture defines the support of the CPU core for debugging capabilities, such as stopping the processor execution, single-step debugging, etc.

[0043] Combined with Figure 2 and the above analysis, it can be seen that whether it is the coresight component, the CPU, or the system memory, they are all bus resources for the AP (accessing system resources through the ARM AMBA bus). As long as the debugger controls the resource address corresponding to the AP operation, it can achieve the debugging and control of the system.

[0044] When designing the JTAG test circuit around the chip, the corresponding peripheral test circuit will be designed according to the requirements of the JTAG protocol, the ADI protocol, and the AMBA bus protocol (other data transmission protocols can also be used according to the actual circuit design requirements. Example 1 takes the AMBA bus protocol as an example for illustration). The created instruction template is created based on the JTAG protocol, the ADI protocol, and the AMBA bus protocol. Among them, not all peripheral test circuits will involve the AMBA bus structure. For example, in the chip peripheral circuit design, only when the DAP debugger accesses the chip resources through the AMBA bus, the instruction template creation will be based on the requirements of the AMBA bus protocol. The purpose of creating the instruction template is to reverse-derive and calculate the combination of data and signals input to the JTAG, including a set of data sequences such as the TDI, TMS, TCK, and RST interface signals (also known as TRST, Test Reset, test reset signal) and the expected TDO output result based on the tasks and related parameters to be achieved by the functional test instructions, so as to realize the automatic test or simulation test of the chip on the ATE device.

[0045] When creating the instruction template, multiple basic instruction templates need to be created according to the basic functions to be executed during the test of the chip to be tested. Each basic instruction template executes one instruction task, and multiple different basic instruction templates are combined to achieve different test functions of the chip. Based on the above explanation of the debugging process of the ARM architecture debugging, when the debugger executes different debugging tasks, it needs to send corresponding commands to the DP port or the AP port. Therefore, the created basic instruction template should at least include the write instruction to the DP port, the read instruction to the DP port, the write instruction to the AP port, and the read instruction to the AP port.

[0046] If there is an AHB bus (a type of AMBA bus, used for high-performance and high-clock-frequency system structures, and the AHB bus is designed according to design requirements and performance requirements) in the ARM architecture, then the created basic instruction template should also include the write instruction to the AP port on the AHB bus, the read instruction to the AP port on the AHB bus; and the write instruction to the DP port on the AHB bus, the read instruction to the DP port on the AHB bus; at the same time, the write instruction to the AP port on the AHB bus and the read instruction to the AP port on the AHB bus need to be further converted into the read-write instructions to the AP port, and the write instruction to the DP port on the AHB bus and the read instruction to the DP port on the AHB bus need to be further converted into the read-write instructions to the DP port.

[0047] The following uses code as an example (for the protocol mentioned above, a specific circuit structure is designed, corresponding to a specific instruction template code. Here, only the instruction template corresponding to a specific circuit structure is described. In practice, specific circuits can be designed according to the protocol requirements, and then specific instruction templates can be created) to illustrate the basic instruction template. Before the "#" is the code, and after the "#" is the meaning of the code.

[0048] Read instruction for the AP port on the AHB bus: jtag_ahb_ap_read(addr, data); # Read instruction for the AP port on the AHB bus; jtag_write_ap("32'h04", addr); # Pass the 31~0 bits of the value of 32'h04 and the addr address as parameters to the jtag_write_ap function; jtag_read_ap("32'h0c", data); # Pass the 32'h0c and data as parameters to the jtag_read_ap function.

[0049] Write instruction for the AP port on the AHB bus: jtag_ahb_ap_write_data(addr, data); # Write instruction for the AP port on the AHB bus; jtag_write_ap("32'h04", addr); # Pass the 31~0 bits of the value of 32'h04 and the addr address as parameters to the jtag_write_ap function; jtag_read_ap("32'h0c", data); # Pass the 32'h0c and data as parameters to the jtag_read_ap function.

[0050] Write instruction for the AP port: jtag_write_ap(addr, data); # Write instruction for the ap port, # Pass the addr address and data as parameters to the jtag_write_ap function; delay_time: 5000ns; # Set the delay time; value = int(addr) & int(32'hffff_fff0); # Specific operation of the above function: Perform an AND operation on the addr parameter and 32'hffff_fff0, retain the high 28 bits and assign them to the intermediate variable value; jtag_dp_wr(2'd2, value, "35'bx100"); / / Pass the three parameters 2'd2, value, and "35'bx100" to another dp write function. delay_time: 3000ns; / / Set the delay time. value = addr[3:2]; Assign the result of slicing the addr address to the intermediate variable value. jtag_ap_wr(value, data, 35'bx100); / / The following are the specific operations for the above jtag_ap_wr function.

[0051] jtag_ap_wr(addr, data, tdo_data); tdi_data = data + addr + "1'b0"; / / Assign value to tdi_data. ir_data = "4'b1011"; / / Assign value to tdi_data. According to the accessed ap port, assign a fixed value. tdo_data = tdo_data; jtag_process(ir_data, tdi_data, tdo_data); / / Pass the three parameters ir_data, tdi_data, and tdo_data to the jtag_process function, and output the TDI, TMS, TCK, and TDO vectors corresponding to the jtag interface. Here, the TDO value is the theoretical output value, used to compare with the output results of simulation or ATE testing.

[0052] Read instruction for the AP port: jtag_read_ap(addr, data); delay_time: 3000ns; value = int(addr) & int(32'hffff_fff0); jtag_dp_wr(2'd2, value, "35'bx100"); delay_time: 3060ns; value = addr[3:2]; jtag_ap_rd(value, "35'bx100"); delay_time = 3000ns; value = data + "3'b100"; jtag_dp_rd(2'd3, value); jtag_dp_rd(addr, data); value = "32'b0" + addr + "1'b1"; ir_data = 4'b1010; tdi_data = value; tdo_data = data; jtag_process(ir_data, tdi_data, tdo_data).

[0053] Write instruction for DP port: tag_write_dp(addr, banksel, data); delay_time: 2000ns; jtag_dp_wr(2'd2, banksel, "35'hx100"); delay_time: 2000ns; value = addr[1:0]; jtag_dp_wr(value, data, "35'hx100"); jtag_dp_wr(addr, data, tdo_data); value = data + addr + "1'b0"; ir_data = "4'b1010"; tdi_data = value; tdo_data = tdo_data; jtag_process(ir_data, tdi_data, tdo_data).

[0054] Read instruction for DP port: jtag_read_dp(addr, banksel, data); delay_time: 2000ns; jtag_dp_wr(2'd2, banksel, "35'hx100"); delay_time: 2000ns; value = addr[1:0]; jtag_dp_rd(value, "35'hx100"); delay_time = 2000ns; value = data + "3'b100"; jtag_dp_rd(2'd3, value); jtag_dp_rd(addr, data); value = "32'b0" + addr + "1'b1"; ir_data = 4'b1010; tdi_data = value; tdo_data = data; jtag_process(ir_data, tdi_data, tdo_data).

[0055] The parameter passing process in the above instruction template, i.e., the intermediate variables set (e.g., "value = "32'b0" + addr + "1'b1";"), and passing the intermediate variables to the TDI data sequence or TDO data, and the calling process between instruction templates are set according to the JTAG protocol, ADI protocol, and AMBA bus protocol. Specifically, the JTAG protocol stipulates the connection method between the debugger and the chip connection port, and the ADI specification (ARM Debug Interface) stipulates how the debugger accesses the DP layer and the AP layer. Therefore, the peripheral test circuit of the chip should be set based on the above protocols, and the parameter passing process mentioned above is the corresponding reverse derivation process of the functions implemented by the peripheral test circuit of the chip (when performing normal circuit tests, based on the functions that can be achieved by the chip test circuit, which corresponds to the layer-by-layer data passing process, and when performing reverse derivation of the instruction template, it is based on the functions of the peripheral test circuit of the chip for reverse derivation). When the chip debugging architecture uses the AMBA bus protocol, the corresponding external test circuit of the chip should also be set based on the used AMBA bus protocol, and the parameter passing process in the instruction template also needs to refer to the AMBA bus protocol. And the calling process between instruction templates is also set according to the above three protocols. The above code is only used to illustrate the framework structure of the instruction template. The design idea of the instruction template is how to access system resources through JTAG on the premise of knowing the function test instructions, the address parameters and register parameters corresponding to the function test instructions. The instruction template calculates the TDI data sequence input into the JTAG interface and the theoretically correct TDO data through the reverse calculation method (reverse derivation of the process from system resources to the JTAG interface).

[0056] The above instruction template is a process of hierarchical parsing. Taking the jtag_write_ap instruction for writing to the AP port as an example, to complete the jtag_write_ap instruction, it is also necessary to call the jtag_dp_wr instruction and the jtag_ap_wr instruction, and the above instructions all have corresponding templates. The corresponding instruction template codes have been given in the above code and will not be elaborated here. After combining the above three basic instruction templates, it is an instruction for writing to the AP port.

[0057] For the call relationship between the basic instruction templates of this application, see Figure 6 , and each basic instruction template can be set according to the JTAG protocol, ADI protocol, and AMBA bus protocol. See Figure 6 , where the jtag_process function generates ir_data, tdi_data, and tdo_data based on the instruction template and uses a state machine to output the TDI, TMS, TCK, and TDO vectors of the JTAG interface. The jtag_process function is explained in detail in Step 2. See Figure 6 , for example, if it is necessary to read and write chip resources (coresight components) through the AHB bus, it can be achieved by combining jtag_write_ap and jtag_read_ap. And the jtag_write_ap and jtag_read_ap instructions are formed by combining the basic instruction templates at the next level.

[0058] Step 2: Associate the basic instruction template with the JTAG test driver function.

[0059] Step 2-1: Based on the called instruction template, obtain ir_data, tdi_data, and tdo_data, and call the JTAG test driver function based on the obtained ir_data, tdi_data, and tdo_data.

[0060] The value of ir_data is selectively set according to whether it is accessing the DP port or the AP port. Among the IR instructions, the more commonly used ones are the DPACC (access to the DP port) and APACC (access to the AP port) instructions, that is, the IR instruction value is equal to 0b1010 (when the basic instruction template executes access to the DP port) or 0b1011 (when the basic instruction template executes access to the AP port). Therefore, in script development, only these two IR instruction values need to be satisfied.

[0061] Step 2-2: The JTAG test driver function is based on the JTAG protocol state machine. Using the state machine, it selects the corresponding operation state under the TMS signal, and operates the IR register under the cooperation of the TCK signal and the TMS signal, outputting the combinations of TDI data, TMS signal, TCK signal, and TDO signal at different times.

[0062] See Figure 5 the schematic diagram of the working state of the DBGTAPSM state machine (the extended state machine for debugging functions). The state machine moves IR and DR data into or out of the JTAG-DP through the DBGTDI (test input data) and DBGTDO signals (test output data). The present invention uses the state machine protocol and the working principle of the state machine for reverse derivation to obtain the TDI data. The present invention selects the state of the state machine through the value of DBGTMS (test state selection signal), controls the state machine to enter the IR register scan state, Capture-IR state, and Shift-IR state in sequence, and operates the IR register jointly through the input TMS value and the TCK clock signal. In the Shift-IR state, the assigned instruction register value is filled bit by bit in accordance with the TDI data sequence format (the tdi_data obtained from the instruction template is the TDI data sequence, which represents the data format of the TDI data, and then filled using the jtag process function) starting from the low bit to output the TDI data, obtaining the combinations of TDI data, TMS signal, TCK signal, and TDO signal at different times.

[0063] The operation process of the JTAG state machine is common general knowledge in the art and will not be elaborated here. This application fills the tdi_data data of the instruction template bit by bit under the control of the TCK signal and the TMS signal by the state machine.

[0064] The following takes a piece of code as an example to illustrate how the JTAG test driver function jtag_process performs the data shift operation of the JTAG instruction register by controlling the state transition of the TAP controller to achieve the bit-by-bit output of the TDI data.

[0065] Where the part before "#" is the code and the part after "#" is the code explanation.

[0066] # First, set the intermediate IR instruction value ir_data_tmp and the intermediate tdi data value wr_tdi_data_tmp according to the instruction type. Among IR instructions, the most commonly used ones are the DPACC (DP access command) and APACC (AP access command) instructions, that is, the IR instruction value is equal to 0b1010 or 0b1011 (when calling the instruction template processing function to test the instruction, the TR instruction value is assigned). Therefore, in script development, only these two IR instruction values need to be satisfied. The assignment of the tdi data value and the IR instruction value is both carried out according to the specific circuit structure and the implemented function.

[0067] # Initialize input parameters: if(tr.Type == JTAG_DP_WR) begin; # The instruction type is JTAG_DP_WR, a write operation to DP; ir_data_tmp = 4'bxxxx; # The value of ir_data_tmp is 4'bxxxx, and here ir_data_tmp is the initial value; wr_tdi_data_tmp = {tr.data_in, tr.addr_in, 1'b0}; # The value of wr_tdi_data_tmp is a simple combination of data_in, addr_in, and 1'b0. This step assigns a value to wr_tdi_data_tmp, and wr_tdi_data_tmp is the initial value of the written tdi_data; End. # The assignment of the write operation to DP ends.

[0068] else if(tr.Type == JTAG_DP_RD) begin # The instruction type is a read instruction for DP; ir_data_tmp = 4'bxxxx; # The initial value of ir_data is 4'bxxxx; wr_tdi_data_tmp = {32'b0, tr.addr in, 1'b1}; # The value of wr_tdi_data_tmp is a simple combination of 32'b0, tr.addr in, and 1'b1; End. # The assignment of the read operation to DP ends.

[0069] else if(tr.Type == JTAG_AP_WR) begin; # The instruction is a write instruction for AP; ir_data_tmp = 4'bxxxx; wr_tdi_data_tmp = {tr.data_in, tr.addr_in, l'b0}; End。

[0070] else if(tr.Type == JTAG_AP_RD) begin; # The instruction is a read instruction for the AP; ir_data_tmp = 4'bxxxx; wr_tdi_data_tmp = {32'b, tr.addr in, 1'b1}; End。

[0071] # Example of the jtag_process code implementation (IR operation, TAP controller to Exit1-IR state): # First, assign values to ir_data_tmp and wr_tdi_data_tmp according to the instruction template type; if(tr.Type == JTAG_DP_WR) begin; # If the instruction template is JTAG_DP_WR; ir_data_tmp = 4'b1010; # Assign the IR register value 4'b1010 copied in the instruction template to ir_data_tmp; wr_tdi_data_tmp = {tr.data_in, tr.addr_in, 1'b0}; End。

[0072] else if(tr.Type == JTAG_DP_RD) begin; ir_data_tmp = 4'b1010; wr_tdi_data_tmp = {32'b0, tr.addr_in, 1'b1}, End。

[0073] else if(tr.Type == JTAG_AP_WR) begin; ir_data_tmp = 4'b1011; wr_tdi_data_tmp = {tr.data_in, tr.addr_in, 1'b0}; End。

[0074] else if(tr.Type == JTAG_AP_RD) begin; ir_data_tmp == 4'b1011; wr_tdi_data tmp = {32'b, tr.addr_in, 1'b1} End

[0075] virtual task jtag_process(ref jtag_items tr); / / Re-execute the jtag_process task / / Obtain the IR = DPACC / APACC instruction through ir_data ir_data = ir_data_tmp; / / Assign the initial value of ir_data_tmp to ir_data, and then obtain the instruction through the value of ir_data wr_tdi_data = wr_tdi_data_tmp; / / The written tdi_data is wr_tdi_data_tmp (initial value) rd_tdo_data = 0; / / The initial read tdo_data is 0

[0076] / / ******** Enter the IR-shift process ********; / / Enter the IR-shift operation state / / From the run-test / idel -> select–IR-Scan process, corresponding to the TMS changing from the 0 value state to 1'b1 for two consecutive beats; / / The state machine enters the IR-Scan state from the run-test / idel state, and the corresponding TMS signal is set to high level within two consecutive clock cycles for (int i = 0; i < 2; i++) begin; / / Execute the logical loop operation @(posedge jtag_intf.clk); / / Wait for the rising edge of the clk signal Jtag_intf.tms = 1'b1; / / Drive the TMS signal to high level for two clock cycles End

[0077] / / capture-IR, the next beat of tms is 0, enter the capture-IR state; / / The next beat of tms is 0, and the current operation enters the capture-IR state @(posedge jtag_intf.clk); / / Wait for the rising edge of the clk signal Jtag_intf.tms = 1'b0; / / Drive the TMS signal to low level / / shift-IR, when the falling edge of tms is 0, enter the shift-IR state; # when the falling edge of tms is 0, the current operation enters the shift-IR state; @(posedge jtag_intf.clk); # Wait for the rising edge of the clk signal; Jtag_intf.tms = 1'b0; # Drive the tms signal to low level; / / Assign values to tdi; for(int i = 0; i < 4; i++) begin; # Loop the following operations 4 times; @(posedge jtag_intf.clk); # Wait for the rising edge of the clk signal; / / jtag_intf.tms = 1'b0, keep the tms signal at 0; Jtag_intf.tdi = ir_data[0]; / / Write ir_data to tdi after 4 clock cycles; # Assign the least significant bit of ir_data to the TDI signal; Ir_data = ir_data >> 1; # Shift ir_data one bit to the right, making the next bit the least significant bit for assignment; / / exit1-IR; # The current operation enters the exit1-IR state; if(i == 3) / / At the 4th clock cycle, set tms to 1 and then enter the exit1-IR state; # When the loop variable i is equal to 3, set the tms signal to 1 and exit the shift-IR state; jtag_intf.tms = 1'b1; Drive the TMS signal to high level; End.

[0078] The above code demonstrates how, under the combined drive of the TMS signal and the clk signal, the state machine enters the shift-IR state and completes the assignment operation of tdi_data in the shift-IR state, to output the combinations of the TMS signal, TCK signal, TDI signal, and TDO signal at different times (the CLK signal is output as the clock signal TCK).

[0079] When outputting TDO data, first the instruction template appends the tail identifier to the data expected to be read (expect_rdata) in the functional test instruction and outputs it as TDO data (for example, in the instruction templates "jtag_read_ap" and "jtag_read_dp", "value=data + "3'b100"" means appending the tail identifier "3'b100" to the data data in the functional test instruction). The jtag test driver function simply fills and outputs the TDO data generated by the instruction template (that is, directly fills and outputs the TDO data in the instruction template according to the format of outputting TDO data). The output TDO data is the theoretically correct TDO data, and the test result can be compared with the theoretically correct TDO data after the jtag_process function generates the functional test vector for testing.

[0080] Taking a piece of code as an example for illustration, for example: Functional test instruction: #comment-->test PV_SDR__REG1; #Test PV_SDR__REG1; delay_time: 2000ns; task_name: jtag_ahb_ap_write_data, addr: 32'h200100c4, wr_data: 32'h5a5a5a5a; task_name: jtag_ahb_ap_read_data, addr: 32'h200100c4, expect_rdata: 32'h5a5a5a5a.

[0081] The above functional test instructions include writing data to the ap port on the ahb bus and reading the data. The data expected to be read is 32'h5a5a5a5a. Through the above description, see Figure 6 , jtag_ahb_ap_read_data will call jtag_read_ap, and at this time the instruction template jtag_read_ap will append the identifier "3’b100" to the data expected to be read.

[0082] Step 3: Obtain the chip functional test instructions and pin information (the generated final wgl file must have pin information), and parse out the task content and task input parameters included in the functional test instructions. The task input content refers to the type of task that the functional test instruction needs to execute, and the task input parameters include address parameters and register parameters.

[0083] Step 4: Select the corresponding instruction template based on the task content, call the instruction template, assign values to the instruction register, and obtain the TDI data sequence and TDO data according to the corresponding address parameters and write / read data in the task input parameters; the instruction template is created based on the JTAG protocol, ADI protocol, and AMBA bus protocol, and the instruction template is associated with the JTAG test driver function; call the JTAG test driver function according to the instruction register value, TDI sequence, and TDO data, and output the content of the functional test instruction as a combination of TDI data, TCK signal, TMS signal, and TDO signal at different times.

[0084] The following takes a functional test instruction as an example to illustrate how to parse the task name from the functional test instruction and how to call the corresponding instruction template.

[0085] #comment-->reset fsm running, reset the state machine; delay_time: 100000ns; #comment-->jtag power up, power up the jtag, directly access dp; task_name: jtag_read_dp, addr: 2'b01, banksel: 4'b0, expect_rdata: 32'h0; task_name: jtag_write_dp, addr: 2'b01, banksel: 4'b0, wr_data: 32'h10000000; delay_time: 1000ns; task_name: jtag_read_ap, addr: 32'hfc, expect_rdata: 32'h84770001; #comment-->test PV_SDR__REG1 test PV_SDR__REG1; delay_time: 2000ns; task_name: jtag_ahb_ap_write_data, addr: 32'h200100c4, wr_data: 32'h5a5a5a5a; task_name: jtag_ahb_ap_read_data, addr: 32'h200100c4, expect_rdata: 32'h5a5a5a5a; #comment-->test s4 sram1; Test s4 sram1; delay_time: 2000ns; task_name: jtag_ahb_ap_write_data, addr: 32'h30040000, wr_data: 32'h6a6a6a6a; task_name: jtag_ahb_ap_read_data, addr: 32'h30040000, expect_rdata: 32'h6a6a6a6a; #comment-->test s9 sram1; Test s9 sram1; delay_time: 2000ns; task_name: jtag_ahb_ap_write_data, addr: 32'h30080000, wr_data: 32'h7a7a7a7a; task_name: jtag_ahb_ap_read_data, addr: 32'h30080000, expect_rdata: 32'h7a7a7a7a; #comment-->test s4 i2c; Test s4 i2c; delay_time: 2000ns; task_name: jtag_ahb_ap_write_data, addr: 32'h40000014, wr_data: 32'h8a8a8a8a; task_name: jtag_ahb_ap_read_data, addr: 32'h40000014, expect_rdata: 32'h8a8a8a8a.

[0086] The above functional test instruction set includes multiple functional test instructions (comment). Taking comment-->jtagpower up as an example, this functional test instruction includes two tasks (task_name). Taking task_name: jtag_read_dp as an example, the parameters of task_name: jtag_read_dp include: address parameter addr: 2'b01, instruction mnemonic banksel: 4'b0, and expected read value expect_rdata: 32'h0. This task_name needs to execute the jtag_read_dp instruction, and the corresponding parameters include addr, banksel, and expect_rdata. Therefore, the created jtag_read_dp instruction template (introduced in detail above) can be directly called. Based on the parameters addr (address parameter), banksel (instruction mnemonic), and expect_rdata (expected read value), the tdi_data and tdo_data are calculated using the instruction template. Then, the jtag test driver function is called to generate the required test vectors.

[0087] The above has described in detail a method for generating test vectors of the present invention. Through the instruction template in the present invention, the functional test instructions written by developers can be converted into jtag interface test vectors, which has the characteristics of high efficiency and easy modification.

[0088] Embodiment 2: Embodiment 2 provides a test vector generation system, which at least includes the following modules: A test instruction parsing module that parses the input functional test instructions and outputs the task content and task input parameters included in the functional test instructions; A test vector generation module that selects a corresponding instruction template based on the task content, calls the instruction template, assigns values to the instruction register, and obtains the TDI data sequence and TDO data based on the corresponding address parameter and write / read data in the task input parameters. The instruction template is created based on the jtag protocol, ADI protocol, and data transmission protocol of the chip test circuit, and the instruction template is associated with the jtag test driver function. According to the instruction register value, TDI sequence, and TDO data, the jtag test driver function is called to output the content of the functional test instruction as a combination of TDI data, TCK signal, TMS signal, and TDO signal at different times.

[0089] The test vector generation system in Embodiment 2 is used to execute the steps of the test vector generation method in Embodiment 1.

[0090] Embodiment 3 Example 3 provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the test vector generation method described in Example 1 are implemented.

[0091] The above has introduced in detail a test vector generation method, system and computer-readable storage medium provided by the present invention. Specific examples are used in this article to elaborate on the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of the claims of the present invention.

Claims

1. A test vector generation method, characterized in that, The method includes: Obtain chip function test instructions, and parse the task content and task input parameters included in the function test instructions; Select a corresponding instruction template based on the task content, call the instruction template, assign values to the instruction register, and obtain the TDI data sequence and TDO data according to the corresponding address parameters and write / read data in the task input parameters; the instruction template is created based on the JTAG protocol, ADI protocol, and the data transmission protocol of the chip test circuit, and the instruction template is associated with the JTAG test driver function; Call the JTAG test driver function according to the instruction register value, TDI sequence, and TDO data, and output the function test instruction content as a combination of TDI data, TCK signal, TMS signal, and TDO signal at different times.

2. The method for generating test vectors according to claim 1, wherein Create multiple basic instruction templates according to the basic tasks that need to be executed when the chip to be tested is tested based on the test protocol. Each basic instruction template executes an instruction task, and multiple different basic instruction templates are combined to implement different test functions of the chip.

3. A test vector generation method according to claim 2, characterized in that, The basic instruction template includes at least a write instruction to the DP port, a read instruction to the DP port, a write instruction to the AP port, and a read instruction to the AP port.

4. A test vector generation method according to claim 3, characterized in that, The basic instruction template includes a write instruction to the AP port on the AHB bus, a read instruction to the AP port on the AHB bus; and a write instruction to the DP port on the AHB bus, a read instruction to the DP port on the AHB bus. The write instruction to the AP port on the AHB bus and the read instruction to the AP port on the AHB bus are further converted into read / write instructions to the AP port, and the write instruction to the DP port on the AHB bus and the read instruction to the DP port on the AHB bus are further converted into read / write instructions to the DP port.

5. A method for generating test vectors according to any one of claims 3 or 4, characterized in that, Based on the task content included in the function test instructions, select the corresponding basic instruction template, and convert the function test instructions into read / write instructions to the AP port and DP port on the chip according to the basic instruction template; The converted read and write instructions for the AP port and DP port on the chip are further associated with the jtag test driver function Link .

6. A test vector generation method according to claim 5, characterized in that, Assign values to the instruction register according to the instruction task executed by the basic instruction template; Set intermediate variables according to the JTAG protocol, ADI protocol, and the data transmission protocol of the chip test circuit, and assign the intermediate variables to the TDI data sequence or TDO data; The intermediate variables are related to the address parameters and write / read data required for the created read / write instructions to the AP port and DP port.

7. A test vector generation method according to claim 6, wherein The JTAG test driver function inputs the TMS value, controls the state machine to enter the IR register scan state, Capture-IR state, and Shift-IR state in sequence, and operates the IR register jointly through the input TMS value and TCK clock signal. In the Shift-IR state, the assigned instruction register value is filled bit by bit in the TDI data sequence format starting from the low bit to output the TDI data, and a combination of TDI data, TMS signal, TCK signal, and TDO signal at different times is obtained.

8. A test vector generation method according to claim 6, characterized in that The instruction template outputs the data expected to be read in the functional test instruction plus a tail identifier as TDO data, and the jtag test driver function outputs the TDO data generated by the instruction template after simple filling.

9. A test vector generation method according to claim 6, characterized in that, When the basic instruction template is used to execute the task of accessing the DP port, the instruction register is assigned 0b1010; when the basic instruction template is used to execute the task of accessing the AP port, the instruction register is assigned 0b1011; The jtag test driver function obtains the value of the instruction register assigned by the instruction template, and fills the assigned value of the instruction register bit by bit in the TDI data sequence format starting from the low bit to output TDI data.

10. A method for generating test vectors according to claim 1, characterized in that, The data transmission protocol of the chip test circuit includes the AMBA bus protocol, and the DAP debugger accesses the system resources on the chip based on the AMBA bus protocol.

11. A test vector generation system, characterized in that, Comprising: A test instruction parsing module that parses the input functional test instruction and outputs the task content and task input parameters included in the functional test instruction; A test vector generation module that selects a corresponding instruction template based on the task content, calls the instruction template, assigns a value to the instruction register, and obtains a TDI data sequence and TDO data based on the corresponding address parameter and write / read data in the task input parameters; The instruction template is created based on the jtag protocol, the ADI protocol, and the data transmission protocol of the chip test circuit, and the instruction template is associated with the jtag test driver function; the jtag test driver function is called according to the instruction register value, the TDI sequence, and the TDO data, and the functional test instruction content is output as a combination of TDI data, TCK signal, TMS signal, and TDO signal at different times.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the test vector generation method described in any one of claims 1 to 10.

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