High-efficiency low-power-consumption communication protocol based on Hall device sensor array

Abstract

The invention discloses an efficient low-power-consumption communication protocol based on a Hall device sensor array, which relates to the technical field of electronic sensing and digital communication crossing and comprises a triggering stage, a data reading stage, a data transmission stage and a dynamic power consumption mode. A Hall device sensor array is formed according to flexible wiring of different use scenes, Hall device sensors detect magnetic field intensity and convert the magnetic field intensity into digital signals, and a main control chip coordinates working logic of all modules to obtain detection results of all the Hall device sensors. The system can be intelligently switched among different modes through adjustment of the main control chip, the high-performance requirement during high load can be met, the detection frequency can be reduced during low load to meet the basic requirement of the system, the OUT pin adopts the open-drain output mode, and the detection efficiency is improved. The low level state of the OUT pin triggers the interruption of the main control chip through the wired AND logic, and data errors or system faults caused by level conflicts can be effectively avoided.

Description

Technical Field

[0001] This invention application relates to the cross - technical field of electronic sensing and digital communication, specifically an efficient and low - power communication protocol based on a Hall device sensor array. Background Art

[0002] Traditional sensor communication protocols usually use bus protocols such as I2C, SMBUS, etc. Currently, there are also more simple methods such as the sensor directly outputting analog signals to be collected by the main control chip uniformly. However, the above - mentioned methods all process single - sensor signals, that is, discrete analog signal transmission is adopted. For a multi - point sensor system, problems such as long response time, slow communication speed, and high power consumption will occur. If multiple sensors are triggered simultaneously, signal interference may also be caused. Moreover, the detection speed of existing protocols is also limited by the serial processing architecture, and the scalability is restricted by the centralized architecture. Summary of the Invention

[0003] To solve the problems existing in the existing communication protocols, the present invention provides an efficient and low - power communication protocol based on a Hall device sensor array, specifically: an efficient and low - power communication protocol based on a Hall device sensor array, including a communication protocol with a trigger stage, a data reading stage, a data transmission stage, and a dynamic power - consumption mode. It is characterized in that: the pin functions of the Hall device sensors are defined, specifically as VDD (positive power supply), GND (negative power supply), MODE (mode control pin), LP (low - power control pin), CLK (clock signal pin), OUT (output pin). Among them, the MODE pin undertakes a key output control task in the system. When the level of the MODE pin is at a low level, the Hall device sensor starts the detection function. If no data is detected, the OUT pin is in a high - impedance state. If data is detected, the level of the OUT pin is pulled low to notify the main control chip to perform data acquisition; in addition, the LP pin is used as a means of low - power control to reduce power consumption by reducing the detection frequency of the Hall device sensor; a Hall device sensor array is formed by flexible wiring according to different usage scenarios. The Hall device sensor detects the magnetic field intensity and converts it into a digital signal, and the main control chip coordinates the working logic of each module to obtain the detection results of all Hall device sensors;

[0004] The trigger stage means that when the Hall device sensor is triggered, the OUT pin will pull the level down to ≤0.4V and send an interrupt signal to the main control chip to inform the main control chip that a trigger event has occurred;

[0005] The data reading stage means that the master chip pulls up the level of the MODE pin and sends a square wave signal of X clock cycles through the CLK pin. At this time, the OUT pin will output X-bit data in sequence. Here, X is determined by the valid bits of the sensor data, and the data resolution can be dynamically adjusted to accurately reflect the information collected by the sensor device.

[0006] The data transmission stage means that the master chip pulls up the level of the MODE pin and releases the level of the OUT pin, and the Hall device sensor enters the data transmission mode.

[0007] The dynamic power consumption mode is that the master chip controls the level of the LP pins of different Hall sensors, enabling the Hall device sensor array to flexibly switch between the full-speed mode, normal mode, and low-speed mode, and the entire sampling system is in different power consumption states.

[0008] Preferably, the OUT pin adopts an open-drain output mode, allowing multiple Hall device sensors to be connected in parallel to form an array. When the MODE pin is at a low level, any Hall device sensor is triggered, and the low-level state of the OUT pin triggers an interrupt of the master chip through the "wired AND" logic. This design method can effectively avoid data errors or system failures caused by level conflicts.

[0009] Preferably, in the full-speed mode, the master chip pulls down the level of the LP pins of all Hall device sensors, and the sampling frequency of the Hall device sensors is adjusted to 500Hz - 2000Hz to ensure that the system can quickly respond to all external trigger operations; in the normal mode, the master chip pulls down the level of the LP pins of the Hall device sensors that require a high response speed, adjusts its sampling frequency to 500Hz - 2000Hz, and at the same time, the master chip pulls up the level of the LP pins of the Hall device sensors with low response speed requirements and adjusts its sampling frequency to 50Hz - 200Hz; in the low-speed mode, the master chip controls to pull up the level of the LP pins of all Hall device sensors, and the sampling frequency of the Hall device sensors is adjusted to 50Hz - 200Hz.

[0010] Preferably, the frequency of the clock signal of the CLK pin is 1 - 20MHz.

[0011] Compared with the prior art, the beneficial effects of the present invention are:

[0012] 1. In the present invention, a new type of Hall device sensor is adopted and flexibly wired to form a parallel array of multiple sensors. Compared with the traditional discrete analog signal transmission method, the response speed of the present invention is faster.

[0013] 2. The dynamic power consumption mode of the present invention involves three types, and through the adjustment of the main control chip, the system can intelligently switch between the three modes, which can not only meet the high-performance requirements under high load, but also reduce the detection frequency under low load to meet the basic requirements of the system, while effectively reducing power consumption.

[0014] 3. The OUT pin of the present invention adopts an open-drain output mode, allowing multiple Hall device sensors to be connected in parallel to form an array. When the MODE pin is at a low level, any Hall device sensor is triggered, and the low-level state of the OUT pin triggers an interrupt of the main control chip through "wired AND" logic. This design method can effectively avoid data errors or system failures caused by level conflicts. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0016] Figure 1 It is a circuit diagram of a preferred wiring method of the Hall device sensor in the present invention;

[0017] Figure 2 It is a schematic diagram of the pins of the Hall device sensor according to the present invention;

[0018] Figure 3 It is a waveform diagram demonstrating the reading of 4-bit data;

[0019] Figure 4 It is a process diagram demonstrating the triggering to reset of the Hall device sensor;

[0020] Figure 5 It is a triggering diagram in the low-speed mode. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] In order to make the application purpose, features, and advantages of the present application more obvious and understandable, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the embodiments described below are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0022] Refer to Figures 1 to 5, A high - efficiency and low - power communication protocol based on a Hall device sensor array, including a communication protocol with a trigger stage, a data reading stage, a data transmission stage, and a dynamic power - consumption mode. It is characterized in that: the pin functions of the Hall device sensors are defined, specifically as VDD (positive power supply), GND (negative power supply), MODE (mode control pin), LP (low - power control pin), CLK (clock signal pin), OUT (output pin). Among them, the MODE pin undertakes a key output control task in the system. When the level of the MODE pin is low, the Hall device sensor starts the detection function. If no data is detected, the OUT pin is in a high - impedance state. If data is detected, the level of the OUT pin is pulled low to notify the main control chip to perform data acquisition; in addition, the LP pin is used as a means of low - power control to reduce power consumption by reducing the detection frequency of the Hall device sensor; a Hall device sensor array is formed by flexible wiring according to different usage scenarios. The Hall device sensor detects the magnetic field intensity and converts it into a digital signal, and the main control chip coordinates the working logic of each module to obtain the detection results of all Hall device sensors;

[0023] The trigger stage means that when the Hall device sensor is triggered, the OUT pin will pull the level low to ≤0.4V and send an interrupt signal to the main control chip to inform the main control chip that a trigger event has occurred;

[0024] The data reading stage means that the main control chip raises the level of the MODE pin, referring to Figure 3 , In this embodiment, a square - wave signal with 4 clock cycles is sent through the CLK pin. At this time, the OUT pin will sequentially output 4 - bit data, and the 4 - bit data here is determined by the valid bits of the sensor data;

[0025] The data transmission stage means that the main control chip raises the level of the MODE pin and releases the level of the OUT pin, and the Hall device sensor enters the data transmission mode;

[0026] The dynamic power - consumption mode is that the main control chip controls the level of the LP pin of different Hall sensors to enable the Hall device sensor array to flexibly switch between full - speed mode, normal mode, and low - speed mode, and the entire sampling system is in different power - consumption states.

[0027] Specifically, the OUT pin adopts an open - drain output mode, allowing multiple Hall device sensors to be connected in parallel to form an array. When the MODE pin is at a low level, any Hall device sensor is triggered, and the low - level state of the OUT pin triggers the interrupt of the main control chip through the "wired - AND" logic. This design method can effectively avoid data errors or system failures caused by level conflicts.

[0028] Specifically, referring to Figure 1, this system realizes three - level dynamic power consumption regulation through dual - channel independent control (LP1 / LP2 pins), accurately adapting to different scenario requirements. In the full - speed mode (LP1 = 0 / LP2 = 0), the two groups of sensors synchronously activate the high - speed sampling frequency up to 2000Hz, which is suitable for device initialization or high - precision monitoring; in the normal mode (LP1 = 0 / LP2 = 1), the sensor performance is managed in zones. The LP1 group maintains a high - speed acquisition of 2000Hz, and the LP2 group reduces the frequency to 50Hz, reducing the overall power consumption while taking into account the real - time performance of core parameters and the energy - efficiency balance; in the low - speed mode (LP1 = 1 / LP2 = 1), all sensors switch to 50Hz low - frequency sampling and redundant circuits are turned off, adapting to standby or periodic monitoring scenarios. The system innovatively adopts a hierarchical strategy, supporting millisecond - level mode switching (<5ms) and multi - level state configuration. Combining hardware - level power - supply topology optimization and anti - conflict circuit design, it realizes intelligent dynamic power distribution while ensuring data integrity, providing a flexible and efficient energy - efficiency management solution for sensor networks in complex environments.

[0029] Specifically, the clock signal frequency of the CLK pin is 10MHz.

[0030] As described above, the above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and inventive concept of the present invention, makes equivalent substitutions or changes, and all should be covered by the protection scope of the present invention.

Claims

1. A high-efficiency and low-power communication protocol based on a Hall device sensor array, including a triggering phase, a data reading phase, a data transmission phase and a communication protocol in a dynamic power consumption mode, characterized in that: The pin functions of the Hall device sensor are defined as VDD (positive power supply), GND (negative power supply), MODE (mode control pin), LP (low power control pin), CLK (clock signal pin), and OUT (output pin). The Hall device sensor array is formed according to the flexible wiring of different usage scenarios. The Hall device sensor detects the magnetic field strength and converts it into a digital signal. The main control chip coordinates the working logic of each module to obtain the detection results of all Hall device sensors; The triggering stage means that when the Hall device sensor is triggered, the OUT pin will pull the level down to ≤0.4V, and send an interrupt signal to the main control chip to inform the main control chip that a triggering event has occurred; The data reading stage refers to the main control chip pulling the MODE pin level high and sending a square wave signal of X clock cycles through the CLK pin. At this time, the OUT pin will output X bits of data in sequence; The data transmission stage refers to the main control chip pulling up the MODE pin level, releasing the OUT pin level, and the Hall device sensor entering the data transmission mode; The dynamic power consumption mode is that the main control chip controls the LP pin levels of different Hall sensors, so that the Hall device sensor array can be flexibly switched between full-speed mode, normal mode and low-speed mode, and the entire sampling system is in different power consumption states.

2. According to claim 1, a high-efficiency and low-power communication protocol based on a Hall device sensor array is characterized in that: The OUT pin adopts an open-drain output mode, allowing multiple Hall device sensors to be connected in parallel to form an array; when the MODE pin is at a low level, any Hall device sensor is triggered, and the low level state of the OUT pin triggers an interrupt of the main control chip through the "wired AND" logic.

3. The high-efficiency and low-power communication protocol based on the Hall device sensor array according to claim 1, characterized in that: In the full-speed mode, the main control chip pulls down the LP pin level of all Hall device sensors, and the sampling frequency of the Hall device sensors is adjusted to 500Hz-2000Hz, ensuring that the system can quickly respond to all external trigger operations; in the normal mode, the main control chip pulls down the LP pin level of the Hall device sensors that require a high response speed, and adjusts its sampling frequency to 500Hz-2000Hz. At the same time, the main control chip pulls up the LP pin level of the Hall device sensors that require a low response speed, and adjusts its sampling frequency to 50Hz-200Hz; in the low-speed mode, the main control chip controls the LP pins of all Hall device sensors to be pulled up, and the sampling frequency of the Hall device sensors is adjusted to 50Hz-200Hz.

4. The high-efficiency and low-power communication protocol based on the Hall device sensor array according to claim 1, characterized in that: The clock signal frequency of the CLK pin is 1-20 MHz.

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