Control method and device, electronic equipment, chip and storage medium

Abstract

The invention provides a control method and device, electronic equipment, a chip and a storage medium, and relates to the technical field of computers. The method comprises the following steps: sending first operation data of a target processor in a first scheduling period to a scheduler, then receiving a target control strategy sent by the scheduler, and finally controlling a working point of a target controller based on the target control strategy. Therefore, the timeliness and the reliability of controlling the working point of the processor are improved, and conditions are provided for improving the scheduling and control performance of the system through two-stage combined control of the scheduler and the controller associated with the processor.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a control method, apparatus, electronic device, chip, and storage medium. Background Art

[0002] With the continuous increase in the working frequency and integration degree of integrated circuits, the power consumption and heat generation of integrated circuits also increase rapidly. How to achieve the real-time and accurate control of power consumption and performance when improving the circuit frequency and integration degree is an urgent problem to be solved at present. Summary of the Invention

[0003] The present disclosure aims to at least solve one of the technical problems in the related art to some extent.

[0004] The first aspect embodiment of the present disclosure provides a control method, including:

[0005] Sending first operation data of a target processor in a first scheduling period to a scheduler;

[0006] Receiving a target control policy sent by the scheduler;

[0007] Controlling an operating point of the target processor based on the target control policy.

[0008] The second aspect embodiment of the present disclosure provides a control method, including:

[0009] Receiving first operation data of a target processor sent by a controller;

[0010] Determining a current target control policy of the target processor based on the first operation data;

[0011] Sending the target control policy to the controller.

[0012] The third aspect embodiment of the present disclosure provides a control apparatus, including:

[0013] A first sending module, configured to send first operation data of a target processor in a first scheduling period to a scheduler;

[0014] A first receiving module, configured to receive a target control policy sent by the scheduler;

[0015] An updating module, configured to control an operating point of the target processor based on the target control policy.

[0016] The fourth aspect embodiment of the present disclosure provides a control apparatus, including:

[0017] A second receiving module, configured to receive first operation data of a target processor sent by a controller;

[0018] A determination module, configured to determine a current target control strategy of the target processor based on the first operation data;

[0019] A second sending module, configured to send the target control strategy to the controller.

[0020] An embodiment of the fifth aspect of the present disclosure provides an electronic device, including: a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the control method provided in the embodiments of the first and second aspects of the present disclosure is implemented.

[0021] An embodiment of the sixth aspect of the present disclosure provides a computer-readable storage medium storing computer-executable instructions. When the computer-executable instructions are executed by a processor, the control method provided in the embodiments of the first and second aspects of the present disclosure is implemented.

[0022] An embodiment of the seventh aspect of the present disclosure provides a chip, including a processing circuit and an interface circuit; wherein, the interface circuit is configured to obtain an instruction and send the instruction to the processing circuit, and the processing circuit is configured to execute the instruction to implement the control method provided in the embodiments of the first and second aspects of the present disclosure.

[0023] An embodiment of the eighth aspect of the present disclosure provides a control system, including a processor, a controller, a scheduler, a processor controller, a memory controller, a clock generator, and a power manager;

[0024] wherein, the controller is configured to collect operation data of the processor and send the processed operation data to the scheduler;

[0025] The scheduler is configured to determine a target control strategy of the processor based on the operation data of the processor, and synchronize the target control strategy to the processor controller and the memory controller respectively through the controller;

[0026] The processor controller is configured to control the working states of the clock generator and the power manager based on the target control strategy to implement control of the working point of the processor.

[0027] The control method, device, electronic device, chip, and storage medium provided by the present disclosure have the following beneficial effects:

[0028] In the embodiments of the present disclosure, the controller first sends the first operation data of the target processor in the first scheduling period to the scheduler, then receives the target control policy sent by the scheduler, and finally controls the operating point of the target controller based on the target control policy. Thus, by sending the operation data of the processor in the scheduling period to the scheduler, receiving the target control policy sent by the scheduler, and controlling the operating point of the processor based on the target control policy, the timeliness and reliability of controlling the operating point of the processor are improved, and through the two-level joint control of the scheduler and the controller associated with the processor, conditions are provided for improving the scheduling and control performance of the system.

[0029] Additional aspects and advantages of the present disclosure will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and / or additional aspects and advantages of the present disclosure will become apparent and be readily understood from the following description of the embodiments in conjunction with the accompanying drawings, where:

[0031] Figure 1 is a schematic flowchart of a control method provided by an embodiment of the present disclosure;

[0032] Figure 2 is a schematic flowchart of a control method provided by another embodiment of the present disclosure;

[0033] Figure 3 is an example diagram of the format of the operation data of the processor in the controller in the control method proposed by the embodiment of the present disclosure;

[0034] Figure 4 is a fine-grained control schematic diagram for determining the target operating points of the target processor and / or the associated memory in the control method provided by the embodiment of the present disclosure;

[0035] Figure 5 is a schematic diagram of the process for determining the target operating points corresponding to the target processor and / or the associated memory respectively in the control method provided by the embodiment of the present disclosure;

[0036] Figure 6 is a schematic flowchart of a control method provided by another embodiment of the present disclosure;

[0037] Figure 7 is an arbitration schematic diagram for determining the target operating point of the target processor in the control method proposed by the embodiment of the present disclosure;

[0038] Figure 8 is a schematic flowchart of a control method provided by another embodiment of the present disclosure;

[0039] Figure 9Schematic flowchart of a control method provided by another embodiment of the present disclosure;

[0040] Figure 10 Schematic flowchart of a control method provided by another embodiment of the present disclosure;

[0041] Figure 11 Schematic structural diagram of a control system provided by another embodiment of the present disclosure;

[0042] Figure 12 Schematic structural diagram of a control system proposed by an embodiment of the present disclosure;

[0043] Figure 13 Schematic flowchart of the control system proposed by an embodiment of the present disclosure for implementing the control method proposed by the present disclosure;

[0044] Figure 14 Schematic structural diagram of a control device provided by another embodiment of the present disclosure;

[0045] Figure 15 Schematic structural diagram of a control device provided by another embodiment of the present disclosure;

[0046] Figure 16 Block diagram of an exemplary electronic device suitable for implementing the embodiments of the present disclosure is shown;

[0047] Figure 17 Schematic structural diagram of a chip proposed by an embodiment of the present disclosure. Detailed implementation manners

[0048] Embodiments of the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, and should not be construed as a limitation of the present disclosure.

[0049] The control method, device, electronic device, chip and storage medium of the embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0050] Figure 1 Schematic flowchart of a control method provided by an embodiment of the present disclosure.

[0051] It should be noted that the control method of the embodiments of the present disclosure can be applied to a control device. In some possible embodiments, the device can be configured in an electronic device or a chip so that the electronic device or the chip can execute the control method proposed by the embodiments of the present disclosure.

[0052] As Figure 1 shown, the control method may include the following steps:

[0053] Step 101: Send the first running data of the target processor in the first scheduling period to the scheduler.

[0054] The target processor can be a processor to be optimized for energy efficiency and can be any type of processor. For example, it can be a Central Processing Unit (CPU), or it can also be a Graphics Processing Unit (GPU), or it can also be a Neural network Processing Unit (NPU), etc. The present disclosure does not limit this.

[0055] The scheduling period can be the period during which the scheduler updates the decision-making strategy for adjusting the voltage and frequency of the target processor. The length of the scheduling period can be preset or can also be determined according to the actual situation. The present disclosure does not limit this.

[0056] The first scheduling period is a historical scheduling period before the current moment. Exemplarily, the first scheduling period is the previous scheduling period adjacent to the current moment.

[0057] The first running data can include data representing the power consumption and performance of the target processor, and can include power consumption data and performance data such as the power consumption value, operating voltage, operating frequency, temperature, running time, and number of instructions executed by the target processor in the first scheduling period. The present disclosure does not limit this.

[0058] The scheduler can be a system scheduler preset according to actual needs, and can be a central processor system scheduler, or it can also be a graphics processor system scheduler, or it can also be a neural network processor scheduler, etc. The present disclosure does not limit this.

[0059] In the present disclosure, after the controller associated with the target processor receives the running data query request sent by the scheduler, it can sample the first running data of the target processor in the first scheduling period through the data sampler in the controller and send the first running data to the scheduler, so that the scheduler can determine the working state and performance of the target processor based on the first running data, providing conditions for optimizing the energy efficiency of the processor. The data sampler can be a module in the controller for sampling the running data of the processor. The present disclosure does not limit this.

[0060] It should be noted that the working state of the target processor can include an idle state, a low-power state, a running state, a paused state, etc. The present disclosure does not limit this.

[0061] Optionally, when the controller sends the first operating data of the target processor in the first scheduling period to the scheduler, it may, in response to the operating data query request sent by the scheduler, send the first operating data of the target processor in the first scheduling period to the scheduler. Here, the first scheduling period may be the previous scheduling period adjacent to the moment when the controller responds to the operating data query request sent by the scheduler.

[0062] Optionally, when the controller sends the first operating data of the target processor in the first scheduling period to the scheduler, it may also, in response to the scheduling period reaching the target processor, send the first operating data of the target processor in the first scheduling period to the scheduler. Here, the first scheduling period may be the previous scheduling period adjacent to the current scheduling period reaching the target processor.

[0063] Step 102: Receive the target control policy sent by the scheduler.

[0064] Among them, the target control policy may be a policy for controlling the working state and working performance of the target processor, and its specific content may be determined according to the actual situation. For example, when the target processor is in the low-power state, it can be determined that the current load of the target processor may be relatively low. At this time, the target control policy may be a policy to reduce the working voltage and working frequency of the target processor to reduce the power consumption of the target processor and optimize the energy efficiency of the target processor. When the target processor is in the high-power state, it can be determined that the current load of the target processor may be relatively high. At this time, in order to maintain the efficient operation of the system, the target control policy may be a policy to increase the working voltage and working frequency of the target processor to improve the performance of the target processor, and so on. When the target processor is in the idle state, the target control policy may be a policy to reduce the working voltage and working frequency of the target processor to reduce the power consumption of the target processor, etc. The present disclosure does not limit this.

[0065] In the present disclosure, after the controller sends the first operating data to the scheduler, it may receive the target control policy sent by the scheduler, thereby providing a data basis for balancing the power consumption and performance of the target processor and realizing the energy efficiency optimization of the target processor.

[0066] Step 103: Control the operating point of the target processor based on the target control policy.

[0067] Among them, the operating point may be the working voltage and working frequency of the target processor.

[0068] In the present disclosure, after receiving the target control policy sent by the scheduler, the controller can control the operating point of the target processor based on the target control policy. For example, when the target control policy is to reduce the operating voltage and operating frequency of the target processor, the operating voltage and operating frequency of the target processor can be reduced based on the target control policy, etc., thereby improving the timeliness and reliability of the control of the processor operating point and providing conditions for improving the scheduling and control performance of the target processor.

[0069] Optionally, after receiving the target control policy sent by the scheduler, when controlling the operating point of the target processor based on the target control policy, the controller can also first update the current operating point decision policy and / or data processing policy corresponding to the target processor based on the target control policy, and then control the operating point of the target processor based on the updated operating point decision policy, and / or process the running data of the target processor based on the data processing policy. The present disclosure does not limit this.

[0070] Among them, the operating point decision policy can be to increase the operating voltage and / or operating frequency of the target processor, or to reduce the operating voltage and / or operating frequency of the target processor, or to keep the operating voltage and / or operating frequency of the target processor unchanged. The present disclosure does not limit this.

[0071] Among them, the data processing policy can be a policy used by the controller to process the running data of the target processor. For example, the data processing policy can be to perform a subtraction operation on the running data of the target processor (such as the temperature and power consumption values of the sensor, etc.) to reveal the change trend or abnormality of the data, or to perform an overflow judgment on the running data to ensure that the data is within the valid range, or to filter the running data to remove outliers or noise data, etc., or to sample the running data (such as the number of instruction executions, the number of loads or stalls, etc.). The present disclosure does not limit this.

[0072] In the embodiment of the present disclosure, the controller first sends the first running data of the target processor in the first scheduling period to the scheduler, then receives the target control policy sent by the scheduler, and finally controls the operating point of the target processor based on the target control policy. Thus, by sending the running data of the processor in the scheduling period to the scheduler, receiving the target control policy sent by the scheduler, and controlling the operating point of the processor based on the target control policy, the timeliness and reliability of the control of the processor operating point are improved, and through the two-level joint control of the scheduler and the controller associated with the processor, conditions are provided for improving the scheduling and control performance of the system.

[0073] Figure 2 It is a schematic flowchart of a control method provided by another embodiment of the present disclosure.

[0074] As Figure 2 shown, the control method may include the following steps:

[0075] Step 201: Send the first operation data of the target processor in the first scheduling period to the scheduler.

[0076] Step 202: Receive the target control policy sent by the scheduler.

[0077] Among them, the specific implementation forms of steps 201 to 202 may refer to the detailed descriptions of other embodiments of the present disclosure, and will not be elaborated here.

[0078] Step 203: Determine the second operation data of the target processor in the first control period.

[0079] Among them, the first control period is any control period within the second scheduling period, and the second scheduling period is the next scheduling period adjacent to the first scheduling period.

[0080] Among them, the control period may be the period during which the controller controls the operating point of the target processor. The length of the control period is less than the scheduling period. The length of the control period may be preset or may also be determined according to actual needs. The present disclosure does not limit this.

[0081] In the present disclosure, after receiving the target control policy sent by the scheduler, the controller may control the operating point of the target processor based on the target control policy, so as to balance the power consumption and performance of the target processor, so as to achieve the energy efficiency optimization of the target processor. When controlling the operating point of the target processor based on the target control policy, the second operation data of the target processor in the first control period may be determined first.

[0082] Optionally, when determining the second operation data of the target processor in the first control period, the controller may first collect the power consumption information and event information of the target processor in the first control period, and then process the power consumption information and event information based on the current data processing policy to obtain the second operation data, thereby improving the reliability and accuracy of the second operation data. For example, according to the data processing policy, difference operation, overflow judgment, filtering and other processing may be performed on the power consumption information and event information. The present disclosure does not limit this.

[0083] It should be noted that the power consumption information may include information such as the operating voltage, operating frequency, power consumption value and temperature of the target processor, and the event information may include information such as the number of instruction executions, running time and processor load or pause number of the target processor. The present disclosure does not limit this.

[0084] It should be noted that the current data processing strategy can be updated and determined based on the target control strategy.

[0085] It should be noted that when the controller determines the power consumption information and event information of the target processor in the first control cycle, the power consumption information and event information in the first control cycle can be combined into the form of a data packet according to Figure 3 the example format of the statistical information shown, Figure 3 which is a schematic diagram of the format of the operation data of the processor in the controller in the control method proposed in this embodiment of the present disclosure. Figure 3 In , taking the example of obtaining the operation data of multiple processors in a control cycle for illustration, as Figure 3 shown, when there are multiple processors, the operation data of these multiple processors can be statistically analyzed separately first, and then the operation data of these multiple processors can be combined into a data packet. For example, the operation data corresponding to Processor #1, Processor #2 to Processor #n in the same control cycle can be statistically analyzed separately, including the working voltage, working frequency, power consumption value, temperature, and Events #1 to #n, and then the operation data corresponding to Processor #1, Processor #2 to Processor #n in the same control cycle can be combined into a data packet, and the combined data packet includes the time stamp of the control cycle. Among them, the specific operation data corresponding to Processor #1 to Processor #n can be determined according to actual needs. In addition, Events #1 to #n can include event information such as the number of instruction executions, running time, and load or stall numbers of the processor. Among them, Figure 3 this is only an example, and the present disclosure does not limit this.

[0086] When the controller determines the second operation data of the target processor in the first control cycle in step 203, when the controller collects the power consumption information and event information of the target processor in the first control cycle, the data can be combined in the form of a data packet according to Figure 3 the data packet shown, which may include the time stamp of the first control cycle, as well as the power consumption information and event information of the target processor in the first control cycle. The present disclosure does not limit this.

[0087] Step 204, based on the target control strategy and the second operation data, determine the target operating points corresponding to the target processor and / or the associated memory respectively.

[0088] Among them, the memory may include the cache and DRAM associated with the target processor.

[0089] Among them, DRAM is the abbreviation of Dynamic Random-Access Memory.

[0090] Among them, the target operating point can be the controlled operating voltage and / or operating frequency corresponding to the target processor and / or the associated memory respectively.

[0091] In the present disclosure, after the controller determines the second operating data of the target processor in the first control period, since the second scheduling period may include multiple control periods and the first control period is any control period in the second scheduling period, when the controller determines the target operating points corresponding to the target processor and / or the associated memory respectively based on the target control strategy and the second operating data of the first control period, it not only realizes the macroscopic regulation (coarse-grained regulation) of the operating points of the target processor and / or the associated memory, but also realizes the refined and fine-grained control of the target processor and / or the associated memory, improving the accuracy of operating point control. As Figure 4 shown, Figure 4 is a schematic diagram of the fine-grained control for determining the target operating points of the target processor and / or the associated memory in the control method provided by the embodiment of the present disclosure. Figure 4 In it, the controller periodically determines the target operating points of the target processor and / or the associated memory based on the target control strategy and the operating data of each control period, such as the target operating points corresponding to the target processor and / or the associated memory respectively determined at time points 1 to n, thereby improving the control fineness and real-time performance of the operating points of the target processor and / or the associated memory.

[0092] It should be noted that when determining the target operating points of the target processor and / or the associated memory based on the target control strategy and the second operating data, in order to improve the computing speed and performance of the system, the target control strategy corresponding to the target processor may pay more attention to the second operating data such as the number of instruction executions and running time. In order to optimize the data access efficiency and improve the overall performance of the system, the target control strategy corresponding to the associated memory may pay more attention to the second operating data such as the number of processor loads or stalls. Among them, processor load refers to the process of the processor reading data from the cache and DRAM, and the number of processor stalls refers to the number of idle states of the processor when waiting for data to arrive.

[0093] Next, in combination with Figure 5 , an example will be given to illustrate the process of the controller in the present disclosure determining the target operating points corresponding to the target processor and / or the associated memory respectively based on the target control strategy and the second operating data. Figure 5 is a schematic diagram of the process for determining the target operating points corresponding to the target processor and / or the associated memory respectively in the control method provided by the embodiment of the present disclosure.

[0094] Figure 5In this case, the target control strategy adjusts the current operating point of the target processor and / or the associated memory by means of threshold judgment, taking the determination of the target operating point as an example. Among them, threshold #1 can be the operating point critical value for judging whether to reduce the operating point, and threshold #2 can be the operating point critical value for judging whether to keep the operating point unchanged or increase it. Threshold #1 and threshold #2 can both be preset or can also be determined according to actual needs. The present disclosure does not make any limitation in this regard. Among them, the gear division and setting and the value of n in "the operating point is reduced by n gears" and "the operating point is increased by n gears" can all be determined according to actual needs, and the present disclosure does not make any limitation in this regard.

[0095] As Figure 5 shown, when the value of the second operating data is less than threshold #1, the current operating point can be reduced by n gears; when the value of the second operating data is greater than or equal to threshold #1 and less than threshold #2, the current operating point can be kept unchanged; when the value of the second operating data is greater than or equal to threshold #2, the current operating point can be increased by n gears, so as to determine the target operating points corresponding to the target processor and / or the associated memory respectively. For example, taking the power consumption value of the target processor as the second operating data as an example, since the increase in processor power consumption is often accompanied by an increase in processor load and the performance requirement also increases accordingly. Therefore, when the power consumption value of the target processor is less than threshold #1, it can be determined that the target processor is in low power consumption, and the target processor may currently be in low load with low performance requirements. At this time, in order to optimize the energy efficiency ratio of the target processor (i.e., the ratio of performance to power consumption), the operating point of the target processor can be reduced, so that unnecessary power consumption can be minimized while maintaining sufficient performance. When the power consumption value of the target processor is greater than or equal to threshold #2, it can be determined that the target processor is in high power consumption, and the target processor may currently be in high load. In order to maintain the stability and response speed of the system and keep the system running efficiently, the operating voltage and operating frequency of the target processor can be increased. And when the power consumption value of the target processor is greater than or equal to threshold #1 and less than threshold #2, it can be determined that the current power consumption of the target processor is moderate, and the current power consumption and performance of the target processor are in a balanced state. At this time, the operating voltage and operating frequency of the target processor can be kept unchanged. The present disclosure does not make any limitation in this regard.

[0096] Step 205: Control the target processor and / or the associated memory respectively based on the target operating point.

[0097] In the present disclosure, after the controller determines the target operating points corresponding to the target processor and / or the associated memory respectively, it can control the operating points of the target processor and / or the associated memory respectively based on the target operating points, thereby achieving energy efficiency optimization of the target processor and / or the associated memory, and improving the efficiency and accuracy of controlling the operating points of the target processor and / or the associated memory.

[0098] It should be noted that when the controller controls the target processor based on the target operating point, it can send the target operating point of the target processor to the V / F controller of the target processor, and control the clock generator through the V / F controller to adjust the operating voltage of the target processor, and control the power manager through the V / F controller to adjust the operating voltage of the target processor, where V / F is the abbreviation of Voltage / Frequency.

[0099] It should be noted that when the controller controls the associated memory based on the target operating point, it can send the target operating point of the associated memory to the operating point controller of the memory, such as the cache operating point controller and the DRAM operating point controller, and adjust the operating voltage and operating frequency of the memory through the operating point controller of the memory.

[0100] It should be noted that in the case where the number of target processors is multiple, a distributed controller can be adopted, that is, each processor or processor cluster is associated with a controller, so that the operating points of each processor can be independently adjusted quickly and finely.

[0101] In an embodiment of the present disclosure, the controller first sends the first operation data of the target processor in the first scheduling period to the scheduler, then receives the target control policy sent by the scheduler, then determines the second operation data of the target processor in the first control period, and based on the target control policy and the second operation data, determines the target operating points corresponding to the target processor and / or the associated memory respectively, and finally controls the target processor and / or the associated memory respectively based on the target operating points. Thus, by sending the operation data of the processor in the current scheduling period to the scheduler and receiving the control policy returned by the scheduler, the controller determines the target operating points corresponding to the processor and / or the associated memory respectively based on the control policy and the operation data of the processor in the current control period, and controls the operating points of the processor and / or the associated memory, so as to finely control the processor by the controller based on the target control policy coarsely issued by the scheduler, and improve the dynamic performance of the processor and / or the associated memory.

[0102] Figure 6 It is a schematic flowchart of a control method provided by another embodiment of the present disclosure.

[0103] As Figure 6 shown, the control method may include the following steps:

[0104] Step 601: Send the first operating data of the target processor in the first scheduling period to the scheduler.

[0105] Step 602: Receive the target control policy sent by the scheduler.

[0106] Step 603: Determine multiple second operating data of the target processor in the first control period.

[0107] Among them, the first control period is any control period within the second scheduling period, and the second scheduling period is the next scheduling period adjacent to the first scheduling period.

[0108] It should be noted that the multiple second operating data may include data such as the operating voltage, operating frequency, power consumption value, temperature, and number of instructions executed of the target processor, and the present disclosure does not limit this.

[0109] Among them, for the specific implementation forms of steps 601 to 603, reference may be made to the detailed descriptions of other embodiments of the present disclosure, and details are not described herein again.

[0110] Step 604: Determine a first reference operating point of the target processor based on the target control policy and each second operating data.

[0111] In the present disclosure, after the controller determines the multiple second operating data of the target processor in the first control period, in order to accurately and reliably determine the target operating point of the target processor, and further improve the accuracy of the operating point control of the target processor, a first reference operating point of the target processor may be determined based on the target control policy and each second operating data. For example, when the target control policy is to lower the operating point of the target processor, and the multiple second operating data includes the operating voltage, operating frequency, and power consumption value of the target processor, a first reference operating point lower than the operating voltage may be determined based on the target control policy and the operating voltage of the target processor, a first reference point lower than the operating frequency may be determined based on the operating frequency of the target processor, and a first reference point may be determined based on the power consumption value of the target processor. The present disclosure does not limit this.

[0112] Step 605: Determine the target operating point of the target processor from multiple first reference operating points based on the weight value corresponding to each second operating data.

[0113] Among them, the weight value corresponding to each second operating data may be preset, or may also be determined according to actual needs, and the present disclosure does not limit this.

[0114] In the present disclosure, after the controller determines a first reference operating point of the target processor based on the target control strategy and each piece of second operating data respectively, in order to improve the accuracy of the determined target operating point of the target processor, the controller may determine the target operating point of the target processor from multiple first reference operating points based on the weight value corresponding to each piece of second operating data, thereby providing conditions for improving the accuracy of controlling the target processor.

[0115] Optionally, when the controller determines the target operating point of the target processor from multiple first reference operating points based on the weight value corresponding to each piece of second operating data, since there may be a situation where the first reference points corresponding to different operating data are the same, therefore, the controller may first determine the weight sum of each first reference operating point based on the weight value of the second operating data corresponding to each first reference operating point, and then determine the first reference operating point corresponding to the maximum weight sum as the target operating point.

[0116] Optionally, when the controller determines the target operating point of the target processor from multiple first reference operating points based on the weight value corresponding to each piece of second operating data, the controller determines the weight sum of each first reference operating point based on the weight value of the second operating data corresponding to each first reference operating point. In the case where there are multiple maximum weight sums, the controller may first determine the type of the second operating data associated with each maximum weight sum, and then determine the first reference operating point whose associated second operating data type includes the preset type as the target operating point.

[0117] Among them, the type of the second operating data may be a physical parameter type, an electrical parameter type, a performance parameter type, etc. For example, when the second operating data is the working voltage and temperature, it may be physical type data. When the second operating data is the working frequency, the number of instruction executions, the number of loads or stalls, it may be performance type data. When the second operating data is the power consumption value, it may be energy consumption type data, etc. The present disclosure does not limit this.

[0118] Among them, the preset type may be any type set in advance, or may also be a type determined according to actual needs. For example, the preset type may be a physical parameter type or an electrical type parameter. The present disclosure does not limit this.

[0119] Optionally, when the controller determines the weight sum of each first reference operating point based on the weight value of the second operating data corresponding to each first reference operating point, in the case where there are multiple maximum weight sums, the controller may also determine the first reference operating point corresponding to any one of the maximum weight sums as the target operating point. The present disclosure does not limit this.

[0120] The following combines Figure 7, an arbitration process for determining a target operating point of a target processor from multiple first reference operating points proposed in the present disclosure is illustrated by way of example. Figure 7 It is an arbitration schematic diagram for determining the target operating point of the target processor in the control method proposed in the embodiment of the present disclosure.

[0121] Figure 7 In, the operating point arbitration is illustrated by taking the arbitration based on the weight values of the second operating data corresponding to each first reference point to determine the target operating point of the target processor as an example. The specific arbitration process can refer to the specific implementation manner of step 605 and will not be elaborated here.

[0122] Such as Figure 7 As shown, taking 3 second operating parameters as an example, when determining the target operating point by performing operating point arbitration on the first reference operating points corresponding to the second operating data #1, the second operating data #2, and the second operating data #3 respectively, the arbitration can be performed based on the weight values of the second operating data corresponding to each first reference operating point, so as to determine the target operating point of the target processor from these three first reference operating points, thereby improving the reliability and accuracy of the determined target operating point.

[0123] Step 606, control the target processor based on the target operating point.

[0124] Among them, the specific implementation form of step 606 can refer to the detailed description of other embodiments of the present disclosure and will not be elaborated here.

[0125] In the embodiment of the present disclosure, the controller first sends the first operating data of the target processor in the first scheduling period to the scheduler, then receives the target control policy sent by the scheduler, then determines multiple second operating data of the target processor in the first control period, and determines a first reference operating point of the target processor based on the target control policy and each second operating data. Finally, based on the weight values corresponding to each second operating data, the target operating point of the target processor is determined from multiple first reference operating points, and the target processor is controlled based on the target operating point. Thus, the controller sends the operating data within the processor scheduling period to the scheduler, receives the control policy sent by the scheduler, determines multiple reference operating points based on the control policy and the multiple operating data of the target processor in the current control period, and determines the target operating point of the processor based on the weight values of the operating data corresponding to each reference operating point, so as to control the operating point of the processor based on the target operating point, improving the reliability and accuracy of the control of the processor operating point.

[0126] Figure 8 It is a schematic flowchart of a control method provided by another embodiment of the present disclosure.

[0127] As Figure 8 shown, the control method may include the following steps:

[0128] Step 801: Send the first operation data of the target processor in the first scheduling period to the scheduler.

[0129] Step 802: Receive the target control policy sent by the scheduler.

[0130] Step 803: Determine the second operation data of the target processor in the first control period.

[0131] Wherein, the first control period is any control period within the second scheduling period, and the second scheduling period is the next scheduling period adjacent to the first scheduling period.

[0132] Wherein, the specific implementation forms of steps 801 to 803 may refer to the detailed descriptions of other embodiments of the present disclosure, and will not be elaborated herein.

[0133] Step 804: Based on the current working point decision policy corresponding to the memory and the second operation data, determine a second reference working point of the memory, wherein the memory is associated with multiple processors.

[0134] It should be noted that when the memory is associated with multiple processors, the specific types of the associated multiple processors may be determined according to actual situations. For example, the multiple processors associated with the memory may include at least one of CPU, GPU, and NPU, and the present disclosure does not limit this.

[0135] It should be noted that the current working point decision policy corresponding to the memory may be updated and determined according to the target control policy, and it may be a policy for controlling the working voltage and / or working frequency of the memory.

[0136] In the present disclosure, after the controller determines the second operation data of the target processor in the first control period, in the case where the memory is associated with multiple processors, it may first determine a second reference working point of the memory based on the current working point decision policy corresponding to the memory and the second operation data of the target processor.

[0137] It should be noted that when the controller determines a second reference operating point of the memory based on the current corresponding operating point decision strategy of the memory and the second operating data, it can determine the second reference operating point based on all types of the second operating data, or it can also determine the second reference operating point only based on partial types of the second operating data. For example, since the operating point decision strategy of the memory pays more attention to performance data such as the processor load and the number of stalls, the controller can determine the second reference operating point only based on the second operating data of the performance type and the operating point decision strategy, and the present disclosure does not limit this.

[0138] Step 805: Based on the operating point decision strategy and the current third operating data of other processors, determine other second reference operating points of the memory.

[0139] It should be noted that the type of other processors may be the same as the type of the target processor, or may be different from the type of the target processor, and the present disclosure does not limit this.

[0140] Among them, the third operating data may be the operating data of other processors within the first control period.

[0141] In the present disclosure, after the controller determines a second reference operating point of the memory based on the operating point decision strategy and the second operating data of the target processor, it can determine other second reference operating points of the memory based on the operating point decision strategy and the current third operating data of other processors.

[0142] It should be noted that the specific process by which the controller determines other second reference operating points of the memory based on the operating point decision strategy and the current third operating data of other processors may be similar to the specific process in step 804 by which the controller determines a second reference operating point of the memory based on the operating point decision strategy and the second operating data of the target processor, and will not be elaborated here.

[0143] Step 806: Based on the voting strategy corresponding to the memory, determine the target operating point of the memory from multiple second reference operating points.

[0144] Among them, the voting strategy may be a strategy for determining the target operating point of the memory, and the specific content of the voting strategy may be pre-configured or may also be indicated by the scheduler. For example, in the voting strategy, it may include weight values corresponding to different types of processors, and the weight values of different types of processors are different, etc., and the present disclosure does not limit this.

[0145] In the present disclosure, after the controller determines the second reference operating point corresponding to each processor associated with the memory, in order to improve the accuracy of the determined target operating point of the memory, based on the voting strategy corresponding to the memory, and based on each second reference operating point and the weight value of its corresponding processor, the target operating point of the memory can be determined from multiple second reference operating points.

[0146] Step 807: Control the memory based on the target operating point.

[0147] Among them, the specific implementation form of step 807 can refer to the detailed description of other embodiments of the present disclosure and will not be elaborated here.

[0148] In the embodiment of the present disclosure, the controller first sends the first operation data of the target processor in the first scheduling period to the scheduler, then receives the target control policy sent by the scheduler, and then determines the second operation data of the target processor in the first control period. Based on the current operating point decision strategy corresponding to the memory and the second operation data, a second reference operating point of the memory is determined. Based on the operating point decision strategy and the current third operation data of other processors, other second reference operating points of the memory are determined. Finally, based on the voting strategy corresponding to the memory, the target operating point of the memory is determined from multiple second reference operating points, and the memory is controlled based on the target operating point. Thus, after the controller sends the operation data in the processor scheduling period to the scheduler, it receives the control policy returned by the scheduler, and based on the control policy, updates the operating point decision strategy corresponding to the memory. Based on the current operating point decision strategy of the memory and the current operation data of each processor associated with the memory, multiple reference operating points are determined, and the target operating line of the memory is determined from multiple reference operating points. Thus, based on the target operating point, the operating point of the memory is controlled, realizing the energy efficiency optimization of the memory and improving the accuracy and reliability of the memory operating point control.

[0149] Figure 9 It is a schematic flowchart of a control method provided by another embodiment of the present disclosure.

[0150] As Figure 9 shown, the control method may include the following steps:

[0151] Step 901: Receive the first operation data of the target processor sent by the controller.

[0152] In the present disclosure, after the scheduler sends a running data query request to the controller associated with the target processor, it can receive the first operation data of the target processor sent by the controller, thereby providing a data basis for determining the control policy of the target processor.

[0153] Optionally, when the scheduler receives the first operation data of the target processor sent by the controller, it may, in response to the scheduling period reaching the target processor, send a request for querying operation data to the controller associated with the target processor and receive the first operation data of the target processor sent by the controller.

[0154] It should be noted that for different processors, the scheduling periods of the processors may be the same or may also be different, and the scheduling moments of the processors may be the same or may also be different. That is to say, when the scheduling periods of multiple processors are the same, the corresponding scheduling moments of the processors may also be different. The present disclosure does not make any limitations in this regard.

[0155] Optionally, when the scheduler receives the first operation data of the target processor sent by the controller, it may also, in response to the scheduling period reaching the target processor, receive the first operation data of the target processor sent by the controller.

[0156] Step 902: Determine the current target control strategy of the target processor based on the first operation data.

[0157] In the present disclosure, after the scheduler receives the first operation data sent by the controller and determines the current target control strategy of the target processor based on the first operation data, it may use a pre-trained and generated model to process the first operation data and then obtain the current target control strategy of the target processor, or may also determine the target control strategy based on other pre-configured rules and the first operation data, etc. The present disclosure does not make any limitations in this regard.

[0158] Step 903: Send the target control strategy to the controller.

[0159] In the present disclosure, after the scheduler determines the current target control strategy of the target processor, it may send the target control strategy to the controller so that the controller can control the operating point of the target processor based on the target control strategy.

[0160] In the embodiment of the present disclosure, the scheduler first receives the first operation data of the target processor sent by the controller, then determines the current target control strategy of the target processor based on the first operation data, and finally sends the target control strategy to the controller. Thus, by determining the current control strategy of the processor based on the operation data of the processor within the scheduling period and sending the control strategy to the controller, the scheduler improves the timeliness and reliability of controlling the operating point of the processor, providing conditions for improving the scheduling and control performance of the system.

[0161] Figure 10 It is a schematic flowchart of a control method provided by another embodiment of the present disclosure.

[0162] As Figure 10As shown, the control method may include the following steps:

[0163] Step 1001: Receive the first operation data of the target processor sent by the controller.

[0164] Among them, for the specific implementation form of step 1001, reference may be made to the detailed description of other embodiments of the present disclosure, which will not be elaborated here.

[0165] Step 1002: Determine the current reference control policy of the target processor based on the first operation data.

[0166] In the present disclosure, after the scheduler receives the first operation data sent by the controller, in order to improve the accuracy of the determined target control policy of the target processor, it may first determine the current reference control policy of the target processor based on the first operation data.

[0167] Step 1003: Modify the reference control policy based on at least one of the following to determine the target control policy: the historical operation data of the target processor, the historical control policy of the target processor, the operation data of other processors, and the control policies of other processors.

[0168] In the present disclosure, after the scheduler determines the current reference control policy of the target processor, it may modify the reference control policy of the target processor based on the historical operation data and historical control policy of the target processor. In addition, since multiple processors may share a cache or DRAM, and there may be heat transfer between multiple processors, which affects the temperature rise of the target processor and further affects the working performance of the target processor, therefore, the operation data and control policies of other processors may also be referred to for modifying the reference control policy of the target processor, so as to determine the target control policy of the target processor and improve the accuracy of the determined target control policy.

[0169] Step 1004: Send the target control policy to the controller.

[0170] Among them, for the specific implementation form of step 1004, reference may be made to the detailed description of other embodiments of the present disclosure, which will not be elaborated here.

[0171] In an embodiment of the present disclosure, the scheduler first receives the first operation data of the target processor sent by the controller, determines the current reference control policy of the target processor based on the first operation data, and then modifies the reference control policy based on at least one of the following to determine the target control policy: the historical operation data of the target processor, the historical control policy of the target processor, the operation data of other processors, and the control policies of other processors. Finally, the scheduler sends the target control policy to the controller. Thus, by determining the current reference control policy of the target processor based on the operation data of the target processor within the scheduling period, and modifying the reference control policy based on at least one of the historical control policy and historical operation data of the target processor, and the control policies and operation data of other processors, the scheduler determines the target control policy of the target processor and sends it to the controller, thereby improving the accuracy of the control method.

[0172] Figure 11 FIG. 4 is a schematic structural diagram of a control system provided by another embodiment of the present disclosure.

[0173] As Figure 11 shown, the control system 1100 includes: a processor 1101, a controller 1102, a scheduler 1103, a processor controller 1104, a memory controller 1105, a clock generator 1106, and a power manager 1107;

[0174] Among them, the controller 1102 is configured to collect the operation data of the processor 1101, and send the processed operation data to the scheduler 1103;

[0175] The scheduler 1103 is configured to determine the target control policy of the processor 1104 based on the operation data of the processor 1104, and synchronize the target control policy to the processor controller 1104 and the memory controller 1105 respectively through the controller 1102;

[0176] The processor controller 1104 is configured to control the working states of the clock generator 1106 and the power manager 1107 based on the target control policy to implement control of the working point of the processor.

[0177] It should be noted that the memory controller 1105 can be used to control the working point of the memory associated with the processor 1101 based on the target control policy.

[0178] When the control system 1100 proposed in the embodiments of the present disclosure implements the control method proposed in the present disclosure, it can first aggregate the operation data of the processor through the controller, and then, through the scheduler, determine the target control strategy based on the operation data of the processor, and automatically and quickly judge the requirements for the frequency and voltage of the processor, cache, and DRAM. At the same time, based on the target control strategy, the target operating points of the processor, cache, and DRAM are determined, so as to achieve rapid follow-up of the frequency and voltage to the load change. Thus, through a combination of software and hardware (the scheduler is software and the controller is hardware), the efficiency and real-time performance of controlling the operating points of the processor, cache, and DRAM are improved, and the system energy efficiency optimization effect is enhanced.

[0179] The following Figure 12 is combined with Figure 12 to illustrate by way of example the control system to which the control method proposed in the present disclosure is applied.

[0180] Figure 12 In

[0181] Among them, Figure 12 the memory associated with the processor, namely the cache and DRAM, is taken as an example for illustration. Therefore, the memory controller, the cache operating point controller 1207, and the DRAM operating point controller 1208 are taken as examples for illustration.

[0182] In the present disclosure, when implementing the control method proposed in the present disclosure based on the control system 1200, the specific process is as Figure 13 shown. Figure 13 It is a schematic flowchart of the control system proposed in the embodiments of the present disclosure for implementing the control method proposed in the present disclosure.

[0183] As Figure 13 shown, implementing the control method proposed in the present disclosure based on the control system 1200 may include the following steps:

[0184] Step 1301, the data sampler 12021 in the controller 1202 obtains the operation data of the processor 1201 in the current scheduling period, and after aggregating the data, transmits it to the data processor 12022.

[0185] Among them, the operating data of the processor may include the power consumption data and performance data of the processor.

[0186] Step 1302: The data processor 12022 processes the operating data transmitted by the data sampler 12021 according to the data processing policy configured by the scheduler 1203 for the scheduler 1203 to query, and reports the processed data to the operating point decision maker 12023.

[0187] It should be noted that the processing of the operating data by the data processor 12022 may include operations such as taking the difference, overflow judgment, filtering, etc. on the motion data, and the present disclosure does not limit this.

[0188] It should be noted that the data processor 12022 may combine the power consumption data and performance data of the processor into the form of a data packet.

[0189] Step 1303: The scheduler 1203 determines the working state and performance level of the current system according to the operating data of the processor summarized by the data processor 12022, and sends the target control policy to the operating point decision maker 12023.

[0190] It should be noted that the current system may be a CPU system, or a GPU system, or an NPU system, etc., and the present disclosure does not limit this.

[0191] Step 1304: The operating point decision maker 12023 combines the target control policy sent by the scheduler 1203 and the operating data of the processor in the current control cycle to determine the target operating points of the processor, cache, and DRAM, and sends the target operating points to the V / F controller 1206, cache operating point controller 1207, and DRAM operating point controller 1208 respectively.

[0192] It should be noted that when the operating point decision maker 12023 determines the target operating points of the cache and DRAM, in the case where multiple processors are associated with the cache and DRAM, it may first obtain the operating data of each processor respectively associated with the cache and DRAM in the current control cycle, and then based on the target control policy and the operating data of each processor, determine multiple reference operating points corresponding to the cache and DRAM respectively. Then, based on the voting policies corresponding to the cache and DRAM respectively, from the multiple reference operating points corresponding respectively, determine the target operating point corresponding to the cache and the target operating point corresponding to the DRAM.

[0193] Step 1305, after the V / F controller 1206 receives the target operating point sent by the operating point decision maker 12023, it controls the clock generator 1204 to adjust the operating frequency of the processor 1202 to the frequency in the target operating point, and controls the power manager 1205 to adjust the operating voltage of the processor 1202 to the voltage in the target operating point.

[0194] Step 1306, the cache operating point controller 1207 adjusts the operating frequency and operating voltage of the cache based on the target operating point sent by the operating point decision maker 12023, and the DRAM operating point controller 1208 adjusts the operating frequency and operating voltage of the DRAM based on the target operating point sent by the operating point decision maker 12023.

[0195] To implement the above embodiments, the present disclosure also proposes a control device.

[0196] Figure 14 It is a schematic structural diagram of the control device provided by another embodiment of the present disclosure.

[0197] As Figure 14 shown, the control device 1400 may include: a first sending module 1401, a first receiving module 1402, and an updating module 1403.

[0198] The first sending module 1401 is configured to send the first operation data of the target processor in the first scheduling period to the scheduler;

[0199] The first receiving module 1402 is configured to receive the target control policy sent by the scheduler;

[0200] The updating module 1403 is configured to control the operating point of the target processor based on the target control policy.

[0201] Optionally, the above first sending module 1402 is specifically configured to perform any one of the following:

[0202] In response to a query request for operation data sent by the scheduler, send the first operation data of the target processor in the first scheduling period to the scheduler;

[0203] In response to the arrival of the scheduling period of the target processor, send the first operation data of the target processor in the first scheduling period to the scheduler.

[0204] Optionally, the above updating module 1403 is specifically configured to:

[0205] Determine the second operation data of the target processor in the first control period, where the first control period is any control period within the second scheduling period, and the second scheduling period is the next scheduling period adjacent to the first scheduling period;

[0206] Based on the target control strategy and the second operating data, determine the target operating points corresponding to the target processor and / or the associated memory respectively;

[0207] Control the target processor and / or the associated memory respectively based on the target operating points.

[0208] Optionally, the above update module 1403 is further configured to:

[0209] Collect the power consumption information and event information of the target processor within the first control cycle;

[0210] Process the power consumption information and event information based on the current data processing strategy to obtain the second operating data.

[0211] Optionally, the above update module 1403 is further configured to:

[0212] Determine a first reference operating point of the target processor based on each second operating data;

[0213] Determine the target operating point of the target processor from multiple first reference operating points based on the weight values corresponding to each second operating data.

[0214] Optionally, the above update module 1403 is further configured to:

[0215] Determine the sum of weights of each first reference operating point based on the weight values of the second operating data corresponding to each first reference operating point;

[0216] Determine the first reference operating point corresponding to the maximum sum of weights as the target operating point.

[0217] Optionally, the above update module 1403 is further configured to:

[0218] When there are multiple maximum sums of weights, determine the types of the second operating data associated with each maximum sum of weights;

[0219] Determine the first reference operating point whose associated second operating data type includes the preset type as the target operating point.

[0220] Optionally, the above update module 1403 is further configured to:

[0221] Determine a second reference operating point of the memory based on the current operating point decision strategy of the memory and the second operating data;

[0222] Determine other second reference operating points of the memory based on the operating point decision strategy and the current third operating data of other processors;

[0223] Based on the voting strategy corresponding to the memory, determine the target operating point of the memory from multiple second reference operating points.

[0224] For the functions and specific implementation principles of the above-mentioned modules in the embodiments of the present disclosure, reference may be made to the above-mentioned method embodiments, and details are not described herein again.

[0225] In the control device of the embodiments of the present disclosure, the controller first sends the first operation data of the target processor in the first scheduling period to the scheduler, then receives the target control policy sent by the scheduler, and finally controls the operating point of the target processor based on the target control policy. Thus, by sending the operation data of the processor in the scheduling period to the scheduling period, receiving the target control policy sent by the scheduler, and controlling the operating point of the target processor based on the target control policy, the timeliness and reliability of the control of the processor operating point are improved, and through the two-level joint control of the scheduler and the controller associated with the processor, conditions are provided for improving the scheduling and control performance of the system.

[0226] To implement the above embodiments, the present disclosure also proposes a control device.

[0227] Figure 15 It is a schematic structural diagram of the control device provided by another embodiment of the present disclosure.

[0228] As Figure 15 shown, the control device 1500 may include: a second receiving module 1501, a determining module 1502, and a second sending module 1503.

[0229] The second receiving module 1501 is configured to receive the first operation data of the target processor sent by the controller;

[0230] The determining module 1502 is configured to determine the current target control policy of the target processor based on the first operation data;

[0231] The second sending module 1503 is configured to send the target control policy to the controller.

[0232] Optionally, the above-mentioned second receiving module 1501 is specifically configured to perform any one of the following:

[0233] In response to the arrival of the scheduling period of the target processor, send a running data query request to the controller associated with the target processor, and receive the first operation data of the target processor sent by the controller;

[0234] In response to the arrival of the scheduling period of the target processor, receive the first operation data of the target processor sent by the controller.

[0235] Optionally, the above-mentioned determining module 1502 is specifically configured to:

[0236] Based on the first running data, determine the current reference control strategy of the target processor;

[0237] Based on at least one of the following, modify the reference control strategy to determine the target control strategy: the historical running data of the target processor, the historical control strategy of the target processor, the running data of other processors, and the control strategies of other processors.

[0238] For the functions and specific implementation principles of the above-mentioned modules in the embodiments of the present disclosure, reference may be made to the above-mentioned method embodiments, and details are not described herein again.

[0239] In the control device according to the embodiments of the present disclosure, the scheduler first receives the first running data of the target processor sent by the controller, then determines the current target control strategy of the target processor based on the first running data, and finally sends the target control strategy to the controller. Thus, by determining the current control strategy of the processor based on the running data of the processor within the scheduling period and sending the control strategy to the controller, the scheduler realizes the timely update of the target control strategy of the processor, providing conditions for improving the scheduling and control performance of the system.

[0240] Figure 16 The block diagram of an exemplary electronic device suitable for implementing the embodiments of the present disclosure is shown. Figure 16 The illustrated electronic device 1600 is only an example and should not impose any limitation on the functions and scope of use of the embodiments of the present disclosure.

[0241] As Figure 16 shown, the electronic device 1600 is presented in the form of a general-purpose computing device. The components of the electronic device 1600 may include, but are not limited to: one or more processors or processing units 1616, a system memory 1628, and a bus 1618 connecting different system components (including the system memory 1628 and the processing unit 1616).

[0242] The bus 1618 represents one or more of several types of bus architectures, including a memory bus or memory controller, a peripheral bus, an Accelerated Graphics Port, a processor, or a local bus using any of the various bus architectures. By way of example, these architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnection (PCI) bus.

[0243] The electronic device 1600 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the electronic device 1600, including volatile and nonvolatile media, removable and non-removable media.

[0244] The memory 1628 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) 1630 and / or cache 1632. The electronic device 1600 may further include other removable / non-removable, volatile / nonvolatile computer system storage media. By way of example only, the storage system 1634 can be used for reading and writing on non-removable, nonvolatile magnetic media ( Figure 16 not shown, typically referred to as a "hard disk drive"). Although Figure 16 not shown in the figure, a disk drive for reading and writing on a removable nonvolatile disk (such as a "floppy disk"), and an optical disk drive for reading and writing on a removable nonvolatile optical disk (such as Compact Disc Read Only Memory (CD-ROM), Digital Video Disc Read Only Memory (DVD-ROM), or other optical media) can be provided. In these cases, each drive can be connected to the bus 1618 through one or more data media interfaces. The memory 1628 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the various embodiments of the present disclosure.

[0245] A program / utilities 1640 having a set (at least one) of program modules 1642 can be stored, for example, in a memory 1628. Such program modules 1642 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. The program modules 1642 generally execute the functions and / or methods in the embodiments described in the present disclosure.

[0246] The electronic device 1600 can also communicate with one or more external devices 1614 (such as a keyboard, a pointing device, a display 1624, etc.), and can also communicate with one or more devices that enable a user to interact with the electronic device 1600, and / or communicate with any device that enables the electronic device 1600 to communicate with one or more other computing devices (such as a network card, a modem, etc.). Such communication can be carried out through an input / output (I / O) interface 1622. Moreover, the electronic device 1600 can also communicate with one or more networks (such as a Local Area Network (LAN), a Wide Area Network (WAN), and / or a public network, such as the Internet) through a network adapter 1620. As shown in the figure, the network adapter 1620 communicates with other modules of the electronic device 1600 through a bus 1618. It should be understood that although not shown in the figure, other hardware and / or software modules can be used in combination with the electronic device 1600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0247] The processing unit 1616 executes various functional applications and data processing by running programs stored in the system memory 1628, such as implementing the methods mentioned in the foregoing embodiments.

[0248] To implement the above embodiments, the present disclosure also proposes a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the control method proposed in the above embodiments of the present disclosure.

[0249] Figure 17 It is a schematic structural diagram of a chip proposed in an embodiment of the present disclosure. Reference can be made to Figure 17 the schematic structural diagram of the chip 1700 shown, but not limited thereto.

[0250] The chip 1700 includes a processing circuit 1701, and the processing circuit 1701 is configured to execute any of the above methods.

[0251] In some embodiments, chip 1700 further includes one or more interface circuits 1702. Optionally, interface circuit 1702 is connected to memory 1703. Interface circuit 1702 can be used to receive signals from memory 1703 or other devices, and interface circuit 1702 can be used to send signals to memory 1703 or other devices. For example, interface circuit 1702 can read instructions stored in memory 1703 and send the instructions to processing circuit 1701.

[0252] In some embodiments, interface circuit 1702 performs at least one of the communication steps such as sending and / or receiving in the above method, and processing circuit 1701 performs other steps.

[0253] In some embodiments, terms such as interface circuit, interface, transceiver pin, transceiver, etc. can be used interchangeably.

[0254] In some embodiments, chip 1700 further includes one or more memories 1703 for storing instructions. Optionally, all or part of memory 1703 can be outside chip 1700.

[0255] In the description of this specification, the descriptions with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0256] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0257] Any process or method description represented in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a customized logical function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations, where functions may be executed in a manner that is not shown or discussed, including in a substantially simultaneous manner according to the functions involved or in a reverse order, which should be understood by those skilled in the art to which the embodiments of the present disclosure pertain.

[0258] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing a logical function, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in conjunction with these instruction execution systems, apparatuses, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection portion having one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or otherwise processing as appropriate, and then stored in a computer memory.

[0259] It should be understood that various parts of the present disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0260] Those of ordinary skill in the art can understand that all or part of the steps carried out in the method of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0261] In addition, in each of the various embodiments of the present disclosure, each functional unit may be integrated into a processing module, or each unit may exist physically alone, or two or more units may be integrated into one module. The above integrated module may be implemented in the form of hardware or in the form of a software functional module. When the above integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0262] The storage medium mentioned above may be a read-only memory, a magnetic disk, an optical disk, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A control method, characterized in that: include: Sending first operation data of the target processor in a first scheduling cycle to the scheduler; Receiving the target control strategy sent by the scheduler; Based on the target control strategy, the operating point of the target processor is controlled.

2. The method according to claim 1, characterized in that The sending the first operation data of the target processor in the first scheduling period to the scheduler includes any one of the following: In response to an operation data query request sent by the scheduler, sending first operation data of the target processor in a first scheduling period to the scheduler; In response to reaching a scheduling cycle of a target processor, first operation data of the target processor in a first scheduling cycle is sent to a scheduler.

3. The method according to claim 1, characterized in that The controlling the operating point of the target processor based on the target control strategy further includes: Determine second operation data of the target processor in a first control cycle, wherein the first control cycle is any control cycle in a second scheduling cycle, and the second scheduling cycle is a next scheduling cycle adjacent to the first scheduling cycle; Determining target operating points corresponding to the target processor and / or associated memory, respectively, based on the target control strategy and the second operating data; Based on the target operating point, the target processor and / or the associated memory are controlled respectively.

4. The method according to claim 3, characterized in that The determining the second operation data of the target processor in the first control cycle includes: Collecting power consumption information and event information of the target processor in the first control cycle; Based on the current data processing strategy, the power consumption information and the event information are processed to obtain the second operation data.

5. The method according to claim 3, characterized in that The second operating data is a plurality of data, and the method for determining the target operating point of the target processor includes: determining a first reference operating point of the target processor based on each of the second operating data; Based on the weight value corresponding to each of the second operating data, a target operating point of the target processor is determined from a plurality of the first reference operating points.

6. The method according to claim 5, characterized in that The step of determining a target operating point of the target processor from a plurality of first reference operating points based on a weight value corresponding to each of the second operating data includes: Determine a weight sum of each of the first reference working points based on a weight value of the second operating data corresponding to each of the first reference working points; A first reference working point corresponding to the maximum weight is determined as a target working point.

7. The method according to claim 6, characterized in that After determining the weight sum of each of the first reference working points, the method further includes: In the case where there are multiple maximum weight sums, determining the type of second operating data associated with each maximum weight sum; A first reference operating point of a preset type included in the type of the associated second operating data is determined as a target operating point.

8. The method according to claim 3, characterized in that The memory is associated with a plurality of processors, and a method for determining a target operating point of the memory includes: Determining a second reference operating point of the memory based on the operating point decision strategy currently corresponding to the memory and the second operating data; Determining other second reference operating points of the memory based on the operating point decision strategy and current third operating data of other processors; Based on the voting strategy corresponding to the memory, a target operating point of the memory is determined from a plurality of the second reference operating points.

9. A control method, characterized in that: include: receiving first operation data of the target processor sent by the controller; Determining a current target control strategy of the target processor based on the first operating data; The target control strategy is sent to the controller.

10. The method according to claim 9, characterized in that The receiving controller sends the first operation data of the target processor, including any one of the following: In response to reaching a scheduling cycle of a target processor, sending an operation data query request to a controller associated with the target processor, and receiving first operation data of the target processor sent by the controller; In response to reaching a scheduling cycle of the target processor, first operation data of the target processor sent by the controller is received.

11. The method according to claim 9, characterized in that The determining, based on the first operating data, a current target control strategy of the target processor includes: Determining a current reference control strategy of the target processor based on the first operating data; The reference control strategy is modified to determine the target control strategy based on at least one of the following: historical operating data of the target processor, historical control strategies of the target processor, operating data of other processors, and control strategies of other processors.

12. A control device, characterized in that: The device comprises: A first sending module, used for sending first operation data of the target processor in a first scheduling period to the scheduler; A first receiving module, used to receive the target control strategy sent by the scheduler; An updating module is used to control the operating point of the target processor based on the target control strategy.

13. A control device, characterized in that: The device comprises: A second receiving module, used for receiving first operation data of the target processor sent by the controller; A determination module, configured to determine a current target control strategy of the target processor based on the first operation data; The second sending module is used to send the target control strategy to the controller.

14. An electronic device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the control method described in any one of claims 1 to 11 is implemented.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the control method according to any one of claims 1 to 11 is implemented.

16. A chip, characterized in that: The chip includes a processing circuit and an interface circuit; wherein the interface circuit is used to obtain instructions and send the instructions to the processing circuit, and the processing circuit is used to execute the instructions to implement the control method as described in any one of claims 1-11.

17. A control system, characterized in that: Includes a processor, a controller, a scheduler, a processor controller, a memory controller, a clock generator, and a power manager; The controller is used to collect the operation data of the processor and send the processed operation data to the scheduler; The scheduler is used to determine a target control strategy of the processor based on the operation data of the processor, and synchronize the target control strategy to the processor controller and the memory controller respectively through the controller; The processor controller is used to control the working states of the clock generator and the power manager based on the target control strategy, so as to control the working point of the processor.

Images