Data writing method and memory storage device

Abstract

The invention provides a data writing method and a memory storage device, which can reduce the capacity demand of a buffer memory and improve the writing efficiency. The data writing method comprises the following steps: receiving a writing instruction from a host system and temporarily storing corresponding writing data to a buffer memory; executing a data write-in operation corresponding to the write-in instruction so as to generate redundant data according to the write-in data in the buffer memory, and writing the write-in data in the buffer memory into a target entity unit of the rewritable nonvolatile memory module; and after the redundant data is generated, erasing the write-in data from the buffer memory.

Description

Technical Field

[0001] The present invention relates to a memory management technology, and more particularly to a data writing method and a memory storage device. Background Art

[0002] In recent years, the growth of smart phones, tablet computers, and personal computers has been very rapid, resulting in a sharp increase in consumers' demand for storage media. Since rewritable non-volatile memory modules (e.g., flash memory) have characteristics such as data non-volatility, power saving, small size, and no mechanical structure, they are very suitable for being built into various portable multimedia devices exemplified above.

[0003] In order to ensure the correctness of the written data, during the data writing operation, the written data is temporarily stored in the buffer memory until the written data is correctly written into the rewritable non-volatile memory module, and then the buffer memory can be released. Therefore, a large-capacity buffer memory is required to timely receive the written data from the host system. Summary of the Invention

[0004] Exemplary embodiments of the present invention provide a data writing method and a memory storage device, which can reduce the capacity requirement of the buffer memory and improve the writing efficiency.

[0005] Exemplary embodiments of the present invention provide a data writing method for a memory storage device. The memory storage device includes a memory control circuit unit and a rewritable non-volatile memory module. The memory control circuit unit includes a buffer memory. The rewritable non-volatile memory module includes a plurality of physical units. The data writing method includes: receiving a write instruction from a host system and temporarily storing the corresponding written data in the buffer memory; performing a data writing operation corresponding to the write instruction to generate redundant data according to the written data in the buffer memory, and writing the written data in the buffer memory into a target physical unit of the rewritable non-volatile memory module; and erasing the written data from the buffer memory after the redundant data is generated, wherein if the execution result of the data writing operation received from the rewritable non-volatile memory module is a successful write, the data writing operation is completed.

[0006] In an exemplary embodiment of the present invention, the step of generating the redundant data according to the write data in the buffer memory further includes: dividing the write data in the buffer memory into a plurality of coding groups, and performing a redundant coding operation on each of the coding groups to generate the corresponding redundant data, wherein the data writing method further includes: if the execution result is a write failure, reading the written data belonging to the same coding group as the data with the write failure from the rewritable non-volatile memory module, and performing a decoding operation on the read written data and its corresponding redundant data to obtain decoded data; and writing the decoded data into the target physical unit.

[0007] In an exemplary embodiment of the present invention, the data writing method further includes: if the write mode is not a single-level cell write mode, dividing the write data in the buffer memory into a plurality of coding groups respectively corresponding to different types of physical programming units.

[0008] In an exemplary embodiment of the present invention, the data writing method further includes: if the write mode is a single-level cell write mode, dividing the write data in the buffer memory into a plurality of coding groups respectively corresponding to a plurality of non-adjacent word lines.

[0009] In an exemplary embodiment of the present invention, the data writing method further includes: during the execution of the data writing operation, if the data writing of the coding group cannot be completed through a single data writing operation, storing the redundant data in a redundant bit area of a specific physical unit corresponding to the coding group.

[0010] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is coupled to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units. The memory control circuit unit includes a buffer memory and an error checking and correcting circuit. The memory control circuit unit receives a write instruction from the host system and temporarily stores its corresponding write data in the buffer memory. The memory control circuit unit performs a data writing operation corresponding to the write instruction to generate redundant data according to the write data in the buffer memory through the error checking and correcting circuit, and writes the write data in the buffer memory into a target physical unit in the rewritable non-volatile memory module. After the redundant data is generated, the memory control circuit unit erases the write data from the buffer memory. If the execution result of the data writing operation received from the rewritable non-volatile memory module is a successful write, the data writing operation is completed.

[0011] In an exemplary embodiment of the present invention, the error checking and correcting circuit divides the write data in the buffer memory into a plurality of coding groups, and performs a redundant coding operation on each of the coding groups to generate the corresponding redundant data. If the execution result is a failure, the memory control circuit unit reads the already written data belonging to the same coding group as the data with a write failure from the rewritable non-volatile memory module, and performs a decoding operation on the read already written data and its corresponding redundant data through the error checking and correcting circuit to obtain decoded data, and the memory control circuit unit writes the decoded data into the target physical unit.

[0012] In an exemplary embodiment of the present invention, if the write mode is not a single-level cell write mode, the error checking and correcting circuit divides the write data in the buffer memory into a plurality of coding groups respectively corresponding to different types of physical programming units.

[0013] In an exemplary embodiment of the present invention, if the write mode is a single-level cell write mode, the error checking and correcting circuit divides the write data in the buffer memory into a plurality of coding groups respectively corresponding to a plurality of non-adjacent word lines.

[0014] In an exemplary embodiment of the present invention, during the execution of the data writing operation, if the data writing of the coding group cannot be completed through a single data writing operation, the memory control circuit unit stores the redundant data in the redundant bit area of a specific physical unit corresponding to the coding group.

[0015] Based on the above, the present invention provides a data writing method and a memory storage device, which can perform a redundant coding operation on the writing data temporarily stored in the buffer memory to generate corresponding redundant data, and after the redundant data is generated, release the buffer memory in advance, so as to reduce the capacity requirement of the buffer memory and improve the writing efficiency without affecting the data correctness.

[0016] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown according to an exemplary embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown according to an exemplary embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of a host system and a memory storage device shown according to an exemplary embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of a memory storage device shown according to an exemplary embodiment of the present invention;

[0021] Figure 5 is a schematic diagram of a memory control circuit unit shown according to an exemplary embodiment of the present invention;

[0022] Figure 6 is a schematic diagram of a management rewritable non-volatile memory module shown according to an exemplary embodiment of the present invention;

[0023] Figure 7 is a flowchart of a data writing method shown according to an exemplary embodiment of the present invention;

[0024] Figure 8 is a flowchart of a data writing method shown according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0026] Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0027] Figure 1 FIG. is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 FIG. is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0028] Please refer to Figure 1 and Figure 2 , the host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be coupled to a system bus 110.

[0029] In an exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 through the data transfer interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 may be coupled to the I / O device 12 through the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0030] In an exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be disposed on a motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 in a wired or wireless manner.

[0031] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a low energy Bluetooth memory storage device (e.g., iBeacon), etc., which are memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be coupled to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0032] In an exemplary embodiment, the host system 11 is a computer system. In an exemplary embodiment, the host system 11 may be any system that can substantially cooperate with the memory storage device to store data. In an exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include Figure 3 the memory storage device 30 and the host system 31.

[0033] Figure 3 is a schematic diagram of the host system and the memory storage device shown in the exemplary embodiment of the present invention.

[0034] Please refer to Figure 3 , the memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 may be various non-volatile memory storage devices such as a secure digital (SD) card 32, a compact flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices such as an embedded multi media card (eMMC) 341 and / or an embedded multi chip package (eMCP) storage device 342, etc., which directly couple the memory module to the substrate of the host system.

[0035] Figure 4It is a schematic diagram of a memory storage device shown in an exemplary embodiment of the present invention.

[0036] Please refer to Figure 4 , the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0037] The connection interface unit 41 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 can also be compliant with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be encapsulated in a chip with the memory control circuit unit 42, or the connection interface unit 41 is disposed outside a chip containing the memory control circuit unit 42.

[0038] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware form and perform operations such as data writing, reading, and erasing in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0039] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module capable of storing 4 bits in one storage cell), other flash memory modules, or other memory modules with the same characteristics.

[0040] Each storage cell in the rewritable non-volatile memory module 43 stores one or more bits by a change in voltage (hereinafter also referred to as the threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each storage cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the storage cell. This operation of changing the threshold voltage of the storage cell is also referred to as "writing data to the storage cell" or "programming the storage cell". With the change in the threshold voltage, each storage cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a storage cell belongs to, and thereby obtain one or more bits stored in this storage cell.

[0041] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can form a plurality of physical programming units, and these physical programming units can form a plurality of physical units. Specifically, the memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be at least classified into lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in a MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0042] In an exemplary embodiment, the physical programming unit is the smallest unit for programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units can include a data bit area and a redundancy bit area. The data bit area contains a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In this exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area can also contain 8, 16, or a larger or smaller number of physical sectors, and the size of each physical sector can also be larger or smaller. On the other hand, the physical unit is the smallest unit for erasing. That is, each physical unit contains the smallest number of memory cells that are erased together. For example, the physical unit is a physical block.

[0043] Figure 5 It is a schematic diagram of a memory control circuit unit shown in an exemplary embodiment of the present invention.

[0044] Please refer to Figure 5 , the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0045] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions will be executed to perform operations such as data writing, reading, and erasing. When explaining the operation of the memory management circuit 51 below, it is equivalent to explaining the operation of the memory control circuit unit 42.

[0046] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into this read-only memory. When the memory storage device 10 operates, these control instructions will be executed by the microprocessor unit to perform operations such as data writing, reading, and erasing.

[0047] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of the rewritable non-volatile memory module 43 in the form of code (for example, the system area in the memory module dedicated to storing system data). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit will first execute this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. After that, the microprocessor unit will execute these control instructions to perform operations such as data writing, reading, and erasing.

[0048] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are coupled to the microcontroller. The storage unit management circuit is used to manage the storage units or groups of storage units of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 43 and the data read from the rewritable non-volatile memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence can each include one or more codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 can also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0049] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify the instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present invention is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0050] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written to the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences can include a write instruction sequence for indicating writing data, a read instruction sequence for indicating reading data, an erase instruction sequence for indicating erasing data, and corresponding instruction sequences for indicating various memory operations (such as changing the read voltage level or performing a garbage collection operation, etc.). These instruction sequences are, for example, generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences can include one or more signals, or data on the bus. These signals or data can include instruction codes or codes. For example, in the read instruction sequence, information such as the read identification code and the memory address will be included.

[0051] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correcting circuit 54, a buffer memory 55, and a power management circuit 56.

[0052] The error checking and correcting circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 receives a write instruction from the host system 11, the error checking and correcting circuit 54 will generate a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to this write instruction, and the memory management circuit 51 will write the data corresponding to this write instruction and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. After that, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it will simultaneously read the corresponding error correcting code and / or error detecting code of this data, and the error checking and correcting circuit 54 will perform error checking and correcting operations on the read data according to this error correcting code and / or error detecting code.

[0053] In an exemplary embodiment, under a redundant array of independent disks (RAID) error correction code architecture, data of multiple physical programming units written into the rewritable non-volatile memory module 43 can be encoded to generate parity data (also referred to as RAID parity data) that can protect multiple physical programming units simultaneously. Thereafter, when the memory management circuit 51 reads data from multiple physical programming units in the rewritable non-volatile memory module 43, the corresponding RAID parity data of this data is read simultaneously, and the error checking and correction circuit 54 performs a decoding operation and / or an error checking and correction operation on the read data based on this RAID parity data.

[0054] The buffer memory 55 is coupled to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0055] In an exemplary embodiment, Figure 4 the rewritable non-volatile memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 the memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 the memory management circuit 51 may include a flash memory management circuit.

[0056] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0057] Please refer to Figure 6 , the memory management circuit 51 can logically group the physical units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602. A physical unit refers to a virtual block (VB). A virtual block may include multiple physical programming units. For example, a virtual block may contain one or more physical units.

[0058] The physical units 610(0) to 610(A) in the storage area 601 are used to store user data (such as from Figure 1user data of the host system 11). For example, the physical units 610(0) to 610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A + 1) to 610(B) in the idle area 602 do not store data (such as valid data). For example, if a physical unit does not store valid data, this physical unit can be associated (or added) to the idle area 602. In addition, the physical units in the idle area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 602 to store this new data. In an exemplary embodiment, the idle area 602 is also referred to as a free pool.

[0059] The memory management circuit 51 can configure the logic units 612(0) to 612(C) to map the physical units 610(0) to 610(A) in the storage area 601. In an exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address can include one or more logical block addresses (LBAs) or other logical management units.

[0060] It should be noted that a logic unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logic unit, it means that the data stored in this physical unit currently contains valid data. On the contrary, if a physical unit is not currently mapped by any logic unit, it means that the data stored in this physical unit does not contain any valid data.

[0061] The memory management circuit 51 can record the management data (also referred to as logical-to-physical mapping information) describing the mapping relationship between the logic units and the physical units in at least one logical-to-physical mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can perform data access operations on the memory storage device 10 according to the information in this logical-to-physical mapping table.

[0062] In an exemplary embodiment, when the host system 11 wants to write a piece of data to the memory storage device 10, the memory management circuit 51 can first temporarily store this data in the buffer memory 55, and then the error checking and correction circuit 54 performs an encoding operation (such as a redundant encoding operation) on this data to generate corresponding parity data (such as redundant data). Then, the memory management circuit 51 writes this data and the corresponding parity data into the rewritable non-volatile memory module 43.

[0063] In the conventional approach, the data writing operations to the memory storage device 10 need to be executed sequentially. During the data writing operation, the memory management circuit 51 first temporarily stores the writing data in the buffer memory 55, and only after all of this writing data has been written to the rewritable non-volatile memory module 43 can this writing data be erased from the buffer memory 55 (i.e., the buffer memory 55 is released). That is to say, the memory management circuit 51 needs to wait until the rewritable non-volatile memory module 43 returns a successful write (Pass) before it can release the buffer memory 55 to perform the next data writing operation. Otherwise, when the memory management circuit 51 prematurely releases the buffer memory 55 and the rewritable non-volatile memory module 43 returns a failed write (Fail), since the writing data temporarily stored in the buffer memory 55 has been erased, the memory management circuit 51 cannot re-execute the failed data writing operation. Therefore, in the conventional approach, a large-capacity buffer memory 55 needs to be used to cope with the actual writing behavior.

[0064] In view of this, the present invention provides a data writing method that can prematurely release the buffer memory 55 before receiving the response of the rewritable non-volatile memory module 43 to the data writing operation, thereby prematurely performing the next data writing operation. Accordingly, the capacity requirement of the buffer memory can be reduced and the writing efficiency can be improved. In other words, the data writing method provided by the present invention can release the buffer memory 55 immediately after the parity data (i.e., redundant data) is generated to improve the writing efficiency.

[0065] Figure 7 It is a flowchart of the data writing method shown in an exemplary embodiment of the present invention.

[0066] Please refer to Figure 7 , in step S701, the memory management circuit 51 can receive a write instruction from the host system 11 and temporarily store the corresponding write data in the buffer memory 55.

[0067] In step S702, the memory management circuit 51 can perform a data writing operation corresponding to the write instruction to generate redundant data based on the write data in the buffer memory 55, and write the write data in the buffer memory 55 to the target physical unit of the rewritable non-volatile memory module 43. Specifically, the memory management circuit 51 can perform a data writing operation corresponding to the write instruction to write the write data temporarily stored in the buffer memory 55 to the physical unit (i.e., the target physical unit) in the rewritable non-volatile memory module 43 based on a write mode. At the same time, the error checking and correction circuit 54 can perform a redundant encoding operation on the write data temporarily stored in the buffer memory 55 to generate redundant data.

[0068] In an exemplary embodiment, the redundant encoding operation is, for example, an Exclusive OR (XOR) logical operation. The error checking and correcting circuit 54 can perform an XOR logical operation on the write data temporarily stored in the buffer memory 55 to generate corresponding redundant data.

[0069] In an exemplary embodiment, the error checking and correcting circuit 54 can divide the write data temporarily stored in the buffer memory 55 into multiple encoding groups, and perform a redundant encoding operation on each encoding group to generate corresponding redundant data.

[0070] In an exemplary embodiment, if the write mode is not a Single-Level Cell (SLC) write mode (for example, a Multi-Level Cell (MLC) write mode, a Triple-Level Cell (TLC) write mode, or a Quad-Level Cell (QLC) write mode), the error checking and correcting circuit 54 can divide the write data temporarily stored in the buffer memory 55 into multiple encoding groups corresponding to different types of physical programming units respectively. Accordingly, the error checking and correcting circuit 54 can perform a redundant encoding operation on each encoding group to generate corresponding redundant data.

[0071] For example, when the write mode is an MLC write mode, the types of physical programming units include upper physical programming units and lower physical programming units. The error checking and correcting circuit 54 can divide the write data to be written into the upper physical programming units into an encoding group, and perform a redundant encoding operation on this encoding group to generate redundant data for protecting the upper physical programming units. Similarly, the error checking and correcting circuit 54 can divide the write data to be written into the lower physical programming units into another encoding group, and perform a redundant encoding operation on this other encoding group to generate redundant data for protecting the lower physical programming units.

[0072] For example, when the write mode is a TLC write mode, the types of physical programming units include upper physical programming units, Middle physical programming units, and lower physical programming units. In addition to the redundant data for protecting the upper physical programming units and the redundant data for protecting the lower physical programming units, the error checking and correcting circuit 54 can also divide the write data to be written into the Middle physical programming units into an encoding group, and perform a redundant encoding operation thereon to generate redundant data for protecting the Middle physical programming units.

[0073] For example, if the writing mode is the QLC writing mode, the categories of the physical programming units include upper physical programming units, middle physical programming units, lower physical programming units, and top physical programming units. In addition to the redundant data for protecting the upper physical programming units, the redundant data for protecting the middle physical programming units, and the redundant data for protecting the lower physical programming units, the error checking and correction circuit 54 can also divide the writing data to be written into the top physical programming unit into a coding group, and perform a redundant coding operation accordingly to generate redundant data for protecting the top physical programming unit.

[0074] In an exemplary embodiment, if the writing mode is the SLC writing mode, the error checking and correction circuit 54 can divide the writing data temporarily stored in the buffer memory 55 into multiple coding groups corresponding to multiple non-adjacent word lines respectively. Specifically, since the writing mode is the SLC writing mode and the categories of the physical programming units are all the same (for example, all are lower physical programming units), the error checking and correction circuit 54 cannot generate multiple redundant data based on the categories of the physical programming units. To improve the protection ability for the writing data, if the writing mode is the SLC writing mode, the error checking and correction circuit 54 can divide the word lines for storing the writing data into multiple word line groups, and divide the writing data to be written into different multiple word line groups into multiple coding groups, so as to perform a redundant coding operation for each coding group to generate corresponding redundant data.

[0075] Further explanation, since adjacent word lines interfere with each other, the error checking and correction circuit 54 can divide multiple non-adjacent word lines to obtain the above-mentioned multiple word line groups. Accordingly, the error checking and correction circuit 54 can perform a redundant coding operation for the writing data written into these word line groups respectively to generate multiple redundant data for protecting these word line groups respectively.

[0076] For example, assume that there are 10 word lines for storing the writing data (for example, WL0~WL9). The error checking and correction circuit 54 can divide multiple non-adjacent word lines into a word line group. For example, it can divide the odd-numbered word lines (that is, WL1, WL3, WL5, WL7, WL9) into a word line group (also called the odd word line group), and divide the even-numbered word lines (that is, WL0, WL2, WL4, WL6, WL8) into another word line group (also called the even word line group). Then, the error checking and correction circuit 54 can divide the writing data to be written into the odd word line group into a coding group, and perform a redundant coding operation for this coding group to generate redundant data for protecting the odd word line group. Similarly, the error checking and correction circuit 54 can divide the writing data to be written into the even word line group into another coding group, and perform a redundant coding operation for this another coding group to generate redundant data for protecting the even word line group.

[0077] Alternatively, the error checking and correcting circuit 54 may also divide multiple non-adjacent word lines into multiple word line groups. For example, it may divide some odd-numbered word lines (i.e., WL1, WL3, WL5) into the first word line group, and then divide other odd-numbered word lines (i.e., WL7, WL9) into the second word line group. In addition, the error checking and correcting circuit 54 may divide some even-numbered word lines (i.e., WL0, WL2, WL4) into the third word line group, and then divide other even-numbered word lines (i.e., WL6, WL8) into the fourth word line group. After that, the error checking and correcting circuit 54 may divide the write data to be written into the first to fourth word line groups into 4 coding groups, and perform redundant coding operations on these 4 coding groups respectively to generate 4 redundant data respectively used to protect the first to fourth word line groups.

[0078] That is to say, in the SLC write mode, the error checking and correcting circuit 54 may divide non-adjacent word lines used to store write data into at least two word line groups, divide the write data to be written into these at least two word line groups into at least two coding groups, and perform redundant coding operations on these at least two coding groups to generate at least two redundant data respectively used to protect these at least two word line groups, thereby enhancing the protection ability for the write data.

[0079] In step S703, after the redundant data is generated, the memory management circuit 51 may erase the write data from the buffer memory 55. That is to say, after the error checking and correcting circuit 54 generates redundant data according to the write data temporarily stored in the buffer memory 55, the memory management circuit 51 may immediately erase the write data from the buffer memory 55 (i.e., release the buffer memory 55), so that the buffer memory 55 can be used in advance to temporarily store the write data corresponding to the next write instruction, thereby enhancing the write speed and reducing the capacity requirement of the buffer memory 55.

[0080] In step S704, the memory management circuit 51 may receive the execution result of the data write operation. In an exemplary embodiment, after the rewritable non-volatile memory module 43 executes an operation, the rewritable non-volatile memory module 43 may return the execution result of this operation to the memory control circuit unit 42 to notify the memory management circuit 51 whether this operation is successful or failed. In an exemplary embodiment, the memory management circuit 51 may receive the execution result of the data write operation from the rewritable non-volatile memory module 43.

[0081] Then, in step S705, the memory management circuit 51 may confirm whether the execution result is successful. If the execution result is a successful write, it indicates that the data write operation is completed, and the Figure 7 data write method can be ended.

[0082] In contrast, if the execution result is a write failure, the process proceeds to step S706.

[0083] In step S706, the memory management circuit 51 may read the written data that belongs to the same coding group as the data with the write failure from the rewritable non-volatile memory module 43, and perform a decoding operation on the read written data and its corresponding redundant data to obtain decoded data.

[0084] For example, if the data with the write failure (i.e., the written data with an error) is stored in the upper physical programming unit (or, the middle physical programming unit, the lower physical programming unit, the top physical programming unit), the memory management circuit 51 may read the written data from the upper physical programming unit (or, the middle physical programming unit, the lower physical programming unit, the top physical programming unit), and the error checking and correcting circuit 54 performs a decoding operation on the read written data and the redundant data used to protect the upper physical programming unit (or, the middle physical programming unit, the lower physical programming unit, the top physical programming unit) to obtain the decoded data (i.e., the correct written data).

[0085] For example, if the data with the write failure is stored in the Nth word line group, the memory management circuit 51 may read the written data from the Nth word line group, and the error checking and correcting circuit 54 performs a decoding operation on the read written data and the redundant data used to protect the Nth word line group to retrieve the correct written data, where N is a positive integer.

[0086] In an exemplary embodiment, the error checking and correcting circuit 54 may perform an XOR logical operation on the read written data and its corresponding redundant data to obtain the decoded data (retrieve the correct data). For example, assume that a write error occurs in the upper physical programming unit of the target physical unit. The memory management circuit 51 first reads the written data in the upper physical programming unit. Then, the error checking and correcting circuit 54 may perform an XOR logical operation on the correct written data in the read written data and the corresponding redundant data to successfully retrieve the data with the write failure. The result of the XOR logical operation is the correct written data.

[0087] Subsequently, in step S707, the memory management circuit 51 may write the decoded data into the target physical unit. Specifically, the memory management circuit 51 may rewrite the decoded data (i.e., the correct written data) into the target physical unit to solve the write failure problem and complete the data writing operation.

[0088] Furthermore, in the conventional approach, when the rewritable non-volatile memory module 43 encounters a write failure upon recovery, the memory management circuit 51 will rewrite the write data temporarily stored in the buffer memory 55 to the rewritable non-volatile memory module 43. Therefore, a large-capacity buffer memory 55 is required to cope with the actual write operation. In Figure 7 the data writing method, the error checking and correction circuit 54 performs a decoding operation on the written data belonging to the same coding group as the data with a write failure and its corresponding redundant data to recover the correct written data. Without the need for the write data temporarily stored in the buffer memory 55, the write failure problem can also be solved.

[0089] According to the above, Figure 7 the data writing method can perform a redundant coding operation on the write data temporarily stored in the buffer memory 55 during the data writing operation to generate redundant data, and after the redundant data is generated, the buffer memory 55 can be released in advance, thereby reducing the capacity requirement of the buffer memory and improving the write efficiency without affecting the data correctness.

[0090] In an exemplary embodiment, during the execution of the data writing operation, if the data writing of a coding group cannot be completed through a single data writing operation, the memory management circuit 51 can store the redundant data in the redundant bit area of a specific physical unit corresponding to this coding group. Specifically, the amount of data that the memory storage device 10 can write in a single time is limited. If the data of a coding group cannot be completely written to the target physical unit through a single data writing operation, the memory management circuit 51 can, for example, store the redundant data in the redundant bit area of a specific physical unit corresponding to this coding group. For example, if this coding group consists of the write data of the upper physical programmed unit that will be written to the target physical unit, the memory management circuit 51 can store the redundant data in the redundant bit area of one of the upper physical programmed units (i.e., the specific physical unit) in the target physical unit, so as to facilitate quickly obtaining the required redundant data when writing the remaining write data in this coding group subsequently.

[0091] In another exemplary embodiment, during the execution of the data writing operation, if the data writing of a coding group cannot be completed through a single data writing operation, the memory management circuit 51 can also store the redundant data at any position in the target physical unit, not limited to the redundant bit area of the specific physical unit mentioned above.

[0092] In an exemplary embodiment, during the execution of a data writing operation, if the data writing of a coding group can be completed through a single data writing operation, the memory management circuit 51 may, for example, first write the coding group to the target physical unit and then write all the redundant data to the target physical unit. Alternatively, the memory management circuit 51 may, for example, also write the coding group and the redundant data to the target physical unit simultaneously.

[0093] In an exemplary embodiment, when the memory management circuit 51 reads the written data from the target physical unit, it will simultaneously read the redundant data corresponding to the written data from the target physical unit, and the error checking and correction circuit 54 will perform a decoding operation and / or an error checking and correction operation on the read written data based on this redundant data.

[0094] Figure 8 is a flowchart of the data writing method shown in an exemplary embodiment of the present invention. Please refer to Figure 8 . In step S801, a write instruction is received from the host system 11 and its corresponding written data is temporarily stored in the buffer memory 55. In step S802, a data writing operation corresponding to the write instruction is performed to generate redundant data based on the written data in the buffer memory 55, and the written data in the buffer memory 55 is written to the target physical unit in the rewritable non-volatile memory module 43. In step S803, after the redundant data is generated, the written data is erased from the buffer memory 55. If the execution result of the data writing operation received from the rewritable non-volatile memory module 43 is a successful write, the data writing operation is completed.

[0095] However, Figure 8 each step has been described in detail above and will not be elaborated here. It should be noted that Figure 8 each step can be implemented as multiple program codes or circuits, and the present invention does not limit this. In addition, Figure 8 the method of

[0096] can be used in conjunction with the above embodiments or used alone, and the present invention does not limit this.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data writing method, characterized in that: Used in a memory storage device, the memory storage device includes a memory control circuit unit and a rewritable non-volatile memory module, the memory control circuit unit includes a buffer memory, the rewritable non-volatile memory module includes a plurality of physical units, and the data writing method includes: receiving a write instruction from a host system and temporarily storing the corresponding write data in the buffer memory; Executing a data write operation corresponding to the write instruction, generating redundant data according to the write data in the buffer memory, and writing the write data in the buffer memory into a target physical unit of the rewritable non-volatile memory module; and After the redundant data is generated, erasing the write data from the buffer memory; and If the execution result of the data writing operation received from the rewritable non-volatile memory module is that the writing is successful, the data writing operation is completed.

2. The data writing method according to claim 1, characterized in that: The write data in the buffer memory is divided into a plurality of coding groups, and a redundant coding operation is performed on each of the coding groups to generate corresponding redundant data, wherein the data writing method further comprises: If the execution result is a write failure, reading written data belonging to the same coding group as the data that failed to be written from the rewritable non-volatile memory module, and performing a decoding operation on the read written data and the corresponding redundant data to obtain decoded data; and The decoded data is written into the target physical unit.

3. The data writing method according to claim 1, further comprising: If the write mode is not the single-level storage unit write mode, the write data in the buffer memory is divided into a plurality of code groups corresponding to different types of physical programming units.

4. The data writing method according to claim 1, further comprising: If the write mode is a single-level memory cell write mode, the write data in the buffer memory is divided into a plurality of coding groups corresponding to a plurality of non-adjacent word lines respectively.

5. The data writing method according to claim 1, further comprising: During the data writing operation, if the data writing of the coding group cannot be completed through a single data writing operation, the redundant data is stored in a redundant bit area in a specific physical unit corresponding to the coding group.

6. A memory storage device, characterized in that: include: A connection interface unit for coupling to a host system; A rewritable non-volatile memory module includes a plurality of physical units; as well as The memory control circuit unit includes a buffer memory and an error checking and correction circuit, and is used to couple to the connection interface unit and the rewritable non-volatile memory module, wherein The memory control circuit unit receives a write instruction from the host system and temporarily stores the corresponding write data in the buffer memory. The memory control circuit unit performs a data write operation corresponding to the write instruction, generates redundant data according to the write data in the buffer memory through the error check and correction circuit, and writes the write data in the buffer memory into a target physical unit in the rewritable non-volatile memory module. After the redundant data is generated, the memory control circuit unit erases the write data from the buffer memory; as well as If the execution result of the data writing operation received from the rewritable non-volatile memory module is that the writing is successful, the data writing operation is completed.

7. The memory storage device according to claim 6, wherein the error checking and correction circuit divides the write data in the buffer memory into a plurality of coding groups, and performs a redundant coding operation on each of the coding groups to generate the corresponding redundant data, If the execution result is a write failure, the memory control circuit unit reads written data belonging to the same coding group as the data that fails to be written from the rewritable non-volatile memory module, and performs a decoding operation on the read written data and the corresponding redundant data through the error checking and correction circuit to obtain decoded data, and The memory control circuit unit writes the decoded data into the target physical unit.

8. The memory storage device of claim 6, wherein if the write mode is not the single-level cell write mode, the ECC circuit divides the write data in the buffer memory into a plurality of code groups corresponding to different types of physical programming units.

9. The memory storage device of claim 6, wherein if the write mode is a single-level cell write mode, the ECC circuit divides the write data in the buffer memory into a plurality of coding groups respectively corresponding to a plurality of non-adjacent word lines.

10. The memory storage device according to claim 6, wherein during the data writing operation, if the data writing of the coding group cannot be completed through a single data writing operation, the memory control circuit unit stores the redundant data in a redundant bit area in a specific physical unit corresponding to the coding group.

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