Storage space sharing method and device, chip, network interface card, computer equipment, readable storage medium and program product

Abstract

The invention relates to a storage space sharing method and device, a chip, a network interface card, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: under the condition that a first processor core performs read-write operation, sending read-write operation information of the first processor core to a second processor core through inter-core communication, the read-write operation information is used for instructing the second processor core to perform read-write operation on a target storage space in storage spaces corresponding to the second processor core, and the target storage space is allocated to the first processor core by the second processor core in advance; wherein the capacity of the storage space corresponding to the second processor core is greater than that of the storage space corresponding to the first processor core. By adopting the method, the first processor core can use the storage space of the second processor core, and the storage space of the first processor core is expanded.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular, to a method, device, chip, network interface card, computer device, computer-readable storage medium, and computer program product for sharing storage space. Background Art

[0002] A DPU (Data Processing Unit) is a dedicated processor constructed around data, which completes acceleration processing tasks for networking, storage, and security. With the rise of technologies such as cloud computing, AI, and big data, higher and higher requirements are put forward for data centers, which need to provide users with certain computing power, storage space, and application service at the same time, and there are a large number of complex scenario applications.

[0003] In the traditional technology, the overall hardware architecture of the DPU consists of multiple components. Taking the common arm architecture as an example, it includes multiple big cores and small cores, N2, SCP (System Control Processor), IMU (Integrated Management Unit), MCP (Manageability Control Processor), and so on. Among them, N2 serves as the main / core big core of the DPU, responsible for the data services and offloading services of the DPU. SCP, IMU, and MCP are small cores of the Cortex-M7 Processor type. SCP is responsible for the power management of the DPU and pulling up each component of the DPU system during the startup phase. IMU is responsible for device emulation of the DPU and services related to data plane forwarding. MCP is mainly responsible for the management plane of the DPU and reporting the status information related to the DPU.

[0004] Due to chip and peripheral resource limitations, DPU small cores usually use NAND FLASH / NOR FLASH as external storage media. Currently, the sizes of the FLASH that small cores can use are fixed and allocated, and the sizes are limited to a certain extent, which is basically only enough to store resources related to the image, and the storage resources are less, which is not conducive to being used as storage resources during the operation of small cores. Summary of the Invention

[0005] Based on this, in order to solve the above technical problems, it is necessary to provide a method, device, chip, network interface card, computer device, computer-readable storage medium, and computer program product for sharing storage space, which can enable a first processor core to use the storage space of a second processor core and expand the storage space of the first processor core.

[0006] In a first aspect, the present application provides a method for sharing storage space, which is applied to a first processor core, and the method includes:

[0007] When a read / write operation is performed on the first processor core, the read / write operation information of the first processor core is sent to the second processor core through inter-core communication. The read / write operation information is used to instruct the second processor core to perform a read / write operation on a target storage space in the storage space corresponding to the second processor core. The target storage space is pre-allocated by the second processor core for the first processor core, where the capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core.

[0008] In one embodiment, the sending the read / write operation information of the first processor core to the second processor core through inter-core communication includes:

[0009] Writing the read / write operation information into the communication front end;

[0010] Sending a first notification to the communication back end including the second processor core through the communication front end. The first notification is used to indicate the storage location of the read / write operation information of the first processor core in the communication front end, and the storage location is used to instruct the second processor core to read the read / write operation information from the communication front end.

[0011] In one embodiment, the communication front end includes a shared memory; the writing the read / write operation information into the communication front end includes:

[0012] Determining the storage information corresponding to the shared memory, and determining a target shared memory space based on the storage information;

[0013] Writing the read / write operation information into the target shared memory space based on the virtual storage device protocol, and updating the storage information corresponding to the shared memory.

[0014] In one embodiment, the communication front end further includes a message processing unit; the sending the first notification to the communication back end including the second processor core through the communication front end includes:

[0015] Sending a first notification to the communication back end including the second processor core through the message processing unit.

[0016] In one embodiment, the method further includes:

[0017] Sending a storage space expansion request to the second processor core through inter-core communication;

[0018] Receiving the target storage space allocated by the second processor core for the first processor core.

[0019] In one embodiment, in one embodiment, the method further includes:

[0020] Receive a second notification sent by the second processor core, where the second notification is sent after the second processor core obtains response data corresponding to the read / write operation and writes the response data into the shared memory, and the second notification is used to instruct the first processor core to read the response result of the read / write operation from the shared memory.

[0021] In one embodiment, the inter-core communication adopts the VIRTIOBLK communication protocol.

[0022] In a second aspect, the present application further provides a storage space sharing method, which is applied to a second processor core. The method includes:

[0023] Receive read / write operation information sent by a first processor core through inter-core communication;

[0024] Based on the read / write operation information, perform a read / write operation on a target storage space in the storage space corresponding to the second processor core, where the target storage space is pre-allocated by the second processor core for the first processor core, and the capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core.

[0025] In one embodiment, the receiving the read / write operation information sent by the first processor core through inter-core communication includes:

[0026] Receive a first notification sent by the first processor core, where the first notification is used to indicate the storage location of the read / write operation information in the shared memory;

[0027] Obtain the read / write operation information from the shared memory based on the storage location.

[0028] In one embodiment, the performing a read / write operation on a target storage space in the storage space corresponding to the second processor core based on the read / write operation information includes:

[0029] Based on the read / write operation information, determine the target storage space in the storage space corresponding to the second processor core;

[0030] Perform a read / write operation on the target storage space based on the read / write operation information.

[0031] In one embodiment, after performing a read / write operation on a target storage space in the storage space corresponding to the second processor core based on the read / write operation information, it includes:

[0032] Obtain response data corresponding to the read / write operation, and write the response data into the shared memory;

[0033] Send a second notification to the first processor core, where the second notification is used to instruct the first processor core to read the response result of the read-write operation from the shared memory.

[0034] In one embodiment, the method further includes:

[0035] Receive a storage space expansion request sent by the first processor core through inter-core communication;

[0036] Based on the storage space expansion request, partition the storage space corresponding to the second processor core to obtain a target storage space corresponding to the first processor core.

[0037] In a third aspect, the present application further provides a storage space sharing device, which is applied to a first processor core. The device includes:

[0038] A sending module, configured to, when the first processor core performs a read-write operation, send the read-write operation information of the first processor core to the second processor core through inter-core communication. The read-write operation information is used to instruct the second processor core to perform a read-write operation on a target storage space in the storage space corresponding to the second processor core. The target storage space is pre-allocated by the second processor core for the first processor core, where the capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core.

[0039] In a fourth aspect, the present application further provides a storage space sharing device, which is applied to a second processor core. The device includes:

[0040] A receiving module, configured to receive the read-write operation information sent by the first processor core through inter-core communication;

[0041] A read-write operation module, configured to perform a read-write operation on a target storage space in the storage space corresponding to the second processor core based on the read-write operation information. The target storage space is pre-allocated by the second processor core for the first processor core, where the capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core.

[0042] In a fifth aspect, the present application further provides a chip, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of the method described in any one of the above embodiments are implemented.

[0043] In a sixth aspect, the present application further provides a network interface card, including the chip described in any one of the above embodiments and a plurality of interfaces. The chip processes data or communicates externally through the interfaces.

[0044] In a seventh aspect, the present application further provides a computer device, including the network interface card in any of the above embodiments, where the network interface card is used to process data or communicate externally.

[0045] In an eighth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method in any of the above embodiments are implemented.

[0046] In a ninth aspect, the present application further provides a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of the method in any of the above embodiments are implemented.

[0047] In the above storage space sharing method, device, chip, network interface card, computer device, computer-readable storage medium, and computer program product, when a read / write operation is performed on a first processor core, the read / write operation information of the first processor core is sent to a second processor core through inter-core communication, where the read / write operation information is used to instruct the second processor core to perform a read / write operation on a target storage space in the storage space corresponding to the second processor core. The target storage space is pre-allocated by the second processor core for the first processor core, and the capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core. In this way, the first processor core can use the storage space of the second processor core to expand the storage space of the first processor core and ensure the normal operation of the functions of the first processor core. Description of the Drawings

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required to be used in the description of the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0049] Figure 1 It is a schematic diagram of a multi-core DPU arm architecture in the traditional technology;

[0050] Figure 2 It is a schematic diagram of the application environment of the storage space sharing method in an embodiment;

[0051] Figure 3 It is a schematic diagram of the process of the storage space sharing method in an embodiment;

[0052] Figure 4 It is a schematic diagram of the front end and the back end in an embodiment;

[0053] Figure 5Schematic flowchart of the storage space sharing method in another embodiment;

[0054] Figure 6 Schematic flowchart of the processing steps of each processor core in an embodiment;

[0055] Figure 7 Schematic block diagram of the storage space sharing device in an embodiment;

[0056] Figure 8 Schematic block diagram of the storage space sharing device in another embodiment. Detailed implementation manners

[0057] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0058] Combined with Figure 1 as shown Figure 1 It is a schematic diagram of a multi-core DPU arm architecture in the traditional technology, where the DPU small cores usually use NAND FLASH / NOR FLASH as the external storage medium. Currently, the sizes of the FLASH that the small cores can use are fixedly allocated, and the sizes are limited to a certain extent. Basically, it is only enough to store resources related to the image, and there is no extra space for other uses.

[0059] Due to such resource limitations of the FLASH, the small cores do not have extra storage resources, which impose certain limitations on the business operation. Specifically:

[0060] Due to the size limitation of the FLASH, there are strict limitations on the size of the runtime logs, and it is impossible to save more relevant log information. During the debugging phase, it can be located by printing the serial port, but without real-time log recording in a long-term stable environment, it will increase the difficulty of problem location. Usually, the logs can also be written into the DDR, but the DDR also has size limitations. More DDR-based logs are generally used for the implementation of the last words, and the data in the DDR will disappear after the system is reset, which will also affect the location and analysis of system problems.

[0061] Due to the size limitation of the FLASH, there are certain limitations on the image backup and data backup of the small cores. It is impossible to flexibly back up the image and data.

[0062] Due to the limitation of the write rate of the FLASH controller, it will have a certain impact on the runtime performance. Basically, the small core only has one CPU and cannot achieve multi-task concurrent processing. If the write to the FLASH occupies the CPU for a long time, it will inevitably cause other pending tasks to hang and affect the normal interaction function of the service.

[0063] Moreover, the services on the DPU side are becoming increasingly complex, the services processed by the small cores are becoming more and more numerous, and the interactions between cores are also increasing. To meet the needs of different cores and different services, a larger storage is required to store updated information to achieve more extended functions. Therefore, in this application, by adopting the idea of distributed storage, the storage space of the small core is expanded through a flexible architecture and configuration to achieve the sharing of storage resources on the DPU side. The storage space of the large core N2 of the DPU is shared with the small core in a certain way. In this application, the storage space of N2 is taken as an example of SATA, and others such as SSD and NVME are similar. The type of the storage space of N2 is not limited here.

[0064] For the convenience of description, in this application, the small core is referred to as the first processor core, the large core is referred to as the second processor core, and the capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core.

[0065] The storage space sharing method provided by the embodiments of this application can be applied to an application environment as Figure 2 shown. Among them Figure 2 the second processor core is labeled as N2, and the first processor core includes IMU0 (Integrated Management Unit), IMU1, SCP (System Control Processor), and MCP (Manageability Control Processor). In other embodiments, it may also include other types. The storage space corresponding to the second processor core is SATA, and the first processor core can share the storage space of the second processor core. The storage space allocated by the second processor core to each first processor core is Figure 2 shown as SHARE SATA in

[0066] When a read / write operation is performed on the first processor core, the read / write operation information of the first processor core is sent to the second processor core through inter-core communication. The read / write operation information is used to instruct the second processor core to perform read / write operations on a target storage space in the storage space corresponding to the second processor core. The target storage space is pre-allocated by the second processor core for the first processor core. The capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core. In this way, the first processor core can use the storage space of the second processor core to expand the storage space of the first processor core and ensure the normal operation of the functions of the first processor core.

[0067] In an exemplary embodiment, as Figure 3 shown, a storage space sharing method is provided. Taking any first processor core in Figure 1 as an example, the following steps 302 are included. Wherein:

[0068] S302: When a read / write operation is performed on the first processor core, the read / write operation information of the first processor core is sent to the second processor core through inter-core communication. The read / write operation information is used to instruct the second processor core to perform read / write operations on a target storage space in the storage space corresponding to the second processor core. The target storage space is pre-allocated by the second processor core for the first processor core. The capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core.

[0069] The capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core. Generally, the first processor core is a small core in the DPU, which usually uses NAND FLASH or NOR FLASH as an external storage medium. The second processor core is a large core in the DPU, and the capacity of the corresponding storage space is greater than the capacity of the storage space corresponding to the first processor core. In this application, in order to expand the capacity of the storage space of the first processor core, the storage space corresponding to the second processor core is shared for the first processor core to use. For example, the storage space corresponding to the second processor core is transparently transmitted to the small core through the pipeline method of inter-core communication.

[0070] Subsequently, when the first processor core uses the corresponding target storage space, that is, when the first processor core performs read / write operations, the read / write operation information of the first processor core is sent to the second processor core through inter-core communication. Then, the second processor core performs read / write operations on the target storage space in the storage space corresponding to the second processor core, so that the first processor core can use the storage space of the second processor core.

[0071] In some alternative embodiments, only when the first processor core performs target read / write operations can the storage space corresponding to the second processor core be used. In the case of non-target read / write operations, NAND FLASH or NOR FLASH is still used as the external storage medium. For example, when processing resources related to images, NAND FLASH or NOR FLASH can still be used as the external storage medium. For other target read / write operations, such as runtime logs, the storage space corresponding to the second processor core is used.

[0072] In some alternative embodiments, all target read / write operations corresponding to the first processor core use the storage space corresponding to the second processor core, so that the first processor core can handle more services.

[0073] In some alternative embodiments, the inter-core communication uses the VIRTIO BLK communication protocol. In other embodiments, other communication protocols can also be used for inter-core communication.

[0074] For the above storage space sharing method, when the first processor core performs read / write operations, the read / write operation information of the first processor core is sent to the second processor core through inter-core communication. The read / write operation information is used to instruct the second processor core to perform read / write operations on the target storage space in the storage space corresponding to the second processor core. The target storage space is pre-allocated by the second processor core for the first processor core, and the capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core. This enables the first processor core to use the storage space of the second processor core, expand the storage space of the first processor core, and ensure the normal operation of the functions of the first processor core.

[0075] In one of the alternative embodiments, sending the read / write operation information of the first processor core to the second processor core through inter-core communication includes: writing the read / write operation information into the communication front end; sending a first notification to the communication back end including the second processor core through the communication front end. The first notification is used to indicate the storage location of the read / write operation information of the first processor core in the communication front end, and the storage location is used to instruct the second processor core to read the read / write operation information from the communication front end.

[0076] Combined with Figure 2As shown, the communication between the first processor core and the second processor core in this application can adopt the method of a communication front end and a communication back end. The communication front end can implement the data plane through a shared memory and a message handling unit (MHU). The communication front end and the communication back end follow the VIRTIO communication protocol. In practical applications, the storage space resource of the second processor core is presented to the first processor core as a VIRTIO BLK device. The first processor core can load the driver corresponding to the VIRTIO BLK device to perform read and write operations on the VIRTIO BLK device. Combined with Figure 4 As shown, the communication back end of the VIRTIO BLK device includes the second processor core and the corresponding storage space. The communication front end of the VIRTIO BLK device implements the VIRTIO data plane through a shared memory and a message handling unit (MHU).

[0077] Since the first processor core has loaded the driver corresponding to the VIRTIO BLK device, it can drive the VIRTIO BLK device to write the read and write operation information into the communication front end. After writing the read and write operation information, the communication front end sends a first notification to the communication back end.

[0078] The first notification is used to notify the communication back end that there is new read and write operation information that needs to be processed. In addition, it is also necessary to inform the storage location of the new read and write operation information in the communication front end, so that the second processor core reads the read and write operation information from the communication front end based on this storage location.

[0079] In one optional embodiment, the communication front end includes a shared memory; writing the read and write operation information into the communication front end includes: determining the storage information corresponding to the shared memory, and determining the target shared memory space based on the storage information; writing the read and write operation information into the target shared memory space based on the virtual storage device protocol, and updating the storage information corresponding to the shared memory.

[0080] The communication front end includes a shared memory, which can include a transmit queue and a receive queue. The transmit queue and the receive queue are relative to the VIRTIO BLK device. Each VIRTIO BLK device can correspond to at least one transmit queue and at least one receive queue. Each transmit queue and receive queue can correspond to a first processor core. The transmit queue and the receive queue both include a descriptor table, an available storage location identifier, an already used storage location identifier, and a queue doorbell mechanism. The depth of the transmit queue and the receive queue depends on the size limit of the shared memory. In this application, the sizes of the transmit queue and the receive queue can be configured based on the size of the shared memory. For example, the sizes of the transmit queue and the receive queue can be configured as fixed values, which can facilitate the management of the resources of the communication front end and the communication back end and make them more reliable and stable.

[0081] Among them, when the first processor core performs data reading and writing operations, it first determines the storage information corresponding to the shared memory. The storage information includes an available storage location identifier and an occupied storage location identifier. The available storage location identifier can be an available ring (avail ring), and the occupied storage location identifier can be a used ring (used ring). Each storage location identifier corresponds to a specific storage space in the shared memory, and this specific storage space is used to store the information in the corresponding descriptor table. The first processor core determines the target shared memory space based on the storage information, and writes the read / write operation information into the target shared memory space based on the virtual storage device protocol, that is, puts the read / write operation information corresponding to the read / write operation (such as a descriptor (descriptor of an instruction) or a data packet) into the descriptor table of the send queue.

[0082] In one alternative embodiment, the communication front end further includes a message processing unit; sending a first notification to the communication back end including the second processor core through the communication front end includes: sending a first notification to the communication back end including the second processor core through the message processing unit.

[0083] Among them, the doorbell mechanism of the queue is implemented by the message processing unit MHU. After the first processor core writes the read / write operation information into the target shared memory space, the message processing unit is used to send a first notification to the communication back end including the second processor core, so that the communication back end can process the read / write operation information stored in the target shared memory space.

[0084] In some alternative embodiments, the method further includes: receiving a second notification sent by the second processor core. The second notification is sent after the second processor core obtains the response data corresponding to the read / write operation and writes the response data into the shared memory, and the second notification is used to instruct the first processor core to read the response result of the read / write operation from the shared memory.

[0085] Among them, after receiving the first notification, the communication back end determines the position of the read / write operation information in the shared memory based on the storage location to obtain the read / write operation information. After processing the read / write operation information, the response data is written into the shared memory, and a second notification is sent to the communication front end through the message processing unit to notify the first processor core that the read / write operation request has been processed.

[0086] Among them, the physical message processing unit supports the doorbell mode and can support multi-bit status to trigger interrupts. Each message processing unit can support more than 128 interrupt sources, so that multiple queues can be extended, that is, each message processing unit can support 64 first processor cores to communicate with the second processor core for inter-core communication.

[0087] In some optional embodiments, the number of message processing units of the communication front end of the present application may include at least one, for example, two or three, etc., to expand the number of first processor cores that can use the storage space of the second processor core.

[0088] In one of the optional embodiments, the method further includes: sending a storage space expansion request to the second processor core through inter-core communication; and receiving a target storage space allocated by the second processor core to the first processor core.

[0089] The storage space corresponding to the second processor core is presented as a virtual storage device to the first processor core. The correspondence between the virtual storage device and the first processor core is one-to-one or one-to-many, that is, each first processor core can use a storage space corresponding to the second processor core individually, or multiple first processor cores can share a storage space corresponding to the second processor core, which is not specifically limited here.

[0090] Among them, the first processor core sends a storage space expansion request to the second processor core through inter-core communication, for example, the storage space expansion request is stored in the shared memory, and the second processor core is informed through the message processing unit. The second processor core obtains the storage space expansion request from the shared memory and allocates the target storage space to the first processor core.

[0091] The second processor core stores the association relationship between the first processor core and the target storage space, so that after receiving the read and write operation information of the first processor core, the corresponding target storage space can be determined for normal reading and writing.

[0092] In an exemplary embodiment, Figure 5 As shown, a storage space sharing method is provided, which is applied to Figure 1 Taking the second processor core in the example as an example, the method includes the following steps 502 to 504. Among them:

[0093] S502: Receive read and write operation information sent by the first processor core through inter-core communication.

[0094] The specific manner in which the first processor core sends the read and write operation information through the inter-core communication can be found above and will not be described in detail here.

[0095] S504: Based on the read and write operation information, perform read and write operations on the target storage space in the storage space corresponding to the second processor core, where the target storage space is pre-allocated by the second processor core to the first processor core, wherein the capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core.

[0096] Among them, after receiving the read / write operation information, the second processor core performs read / write operations on the target storage space in the storage space based on the read / write operation information to complete the read / write operations of the first processor core, thereby converting the read / write operations of the first processor core to the target storage space corresponding to the second processor core. In this way, the first processor core can use the storage space of the second processor core to expand the storage space of the first processor core and ensure the normal operation of the functions of the first processor core.

[0097] In one alternative embodiment, receiving the read / write operation information sent by the first processor core through inter-core communication includes: receiving a first notification sent by the first processor core, where the first notification is used to indicate the storage location of the read / write operation information in the shared memory; and obtaining the read / write operation information from the shared memory based on the storage location.

[0098] The storage location of the read / write operation information in the shared memory is sent through the first notification, and the first notification is sent by the message processing unit to the communication backend. Thus, the second processor core can know the storage location of the read / write operation information, obtain the read / write operation information from this storage location, and perform read / write operations on the target storage location based on the read / write operation information.

[0099] In one alternative embodiment, performing read / write operations on the target storage space in the storage space corresponding to the second processor core based on the read / write operation information includes: determining the target storage space in the storage space corresponding to the second processor core based on the read / write operation information; and performing read / write operations on the target storage space based on the read / write operation information.

[0100] Among them, the second processor core has pre-allocated corresponding target storage spaces for each first processor core. Therefore, after receiving the first notification, it can obtain the read / write operation information, determine the target storage space based on the first processor core identifier, etc. in the read / write operation information, and then perform read / write operations on the target storage space based on the read / write operation information.

[0101] In one alternative embodiment, after performing read / write operations on the target storage space in the storage space corresponding to the second processor core based on the read / write operation information, it includes: obtaining response data corresponding to the read / write operation, writing the response data into the shared memory; and sending a second notification to the first processor core, where the second notification is used to indicate that the first processor core reads the response result of the read / write operation from the shared memory.

[0102] Among them, after receiving the first notification, the communication backend determines the location of the read / write operation information in the shared memory based on the storage location to obtain the read / write operation information. After processing the read / write operation information, the response data is written into the shared memory, and a second notification is sent to the communication frontend through the message processing unit to notify the first processor core that the processing of the read / write operation request is completed. Thus, the first processor core obtains the corresponding response data from the shared memory based on the second notification to determine whether the corresponding read / write operation is successful.

[0103] In one alternative embodiment, the method further includes: receiving a storage space expansion request sent by the first processor core through inter-core communication; partitioning the storage space corresponding to the second processor core based on the storage space expansion request to obtain a target storage space corresponding to the first processor core.

[0104] Among them, the storage space corresponding to the second processor core is presented to the first processor core as a virtual storage device. The correspondence between the virtual storage device and the first processor core is one-to-one or one-to-many, that is, each first processor core can independently use a piece of storage space corresponding to the second processor core, or multiple first processor cores can share a piece of storage space corresponding to the second processor core, which is not specifically limited here.

[0105] Among them, the first processor core sends a storage space expansion request to the second processor core through inter-core communication, for example, stores the storage space expansion request in the shared memory, and notifies the second processor core through the message processing unit. The second processor core obtains the storage space expansion request from the shared memory and allocates a target storage space for the first processor core.

[0106] Among them, the second processor core stores the association relationship between the first processor core and the target storage space, so that after receiving the read / write operation information of the first processor core subsequently, the corresponding target storage space can be determined for normal reading and writing.

[0107] Specifically, in combination with Figure 4 As shown, the second processor core mainly includes the JM daemon module, which is mainly responsible for managing the backend disk space management and interacting with the front-end VIRTIO BLK protocol. If the small core disk expansion function is enabled on the DPU side, a corresponding extended partition will be created on the SATA, and the specific partition size can be adjusted according to the actual disk size. After determining the extended partition, the JM daemon module can be loaded to take over the data messages of the front-end VIRTIO.

[0108] Among them, for easy understanding, in combination with Figure 6 As shown, Figure 6It is a flowchart of the processing steps of each processor core in an embodiment. The first processor core starts and waits for the communication front end and the communication back end to be initialized, and then checks whether the VIRTIO BLK status allows operation. If so, read and write operations are performed. It should be noted that each read and write operation needs to first check whether the VIRTIO BLK status allows operation. When it is a Shutdown operation, the back end needs to be notified to complete the sync synchronization operation.

[0109] After the second processor core starts, it completes the initialization of the communication front end and the communication back end. Then the communication back end continuously sends a BLK ready message to the communication front end, that is, a message indicating that the VIRTIO BLK status allows operation. Subsequently, it responds to the read and write operations sent by the first processor core. In addition, the second processor core also responds to the Shutdown operation of the first processor core and completes the sync synchronization operation. Finally, the second processor core resets the communication front end and the communication back end, that is, resets them to the initialization state.

[0110] In summary, in this application, taking the VIRTIO BLK protocol as an example, SATA is directly passed to the small core for use, enabling the small core to read and write SATA as if it were operating on a local disk. Moreover, the data plane is implemented based on shared memory and MHU, and the overall read and write performance is much higher than the rate of reading and writing FLASH via the QSPI bus. It enables the small core to record necessary logs during operation or can be used as a backup disk for operations such as backing up images. This greatly reduces the difficulty of problem location for the long-term stable operation of the DPU and at the same time greatly enriches the storage resources of the small core for various function expansions.

[0111] It should be understood that although the steps in the flowcharts involved in the above embodiments are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless specifically stated in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least some of the steps or stages in other steps or other steps.

[0112] Based on the same inventive concept, an embodiment of the present application further provides a storage space sharing device for implementing the storage space sharing method involved above. The solution provided by this device to solve the problem is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the storage space sharing device provided below can refer to the limitations on the storage space sharing method in the above text, and will not be repeated here.

[0113] In an exemplary embodiment, as Figure 7 shown, a storage space sharing device is provided, including: a sending module 701, where:

[0114] The sending module 701 is configured to, when a first processor core performs read and write operations, send the read and write operation information of the first processor core to a second processor core through inter-core communication. The read and write operation information is used to instruct the second processor core to perform read and write operations on a target storage space in the storage space corresponding to the second processor core. The target storage space is pre-allocated by the second processor core for the first processor core, where the capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core.

[0115] In one optional embodiment, the above sending module is specifically configured to write the read and write operation information into the communication front end; send a first notification to a communication back end including the second processor core through the communication front end. The first notification is used to indicate the storage location of the read and write operation information of the first processor core in the communication front end, and the storage location is used to instruct the second processor core to read the read and write operation information from the communication front end.

[0116] In one optional embodiment, the communication front end includes a shared memory; the above sending module is specifically configured to determine the storage information corresponding to the shared memory, and determine the target shared memory space based on the storage information; write the read and write operation information into the target shared memory space based on the virtual storage device protocol, and update the storage information corresponding to the shared memory.

[0117] In one optional embodiment, the communication front end further includes a message processing unit; the above sending module is specifically configured to send a first notification to a communication back end including the second processor core through the message processing unit.

[0118] In one optional embodiment, the above sending module is specifically configured to send a storage space expansion request to the second processor core through inter-core communication; receive the target storage space allocated by the second processor core for the first processor core.

[0119] In one alternative embodiment, the above-mentioned sending module is specifically configured to receive a second notification sent by a second processor core. The second notification is sent after the second processor core obtains response data corresponding to a read / write operation and writes the response data into the shared memory, and the second notification is used to instruct the first processor core to read the response result of the read / write operation from the shared memory.

[0120] In one alternative embodiment, the inter-core communication adopts the VIRTIO BLK communication protocol.

[0121] In an exemplary embodiment, as Figure 8 shown, a storage space sharing device is provided, including: a receiving module 801 and a read / write operation module 802, where:

[0122] The receiving module 801 is configured to receive read / write operation information sent by a first processor core through inter-core communication;

[0123] The read / write operation module 802 is configured to perform read / write operations on a target storage space in the storage space corresponding to the second processor core based on the read / write operation information. The target storage space is pre-allocated by the second processor core for the first processor core, and the capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core.

[0124] In one alternative embodiment, the above-mentioned receiving module is specifically configured to receive a first notification sent by the first processor core. The first notification is used to indicate the storage location of the read / write operation information in the shared memory;

[0125] Obtain the read / write operation information from the shared memory based on the storage location.

[0126] In one alternative embodiment, the above-mentioned read / write operation module is specifically configured to determine the target storage space in the storage space corresponding to the second processor core based on the read / write operation information; perform read / write operations on the target storage space based on the read / write operation information.

[0127] In one alternative embodiment, the above-mentioned device further includes: a response module specifically configured to obtain response data corresponding to the read / write operation, write the response data into the shared memory; send a second notification to the first processor core, and the second notification is used to instruct the first processor core to read the response result of the read / write operation from the shared memory.

[0128] In one alternative embodiment, the above-mentioned receiving module is specifically configured to receive a storage space expansion request sent by the first processor core through inter-core communication; partition the storage space corresponding to the second processor core based on the storage space expansion request to obtain a target storage space corresponding to the first processor core.

[0129] Each module in the above storage space sharing device can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above modules can be embedded in the processor of the computer device in hardware form or be independent of it, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each of the above modules.

[0130] In one embodiment, a chip is further provided, which includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps in each of the above method embodiments are implemented.

[0131] In one embodiment, a network interface card is further provided, which includes the chip in any of the above embodiments and a plurality of interfaces. Among them, the interfaces can include communication interfaces such as PCI / PCIE interfaces, UART interfaces, SPI interfaces, USB interfaces, and network interfaces. The chip processes data or communicates externally through the interfaces.

[0132] In one embodiment, a computer device is further provided, which includes the network interface card in any of the above embodiments. The network interface card is used to process data or communicate externally.

[0133] In one embodiment, a computer device is further provided, which includes a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps in each of the above method embodiments are implemented.

[0134] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in each of the above method embodiments are implemented.

[0135] In one embodiment, a computer program product is provided, which includes a computer program. When the computer program is executed by a processor, the steps in each of the above method embodiments are implemented.

[0136] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data that have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with relevant regulations.

[0137] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processors, graphics processors, digital signal processors, programmable logic devices, data processing logics based on quantum computing, artificial intelligence (AI) processors, etc., without limitation.

[0138] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in the present application.

[0139] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A storage space sharing method, characterized in that: Applied to a first processor core, the method comprises: When the first processor core performs read and write operations, the read and write operation information of the first processor core is sent to the second processor core through inter-core communication, and the read and write operation information is used to instruct the second processor core to perform read and write operations on the target storage space in the storage space corresponding to the second processor core, and the target storage space is pre-allocated by the second processor core to the first processor core, wherein the capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core.

2. The method according to claim 1, characterized in that The sending the read and write operation information of the first processor core to the second processor core through inter-core communication includes: Write the read and write operation information into the communication front end; A first notification is sent through the communication front end to a communication back end including a second processor core, wherein the first notification is used to indicate a storage location of read and write operation information of the first processor core in the communication front end, and the storage location is used to indicate that the second processor core reads the read and write operation information from the communication front end.

3. The method according to claim 2, characterized in that The communication front end includes a shared memory; the step of writing the read and write operation information into the communication front end includes: Determine storage information corresponding to the shared memory, and determine a target shared memory space based on the storage information; The read and write operation information is written into the target shared memory space based on the virtual storage device protocol, and the storage information corresponding to the shared memory is updated.

4. The method according to claim 3, characterized in that The communication front end also includes a message processing unit; the sending of a first notification to a communication back end including a second processor core through the communication front end includes: A first notification is sent to a communication backend including a second processor core through the message processing unit.

5. The method according to claim 3, characterized in that: The method further comprises: Sending a storage space expansion request to the second processor core through inter-core communication; Receive a target storage space allocated by the second processor core to the first processor core.

6. The method according to claim 3, characterized in that The method further comprises: Receive a second notification sent by the second processor core, where the second notification is sent after the second processor core obtains response data corresponding to the read / write operation and writes the response data into the shared memory, and the second notification is used to instruct the first processor core to read the response result of the read / write operation from the shared memory.

7. The method according to claim 1, characterized in that The inter-core communication adopts the VIRTIO BLK communication protocol.

8. A storage space sharing method, characterized in that: Applied to the second processor core, the method comprises: Receiving read and write operation information sent by the first processor core through inter-core communication; Based on the read and write operation information, read and write operations are performed on the target storage space in the storage space corresponding to the second processor core, where the target storage space is pre-allocated by the second processor core to the first processor core, and the capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core.

9. The method according to claim 8, characterized in that The receiving the read / write operation information sent by the first processor core through inter-core communication includes: receiving a first notification sent by a first processor core, wherein the first notification is used to indicate a storage location of read and write operation information of the first processor core in a shared memory; Read and write operation information is obtained from the shared memory based on the storage location.

10. The method according to claim 9, characterized in that The performing a read and write operation on a target storage space in a storage space corresponding to the second processor core based on the read and write operation information includes: Based on the read and write operation information, determining a target storage space in the storage space corresponding to the second processor core; Perform read and write operations on the target storage space based on the read and write operation information.

11. The method according to claim 9, characterized in that After performing the read and write operations on the target storage space in the storage space corresponding to the second processor core based on the read and write operation information, the method includes: Acquire response data corresponding to the read / write operation, and write the response data into the shared memory; A second notification is sent to the first processor core, where the second notification is used to instruct the first processor core to read a response result of the read and write operation from the shared memory.

12. The method according to any one of claims 8 to 11, characterized in that: The method further comprises: receiving a storage space expansion request sent by the first processor core through inter-core communication; Based on the storage space expansion request, the storage space corresponding to the second processor core is partitioned to obtain a target storage space corresponding to the first processor core.

13. A storage space sharing device, characterized in that: Applied to a first processor core, the device comprises: A sending module is used to send the read and write operation information of the first processor core to the second processor core through inter-core communication when the first processor core performs read and write operations, and the read and write operation information is used to instruct the second processor core to perform read and write operations on a target storage space in the storage space corresponding to the second processor core, and the target storage space is pre-allocated by the second processor core to the first processor core, wherein the capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core.

14. A storage space sharing device, characterized in that: Applied to the second processor core, the device comprises: A receiving module, used for receiving the read and write operation information sent by the first processor core through inter-core communication; A read-write operation module is used to perform read-write operations on a target storage space in the storage space corresponding to the second processor core based on the read-write operation information, wherein the target storage space is pre-allocated by the second processor core to the first processor core, wherein the capacity of the storage space corresponding to the second processor core is greater than the capacity of the storage space corresponding to the first processor core.

15. A chip comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 or 8 to 12 are implemented.

16. A network interface card, characterized in that: It comprises the chip as claimed in claim 15 and a plurality of interfaces, and the chip processes data or communicates externally through the interfaces.

17. A computer device, characterized in that: The network interface card comprises the network interface card as claimed in claim 16, wherein the network interface card is used for processing data or external communication.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 or 8 to 12 are implemented.

19. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 or 8 to 12 are implemented.

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