Instruction processing method, processor, electronic device and storage medium

Abstract

At least one embodiment of the invention provides an instruction processing method, a processor, an electronic device and a storage medium. The instruction processing method comprises the steps that a target record item is selected in an instruction submission queue, and a field of a target logic register number of the target record item and a field of a physical register number to be released are empty; respectively writing an object logic register number and an object physical register number mapped with the object logic register number through register renaming in a field of a target logic register number of the target record item and a field of a physical register number to be released; and submitting a target instruction corresponding to the target record item. According to the instruction processing method, simple and effective release of the physical register can be realized in a convenient vehicle building mode.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method for processing instructions, a processor, an electronic device, and a storage medium. Background Art

[0002] A processor, or a central processing unit (CPU), as the core component of a computer, is responsible for executing instructions, processing data, and controlling the operation of other hardware. Among them, physical registers play a crucial role. They are high-speed storage units used to temporarily store data and instruction operands. Each physical register is a resource inside the processor, helping to improve the operation efficiency and data access speed.

[0003] Due to the limited number of physical registers, modern processors adopt advanced technologies such as register renaming, allowing programs to use logical registers to map to these limited physical registers, thereby achieving more efficient parallel processing and a more flexible scheduling mechanism. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a method for processing instructions, including: selecting a target record item in an instruction submission queue, where the fields of the destination logical register number and the physical register number to be released of the target record item are empty; writing an object logical register number and an object physical register number mapped to the object logical register number through register renaming into the fields of the destination logical register number and the physical register number to be released of the target record item respectively; and submitting a target instruction corresponding to the target record item.

[0005] At least one embodiment of the present disclosure provides a processor, including: a renaming unit and an instruction submission unit. The instruction submission unit includes an instruction submission queue, and the renaming unit is configured to: select a target record item in the instruction submission queue, where the fields of the destination logical register number and the physical register number to be released of the target record item are empty; write an object logical register number and an object physical register number mapped to the object logical register number through register renaming into the fields of the destination logical register number and the physical register number to be released of the target record item respectively; the instruction submission unit is configured to: submit a target instruction corresponding to the target record item.

[0006] At least one embodiment of the present disclosure provides an electronic device, including: at least one processing unit; at least one memory storing instructions thereon, where when the instructions are executed by the processing unit, the at least one processing unit executes the method for processing instructions as described above.

[0007] At least one embodiment of the present disclosure provides a computer-readable storage medium storing computer-readable instructions, wherein when the computer-readable instructions are executed by a processor, the processor is caused to execute the method of the processing instructions as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0009] Figure 1 A schematic diagram showing a pipeline of a processor core is shown;

[0010] Figure 2 A flowchart showing a method of processing instructions according to at least one embodiment of the present disclosure is shown;

[0011] Figure 3 A schematic diagram showing a processor according to at least one embodiment of the present disclosure is shown;

[0012] Figure 4 A schematic diagram showing an electronic device according to at least one embodiment of the present disclosure is shown;

[0013] Figure 5 A schematic diagram showing a computer-readable storage medium according to at least one embodiment of the present disclosure is shown;

[0014] Figure 6 A schematic diagram showing another electronic device according to at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. On the contrary, it is intended to cover modifications, variations, and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of both.

[0016] To better understand the present disclosure by those skilled in the art, the present disclosure will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0017] Note that the examples to be introduced next are only specific examples and do not limit that the embodiments of the present disclosure must be the specific shapes, hardware, connection relationships, operations, numerical values, conditions, data, sequences, etc. shown and described. Those skilled in the art can use the concept of the present disclosure to construct more embodiments not mentioned in this specification by reading this specification.

[0018] The terms used in the present disclosure are those general terms currently widely used in the art in consideration of the functions of the present disclosure, but these terms may vary according to the intentions of those of ordinary skill in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but based on the meanings of the terms and the overall description of the present disclosure.

[0019] Flowcharts are used in the present disclosure to illustrate the operations performed by the systems according to the embodiments of the present disclosure. It should be understood that the operations before or below do not necessarily need to be executed precisely in order. Instead, various steps can be processed in reverse order or simultaneously as needed. At the same time, other operations can also be added to these processes, or one or several operations can be removed from these processes.

[0020] First, the abbreviations and related terms related to the processor involved in the present disclosure are defined and explained.

[0021] Logical register: A register used by programmers during programming. It is an abstraction of the registers inside the processor, allowing developers to allocate and operate variables more flexibly. Correspondingly, the logical register number is the number used to identify the logical register.

[0022] Physical register: Responsible for actual data storage and operations. They are located inside the processor and belong to the hardware level. For example, in order to implement out-of-order execution of the processor, through register renaming, the logical registers in the instructions are mapped to physical registers. Correspondingly, the physical register number is the number used to identify the physical register.

[0023] Producer: The unit responsible for generating data or instructions. For example, in the add operation r1 = r2 + r3, the add operation is the producer of r1.

[0024] Consumer: The unit that receives or processes data. For example, in the mul operation r4 = r1 * r5, the mul operation is the consumer of r1.

[0025] Physical register allocation: The process of mapping the target logical register number to the target physical register.

[0026] Physical register release: After the instruction execution is committed, the old physical register number is released and sent back to the processor, indicating that this physical register can be reallocated.

[0027] Commit queue: Also known as the instruction commit queue, it is a storage unit in the processor that stores information of uncommitted instructions. It stores the destination logical register of the current instruction, as well as the old and new physical registers corresponding to this logical register. Depending on the data format, the commit queue can include a floating-point instruction commit queue, a fixed-point instruction commit queue, etc.

[0028] Commit queue entry: An entry in the commit queue, including information such as the destination logical register of the current instruction, the new physical register, and the old physical register. One or more commit queue entries can form the commit queue.

[0029] Store-type instruction: An instruction that stores data into memory.

[0030] Zero flag bit: When the value of the logical register is zero, it can be indicated by the zero flag bit.

[0031] Commit register mapping table: A mapping table of physical registers and logical registers after the instruction execution is committed.

[0032] Speculative register mapping table: A mapping table of physical registers and logical registers after the instruction issue and renaming.

[0033] Instruction commit and execution: Instruction execution can be out-of-order, but after execution, it needs to be committed in order. Information that has not been committed is stored in the commit queue.

[0034] Processor pipeline flush operation: When the processor encounters an instruction execution exception or a branch prediction failure, it is the process of clearing uncommitted instructions. The processor pipeline flush operation generally includes operations such as reclaiming physical registers, restoring the speculative register mapping table, and reclaiming new physical registers.

[0035] Commit pointer: A pointer that points to the earliest instruction to be committed in the current commit queue.

[0036] Pipeline flush operation: When the processor encounters an exception or other situations, it is the process of clearing unexecuted instructions in the current processor and reclaiming resources such as physical registers.

[0037] Pipeline flush operation pointer: A pointer that points to the instructions to be cleared.

[0038] Clock cycle: The clock cycle of the processor execution.

[0039] It is understood that the terms defined above are only exemplary definitions in specific application scenarios for better understanding of the present disclosure, and the present disclosure is not limited thereto. For example, the terms defined above may be terms for a certain processor architecture (x86 architecture, ARM architecture, RISC-V architecture, MIPS architecture, etc.), and may be applicable to other types of processor architectures, as well as to single-threaded processors or simultaneous multi-threaded (SMT) processors.

[0040] In addition, for the convenience of description, without contradiction, the registers and register numbers in this article are not semantically distinguished and may refer to the same object. However, it can be understood that the above terms may refer to different objects, but various aspects of the present disclosure can be applied to these differences or variations with or without modification, without exceeding the protection scope of the present disclosure.

[0041] In a processor, the possible pipeline conflicts of WAW (write-after-write) and WAR (read-after-write) can be resolved through register renaming technology. This technology does not increase the number of logical registers in the instruction set, but redefines physical registers (PRs) inside the processor. The logical registers defined in the instruction set are also called logical registers (LRs). Physical registers actually exist in the processor, such as a physical register file (PRF). The processor dynamically maps logical registers to physical registers to solve the problems of WAW and WAR dependencies; for example, the processor completes the register renaming process through a register renaming mapping table and a free physical register table. When the processor performs register renaming on the logical registers used in a current instruction, both the source register and the destination register (both are logical registers, and the word "architecture" is sometimes omitted hereinafter) in this instruction need to be processed. For the source register, the processor will look up the register renaming mapping table to find the corresponding physical register number (PRN, PR No.), and for the destination register, it needs to read a physical register number from the free physical register table, establish a mapping relationship between this physical register number and the destination register, and write it into the register renaming mapping table. If the free physical register table is empty, the pipeline of the processor needs to pause and wait until an instruction retires to release the previously mapped physical register.

[0042] Due to the limited number of physical registers, although modern processors can adopt, for example, register renaming to achieve more efficient parallel processing and more flexible scheduling mechanisms, however, during specific instruction execution and data processing, available physical registers (i.e., free physical registers) need to exist. Therefore, releasing physical registers for instruction execution and data processing is crucial for the execution efficiency of the processor.

[0043] Generally, in order to release physical registers (for example, when the result of the logical register corresponding to the physical register is zero, or other physical registers that need to be released), new instructions can be used to write to the logical register, and then a new physical logical register number (prn) is allocated to achieve the release of the physical register. However, this method is not simple and effective.

[0044] For example, when the result of the logical register is zero, some flag bits (referred to as zero value flag bits) are used to indicate that the value of the logical register is zero. Subsequent instructions can know that the value of the logical register is zero when they see this zero value flag bit. When the logical register indicates that its value is zero through the zero value flag bit, the physical register corresponding to the logical register is actually no longer used, and the situation where the processor occupies the physical register for a long time will occur. In order to release the physically occupied register for a long time, generally, new instructions are relied on to write to the logical register, and then a new physical logical register number (prn) is allocated to achieve the release of the physical register.

[0045] Exemplarily, for the current logical register 1, the corresponding physical register number is 0x10, and the zero value flag bit indicates that the value of logical register 1 is zero (0). When a new instruction writes to logical register 1, a new physical register 0x20 is allocated to it, a new corresponding relationship (also called a mapping relationship) is established, and the physical register 0x10 to be released is recorded in the submission queue. Then, after the new instruction is executed, the physical register 0x10 can be released, and logical register 1 corresponds to physical register 0x20, and its value is the value in physical register 0x20.

[0046] However, the above exemplary method is not simple and effective. For example, if there are no new instructions to write to the above logical register 1 for a long time afterwards, then the physical register 0x10 cannot be released all the time, resulting in the unavailability of this physical register, thereby slowing down the program execution speed, which is particularly obvious in a multi-threaded processor.

[0047] At least one embodiment of the present invention provides a method for processing instructions, which can release physical registers in a simple and effective manner.

[0048] The processor can complete the processing of an instruction through one instruction cycle. A typical instruction cycle includes the following steps: instruction fetch, decode, execute, instruction store, and update program counter (PC), etc. These steps are repeated at an extremely high speed, enabling the processor to quickly execute a large number of instructions.

[0049] In modern processors, through pipeline technology, different stages of multiple instructions can be executed in parallel in different components simultaneously to improve instruction throughput.

[0050] Figure 1 A schematic diagram of the pipeline of a processor core is shown. The dashed line with an arrow in the figure represents the redirected instruction stream.

[0051] As Figure 1 shown, the processor core (such as a CPU core) of a single-core processor or a multi-core processor improves instruction-level parallelism through pipeline technology. Inside the processor core, there are multiple pipeline stages. For example, after the program counter from various sources is fed into the pipeline and the next program counter (PC) is selected through a multiplexer (Mux), the instruction corresponding to this program counter has to go through various stages of processing such as branch prediction, instruction fetch (also known as instruction fetching), instruction decoding, instruction dispatch and renaming, instruction execution, and instruction retirement / instruction commit.

[0052] Between each pipeline stage, waiting queues are set as needed. These queues are usually first-in-first-out (FIFO) queues. For example, after the branch prediction unit, there is a branch prediction (BP) FIFO queue to store the branch prediction results; after the instruction fetch unit, there is an instruction cache (IC) FIFO to cache the fetched instructions; after the instruction decoding unit, there is a decoding (DE) FIFO to cache the decoded instructions; after the instruction dispatch and renaming unit, there is a retirement (RT) FIFO (for example, embodied as an instruction retirement queue) to cache the instructions waiting for confirmation to end after execution. At the same time, the pipeline of the processor core also includes an instruction queue to cache the instructions waiting for the instruction execution unit to execute after instruction dispatch and renaming.

[0053] To support a high operating frequency, each pipeline stage may in turn contain multiple pipeline levels (clock cycles). Although each pipeline level performs limited operations, in this way each clock can be made the shortest, and the performance of the processor core is improved by increasing the operating frequency of the processor core. Each pipeline level can also further improve the performance of the processor core by accommodating more instructions (i.e., superscalar technology).

[0054] It can be understood that Figure 1A schematic diagram of a pipeline of a processor core is shown, in which the method for processing instructions of the present disclosure can be implemented and applied. However, the embodiments of the present disclosure are not limited thereto, and the method for processing instructions of the present disclosure can be applied to other processor cores or processors.

[0055] Figure 2 A flowchart of a method 200 for processing instructions according to at least one embodiment of the present disclosure is shown. Refer to Figure 2 The described method 200 for processing instructions and its additional aspects can be implemented in the processor, electronic device, hardware structure, software structure, or hardware structure and software structure described below. Figure 3 Refer to

[0056] Refer to Figure 2 and the method 200 for processing instructions includes steps S210 to S220.

[0057] In step S210, a target record entry is selected in the instruction submission queue. Among them, the fields of the destination logical register number and the physical register number to be released of the target record entry are empty.

[0058] In step S220, an object logical register number and an object physical register number mapped to the object logical register number through register renaming are respectively written into the fields of the destination logical register number and the physical register number to be released of the target record entry.

[0059] In step S230, the target instruction corresponding to the target record entry is submitted.

[0060] In some embodiments, after the target instruction corresponding to the target record entry is executed to release the object physical register corresponding to the object physical register number, the target instruction corresponding to the target record entry can be submitted. For example, of course, the embodiments of the present disclosure are not limited thereto, additionally or alternatively, the target instruction corresponding to the target record entry can be submitted regardless of the execution of the target instruction corresponding to the target record entry.

[0061] Since the fields of the destination logical register number and the physical register number to be released of the target record entry are empty, the physical register number to be released and the corresponding logical register number can be written, so that the physical register can be simply and effectively released by hitching a ride on the instruction corresponding to the target record entry (also referred to as a free ride instruction in this article, corresponding to the target instruction in the context).

[0062] In some embodiments, during the renaming phase, the old physical register number (old prn) of the object logical register number in the renaming mapping table can be set to the physical register number to be released, and the new physical register number (new prn) can be set to an invalid value, so as to facilitate the release of the object physical register corresponding to the object physical register number via the execution of the target instruction.

[0063] As described above, the method for processing instructions according to at least one embodiment of the present disclosure can achieve simple and effective release of physical registers in a free-riding manner.

[0064] The following describes the process of normally releasing physical registers.

[0065] The instruction submission queue includes one or more record entries, called submission queue record entries. In the instruction submission queue record entry, there is usually the following information: the destination logical register number, the physical register number to be released, the physical register number to be submitted, other information required when the instruction is submitted, etc.

[0066] Table 1 below shows an exemplary floating-point instruction submission queue according to at least one embodiment of the present disclosure. In Table 1, entryx stores the destination logical register number 1, the physical register number 0x20 to be released, the physical register number 0x30 to be submitted, and other information required when the instruction is submitted. When the entryx instruction is executed and submitted, the physical register number corresponding to the destination logical register number 1 will be updated to 0x30, the physical register number 0x20 will be released, and the status and other information will be updated according to other information required when the instruction is submitted.

[0067] Table 1 Floating-point Instruction Submission Queue

[0068]

[0069] See Figure 2 The method 200 for processing instructions described proposes to release physical registers in a free-riding manner. For example, find an entry entry in the submission queue record entry where the destination logical register number and the physical register number to be released are free, that is, the corresponding fields are empty, and write the physical register number to be released and the corresponding logical register number, and hitch a ride on the instruction corresponding to the target record entry (i.e., the free-riding instruction) to release the physical register to be released.

[0070] For example, to release a floating-point physical register, a store instruction can be used as a hitchhiking instruction. The store instruction writes to memory, and the physical register number to be released does not need to be written in the corresponding commit queue entry. Therefore, the physical register to be released can hitchhike on the store instruction. For another example, to release a floating-point physical register, a fixed-point instruction can also be used as a hitchhiking instruction. Since the content of the fixed-point instruction usually exists in the fixed-point commit queue and the floating-point commit queue is empty, this space can be utilized to release the physical register. Of course, the above specific hitchhiking instructions are only exemplary, and any suitable instruction can be used as a hitchhiking instruction as long as the fields of the destination logical register number and the physical register number to be released are free.

[0071] In other aspects, for releasing fixed-point physical registers, the store instruction and the floating-point instruction can also be used as hitchhiking instructions to release the physical registers.

[0072] For ease of description, the subsequent examples will use releasing floating-point physical registers and using store instructions and fixed-point instructions as hitchhiking instructions to describe the hitchhiking process. It can be understood that this hitchhiking process is also applicable to releasing fixed-point physical registers.

[0073] Table 2 below shows another exemplary floating-point instruction commit queue according to at least one embodiment of the present disclosure. In Table 2, the store instruction is stored in entry1. Under normal circumstances, the store instruction does not need to store information such as the destination logical register number, the physical register number to be released, and the physical register number to be committed, that is, the corresponding fields are empty. Therefore, the physical register can be released by hitchhiking on the free fields or space of the store instruction.

[0074] Similarly, entry2 in Table 2 is a fixed-point instruction. Since the fixed-point instruction is in the floating-point instruction commit queue and does not need to store any information, these fields or space can be used to release the physical register.

[0075] Table 2 Another Floating-Point Instruction Commit Queue

[0076]

[0077] For example, the method for processing instructions according to at least one embodiment of the present disclosure may further include: in response to the zero value flag bit of at least one logical register number of the processor executing the method being valid, determining at least one logical register number as the object logical register number.

[0078] As described above, the zero value flag bit of the logical register number is a valid indication that the value of the logical register is zero. At this time, the physical register corresponding to the logical register will actually no longer be used, so it is necessary to release this physical register.

[0079] Thus, the method for processing instructions according to at least one embodiment of the present disclosure can simply and effectively release the corresponding physical register for the application scenario where the zero value flag bit of the logical register number is valid.

[0080] In one example, the current logical register 1 has a corresponding physical register number of 0x10, and the zero value flag bit indicates that the value of logical register 1 is 0. Since there has been no new instruction to write to logical register 1, the physical register 0x10 has been occupied for a long time. After many similar scenarios occur, the instruction will often stop issuing due to the lack of physical registers when the instruction occurs, affecting the program execution speed.

[0081] With the method for processing instructions according to at least one embodiment of the present disclosure, in this example, although there is no new instruction to write to logical register 1, these physical registers can be released by means of a free ride instruction.

[0082] It should be noted that although one or more aspects of the present disclosure are described in the context of an application scenario where the zero value flag bit of the logical register number is valid, the embodiments of the present disclosure are not limited thereto. For example, the physical registers released by means of a free ride in the present disclosure can be other physical registers released according to the needs of the processor.

[0083] In some embodiments, in response to the zero value flag bit of at least one logical register number of the processor executing the method being valid, the operation of determining at least one logical register number as the target logical register number can be implemented by the checking circuit described below.

[0084] For example, according to the method for processing instructions according to at least one embodiment of the present disclosure, in response to the zero value flag bit of at least one logical register number of the processor executing the method being valid, determining at least one logical register number as the target logical register number may include: checking whether the zero value flag bits of all logical register numbers of the executing processor are valid; and determining the logical register numbers with valid zero value flag bits among all logical register numbers as the target logical register numbers.

[0085] Thus, the method for processing instructions according to at least one embodiment of the present disclosure can facilitate the release of physical registers in the application scenario where the zero value flag bit of the logical register number is valid.

[0086] For example, in a method of processing instructions according to at least one embodiment of the present disclosure, in response to a zero value flag bit of at least one logical register number of a processor executing the method being valid, determining at least one logical register number as an object logical register number may include: checking whether zero value flag bits of all logical register numbers of the executing processor are valid; checking whether physical register numbers mapped by register renaming of logical register numbers with valid zero value flag bits among all logical register numbers do not have a register renaming mapping relationship with other logical register numbers of the processor; and determining, as the object logical register number, a logical register number whose physical register number mapped by register renaming does not have a register renaming mapping relationship with other logical register numbers of the processor.

[0087] In some cases, when the zero flag bit of a certain logical register number is valid, but its corresponding physical register number is the same as the physical register number corresponding to another logical register number, and the zero flag bit of the other logical register number is invalid, it indicates that the physical register is still in use. In this case, it may be beneficial not to release the physical register to avoid affecting the execution of another operation.

[0088] Table 3 shows an exemplary logical register number and physical register number mapping table according to at least one embodiment of the present disclosure. In some embodiments, Table 3 may be a register renaming mapping table of the processor or derived from the register renaming mapping table of the processor.

[0089] Table 3 Logical register number and physical register number mapping table

[0090]

[0091] Referring to Table 3, there are 7 logical registers, and their logical register numbers are respectively shown as logical register 0 to logical register 7.

[0092] In one case, although the zero value flag bit of logical register 0 is valid, the physical register number of logical register 2 is also 0x11, that is, the same as the physical register number of logical register 0, and the zero value flag bit of logical register 2 is invalid, which indicates that physical register 0x11 is still in use and may not be released.

[0093] In another case, for logical registers 3 and 4, the zero value flag bits of ZH (zero high) are valid (for example, set to 1, indicating that, for example, the high 128 bits of the 256-bit value stored in the logical register are 0), but their corresponding physical registers are both 0x20. For the sake of simplifying the design, it may be selected not to release.

[0094] Of course, the embodiments of the present disclosure are not limited thereto. Aspects of at least one embodiment of the present disclosure may release any physical register that is desired to be released. For example, when the importance of releasing a physical register to execute other instructions or data processing is greater than the instructions or data processing currently being executed while occupying the physical register, the physical register may be released.

[0095] Continuing with the example of Table 3, in the above two cases, all zero-valued flag bits are valid and the physical register numbers that can be released are shown in Table 4.

[0096] Table 4 Logical register number and physical register number mapping table containing only the physical register numbers that can be released

[0097]

[0098] In Table 4, only the physical register 0x10 corresponding to logical register 1 and the physical register 0x30 corresponding to logical register 5 can be released.

[0099] For example, the method for processing instructions according to at least one embodiment of the present disclosure may further include: in response to there being a plurality of object logical register numbers, performing a priority ranking on the plurality of object logical register numbers; and writing the object logical register numbers and the object physical register numbers mapped by register renaming to the object logical register numbers in the fields of the destination logical register number and the physical register number to be released of the target record entry may include: based on the priority ranking, sequentially writing the plurality of object logical register numbers and the plurality of object physical register numbers mapped by register renaming to the plurality of object logical register numbers in the fields of the destination logical register number and the physical register number to be released of the target record entry.

[0100] For example, continuing with the example of Table 4, there may be a plurality of (e.g., 2) logical registers that need to be released, and for example, depending on the data of the free ride instruction or the limitations involved in the processor, only a limited number of (e.g., 1) logical registers can be released at a time.

[0101] In this way, the method for processing instructions according to at least one embodiment of the present disclosure can achieve effective physical register release within the limit of the number released simultaneously.

[0102] For example, in the method of processing instructions according to at least one embodiment of the present disclosure, prioritizing a plurality of object logical register numbers may include: prioritizing the plurality of object logical register numbers based on the magnitudes of the plurality of object logical register numbers, where a smaller object logical register number has a higher priority; or prioritizing the plurality of object logical register numbers based on the lengths of time that the respective logical registers corresponding to the plurality of object logical register numbers are occupied, where the object logical register number of the logical register with a longer occupied time has a higher priority.

[0103] For example, continuing with the example in Table 4, the scheme for selecting the physical registers to be released may include:

[0104] Scheme 1: Select the physical register numbers corresponding to the logical register numbers in ascending order of the logical register numbers (e.g., physical register 0x10) for release, or vice versa, select the physical register numbers corresponding to the logical register numbers in descending order (e.g., physical register 0x30) for release.

[0105] Scheme 2: Each logical register may correspond to a counter for calculating the time it occupies the current physical register, and the physical register with a longer occupied time is preferentially released.

[0106] Of course, the scheme for selecting the physical registers to be released is not limited to this. For example, physical registers within a predetermined range can be preferentially selected for release according to needs.

[0107] For example, the method of processing instructions according to at least one embodiment of the present disclosure may further include: checking whether the currently issued instruction is a store instruction and / or whether the data format of the currently issued instruction is different from the data format of the object physical register; and selecting a target record entry in the instruction submission queue, including: selecting, in the instruction submission queue, the record entry corresponding to the instruction that is a store instruction and / or has a data format different from the data format of the object physical register as the target record entry.

[0108] Since for a store instruction, i.e., the store instruction described above, there is no need to write the released physical register number in the corresponding submission queue record entry, it can be used as a free - ride instruction. Additionally, when a physical register of a certain data format needs to be released, the instruction submission queue of the same data format is used, and instructions of different data formats are empty in this instruction submission queue, so they can also be used as free - ride instructions.

[0109] In this way, the method of processing instructions according to at least one embodiment of the present disclosure can check these specific instructions to determine the existence of free - ride instructions.

[0110] In an additional aspect, it is possible to check only one type of instruction to determine the existence of a free-rider instruction. For example, it is possible to check only for the existence of a store instruction and determine it as a free-rider instruction. In this way, it is possible to facilitate the implementation of hitching a specific type of free-rider instruction to release physical registers, and it is possible to reduce the logical complexity and the power consumption of the check.

[0111] Alternatively, it is also possible to check various instructions to determine the existence of a free-rider instruction. For example, it is possible to check for the existence of both a store instruction and an instruction whose data format is different from the data format of the target physical register and determine it as a free-rider instruction. In this way, it is possible to enrich the free-rider instructions, facilitate the implementation of hitching various types of free-rider instructions to release physical registers, and improve the release efficiency.

[0112] For example, according to the method of processing instructions of at least one embodiment of the present disclosure, the data format of the currently issued instruction being different from the data format of the target physical register may include: the data format of the target physical register is a floating-point data format, and the data format of the currently issued instruction is a fixed-point data format; or the data format of the target physical register is a fixed-point data format, and the data format of the currently issued instruction is a floating-point data format.

[0113] In this way, the method of processing instructions according to at least one embodiment of the present disclosure can facilitate the check of free-rider instructions whose data format is different from the data format of the target physical register.

[0114] In some embodiments, the operation of checking for free-rider instructions, including checking whether the currently issued instruction is a store instruction and / or whether the data format of the currently issued instruction is different from the data format of the target physical register, can be implemented by the checking circuit described below.

[0115] An exemplary checking circuit is described below. The checking circuit can implement the operations of determining the target logical register number, free-rider instructions, and optionally priority sorting described above. Therefore, the checking circuit can include a target logical register number checking circuit, a target instruction checking circuit, and an optional target logical register number priority sorting circuit.

[0116] In one example, it is possible to add a checking circuit to check whether the conditions for hitching a ride can be met, such as whether the zero value flag bit of the logical register number is valid and whether there is a free-rider instruction. The checking circuit can be provided in the processor. More specifically, for example, the checking circuit can be provided between the instruction distribution and renaming, instruction queue of the processor described in Figure 1 or in the instruction distribution and renaming, instruction queue unit.

[0117] In terms of checking whether the zero flag bit of the logical register number is valid, the object logical register number checking circuit may include a first object logical register number checking circuit, the input of which may include the zero flag bits of some or all logical registers; or a second object logical register number checking circuit, the input of which may include the zero flag bits of some or all logical registers and the physical register numbers corresponding to the some or all logical registers.

[0118] In terms of checking the free ride instruction, the input of the target instruction checking circuit may include whether the currently issued instruction is a store instruction / fixed-point instruction.

[0119] In terms of priority sorting, the object logical register number priority sorting circuit may perform priority sorting on multiple object logical register numbers and determine the physical register numbers that need to be released preferentially and the corresponding physical register numbers.

[0120] In one example, taking the above object logical register number checking circuit, target instruction checking circuit, and optionally the object logical register number priority sorting circuit as a whole, the input of the checking circuit may include: the zero flag bits of all logical registers; the physical register numbers corresponding to all logical registers; and whether the currently issued instruction is a free ride instruction. The output of the checking circuit may include: a signal indicating whether a free ride is possible; and the physical register number and logical register number to be released for the free ride. For example, the physical register number that can be released for the free ride should meet the following conditions: there is a zero flag bit indicating that the value of the corresponding logical register is zero, and at the same time, the physical register to be released does not establish a correspondence with other logical registers and is only mapped to the current logical register.

[0121] For example, the method for processing instructions according to at least one embodiment of the present disclosure may be applicable to processors with any architecture and any instruction set.

[0122] Another embodiment of the present disclosure further provides a method for processing instructions, the method for processing instructions including: determining that there are object logical registers and target instructions in the processor, wherein the value of the object logical register is zero, and the fields of the logical register number and the physical register number to be released in the commit queue record item corresponding to the target instruction are empty; releasing the object physical register corresponding to the object logical register based on the target instruction.

[0123] In this way, the method for processing instructions according to at least one embodiment of the present disclosure can simply and effectively release the corresponding physical register for the application scenario where the zero flag bit of the logical register number is valid.

[0124] Additional aspects of a method for processing instructions according to another embodiment of the present disclosure are described below. It should be understood that these additional aspects are merely exemplary, and for other aspects of the method for processing instructions according to another embodiment of the present disclosure, reference may be made to or combined with other aspects described in the context, for example, refer to Figure 2 the described method for processing instructions and its additional aspects.

[0125] For example, in a method for processing instructions according to at least one embodiment of the present disclosure, releasing an object physical register corresponding to an object logical register based on a target instruction may include: writing the object logical register number and the object physical register number mapped from the object logical register number through register renaming into fields of a logical register number and a physical register number to be released, respectively, where the physical register corresponding to the object physical register number is the object physical register.

[0126] For example, in a method for processing instructions according to at least one embodiment of the present disclosure, releasing an object physical register corresponding to an object logical register based on a target instruction may include: after the target instruction is executed to release the object physical register corresponding to the object physical register number, the target instruction may be committed.

[0127] For example, in a method for processing instructions according to at least one embodiment of the present disclosure, determining that there is an object logical register in a processor may include: checking whether the zero value flag bits of all logical register numbers of the executing processor are valid; and determining the logical register corresponding to the logical register number with a valid zero value flag bit among all logical register numbers as the object logical register number, where the logical register corresponding to the object logical register number is the object logical register.

[0128] For example, in a method for processing instructions according to at least one embodiment of the present disclosure, determining that there is an object logical register in a processor may include: checking whether the zero value flag bits of all logical register numbers of the executing processor are valid; checking whether the physical register number mapped from the logical register number with a valid zero value flag bit among all logical register numbers has no register renaming mapping relationship with other logical register numbers of the processor; and determining the logical register number whose physical register number mapped through register renaming has no register renaming mapping relationship with other logical register numbers of the processor as the object logical register number, where the logical register corresponding to the object logical register number is the object logical register.

[0129] For example, in a method for processing instructions according to at least one embodiment of the present disclosure, determining the presence of object logical registers in a processor may include: in response to there being multiple object logical register numbers, performing a priority ranking on the multiple object logical register numbers; and writing the object logical register numbers and the object physical register numbers mapped to the object logical register numbers through register renaming in the fields of the logical register number and the physical register number to be released may include: based on the priority ranking, sequentially writing the multiple object logical register numbers and the multiple object physical register numbers mapped to the multiple object logical register numbers through register renaming in the fields of the destination logical register number and the physical register number to be released.

[0130] For example, in a method for processing instructions according to at least one embodiment of the present disclosure, determining the presence of a target instruction in a processor may include: checking whether the currently issued instruction is a store instruction and / or whether the data format of the currently issued instruction is different from the data format of the object physical register; and determining an instruction that is a store instruction and / or has a data format different from the data format of the object physical register as the target instruction.

[0131] For example, in a method for processing instructions according to at least one embodiment of the present disclosure, in response to the data format of the object physical register being a floating-point data format, the data format of the target instruction is a fixed-point data format or a store instruction; or in response to the data format of the object physical register being a fixed-point data format, the data format of the target instruction is a floating-point data format or a store instruction.

[0132] In some embodiments, the above determination of the presence of object logical registers and target instructions in the processor may be implemented by the checking circuit described in the context.

[0133] Corresponding to the method for processing instructions according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure further provides a processor.

[0134] Figure 3 A schematic diagram of a processor 300 according to at least one embodiment of the present disclosure is shown.

[0135] See Figure 3 , the processor 300 may include a renaming unit 305 and an instruction commit unit 310. Among them, the instruction commit unit 310 includes an instruction commit queue. Exemplarily, the renaming unit 305 and the instruction commit unit 310 may be distributed and embodied in the instruction distribution and renaming unit and the instruction commit unit described in See Figure 1 description.

[0136] In some embodiments, the processor 300 may further include other components in the pipeline, such as a branch prediction unit, an instruction fetch unit, an instruction decoding unit, an instruction distribution unit, an instruction execution unit, etc. In one example, the branch prediction unit, the instruction fetch unit, the instruction decoding unit, the instruction distribution unit, and the instruction execution unit may be the same as or similar to the corresponding units described in Figure 1 The description of the corresponding unit is the same or similar.

[0137] The rename unit 305 is configured to: select a target record entry in the instruction commit queue, where the fields of the destination logical register number and the physical register number to be released of the target record entry are empty; write the object logical register number and the object physical register number mapped to the object logical register number through register renaming into the fields of the destination logical register number and the physical register number to be released of the target record entry respectively.

[0138] The instruction commit unit 310 is configured to: commit the target instruction corresponding to the target record entry.

[0139] In some embodiments, the rename unit 305 may write the target instruction into the scheduling queue, and the scheduling queue confirms the execution time of the target instruction. After the target instruction is executed, when the pipeline scheduling unit receives the execution completion signal, it issues the instruction commit valid signal in sequence according to the instruction issue order to indicate that the corresponding item in the instruction commit queue needs to be committed. The commit unit may read out the corresponding item in the instruction commit queue after receiving the commit valid signal to complete the release of the corresponding physical register.

[0140] As described above, the processor according to at least one embodiment of the present disclosure can achieve a simple and effective release of physical registers in a free-riding manner.

[0141] The processor 300 may be an improvement of a processor based on any architecture and any instruction set. The processor 300 is, for example, an SMT processor. The maximum number of threads supported by the SMT processor may be, for example, 2, 4, 8, etc., and it may be a single-core or multi-core processor. For example, the processor may adopt microarchitectures such as X86, ARM, RISC-V, etc., and may include one or more levels of caches. The embodiments of the present disclosure do not limit this.

[0142] For example, the processor according to at least one embodiment of the present disclosure may further include an object logical register number checking circuit, and the object logical register number checking circuit may be configured to: in response to the zero value flag bit of at least one logical register number of the processor being valid, determine at least one logical register number as the object logical register number.

[0143] In some embodiments, the object logical register number checking circuit may be disposed in the rename unit, between the rename unit and the instruction queue, or at other suitable positions. For example, the object logical register number checking circuit may determine whether the zero value flag bit of the logical register number is valid based on the rename mapping table.

[0144] For example, in a processor according to at least one embodiment of the present disclosure, the object logical register number checking circuit may include a first object logical register number checking circuit, and the first object logical register number checking circuit may be configured to: check whether the zero value flag bits of all logical register numbers of the executing processor are valid; and determine the logical register numbers with valid zero value flag bits among all logical register numbers as object logical register numbers.

[0145] For example, in a processor according to at least one embodiment of the present disclosure, the object logical register number checking circuit may include a second object logical register number checking circuit, and the second object logical register number checking circuit may be configured to: check whether the zero value flag bits of all logical register numbers of the executing processor are valid; check whether the physical register numbers obtained by register renaming of the logical register numbers with valid zero value flag bits among all logical register numbers have no register renaming mapping relationship with other logical register numbers of the processor; and determine the logical register numbers whose physical register numbers obtained by register renaming have no register renaming mapping relationship with other logical register numbers of the processor as object logical register numbers.

[0146] For example, a processor according to at least one embodiment of the present disclosure may further include an object logical register number priority sorting circuit, and the object logical register number priority sorting circuit may be configured to: in response to there being multiple object logical register numbers, perform priority sorting on the multiple object logical register numbers; and the instruction submission unit may also be configured to: based on the priority sorting, sequentially write the multiple object logical register numbers and the multiple object physical register numbers mapped by register renaming of the multiple object logical register numbers into the fields of the destination logical register number and the physical register number to be released in the target record entry, respectively.

[0147] In some embodiments, the object logical register number priority sorting circuit may be disposed in the rename unit, between the rename unit and the instruction queue, or at other suitable positions. For example, the object logical register number priority sorting circuit may perform priority sorting on multiple object logical register numbers after determining that there are multiple object logical register numbers.

[0148] For example, a processor according to at least one embodiment of the present disclosure may further include a target instruction checking circuit configured to: check whether the currently issued instruction is a store instruction and / or whether the data format of the currently issued instruction is different from the data format of the target physical register; and the instruction submission unit may also be configured to: select, in the instruction submission queue, the record item corresponding to the instruction that is a store instruction and / or has a data format different from the data format of the target physical register as the target record item.

[0149] In some embodiments, the target instruction checking circuit may be disposed in the rename unit, between the rename unit and the instruction queue, or at other suitable positions to implement the above checking operations.

[0150] The additional aspects of the processor 300 according to at least one embodiment of the present disclosure may correspond to the additional aspects of the method for processing instructions according to at least one embodiment of the present disclosure. Therefore, the technical effects of the additional aspects of the method for processing instructions according to at least one embodiment of the present disclosure can also be mapped to the additional aspects of the processor 300 according to at least one embodiment of the present disclosure, and will not be elaborated herein.

[0151] Figure 4 A schematic diagram of an electronic device 400 according to at least one embodiment of the present disclosure is shown.

[0152] As Figure 4 shown, the electronic device 400 includes at least one processing unit 420 and a memory 410. The memory 410 stores computer-readable instructions and is communicatively connected to the processing unit 420. For example, the electronic device may be embodied as a processor. The processing unit 420 executes the computer-readable instructions stored in the memory 410 to implement the method for processing instructions according to at least one embodiment of the present disclosure and its additional aspects.

[0153] For example, the memory 410 and the processing unit 420 may communicate directly or indirectly with each other. For example, in some examples, as Figure 4 shown, the electronic device 400 may further include a system bus 430, and the memory 410 and the processing unit 420 may communicate with each other through the system bus 430. For example, the processing unit 420 may access the memory 410 through the system bus 430. For example, in other examples, components such as the memory 410 and the processing unit 420 may communicate through a network-on-chip (NOC) connection.

[0154] For example, the processing unit 420 may control other components in the electronic device 400 to perform desired functions. The processing unit 420 may be a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), a graphics processing unit (GPU), or other devices with data processing capabilities and / or program execution capabilities. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0155] For example, the memory 410 may include any combination of one or more computer program products. The computer program products may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0156] For example, one or more computer-readable instructions may be stored on the memory 410, and the processing unit 420 may run the computer-readable instructions to implement various functions. Various application programs and various data may also be stored in the computer-readable storage medium, such as instruction processing code and various data used and / or generated by the application programs, etc.

[0157] For example, when some computer instructions stored in the memory 410 are executed by the processing unit 420, one or more steps in the method of processing instructions described above may be executed.

[0158] For example, as Figure 4 shown, the electronic device 400 may further include an input interface 440 that allows external devices to communicate with the electronic device 400. For example, the input interface 440 may be used to receive instructions from external computer devices, from users, etc. The electronic device 400 may also include an output interface 450 that interconnects the electronic device 400 and one or more external devices. For example, the electronic device 400 may communicate through the output interface 450, etc.

[0159] It should be noted that the electronic device 400 according to at least one embodiment of the present disclosure is exemplary, not restrictive. According to actual application needs, the electronic device 400 may further include other conventional components or structures. For example, to implement the necessary functions of the electronic device, those skilled in the art may set other conventional components or structures according to specific application scenarios, and the embodiments of the present disclosure do not limit this.

[0160] At least one embodiment of the present disclosure also provides a computer-readable storage medium. Figure 5 FIG. shows a schematic diagram of a computer-readable storage medium 500 according to at least one embodiment of the present disclosure.

[0161] For example, as Figure 5 shown, the computer-readable storage medium 500 stores computer-readable instructions 510, which, when executed by a computer (including a processor), can implement the method for processing instructions and its additional aspects according to at least one embodiment of the present disclosure.

[0162] For example, one or more computer-readable instructions may be stored on the computer-readable storage medium 500. Some of the computer-readable instructions stored on the computer-readable storage medium 500 may be instructions for implementing one or more steps in the method for processing instructions described above.

[0163] For example, the computer-readable storage medium may include a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a compact disc read-only memory (CD-ROM), a flash memory, or any combination of the above computer-readable storage media, and may also be other applicable storage media. For example, the computer-readable storage medium 500 may include the memory 410 in the above-described electronic device 400.

[0164] At least some embodiments of the present disclosure also provide an electronic device. Figure 6 FIG. shows a schematic diagram of another electronic device 600 according to at least one embodiment of the present disclosure.

[0165] The electronic device according to at least one embodiment of the present disclosure may be implemented as, but not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (such as in-vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc.

[0166] Figure 6 The shown electronic device 600 is merely an example and should not impose any limitation on the functions and usage scope of the embodiments of the present disclosure.

[0167] For example, as Figure 6As shown, in some examples, the electronic device 600 includes a processor 601, which may include the processor of any of the above embodiments (e.g., an SMT processor), and which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage device 608 into a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the computer system are also stored. The processor 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0168] For example, the following components may be connected to the I / O interface 605: an input device 606 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 607 including, such as a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 608 including, for example, a magnetic tape, a hard disk, etc.; a communication device 609 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 609 may allow the electronic device 600 to communicate with other devices wirelessly or wiredly to exchange data and perform communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 610 as needed so that a computer program read from it can be installed into the storage device 608 as needed. Although Figure 6 an electronic device 600 including various devices is shown, it should be understood that it is not required to implement or include all the shown devices. More or fewer devices may be alternatively implemented or included.

[0169] For example, the electronic device 600 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 609 may communicate with the network and other devices through wireless communication. The network may be, for example, the Internet, an intranet, and / or a wireless network such as a cellular phone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). The wireless communication may use any one of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on the IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), WiMAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0170] Regarding the present disclosure, in addition to the above exemplary description, the following points need to be noted:

[0171] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0172] (2) Without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments.

[0173] The above is only an exemplary implementation manner of the present disclosure, and is not used to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A method for processing an instruction, comprising: Selecting a target record item in the instruction submission queue, wherein a field of a destination logical register number and a field of a physical register number to be released of the target record item are empty; Writing the object logical register number and the object physical register number mapped to the object logical register number through register renaming into the field of the destination logical register number and the field of the physical register number to be released of the target record item respectively; and Submit the target instruction corresponding to the target record item.

2. The method according to claim 1, further comprising: In response to a zero-value flag bit of at least one logical register number of a processor executing the method being valid, the at least one logical register number is determined as the target logical register number.

3. The method according to claim 2, wherein: In response to the zero value flag bit of at least one logical register number of the processor executing the method being valid, determining the at least one logical register number as the object logical register number comprises: Checking whether the zero-valued flag bits of all logical register numbers executing the processor are valid; and The logical register number with a valid zero-value flag bit among all the logical register numbers is determined as the object logical register number.

4. The method according to claim 2, wherein: In response to the zero value flag bit of at least one logical register number of the processor executing the method being valid, determining the at least one logical register number as the object logical register number comprises: Check whether the zero value flag bits of all logical register numbers executing the processor are valid; Check whether the physical register number to which the zero-value flag bit of all the logical register numbers is mapped through register renaming has no register renaming mapping relationship with other logical register numbers of the processor; and A logical register number whose physical register number mapped through register renaming does not have a register renaming mapping relationship with other logical register numbers of the processor is determined as the object logical register number.

5. The method according to claim 1, further comprising: In response to the object logical register number being multiple, prioritizing the multiple object logical register numbers; and Writing the object logical register number and the object physical register number mapped to the object logical register number through register renaming into the field of the destination logical register number of the target record item and the field of the physical register number to be released comprises: Based on the priority sorting, in the field of the destination logical register number and the field of the physical register number to be released of the target record item, a plurality of the object logical register numbers and a plurality of object physical register numbers mapped to the plurality of the object logical register numbers through register renaming are written in sequence.

6. The method according to claim 5, wherein: The prioritizing of the plurality of object logical register numbers comprises: Prioritizing the plurality of target logical register numbers based on their sizes, wherein smaller or larger target logical register numbers have higher priorities; or The plurality of object logical register numbers are prioritized based on the length of time that the logical registers corresponding to the plurality of object logical register numbers are occupied, wherein the object logical register number of the logical register that has been occupied for a longer time has a higher priority.

7. The method according to any one of claims 1 to 6, further comprising: Checking whether the currently issued instruction is a storage instruction and / or whether the data format of the currently issued instruction is different from the data format of the object physical register; and The step of selecting a target record item in the instruction submission queue includes: In the instruction submission queue, a record item corresponding to a storage instruction and / or an instruction whose data format is different from the data format of the object physical register is selected as the target record item.

8. The method according to claim 7, wherein: The data format of the currently issued instruction is different from the data format of the target physical register, including: The data format of the target physical register is a floating-point data format, and the data format of the currently issued instruction is a fixed-point data format; or The data format of the target physical register is a fixed-point data format, and the data format of the currently issued instruction is a floating-point data format.

9. A processor, comprising: a renaming unit and an instruction submitting unit, the instruction submitting unit including an instruction submitting queue, and The renaming unit is configured to: Selecting a target record item in the instruction submission queue, wherein a field of a destination logical register number and a field of a physical register number to be released of the target record item are empty; Writing the object logical register number and the object physical register number mapped to the object logical register number through register renaming into the field of the destination logical register number and the field of the physical register number to be released of the target record entry respectively; and The instruction submitting unit is configured to: Submit the target instruction corresponding to the target record item.

10. The processor of claim 9, further comprising: The object logical register number checking circuit is configured to: in response to a zero value flag bit of at least one logical register number of the processor being valid, determine the at least one logical register number as the object logical register number.

11. The processor of claim 10, wherein: The object logic register number checking circuit comprises: The first object logic register number check circuit is configured as follows: Checking whether the zero-valued flag bits of all logical register numbers executing the processor are valid; and The logical register number with a valid zero-value flag bit among all the logical register numbers is determined as the object logical register number.

12. The processor of claim 10, wherein: The object logic register number checking circuit comprises: The second object logic register number check circuit is configured as follows: Check whether the zero value flag bits of all logical register numbers executing the processor are valid; Check whether the physical register number to which the zero-value flag bit of all the logical register numbers is mapped through register renaming has no register renaming mapping relationship with other logical register numbers of the processor; and A logical register number whose physical register number mapped through register renaming does not have a register renaming mapping relationship with other logical register numbers of the processor is determined as the object logical register number.

13. The processor of claim 9, further comprising: The object logic register number prioritization circuit is configured as: In response to the plurality of target logical register numbers being present, priority sorting is performed on the plurality of target logical register numbers; and The instruction submitting unit is further configured to: Based on the priority sorting, in the field of the destination logical register number and the field of the physical register number to be released of the target record item, a plurality of the object logical register numbers and a plurality of object physical register numbers mapped to the plurality of the object logical register numbers through register renaming are written in sequence.

14. The processor according to any one of claims 9 to 13, further comprising: The target instruction checking circuit is configured as follows: Checking whether the currently issued instruction is a storage instruction and / or the data format of the currently issued instruction is different from the data format of the target physical register; and The instruction submitting unit is further configured to: In the instruction submission queue, a record item corresponding to a storage instruction and / or an instruction whose data format is different from the data format of the object physical register is selected as the target record item.

15. An electronic device comprising: at least one processing unit; at least one memory having instructions stored therein, When the instruction is executed by the processing unit, the at least one processing unit executes the method as claimed in any one of claims 1 to 8.

16. A computer-readable storage medium having computer-readable instructions stored thereon, in, When the computer readable instructions are executed by a processor, the processor is caused to perform the method according to any one of claims 1 to 8.

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