Address mapping rule determination method, memory access method and related equipment

Abstract

The embodiment of the invention provides an address mapping rule determination method, a memory access method and related equipment, and the address mapping rule determination method comprises the steps: determining historical information corresponding to each access request during the operation period of a sample object; on the basis of the historical information, a flipping probability coefficient of each address bit in the address to be accessed is calculated, the flipping probability coefficient is determined on the basis of the flipping probability of each address bit in the address to be accessed in an effective time period, and the duration of the effective time period is determined on the basis of the longest activation duration of a memory line; determining an address mapping rule of a to-be-accessed address based on the overturning probability coefficient; wherein the determined address mapping rule at least comprises the step of mapping a group of address bits with the lowest flipping probability coefficient into a row address of the memory address. The scheme is used for improving the access efficiency of the memory system.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technologies, and in particular, to a method for determining an address mapping rule, a memory access method, and related devices. Background Art

[0002] The access efficiency of the memory system is a main factor affecting the computing performance of the computing system. In scenarios with high data throughput, the impact of access efficiency on the performance of the computing system is even more significant. With the rapid development and wide application of artificial intelligence and intelligent driving, high-bandwidth memories such as HBM (High Bandwidth Memory) and GDDR (Graphics Double Data Rate DRAM) are widely used in high-performance computing systems. How to improve the access efficiency of the memory system has become a research focus in this field. Summary of the Invention

[0003] In view of this, the embodiments of the present application provide a method for determining an address mapping rule, a memory access method, and related devices to improve the access efficiency of the memory system.

[0004] To achieve the above object, the embodiments of the present application provide the following technical solutions.

[0005] In a first aspect, the embodiments of the present application provide a method for determining an address mapping rule, including:

[0006] Determine the historical information corresponding to each access request during the operation of the sample object, where the historical information includes the to-be-accessed address corresponding to the access request and the time information; the to-be-accessed address includes multiple address bits, and the time information is used to indicate the interval duration between adjacent access requests for performing access operations;

[0007] Based on the historical information, calculate the flip probability coefficient of each address bit in the to-be-accessed address, where the flip probability coefficient is determined based on the flip probability of each address bit in the to-be-accessed address within the effective period, and the duration of the effective period is determined based on the longest activation duration of the memory row;

[0008] Based on the flip probability coefficient, determine the address mapping rule of the to-be-accessed address; where the determined address mapping rule at least includes: mapping the group of address bits with the lowest flip probability coefficient to the row address of the memory address.

[0009] Optionally, in the step of determining the address mapping rule of the to-be-accessed address based on the flip probability coefficient, the determined address mapping rule at least further includes: in the order of the flip probability coefficient from high to low, the mapping order of the address bits is at least the bank group address, the bank address, and the row address.

[0010] Optionally, calculating the flip probability coefficient of each address bit in the to-be-accessed address based on the historical information includes:

[0011] Based on the historical information, determining the flip probability of each address bit in the to-be-accessed address corresponding to each access request within the valid period;

[0012] Based on the flip probability, calculating the weighted average value of the flip probability corresponding to each address bit; the weighted average value of the flip probability is used to indicate the weighted average value of the flip probability of the corresponding address bit in each access request during the running of the sample object under the preset weight value; the preset weight value is used to indicate the density of the access requests executed within the valid period of the corresponding access request;

[0013] Wherein, using the weighted average value of the flip probability as the flip probability coefficient corresponding to each address bit in the to-be-accessed address within the valid period.

[0014] Optionally, for an access request, the step of determining the historical information corresponding to each access request during the running of the sample object is specifically:

[0015] Obtaining the historical information of each access request in the historical instruction queue; wherein, the historical instruction queue is used to store the access requests executed within the valid period;

[0016] The step of determining the flip probability of each address bit in the to-be-accessed address corresponding to each access request within the valid period based on the historical information is specifically: using the access request stored at the tail of the historical instruction queue as the to-be-calculated access request, using the other access requests in the historical instruction queue as associated access requests, comparing the access addresses of the to-be-calculated access request and the associated access requests, and determining the flip probability of each address bit.

[0017] Optionally, calculating the weighted average value of the flip probability corresponding to each address bit based on the flip probability includes:

[0018] Obtaining the flip probability of each address bit in each access request and the corresponding access request;

[0019] Assigning the preset weight value corresponding to each access request as the number of associated access requests corresponding to this access request;

[0020] Based on the flip probability and the preset weight value, calculating the weighted average value of the flip probability corresponding to each address bit.

[0021] Optionally, after the step of determining the flip probability of each address bit in the to-be-accessed address corresponding to each access request within the valid period based on the historical information and before the step of calculating the weighted average value of the flip probability corresponding to each address bit based on the flip probability, it further includes:

[0022] At a preset node, determine whether the sample object has finished execution;

[0023] If so, execute the step of calculating the weighted mean of the inversion probabilities corresponding to each address bit based on the inversion probability; if not, continue to execute the memory access process and execute the step of obtaining the historical information corresponding to each access request during the operation of the sample object, and determining the inversion probability of each address bit of the to-be-accessed address corresponding to each access request within the effective period based on the historical information;

[0024] Wherein, the preset node is that a preset number of access requests have been executed, or the preset node is a preset moment.

[0025] Optionally, in the step of determining the historical information corresponding to each access request during the operation of the sample object, before obtaining the historical information of each access request in the historical instruction queue, it further includes:

[0026] When storing an access request in the instruction queue, synchronously store the access request in the historical instruction queue, and record the time information corresponding to the access request into the historical information of the access request; according to the time information, calculate the time distance between each access request in the historical instruction queue and the access request to be calculated, and delete the access requests in the historical instruction queue whose time distance is greater than the effective period.

[0027] Optionally, the time information is the time corresponding to when the access request is parsed to obtain the address information of the storage unit to be accessed and stored in the instruction queue;

[0028] Wherein, the step of storing the access request in the historical instruction queue and recording the time information corresponding to the access request into the historical information of the access request is specifically that when the access request is parsed to obtain the address information of the storage unit to be accessed and stored in the instruction queue, a timestamp is provided for the access request, and the timestamp is recorded into the corresponding access request in the historical request queue.

[0029] Optionally, the step of determining the inversion probability of each address bit of the to-be-accessed address corresponding to each access request within the effective period based on the historical information includes:

[0030] Perform a sliding window operation on the access requests during the operation period of the sample object based on the duration of the effective period; wherein, one access request corresponds to one window to be calculated, and the access request is located within the window to be calculated corresponding to it;

[0031] Based on the historical information, calculate the inversion probability corresponding to each address bit in the to-be-accessed address for each access request within each window to be calculated one by one.

[0032] Optionally, after executing an access request, using the access request as the access request to be calculated, trigger the step of calculating the flip probability coefficients of each address bit in the to-be-accessed address based on the historical information.

[0033] Optionally, the address mapping rule includes: when the row address is a bits, the group of address bits with the lowest flip probability coefficient is the lowest a address bits; when the bank group address is b bits, the group of address bits with a flip probability coefficient higher than the row address is the highest b address bits, where a and b are integers greater than or equal to 1.

[0034] Optionally, in the step of determining the address mapping rule of the to-be-accessed address based on the flip probability coefficient, the determined address mapping rule at least further includes: in the order of the flip probability coefficient from high to low, the mapping order of the address bits is at least the bank group address, column address, bank address, and row address;

[0035] Or,

[0036] Determining the address mapping rule of the to-be-accessed address based on the flip probability coefficient includes: dividing the column address into a first column address segment and a second column address segment; in the order of the flip probability coefficient from high to low, determining that the mapping order of the address bits is at least the bank group address, the first column address segment, the bank address, the second column address segment, and the row address.

[0037] Optionally, in the step of determining the address mapping rule of the to-be-accessed address based on the flip probability coefficient, the determined address mapping rule at least further includes: in the order of the flip probability coefficient from high to low, the mapping order of the address bits is at least the pseudo-channel address segment, bank group address, column address, stack identification address segment, bank address, and row address.

[0038] In a second aspect, an embodiment of the present application further provides a memory access method, including:

[0039] Obtaining an access request, where the access request includes a to-be-accessed address;

[0040] Based on the address mapping rule, parsing the address information of the to-be-accessed storage unit from the to-be-accessed address; where the address mapping rule is determined based on the address mapping rule determination method described in the first aspect;

[0041] Performing the access of the access request based on the address mapping rule of the storage unit.

[0042] Optionally, before obtaining the access request, further includes:

[0043] Initialize the address mapping rule determined by the address mapping rule determination method described in the first aspect to the system.

[0044] Optionally, the performing the access of the access request includes:

[0045] Store the address information of the storage unit obtained by parsing into the instruction queue in the access order;

[0046] Arbitrate the access requests in the instruction queue according to the memory state information, and select the instruction of the access request whose timing constraint is satisfied and send it to the memory so that the memory performs the corresponding access operation;

[0047] Update the memory state information until the memory completes the access operation of the corresponding instruction.

[0048] In a third aspect, an embodiment of the present application further provides a memory controller, including:

[0049] An address decoding logic, an instruction queue, and an instruction arbitration logic connected in sequence, and a historical information determination logic connected to the instruction queue and a flip probability coefficient determination logic connected to the historical information determination logic;

[0050] Wherein, the historical information determination logic is used to determine the historical information corresponding to each access request during the operation of the sample object; the flip probability coefficient determination logic is used to statistically determine the flip probability coefficient corresponding to each address bit in the to-be-accessed address during the effective period based on the historical information, so as to determine the address mapping rule of the to-be-accessed address based on the flip probability coefficient;

[0051] The historical information includes the to-be-accessed address corresponding to the access request and the time information; the to-be-accessed address includes a plurality of address bits, and the time information is used to indicate the order of performing the access operation of adjacent access requests and the execution interval duration; the duration of the effective period is determined based on the longest activation duration of the memory row; wherein, the determined address mapping rule at least includes: mapping a group of address bits with the lowest flip probability coefficient to the row address of the memory address.

[0052] Optionally, the historical information determination logic includes a historical request queue and a timing module, wherein the historical request queue is used to record the historical information corresponding to the access request during the effective period, and the timing module is used to provide time information for the access request.

[0053] Optionally, the address decoding logic is configured to parse the address information of the storage unit to be accessed from the address to be accessed in the access request; the instruction queue is configured to sequentially store the address information corresponding to the access request; the instruction arbitration logic is configured to arbitrate the access requests in the instruction queue, and select the instruction whose timing constraint is satisfied and send it to the memory, so that the memory performs corresponding access operations.

[0054] In a fourth aspect, an embodiment of the present application further provides a computing device, including:

[0055] The memory controller described in the third aspect;

[0056] The rule determination logic connected to the memory controller is configured to determine the address mapping rule of the address to be accessed based on the flip probability coefficient; wherein, the determined address mapping rule at least includes: mapping a group of address bits with the lowest flip probability coefficient to the row address of the memory address.

[0057] Optionally, the computing device further includes: a register management unit configured to obtain and store the flip probability coefficient corresponding to each address bit during the valid period;

[0058] The rule determination logic is configured to determine the address mapping rule based on the flip probability coefficient stored by the register management unit.

[0059] In a fifth aspect, an embodiment of the present application further provides a computer program, including one or more computer-executable instructions, and when the one or more computer-executable instructions are executed, they implement the address mapping rule determination method described in the first aspect, or implement the memory access method described in the second aspect.

[0060] An embodiment of the present application provides an address mapping rule determination method, a memory access method and related devices. The address mapping rule determination method includes: determining the historical information corresponding to each access request during the operation of the sample object, where the historical information includes the address to be accessed and the time information corresponding to the access request; the address to be accessed includes multiple address bits, and the time information is used to indicate the interval duration between adjacent access requests for performing access operations; based on the historical information, calculating the flip probability coefficient of each address bit in the address to be accessed, where the flip probability coefficient is determined based on the flip probability of each address bit in the address to be accessed during the valid period, and the duration of the valid period is determined based on the longest activation duration of the memory row; based on the flip probability coefficient, determining the address mapping rule of the address to be accessed; wherein, the determined address mapping rule at least includes: mapping a group of address bits with the lowest flip probability coefficient to the row address of the memory address.

[0061] It can be seen that in the method for determining the address mapping rule provided by the embodiments of the present application, during the running of the sample object, based on historical information, the flip probability coefficient corresponding to each address bit in the to-be-accessed address within the effective period determined based on the longest activation duration of the memory row is calculated, and then the address mapping rule of the to-be-accessed address is determined, so that at least a group of address bits with the lowest flip probability coefficient can be mapped to the row address of the memory address. Thus, at the address mapping rule level, the address bit with the lowest change probability is selected as the row address. Furthermore, in the scenario corresponding to the sample object, when the address mapping rule determined by the address mapping rule determination method is adopted, the change probability of the row address in the corresponding memory access process is reduced, the memory access process tends to access the same row of the memory, and accessing different rows of the memory is avoided, that is, the probability of page hit is increased, the probability of page conflict is reduced, and the memory access efficiency is improved.

[0062] Further, in a further optional example, in the order from the highest to the lowest flip probability coefficient, the address bits are sequentially mapped to the bank group address, the bank address, and the row address of the memory. Thus, in the address mapping rule of the to-be-accessed address, a group of address bits with a higher flip probability coefficient is mapped to the bank group address of the memory address, so as to select the address bit with a higher change probability as the bank group address at the address mapping rule level. Based on the relatively independent nature of the memory bank groups and the characteristic that the switching time between bank groups is the shortest, when running the scenario corresponding to the sample object and adopting the address mapping rule determined by the address mapping rule determination method, the switching time between memory access requests is reduced, and the memory access efficiency is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0064] Figure 1 It is a schematic diagram of an optional physical structure of a memory.

[0065] Figure 2 It is an optional flowchart of a method for determining an address mapping rule provided by an embodiment of the present application.

[0066] Figure 3 It is another optional flowchart of a method for determining an address mapping rule provided by an embodiment of the present application.

[0067] Figure 4 It is a schematic diagram of a calculation method of a flip probability provided by an embodiment of the present application.

[0068] Figure 5 This is a further schematic diagram of the calculation process for the examples provided in the embodiments of the present application. Figure 4 in the figure.

[0069] Figure 6 This is another optional flowchart of a method for determining an address mapping rule provided in the embodiments of the present application.

[0070] Figure 7 This is an optional flowchart of a memory access method provided in the embodiments of the present application.

[0071] Figure 8 This is another optional flowchart of a memory access method provided in the embodiments of the present application.

[0072] Figure 9 This is an optional structural diagram of a memory controller provided in the embodiments of the present application.

[0073] Figure 10 This is an optional structural schematic diagram of a computing device provided in the embodiments of the present application. Detailed implementation manners

[0074] Some embodiments of the present disclosure are described as processing flows. Although the individual operation steps of the flow may be labeled with sequential step numbers, the operation steps can be implemented in parallel, concurrently, or simultaneously.

[0075] In the embodiments of the present disclosure, terms such as "first" and "second" may be used to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.

[0076] In the embodiments of the present disclosure, the term "and / or" may be used. "And / or" includes any and all combinations of one or more of the listed associated features. It should be understood that when describing the connection relationship or communication relationship between two components, unless it is explicitly specified that the two components are directly connected or directly communicate, otherwise, the connection or communication between the two components can be understood as direct connection or communication, or can also be understood as indirect connection or communication through an intermediate component.

[0077] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0078] An optional physical structure of the memory can be referred to Figure 1 as shown in Figure 1It is a schematic diagram of an optional physical structure of a memory. The memory can be composed of multiple bank groups, where each bank group is composed of multiple banks, and a bank is a memory array including memory cells (cells) with multiple rows and multiple columns. Figure 1 Taking the memory as DRAM as an example, the bank group can be, for example, a Bank Group (labeled as BG in the figure), the bank can be, for example, a Bank, the row can be a Row, and the column can be a Column (labeled as Col in the figure). Among them, Figure 1 in which DQ is the Data signal line and CA is the Command / Address signal line.

[0079] Among them, the memory cells corresponding in the memory array can be confirmed based on the indication of the memory address. In a specific example, the memory address can include a bank group address segment (also called a bank group address), a bank address segment (also called a bank address), a row address segment (also called a row address), and a column address segment (also called a column address), so that the specific memory cells in the memory can be determined based on the addressing of the memory address. It should be noted that the address segments in the memory address can be data segments composed of data on a continuous address bit in the memory address, or data segments composed of data on multiple discontinuous address bits in the memory address.

[0080] In a specific example, after receiving an access request sent by an upstream device, the memory controller can, based on a preset address mapping mode (i.e., an address mapping rule), resolve the address information required to access the memory cells from the to-be-accessed address (i.e., the memory address) of the access request. For example, the DRAM memory can correspondingly include a bank group address segment, a bank address segment, a row address segment, a column address segment, etc., and execute the access of the access request based on the address information of the memory cells.

[0081] Specifically, when performing an access operation on a memory cell, it is necessary to first activate the row where the memory cell is located, and then perform an access operation on the column where the memory cell is located. In a specific implementation, the scenario where no row in the to-be-accessed bank is in an active state is called a page miss.

[0082] However, since only one row in the same bank is allowed to be activated at the same time, direct access to different rows of the same memory bank cannot be achieved for accessing the memory cells. When it is necessary to access different rows of the same memory bank, the previously operated row needs to be precharged, the activated row is closed and after waiting for a certain time, the row to be operated is then activated. Obviously, this situation causes a relatively large delay in the corresponding access operation, and the corresponding access efficiency will also decrease. In a specific implementation, the scenario where other rows in the memory bank to be accessed have been activated is called a page conflict.

[0083] In a relatively different scenario, when accessing the same row of the same memory bank, the corresponding column in the activated row can be directly accessed. Obviously, this situation can quickly implement the corresponding access operation, and the corresponding access efficiency is higher than page miss and page conflict. In a specific implementation, the scenario where the row of the memory bank to be accessed has been activated by a previous access is called a page hit.

[0084] Obviously, in the memory access process, the proportions of page conflict and page hit directly determine the level of memory access efficiency.

[0085] To address this problem, the inventor believes that for a preset scenario, the accessed addresses can be statistically analyzed, and the address bits with a relatively low flip probability (i.e., change probability) in the accessed addresses can be selected as the row addresses, so as to reduce the change probability of the row addresses from the perspective of the address mapping rule. That is to say, to maximize the access process to access the same row of the memory, thereby increasing the probability of page hit and reducing the probability of page conflict.

[0086] Furthermore, based on the characteristic that the memory banks in the memory are relatively independent of each other and the switching time between memory banks is minimized, the address bits with a relatively high flip probability coefficient (i.e., change probability) in the accessed addresses can also be selected as the memory bank addresses, so as to increase the change probability of the memory bank addresses from the perspective of the address mapping rule, reduce the switching time between memory access requests, and improve the memory access efficiency.

[0087] In view of this, embodiments of the present application provide an address mapping rule determination method, a memory access method, and related devices. The address mapping rule determination method includes: determining historical information corresponding to each access request during the running of a sample object, where the historical information includes the to-be-accessed address corresponding to the access request and time information; the to-be-accessed address includes multiple address bits, and the time information is used to indicate the interval duration between adjacent access requests for performing access operations; based on the historical information, calculating the flip probability coefficient of each address bit in the to-be-accessed address, where the flip probability coefficient is determined based on the flip probability of each address bit in the to-be-accessed address within an effective period, and the duration of the effective period is determined based on the longest activation duration of a memory row; based on the flip probability coefficient, determining the address mapping rule of the to-be-accessed address; where the determined address mapping rule at least includes: mapping a group of address bits with the lowest flip probability coefficient to the row address of the memory address.

[0088] It can be seen that in the address mapping rule determination method provided by the embodiments of the present application, during the running of the sample object, based on the historical information, the flip probability coefficient of each address bit in the to-be-accessed address within the effective period determined based on the longest activation duration of the memory row is calculated, and then the address mapping rule of the to-be-accessed address is determined, so that at least a group of address bits with the lowest flip probability coefficient can be mapped to the row address of the memory address, thereby selecting the address bit with the lowest change probability as the row address at the address mapping rule level. Furthermore, in the scenario corresponding to the sample object, when the address mapping rule determined by the address mapping rule determination method is adopted, the change probability of the row address in the corresponding memory access process is reduced, so that the memory access process tends to access the same row of the memory and avoids accessing different rows of the memory, that is, the probability of page hit is increased, the probability of page conflict is reduced, and the memory access efficiency is improved.

[0089] In an optional example, in the order from high to low of the flip probability coefficient, the address bits are sequentially mapped to the bank group address, column address, bank address, and row address of the memory address. Thus, in the address mapping rule of the to-be-accessed address, a group of address bits with a higher flip probability coefficient is mapped to the bank group address of the memory address, so as to select the address bit with a higher change probability as the bank group address at the address mapping rule level. Based on the relatively independent characteristics between the bank groups of the memory and the minimum switching time consumption between the bank groups, in the scenario corresponding to the running of the sample object, when the address mapping rule determined by the address mapping rule determination method is adopted, the switching time consumption between memory access requests is reduced, and the memory access efficiency is improved.

[0090] Next, the solution provided by the embodiments of the present application will be described in detail.

[0091] Refer to Figure 2 The optional flowchart of an address mapping rule determination method shown, the method includes:

[0092] Step S100: Determine the historical information corresponding to each access request during the operation of the sample object.

[0093] The historical information includes the address to be accessed and the time information corresponding to the access request; the address to be accessed includes multiple address bits, and the time information is used to indicate the interval duration between the execution of adjacent access requests for access operations.

[0094] By determining the corresponding historical information, the flip probability coefficient of the corresponding address bit is determined.

[0095] Among them, the sample object can be a preset application program, or a preset system of a preset user. Or, in a further example, the sample object can also be a preset system in a preset scenario, such as a preset system in a certain specific time period, etc. By analyzing and statistically analyzing the data during the operation of the sample object, the access characteristics of the data in the scenario with the same access characteristics as the sample object are determined, so as to improve the memory access efficiency of the operation scenario corresponding to the sample object under the address mapping rule determined based on the access characteristics.

[0096] The running time of the sample object can be a specific time period, or the time required for the sample object to execute a preset number of preset tasks, or the time required for the sample object to run to a certain node. It can be understood that the running data of the sample object within this running time at least reflects the access characteristics of the sample object, and the embodiments of the present application do not make specific limitations here.

[0097] The historical information is used to provide a data basis for determining the flip probability coefficient of the corresponding address bit. In a specific example, the historical information can be recorded based on a historical request queue. Specifically, the request information of the access request can be stored in the historical request queue (for example, when the access request enters the memory controller, its copy is stored in the historical request queue), and the corresponding historical information can be stored in the access request corresponding to the historical request queue after the corresponding information is generated. For example, after the time information is generated, the time information can be stored in the corresponding access request in the historical access queue.

[0098] Among them, the historical information may include the address to be accessed and the time information corresponding to the access request. The time information is used to indicate the order and execution interval duration of adjacent access requests for access operations, so as to determine the access requests involved within the longest activation duration of the memory row based on the execution interval duration.

[0099] It should be noted that in the embodiments of the present application, the execution of the access request refers to the period from the self-activation start until the access operation is completed. Correspondingly, the execution interval duration can be understood as the time from the activation moment of the previous access request to the activation moment of the subsequent access request.

[0100] The moment information can directly indicate the execution interval duration, or can directly or indirectly indicate the moment when the access request is executed. When the moment information directly or indirectly indicates the moment when the access request is executed, the execution interval duration can be obtained by subtracting the moment corresponding to the previously executed access request from the moment corresponding to the subsequently executed access request.

[0101] In an optional example, the moment information can be the moment when the access request is parsed to obtain the address information of the storage unit to be accessed and stored in the instruction queue. It can be understood that the moment when the access request is parsed to obtain the address information of the storage unit to be accessed and stored in the instruction queue can be understood as the moment when the access request is executed at the software level. Correspondingly, the execution interval duration can be obtained by subtracting the moment information corresponding to adjacent access requests.

[0102] In a specific example, when an access request is stored in the instruction queue, the access request is synchronously stored in the historical instruction queue, and the moment information corresponding to the access request is recorded in the historical information of the access request.

[0103] For example, when the access request is parsed to obtain the address information of the storage unit to be accessed and stored in the instruction queue, a timestamp can be provided for the access request. In a specific example, the timestamp can also include an overflow flag bit at the same time to implement cyclic counting of the counter. Correspondingly, in the example where the historical information of the access request is recorded in the historical request queue, when the timestamp is generated, the timestamp can be recorded in the corresponding access request in the historical request queue.

[0104] The address to be accessed can be understood as the physical address of the memory in the system. Among them, a preset address bit or an address segment composed of a preset plurality of address bits can indicate the address information of the storage unit. For example, it can be used as the storage bank group address to indicate the storage bank group where the storage unit is located, can be used as the storage bank address to indicate the storage bank where the storage unit is located, can be used as the row address to indicate the row where the storage unit is located, can be used as the column address to indicate the column where the storage unit is located, etc.

[0105] It can be understood that during the operation of the sample object, multiple access requests are usually executed, and even a large number of access requests are executed. Correspondingly, the historical information obtained in this step is the historical information corresponding to each access request executed during the operation of the sample object.

[0106] Among them, considering the subsequent steps, the flipping probability coefficient is determined based on the flipping probabilities of each address bit in the to-be-accessed address within the effective period. In an alternative implementation, the historical request queue can be used to store the access requests executed within the effective period.

[0107] Correspondingly, when storing an access request in the instruction queue, synchronously store the access request in the historical instruction queue, and record the corresponding time information of the access request into the historical information of the access request. Then, further according to the time information, calculate the time distance between each access request in the historical instruction queue and the to-be-calculated access request, and delete the access requests in the historical instruction queue whose time distance is greater than the effective period.

[0108] Taking the effective period duration as T as an example, the historical request queue stores the historical access requests within the T-time window forward from the time information corresponding to the access request at the tail of the historical instruction queue, so that corresponding calculations can be performed in real time based on the historical request queue.

[0109] In a specific example, the historical instruction queue can be a first-in-first-out queue. The access request at the tail of the historical instruction queue is the access request with the latest time information, and the access requests at other positions in the historical instruction queue are the historical access requests within the T-time window forward from the time information corresponding to the access request at the tail of the historical instruction queue. Correspondingly, when indicating the corresponding time information with timestamps, the time distance between all access requests in the historical instruction queue and the latest access request can be calculated according to the timestamp information, and the older historical access requests whose time distance is greater than the effective period are deleted to ensure that the access requests in the historical instruction queue are all access requests executed within the effective period.

[0110] In another alternative example, for example, in the scenario of software-simulating the running of a sample object, the historical information corresponding to each access instruction during the running of the sample object can be completely recorded, and then the calculation of the corresponding flipping probability is performed based on this historical information. Specifically, in this example, a sliding window operation can be performed on the access requests during the running period of the sample object based on the duration of the effective period; among them, an access request corresponds to a to-be-calculated window, and the access request is located within the to-be-calculated window corresponding to it; then, based on the historical information, the flipping probabilities corresponding to each address bit in the access requests within each to-be-calculated window can be calculated one by one.

[0111] Step S110: Calculate the flipping probability coefficient of each address bit in the to-be-accessed address based on the historical information. The flipping probability coefficient is determined based on the flipping probabilities of each address bit in the to-be-accessed address within the effective period, and the duration of the effective period is determined based on the longest activation duration of the memory row.

[0112] By determining the flip probability coefficient of each address bit, a data basis is provided for subsequent determination of the address mapping rule. The longest activation duration of the memory row refers to the longest time that the row to be accessed can remain in the activated state when it is activated and not pre-charged and closed.

[0113] According to the physical characteristics of the memory (such as DRAM, full name Dynamic Random Access Memory, dynamic random access memory), during the execution of an access request, the row activated based on the access request will not always remain in the activated state, but must be closed based on operations such as refresh after a certain time. Therefore, in the embodiments of the present application, by statistically calculating the flip probability coefficient based on the valid period, data interference from data access information at other times outside the valid period can be avoided. Obviously, by distinguishing the valid period and the invalid period, the association between the flip probability coefficient and page conflict or page hit can be more accurately reflected.

[0114] The duration of the valid period is determined based on the longest activation duration of the memory row. For example, the duration of the valid period can be less than or equal to the longest activation duration of the memory row. When the duration of the valid period can be the longest activation duration of the memory row, the probability of address bit flipping can be estimated within the broadest range; when the duration of the valid period is less than the longest activation duration of the memory row, the duration of the valid period can be, for example, C times the longest activation duration of the memory row, where C is less than 1 and greater than or equal to 0.5, such as 0.8 times, etc., so as to reduce the data processing volume while ensuring the accuracy.

[0115] In a specific example, the duration of the valid period can be the longest activation duration of each address bit in the memory row. It can be understood that within the longest activation duration of the memory row, if the row address flips, it may lead to a page conflict. Therefore, statistically confirming the flip probability coefficient corresponding to each address bit within the longest activation duration of the memory row can provide an accurate data basis for the determination of the row address in the subsequent address mapping rule.

[0116] In a specific example, when a row to be accessed in DRAM is activated and not pre-charged and closed, the longest time it can remain in the activated state is 9*tREFI (Refresh Interval, memory refresh interval time). Correspondingly, the longest activation duration of the memory row, that is, the duration of the valid period (also called the time window), is 9*tREFI after the memory row is activated.

[0117] It can be understood that the running duration of the sample object is usually much greater than the duration of the effective period, and the total amount of memory access requests is huge. Correspondingly, the determination of the flip probability coefficient corresponding to each address bit within the effective period can be calculated based on statistical methods.

[0118] From the perspective of access requests, the statistics of the corresponding flip probability coefficients can be based on the time information of the access requests. For each access request, calculate the flip probability of each address bit in the to-be-accessed address corresponding to the access request within the effective period one by one, and further calculate the weighted average of the flip probabilities of each address bit. Use this weighted average of the flip probabilities as the flip probability coefficient of the address bit.

[0119] In a specific example, refer to Figure 3 Another optional flowchart showing a method for determining an address mapping rule. Step S110 may include the following processes:

[0120] Step S111: Based on the historical information, determine the flip probability of each address bit in the to-be-accessed address corresponding to each access request within the effective period.

[0121] Among them, if the statistics of the corresponding flip probability coefficients are carried out from the perspective of access requests, for an access request (hereinafter referred to as the to-be-calculated access request), the flip probability can be determined based on the request information of the access requests in the historical instruction queue. Specifically: Take the access request stored at the tail of the historical instruction queue as the to-be-calculated access request, and take the other access requests in the historical instruction queue as associated access requests. Compare the access address of the to-be-calculated access request with the access addresses in the associated access requests to determine the flip probability of each address bit.

[0122] In the specific process of determining the flip probability, for an address bit, the number of times the address bit flips can be determined, and then the number of flips is divided by the total number of associated access requests to obtain the flip probability of the address bit.

[0123] Among them, the flip probability can be calculated in real time during the access request execution process, that is, when an access request is stored in the historical instruction queue, based on step S100, obtain the historical information of each access request in the historical instruction queue. The time window of the historical instruction queue is the effective period. At this time, the access instruction stored in the historical instruction queue is the access request at the tail of the historical instruction queue. Thus, this step can be executed. Take this access request as the to-be-calculated access request, and take other access requests as associated access requests to calculate the flip probability of the corresponding to-be-calculated access request.

[0124] It is understandable that as new access requests are continuously stored, the access requests stored in the historical instruction queue are dynamically updated. That is, the historical instruction queue continuously stores new access requests and continuously eliminates access requests that exceed the effective time period, so as to always keep the time interval between all access requests in it and the access request at its tail (i.e., the latest stored) within the effective time period T, and calculate the flip probability corresponding to the access request at the tail (i.e., the latest stored) in real time, so as to calculate the weighted mean of the flip probability based on this flip probability.

[0125] The effective time period corresponding to the access request to be calculated can be the duration range of the effective time period before the row activation of the access request to be calculated. For example, in the scenario of software-simulating the operation of a sample object, the historical information of all access requests can be recorded, and then based on this historical information, the flip probability corresponding to each access request can be calculated one by one.

[0126] In the specific calculation of the flip probability, after determining the access request to be calculated and the associated access requests, the specific flip probability can be determined based on the number of associated access requests and whether there is a data flip in the corresponding address bits of the access addresses of the associated access requests compared with the address bits corresponding to the access request to be calculated.

[0127] Specifically, taking the time stamp as the moment information, the access address to be accessed is 4 bits, and the duration of the effective moment is T as an example, referring to Figure 4 a schematic diagram showing a calculation method of the flip probability, during the operation of a sample object, 8 access requests are generated, and among them, the flip probability corresponding to each access request can be calculated in turn.

[0128] Specifically, taking the access request Req2 as the access request to be calculated as an example, based on its time stamp 2T, the corresponding effective time period is from T to 2T, and there are no other access requests during this time period. Therefore, in the historical request queue corresponding to Req2, only Req2 is included; when Req7 is the access request to be calculated, based on its time stamp 4T, the corresponding effective time period is from 3T to 4T. It can be seen that the time stamps of Req4 and Req7 differ by 1T and are within the effective time period, and the time stamps of Req3 and Req7 differ by 1.4T and are not within the effective time period. Therefore, Req4, Req5, and Req6 are within this effective time period. Correspondingly, Req4, Req5, and Req6 are the associated access requests of Req7. Therefore, in the historical request queue corresponding to Req7, Req4, Req5, Req6, and Req7 are included.

[0129] In the process of calculating the specific flip probability, the number of associated access requests based on Req2 is 0. Therefore, the flip probability corresponding to Req2 is 0. The number of associated access requests based on Req7 is 3. Correspondingly, among the comparison associated access requests Req4, Req5, and Req6, for each address bit compared with Req7, determine whether it flips and the number of flips. For example, in the 0th address bit, compared with the data "1" in the 0th bit of Req7, Req4 and Req5 flip, that is, the value is different from the data in the 0th bit of Req7 and is "0", and the corresponding number of flips is 2. The flip probability of this address bit of Req7 is 2 / 3.

[0130] Similarly, based on the above method, the flip probability of the 1st bit of Req7 can be determined to be 1 / 3, the flip probability of the 2nd bit is 0 / 3, and the flip probability of the 3rd bit is 2 / 3.

[0131] In the process of calculating the corresponding flip probability, the judgment of whether the address bit flips can be based on the to-be-accessed address of the prior access request, or can be based on the to-be-accessed address of the subsequent access request. This application does not make specific limitations here.

[0132] It can be understood that for a certain address bit, the greater the flip probability, the more opportunities the corresponding address bit introduces DRAM timing constraints for the access request, and the greater the ability of this address bit to cause the access request to be subject to the timing constraints of historical memory access requests. Therefore, the flip probability of the address bit can be selected as the characteristic data for optimizing the address mapping mode.

[0133] Reference Figure 3 , continue to execute step S112: Based on the flip probability, calculate the weighted average value of the flip probabilities corresponding to each address bit; use the weighted average value of the flip probabilities as the flip probability coefficient corresponding to each address bit in the to-be-accessed address during the effective period.

[0134] The weighted average value of the flip probabilities is used to indicate the weighted average value of the flip probabilities of the corresponding address bits in each access request during the operation of the sample object under the preset weight value. The preset weight value is used to indicate the density of the access requests executed during the effective period of the corresponding access request.

[0135] It can be understood that during the intensive access period, a high weight value can be given to the flip probability of the access request, and a low weight value can be given during the sparse period, so that the importance of the flip probability of the address bit of the access request in the entire memory access process can be reflected based on the preset weight value of the access request. In some examples, the preset weight value can be the number of associated access requests corresponding to this access request. Or, in other examples, the preset weight value can also be determined based on the density of the access requests executed by the sample object during different periods.

[0136] After determining the flip probabilities of each address bit in each access request, the weighted average of the flip probabilities of each address bit in each access request can be calculated based on a preset weight value to obtain the weighted average of the flip probabilities of the corresponding address bit, so as to comprehensively determine the weighted average of the flip probabilities of each address bit during the operation of the entire sample object.

[0137] In a specific example, step S112 may include:

[0138] Step S112a: Obtain each access request and the flip probability of each address bit in the corresponding access request;

[0139] Among them, the obtained access requests and the flip probabilities of each address bit in the corresponding access requests are used as the basis for calculating the weighted average of the flip probabilities.

[0140] Step S112b: Assign the preset weight value corresponding to each access request to the number of associated access requests corresponding to the access request;

[0141] It can be understood that the preset weight value is used to indicate the density of the access requests executed during the effective period of the corresponding access request. In a specific example, the assignment of the preset weight value can be the number of associated access requests corresponding to the access request to reflect the density of the access requests executed during the effective period.

[0142] Step S112c: Calculate the weighted average of the flip probabilities corresponding to each address bit based on the flip probability and the preset weight value.

[0143] By calculating the weighted average of the flip probabilities of the address bits in each access request, the weighted average of the flip probabilities of the corresponding address bit is obtained, so as to comprehensively reflect the flip probability of the address bit from the overall access requests.

[0144] Among them, in an optional example, the weighted average of the flip probabilities can be calculated based on the following formula:

[0145]

[0146] Among them, K is the total number of address bits of the access request, N is the total number of access requests during the operation of the sample object, Lx is the access request to be calculated, and the number of times the associated access request within the forward T time window and the access request to be calculated flip at the x-th address bit; M is the total number of associated access requests of the access request to be calculated within the forward T time window; w is the weight corresponding to the access request to be calculated, and the value is M as described above.

[0147] Still taking the Figure 4 example shown as an example, referring to Figure 5 shown forFigure 4 A further schematic diagram of the calculation process of the example in Figure 4 can calculate the flipping probability of each address bit corresponding to each access request in sequence based on the records in the historical request queue, and further calculate the weighted average of the flipping probabilities of each address bit corresponding to all access requests.

[0148] Specifically, for the 0th address bit, the weighted average of the corresponding flipping probability is:

[0149] P0 = (0 + 0 + 0 + 2 / 2 * 2 + 1 / 2 * 2 + 2 / 3 * 3 + 2 / 3 * 3 + 2 / 3 * 3) / (0 + 0 + 1 + 2 + 2 + 3 + 3 + 3) = 9 / 14 ≈ 0.64

[0150] By analogy, the weighted average of the flipping probability of the 1st address bit can be obtained as 0.36; the weighted average of the flipping probability of the 2nd address bit is 0.29; the weighted average of the flipping probability of the 3rd address bit is 0.43.

[0151] Among them, in this example, the weighted average of the flipping probability is used as the flipping probability coefficient corresponding to each address bit in the to-be-accessed address during the valid period.

[0152] Reference Figure 2 , continue to execute step S120: Determine the address mapping rule of the to-be-accessed address based on the flipping probability coefficient.

[0153] Among them, the determined address mapping rule at least includes: mapping the group of address bits with the lowest flipping probability coefficient to the row address of the memory address.

[0154] After determining the flipping probability coefficient of the specific address bit, the address mapping rule can be determined based on this flipping probability coefficient. Among them, by mapping the group of address bits with the lowest flipping probability coefficient to the row address of the memory address, the flipping probability coefficient of the row address is reduced, the page hit probability is increased, and the page conflict probability is reduced. And, by mapping the group of address bits with a flipping probability coefficient higher than the row address to the bank group address of the memory address, the switching time consumption between access requests is reduced.

[0155] It should be noted that the row address can be one bit or multiple bits. Specifically, when the row address is a bits (a is an integer greater than or equal to 1), the group of address bits with the lowest flipping probability coefficient can be understood as the a address bits with the lowest flipping probability coefficient. The bank group address can be one bit or multiple bits. Specifically, when the bank group address is b bits, the group of address bits with a flipping probability coefficient higher than the row address is the b address bits with the highest flipping probability coefficient higher than the row address, and b is an integer greater than or equal to 1.

[0156] In further address mapping rules, the bank group address, bank address, and column address can be further determined based on the inversion probability coefficient.

[0157] Specifically, according to the physical characteristics of memory (such as DRAM), bank groups are relatively independent physical components and perform prefetch operations independently. That is to say, there are fewer time constraints for data access operations on the banks of two bank groups. When performing access operations on the same bank group, it is required that the next bank operation can only be performed after the prefetch operation of the previous bank is completed. The relative independence between bank groups improves the parallelism of internal access operations in DRAM. Therefore, the bank group can correspond to the address bits with the highest inversion probability coefficient, so that a large number of access requests can be quickly deployed to multiple bank groups when processed sequentially, improving the parallelism of internal access operations in DRAM and increasing the bandwidth during large data volume access.

[0158] Correspondingly, in some optional examples, a group of address bits with an inversion probability coefficient higher than the row address can be mapped as the bank group address of the memory address. For example, the determined address mapping rule may include: in the order of the inversion probability coefficient from high to low, the mapping order of the address bits is at least the bank group address, bank address, and row address.

[0159] The inventor further believes that if the inversion of the address bits in consecutive memory access requests occurs in the column, the arbitration state of the memory controller is page hit, while the switching of the bank may cause page miss or even page conflict. That is to say, the access switching speed of the column is greater than that of the bank. Therefore, the column address can correspond to the address bits with the second highest inversion probability coefficient to increase the page hit probability, and the bank can be next; for the row address, it is required to correspond to the address bits with the lowest inversion probability coefficient to minimize the page conflict and page miss probabilities.

[0160] In an optional example, the address mapping rule includes: in the order of the inversion probability coefficient from high to low, the address bits can be sequentially mapped as the bank group address, column address, bank address, and row address.

[0161] Still taking Figure 5For example, based on the weighted mean of the inversion probabilities of each address bit, the 0th address bit can be mapped to the bank group address (marked as BG in the figure); the 1st address bit can be mapped to the bank address (marked as bank in the figure); the 2nd address bit can be mapped to the row address (marked as row in the figure); the 3rd address bit can be mapped to the column address (marked as column in the figure).

[0162] In a further optional example, the address information of the storage unit can also be divided into different data segments for mapping. For example, the column address can be divided into a first column address segment and a second column address segment. According to the order from high to low of the inversion probability coefficients, the mapping order of the address bits can be at least the bank group address, the first column address segment, the bank address, the second column address segment, and the row address.

[0163] In a further example, the to-be-accessed address may further include other information. For example, in an example where the memory is an HBM (High Bandwidth Memory) device, the HBM die may include Pseudo Channels (PC, usually 2) and Stack IDs (SID). The data buses of the 2 Pseudo Channels are completely independent, and the CA bus is time-division multiplexed, so as to make full use of the characteristic that the physical bank access has a certain delay to implement the parallel operation of the two Pseudo Channels; correspondingly, there are also Pseudo Channel (PC) address segments and Stack ID (SID) address segments in the memory address. Based on the fact that the stack and the bank group have the same characteristics, the corresponding address bits can also correspond to the address bits with relatively high inversion probability coefficients. In a specific example, the address mapping rule in this scenario can be, for example: according to the order from high to low of the inversion probability coefficients, the mapping order of the address bits is at least the Pseudo Channel address segment (which can also be called the Pseudo Channel address), the bank group address, the column address segment, the Stack ID address segment (which can also be called the Stack ID address), the bank address, and the row address.

[0164] It should be noted that in the embodiments of the present application, the method for determining the address mapping rule can be implemented independently based on the historical information recorded in the memory access process, or can be implemented simultaneously based on the memory access process. In a specific example, after executing an access request, taking this access request as the to-be-calculated access request, triggering the process for determining the inversion probability in step S111, so as to calculate the inversion probability for the access request in real time.

[0165] Further, referring to Figure 6Another optional flowchart of an address mapping rule determination method is shown, and step S130 can be executed: At a preset node, determine whether the sample object has finished execution. If so, execute step S112, and calculate the weighted average of the flipping probabilities corresponding to each address bit based on the flipping probability; use the weighted average of the flipping probabilities as the flipping probability coefficient corresponding to each address bit in the to-be-accessed address during the valid period; if not, continue to execute the corresponding memory access process and return to execute the process of determining the historical information in step S100, and the process in step S111 of determining the flipping probability of each address bit in the to-be-accessed address corresponding to each access request during the valid period.

[0166] Among them, the preset node can be that a preset number of access requests have been executed. That is, at the end of every preset number of access requests, the corresponding judgment in step S130 is executed. This preset number can be 1 or multiple. Or, in other examples, the preset node can also be a preset moment, that is, at the preset moment, the corresponding judgment in step S130 is executed.

[0167] In the address mapping rule determination method provided in the embodiments of the present application, during the running of the sample object, based on historical information, calculate the flipping probability coefficient corresponding to each address bit in the to-be-accessed address during the valid period determined based on the longest activation duration of the memory row, and then determine the address mapping rule of the to-be-accessed address, so that at least a group of address bits with the lowest flipping probability coefficient can be mapped to the row address of the memory address. Thus, at the address mapping rule level, select the address bit with the lowest change probability as the row address. Furthermore, in the scenario corresponding to the sample object, when using the address mapping rule determined by this address mapping rule determination method, the change probability of the row address in the corresponding memory access process is reduced, making the memory access process tend to access the same row of the memory and avoiding accessing different rows of the memory, that is, increasing the probability of page hit and reducing the probability of page conflict, and improving the memory access efficiency.

[0168] Further, in the order from high to low of the flipping probability coefficients, the address bits are sequentially mapped to the bank group address, column address, bank address, and row address of the memory address. Thus, in the address mapping rule of the to-be-accessed address, map a group of address bits with a higher flipping probability coefficient to the bank group address of the memory address, so as to select an address bit with a higher change probability as the bank group address at the address mapping rule level. Based on the characteristic that the memory bank groups are relatively independent and the switching time between bank groups is the shortest, in the scenario corresponding to the running sample object, when using the address mapping rule determined by this address mapping rule determination method, the switching time between memory access requests is reduced, and the memory access efficiency is improved.

[0169] In an embodiment of the present application, a memory access method is further provided. The memory access method can be understood as an access process executed based on the determined address mapping rule after determining the corresponding address mapping rule based on the foregoing address mapping rule determination method. Among them, the memory method is applied to the running scenario corresponding to the sample object, so that the memory access method has the same access characteristics as the sample object. Furthermore, under the address mapping rule determined based on this access characteristic, the memory access efficiency of the running scenario corresponding to the sample object is improved.

[0170] Reference Figure 7 An optional flowchart of a memory access method shown, the method includes:

[0171] Step S200: Obtain an access request.

[0172] Among them, the access request includes the address to be accessed.

[0173] Step S210: Based on the address mapping rule, parse the address information of the storage unit to be accessed from the address to be accessed;

[0174] It can be understood that the address mapping rule determined for the foregoing method based on the embodiment of the present application enables different address information in the corresponding storage unit to correspond to different flip probability coefficients.

[0175] Specifically, based on the address mapping rule, address decoding can be performed to sequentially parse and determine the address bits for the memory bank group address, the memory bank address, as well as the column address bits and row address bits in the address to be accessed. Correspondingly, based on the foregoing description, it can be known that the flip probability coefficient corresponding to the row address bits is the lowest, and the flip probability coefficient corresponding to the memory bank group address bits can be the highest. The column address and the memory bank address bits can be adaptively configured with address bits of different flip probability coefficients based on different considerations.

[0176] Step S220: Based on the address mapping rule of the storage unit, execute the access of the access request.

[0177] It can be understood that based on the address mapping rule determined by the foregoing method, the access process of the storage unit in the embodiment of the present application can avoid page conflicts to the greatest extent and improve the page hit probability.

[0178] Specifically, the access for executing the access request may include: storing the parsed address information of the storage unit into the instruction queue in the access order; arbitrating the access requests in the instruction queue according to the memory status information, selecting the instruction of the access request whose timing constraint is satisfied and sending it to the memory, so that the memory performs corresponding access operations, and updating the memory status information until the memory completes the access operation corresponding to the instruction.

[0179] In a further specific example, the memory access method may further include a configuration process for the determined address mapping rule. Specifically, referring to Figure 8 Another optional flowchart of a memory access method shown, before the memory access method executes step S200, it further includes:

[0180] Step S300: Initialize the determined address mapping rule to the system.

[0181] In a specific example, the host system can initialize the determined address mapping rule to the system by resetting the hardware platform and the software system, so that the host system running again realizes the access to the memory based on the determined address mapping rule.

[0182] In the embodiments of the present application, a memory controller is further provided. The memory controller can be understood as an optional product for implementing the address mapping rule determination method described in the embodiments of the present application. Specifically, referring to Figure 9 The optional structural schematic diagram of the memory controller shown, the memory controller includes:

[0183] An address decoding logic, an instruction queue, and an instruction arbitration logic connected in sequence, and a historical information determination logic connected to the instruction queue and a flip probability coefficient determination logic connected to the historical information determination logic;

[0184] Wherein, the historical information determination logic is used to determine the historical information corresponding to each access request during the operation of the sample object; the flip probability coefficient determination logic is used to statistically determine the flip probability coefficient corresponding to each address bit in the to-be-accessed address during the effective period based on the historical information, so as to determine the address mapping rule of the to-be-accessed address based on the flip probability coefficient;

[0185] The historical information includes the to-be-accessed address corresponding to the access request and the time information; the to-be-accessed address includes a plurality of address bits, and the time information is used to indicate the order and the execution interval duration of adjacent access requests to perform access operations; the duration of the effective period is determined based on the longest activation duration of the memory row; wherein, the determined address mapping rule at least includes: mapping the group of address bits with the lowest flip probability coefficient to the row address of the memory address.

[0186] In an alternative example, the historical information determination logic includes a historical request queue and a timing module. The historical request queue is used to record historical information corresponding to access requests (including the address to be accessed and time information) within a valid period, and the timing module is used to provide time information for access requests. It can be understood that when the access request generates time information, the timing module provides the time information for the access request and records the time information in the historical request queue.

[0187] The historical request queue can obtain the address to be accessed from the instruction queue and obtain time information based on the timing module to obtain corresponding historical information.

[0188] In a further example, the memory control further includes:

[0189] Address decoding logic for parsing the address information of the storage unit to be accessed from the address to be accessed; among them, the address to be accessed of the access request can be parsed sequentially based on the order in the access request sequence.

[0190] An instruction queue for sequentially storing the address information corresponding to access requests;

[0191] Instruction arbitration logic for arbitrating access requests in the instruction queue, selecting the instruction whose timing constraint is satisfied and sending it to the memory to enable the memory to perform corresponding access operations, and simultaneously updating the memory status information until the memory completes the access operation (also referred to as the access operation) of the corresponding instruction.

[0192] It can be understood that the address decoding logic parses the address to be accessed based on the configured address mapping rule. After determining the address mapping rule for the address to be accessed in the embodiment of the present application, the corresponding address mapping rule can be configured to the address decoding logic.

[0193] In the embodiment of the present application, a computing device is further provided. The computing device can be understood as an optional product for implementing the address mapping rule determination method described in the embodiment of the present application. Specifically, referring to Figure 10 the optional structural schematic diagram of the computing device shown, the computing device includes:

[0194] The memory controller provided by the present application;

[0195] A rule determination logic connected to the memory controller for determining the address mapping rule of the address to be accessed based on the flip probability coefficient; among them, the determined address mapping rule at least includes: mapping the group of address bits with the lowest flip probability coefficient to the row address of the memory address.

[0196] In a further example, the computing device further includes:

[0197] A register management unit is configured to obtain and store the flip probability coefficients corresponding to each address bit during the valid period. Specifically, the register management unit may obtain the corresponding flip probability coefficients from the flip probability coefficient determination logic of the memory controller.

[0198] Correspondingly, the rule determination logic is configured to determine an address mapping rule based on the flip probability coefficients stored in the register management unit.

[0199] In a specific example, the host system may initialize the determined address mapping rule to the system by resetting the hardware platform and the software system, so that the host system running again can access the memory based on the determined address mapping rule. Among them, the rule determination logic may be configured in the host system as a sub-module of the host. After the rule determination logic determines the corresponding address mapping rule, the host system may also configure the corresponding address mapping rule to the memory controller through the register management unit to complete the access operation of the optimized application program.

[0200] It can be understood that the computing acceleration unit in the computing device may generate an access request sequence for access, and convert the address information in the access request into a physical address through the page table translation unit and then send it to the memory controller, so that the memory controller executes the access requests in the corresponding access request sequence to access the memory.

[0201] The embodiment of the present application also provides a computer program, including one or more computer-executable instructions, and when the one or more computer-executable instructions are executed, the method for determining the address mapping rule as described in the embodiment of the present application is implemented, or the method for accessing the memory as described in the embodiment of the present application is implemented.

[0202] The above describes multiple embodiment solutions provided by the embodiment of the present application. The optional ways described in each embodiment solution may be combined and cross-referenced with each other without conflict, so as to extend multiple possible embodiment solutions, and all of these can be considered as the embodiment solutions disclosed and made public by the embodiment of the present application.

[0203] Although the embodiment of the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method for determining an address mapping rule, characterized in that: include: Determine historical information corresponding to each access request during the running of the sample object, wherein the historical information includes the address to be accessed and time information corresponding to the access request; The address to be accessed includes a plurality of address bits, and the time information is used to indicate the interval between adjacent access requests to perform access operations; Based on the historical information, calculating the flip probability coefficient of each address bit in the address to be accessed, wherein the flip probability coefficient is determined based on the flip probability of each address bit in the address to be accessed within a valid period, and the duration of the valid period is determined based on the longest activation duration of the memory row; Based on the flip probability coefficient, an address mapping rule of the address to be accessed is determined; wherein the determined address mapping rule at least includes: mapping a group of address bits with the lowest flip probability coefficient to a row address of a memory address.

2. The method for determining address mapping rules according to claim 1, characterized in that: In the step of determining the address mapping rule of the address to be accessed based on the flip probability coefficient, the determined address mapping rule also includes at least: in the order of the flip probability coefficient from high to low, the mapping order of the address bits is at least the storage group address, the storage body address and the row address.

3. The method for determining address mapping rules according to claim 1, characterized in that: The calculating, based on the historical information, a flip probability coefficient of each address bit in the address to be accessed comprises: Based on the historical information, determining the flip probability of each address bit of the to-be-accessed address corresponding to each access request within a valid period; Based on the flip probability, a weighted mean flip probability corresponding to each address bit is calculated; the weighted mean flip probability is used to indicate the weighted mean flip probability of the corresponding address bit in each access request during the running of the sample object under a preset weight value; the preset weight value is used to indicate the density of the access request executed within the valid period of the corresponding access request; The weighted mean of the flip probability is used as the flip probability coefficient corresponding to each address bit in the address to be accessed within the valid time period.

4. The method for determining address mapping rules according to claim 3, characterized in that: For an access request, the step of determining the historical information corresponding to each access request during the running of the sample object is specifically: Acquire historical information of each access request in a historical instruction queue; wherein the historical instruction queue is used to store access requests executed within a valid period; The step of determining the flip probability of each address bit of the to-be-accessed address corresponding to each access request within a valid period based on the historical information is specifically as follows: taking the access request stored at the tail of the historical instruction queue as the access request to be calculated, and taking other access requests in the historical instruction queue as associated access requests, comparing the access address of the access request to be calculated with the access address in the associated access request, and determining the flip probability of each address bit.

5. The method for determining address mapping rules according to claim 4, characterized in that: The calculating, based on the flip probability, a weighted mean of the flip probability corresponding to each address bit includes: Obtaining each access request and the flip probability of each address bit in the corresponding access request; Assigning a preset weight value corresponding to each access request to the number of associated access requests corresponding to the access request; Based on the flip probability and the preset weight value, a weighted mean of the flip probability corresponding to each address bit is calculated.

6. The method for determining address mapping rules according to claim 3, characterized in that: After the step of determining the flip probability of each address bit of the to-be-accessed address corresponding to each access request within the valid period based on the historical information and before the step of calculating the weighted mean of the flip probability corresponding to each address bit based on the flip probability, the method further includes: At a preset node, determining whether the sample object has been executed; If yes, the step of calculating the weighted mean of the flip probability corresponding to each address bit based on the flip probability is executed; if no, the step of continuing to execute the memory access process and executing the step of determining the historical information corresponding to each access request during the operation of the sample object, and determining the flip probability of each address bit of the to-be-accessed address corresponding to each access request within the valid period based on the historical information; The preset node is when a preset number of access requests are completed, or the preset node is a preset time.

7. The method for determining address mapping rules according to claim 4, characterized in that: In the step of determining the historical information corresponding to each access request during the running of the sample object, before acquiring the historical information of each access request in the historical instruction queue, the step further includes: When an access request is stored in the instruction queue, the access request is synchronously stored in the historical instruction queue, and the time information corresponding to the access request is recorded in the historical information of the access request; based on the time information, the time distance between each access request in the historical instruction queue and the access request to be calculated is calculated, and the access requests in the historical instruction queue whose time distance is greater than the valid period are deleted.

8. The method for determining address mapping rules according to claim 7, characterized in that: The time information is the time corresponding to when the access request is parsed to obtain the address information of the storage unit to be accessed and is stored in the instruction queue; Among them, the access request is stored in the historical instruction queue, and the time information corresponding to the access request is recorded in the historical information of the access request. Specifically, when the access request is parsed to obtain the address information of the storage unit to be accessed and stored in the instruction queue, a timestamp is provided for the access request, and the timestamp is recorded in the corresponding access request in the historical request queue.

9. The method for determining address mapping rules according to claim 3, characterized in that: The determining, based on the historical information, the flip probability of each address bit of the to-be-accessed address corresponding to each access request within the valid period includes: A sliding window operation is performed on the access requests during the running period of the sample object based on the length of the valid period; wherein one access request corresponds to one window to be calculated, and the access request is located within the corresponding window to be calculated; Based on the historical information, the flip probability corresponding to each address bit in the address to be accessed in the access request in each window to be calculated is calculated one by one.

10. The method for determining address mapping rules according to claim 4, characterized in that: After executing an access request, the access request is used as the access request to be calculated, triggering the step of calculating the flip probability coefficient of each address bit in the address to be accessed based on the historical information.

11. The method for determining address mapping rules according to claim 1, characterized in that: The address mapping rule includes: when the row address is a bit, the group of address bits with the lowest flip probability coefficient is the a-bit address bits with the lowest flip probability coefficient, where a is an integer greater than or equal to 1; In the step of determining the address mapping rule of the address to be accessed based on the flip probability coefficient, the determined address mapping rule at least includes: in the order of the flip probability coefficient from high to low, the mapping order of the address bits is at least the storage group address, column address, storage address and row address; or, the address mapping rule of the address to be accessed based on the flip probability coefficient includes: dividing the column address into a first column address segment and a second column address segment; in the order of the flip probability coefficient from high to low, determining the mapping order of the address bits is at least the storage group address, the first column address segment, the storage address, the second column address segment and the row address; or, in the step of determining the address mapping rule of the address to be accessed based on the flip probability coefficient, the determined address mapping rule at least includes: in the order of the flip probability coefficient from high to low, the mapping order of the address bits is at least the pseudo channel address segment, the storage group address, the column address, the stack identification address segment, the storage address and the row address.

12. A memory access method, characterized in that: include: Obtaining an access request, wherein the access request includes an address to be accessed; Based on the address mapping rule, the address information of the storage unit to be accessed is parsed from the address to be accessed; wherein the address mapping rule is determined based on the address mapping rule determination method according to any one of claims 1 to 11; Based on the address mapping rule of the storage unit, the access of the access request is performed.

13. The memory access method according to claim 12, characterized in that: Before obtaining the access request, the method further includes: Initialize the address mapping rule determined by the address mapping rule determination method according to any one of claims 1 to 11 to the system.

14. The memory access method according to claim 12, characterized in that: The access of executing the access request includes: The address information of the storage unit obtained by parsing is stored in the instruction queue according to the access order; Arbitrate the access requests in the instruction queue according to the memory status information, select the access request instructions whose timing constraints are satisfied and send them to the memory, so that the memory performs the corresponding access operation; Update the memory status information until the memory completes the access operation of the corresponding instruction.

15. A memory controller, characterized in that: include: An address decoding logic, an instruction queue, and an instruction arbitration logic connected in sequence, and a history information determination logic connected to the instruction queue and a flip probability coefficient determination logic connected to the history information determination logic; The historical information determination logic is used to determine the historical information corresponding to each access request during the operation of the sample object; the flip probability coefficient determination logic is used to statistically determine the flip probability coefficient corresponding to each address bit in the address to be accessed within the valid period based on the historical information, so as to determine the address mapping rule of the address to be accessed based on the flip probability coefficient; The historical information includes the address to be accessed and the time information corresponding to the access request; the address to be accessed includes multiple address bits, and the time information is used to indicate the order and execution interval length of adjacent access requests to perform access operations; the length of the valid period is determined based on the longest activation duration of the memory row; wherein the determined address mapping rules include at least: mapping a group of address bits with the lowest flip probability coefficient to the row address of the memory address.

16. The memory controller according to claim 15, characterized in that: The historical information determination logic includes a historical request queue and a timing module, wherein the historical request queue is used to record historical information corresponding to access requests within a valid period, and the timing module is used to provide time information for access requests.

17. The memory controller according to claim 15, characterized in that: The address decoding logic is used to parse the address to be accessed in the access request to obtain the address information of the storage unit to be accessed; the instruction queue is used to store the address information corresponding to the access request in sequence; The instruction arbitration logic is used to arbitrate the access requests in the instruction queue, select instructions with satisfied timing constraints and send them to the memory, so that the memory performs corresponding access operations.

18. A computing device, characterized in that include: The memory controller according to any one of claims 15 to 17; The rule determination logic connected to the memory controller is used to determine the address mapping rule of the address to be accessed based on the flip probability coefficient; wherein the determined address mapping rule at least includes: mapping a group of address bits with the lowest flip probability coefficient to the row address of the memory address.

19. The computing device according to claim 18, characterized in that Also includes: A register management unit, used to obtain and store the corresponding flip probability coefficient of each address bit within the valid period; The rule determination logic is used to determine an address mapping rule based on the flip probability coefficient stored in the register management unit.

20. A computer program, characterized in that It comprises one or more computer executable instructions, and when the one or more computer executable instructions are executed, it implements the address mapping rule determination method as described in any one of claims 1-11, or implements the memory access method as described in any one of claims 12-14.

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