Memory access control chip, data memory access method and data memory access system

Abstract

The invention provides a memory access control chip, a data memory access method and a data memory access system, and relates to the technical field of computers, in particular to the technical field of chips and artificial intelligence. The invention discloses a memory access control chip. Comprising m AI interconnection control logic units, a first interconnection bus used for connecting the m AI interconnection control logic units, k CXL uplink port control logic units, f CXL downlink port control logic units and a second interconnection bus used for connecting all the CXL uplink port control logic units and all the CXL downlink port control logic units, the protocol conversion logic unit is used for connecting the first interconnection bus and the second interconnection bus, the protocol conversion logic unit is used for executing conversion between a CXL protocol and an AI protocol, and m, k and f are respectively positive integers. Moreover, the data access method can be realized through the access control chip, and the data access system comprises the access control chip.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, in particular to technologies such as chips and artificial intelligence, and specifically relates to a memory access control chip, a data memory access method, and a data memory access system. Background Art

[0002] In an artificial intelligence (AI) server, a central processing unit (CPU) is good at processing complex logic control and serial computing tasks, and an AI chip is good at processing large-scale parallel computing tasks. In order to achieve efficient parallel computing, high-speed data exchange is required between the CPU and the AI chip to reduce the latency of data transmission.

[0003] Compute Express Link (CXL) is an open standard high-speed interconnection protocol that can solve the interconnection problem between computing devices and memory, providing higher data throughput and lower latency, and is the core technology for realizing memory-computation separation. How to apply CXL technology in an AI chip to achieve high-speed data exchange between the CPU and the AI chip in an AI server is of great significance to the development of AI technology. Summary of the Invention

[0004] The present disclosure aims to solve at least one of the technical problems in the related art to some extent.

[0005] To this end, the purpose of the present disclosure is to provide a memory access control chip, a data memory access method, and a data memory access system. By implementing the mutual conversion between the CPU high-speed interconnection protocol and the AI chip high-speed interconnection within the memory access control chip, the CXL technology can be applied to the AI chip to reduce the latency of data transmission, and by combining a CXL memory expansion card with the memory access control chip, the memory expansion and pooling of the AI chip can be further realized.

[0006] According to a first aspect of the present disclosure, there is provided a memory access control chip, including:

[0007] m AI interconnection control logic units;

[0008] A first interconnection bus for connecting the m AI interconnection control logic units;

[0009] k CXL upstream port control logic units;

[0010] f CXL downstream port control logic units;

[0011] A second interconnection bus for connecting all CXL upstream port control logic units and CXL downstream port control logic units;

[0012] A protocol conversion logic unit for connecting the first interconnect bus and the second interconnect bus, the protocol conversion logic unit being configured to perform conversion between the CXL protocol and the AI protocol;

[0013] Wherein, m, k, and f are positive integers respectively.

[0014] According to a second aspect of the present disclosure, there is provided a data access method, including:

[0015] Receiving a first data access request sent by a connected first chip, wherein the first data access request includes a target address, and the first chip is a CXL chip or an AI chip;

[0016] Determining a second chip where the target address is located according to configuration information;

[0017] When the type of the second chip is different from that of the first chip, converting the first data access request into a second data access request conforming to the protocol corresponding to the second chip, so as to perform data access to the second chip based on the second data access request.

[0018] According to a third aspect of the present disclosure, there is provided a data access system, including a memory access control chip as described in the first aspect of the present disclosure, m AI chips respectively connected to the memory access control chip, k CXL chips respectively connected to the memory access control chip, and f CXL memory cards respectively connected to the memory access control chip.

[0019] According to a fourth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions, the computer instructions being used to cause the computer to execute the data access method as described in the second aspect.

[0020] According to a fifth aspect of the present disclosure, there is provided a computer program product, including a computer program, the computer program realizing the data access method as described in the second aspect when executed by a processor.

[0021] The memory access control chip, data access method, and data access system provided by the present disclosure have the following beneficial effects:

[0022] By designing a protocol conversion logic unit in the memory access control chip, the interconnection bus providing the data path between the CXL uplink and downlink ports is connected to the interconnection bus providing the data access path between AI chips, enabling the memory access control chip to integrate the CXL Switch function and the AI Switch function. While implementing the sharing and high-speed transmission of data between CPUs using CXL technology, CXL technology is also applied to AI chips to improve the data transmission rate between the CPU and AI chips, facilitating the memory expansion and pooling of AI chips and optimizing the performance of AI servers.

[0023] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and / or additional aspects and advantages of the present disclosure will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, which are used to better understand the solution and do not constitute a limitation to the present disclosure, where:

[0025] Figure 1 is a schematic structural diagram of a memory access control chip according to an embodiment of the present disclosure;

[0026] Figure 2 is a schematic flowchart of a data memory access method according to an embodiment of the present disclosure;

[0027] Figure 3 is a schematic structural diagram of a data memory access system according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The following makes an illustration of the exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted below.

[0029] The embodiments of the present disclosure relate to technical fields such as chips and artificial intelligence.

[0030] A chip, also known as a microcircuit, microchip or integrated circuit, is the core component of modern electronic devices. It is a miniature electronic circuit that integrates a large number of electronic components (such as transistors, resistors, capacitors, etc.) on a tiny semiconductor material. Its working principle is based on the physical properties of semiconductor materials. By processes such as doping, the electrical properties of the semiconductor material are changed, and then semiconductor devices with different functions are manufactured. These devices are then combined into a complex circuit system to achieve specific electronic functions.

[0031] The chips involved in this disclosure include memory access control chips, AI chips, and CXL chips.

[0032] The memory access control chip is a hybrid control chip proposed in this disclosure that integrates both the Compute Express Link (CXL) switch function and the Artificial Intelligence (AI) switch function. It can provide low-latency and high-bandwidth connections for data transmission among multiple devices supporting the CXL protocol, and can also provide a high-speed connection path for data exchange between devices and AI.

[0033] An AI chip is a processor designed specifically for artificial intelligence tasks. By optimizing the architecture and instruction set, it accelerates the operation of algorithms such as machine learning, deep learning, and neural networks. Different from traditional CPUs (general-purpose computing), AI chips are specialized for core AI operations such as matrix operations and parallel computing, significantly improving the energy efficiency ratio and performance.

[0034] A CXL chip refers to a master device that supports the CXL protocol. For example, a CPU chip can have a built-in CXL controller to support high-speed communication with other devices.

[0035] In this disclosure, the memory access control chip, AI chip, and CXL chip are chips with different functions. The memory access control chip can be connected to the AI chip and CXL chip, receive data memory access requests sent by the AI chip or CXL chip, and can access the memory of the connected AI chip or CXL chip according to the request.

[0036] Artificial Intelligence, abbreviated as AI in English, is a new technical science that studies, develops theories, methods, technologies, and application systems for simulating, extending, and expanding human intelligence. It is a discipline that studies the use of computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, planning, etc.), mainly including the principles of computers achieving intelligence, manufacturing computers similar to human brain intelligence, and enabling computers to achieve higher-level applications.

[0037] In the technical solution of the present disclosure, the processing of the collection, storage, use, processing, transmission, provision, and disclosure of the user's personal information complies with the provisions of relevant laws and regulations and does not violate public order and good customs.

[0038] The memory access control chip, data memory access method, and data memory access system according to the embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0039] Figure 1 It is a schematic structural diagram of a memory access control chip according to an embodiment of the present disclosure.

[0040] As Figure 1 shown, the memory access control chip, which can also be called a hybrid switch chip, can support both high-speed interconnection of CPUs and high-speed interconnection of AI chips.

[0041] In the present disclosure, the memory access control chip includes m AI interconnection control logic units, a first interconnection bus for connecting the m AI interconnection control logic units, k CXL uplink port control logic units, f CXL downlink port control logic units, a second interconnection bus for connecting all the CXL uplink port control logic units and the CXL downlink port control logic units, and a protocol conversion logic unit for connecting the first interconnection bus and the second interconnection bus.

[0042] Among them, the AI interconnection control logic unit is the artificial intelligence (AI) interconnection control logic unit, that is, Figure 1 the AI interconnection control logic marked in

[0043] In the embodiments of the present disclosure, the number m of the AI interconnection control logic units in the memory access control chip can be set according to the needs of the actual AI server, and m is a positive integer. For example, in Figure 1 the shown chip, m is 2, and the two AI interconnection control logic units can be respectively marked as AI interconnection control logic 0 and AI interconnection control logic 1.

[0044] Among them, the first interconnection bus, that is, Figure 1 the non-cache coherent interconnection bus shown in

[0045] In the embodiments of the present disclosure, since AI tasks are mainly data parallel, and the computing units usually process independent data blocks rather than frequently sharing the same memory address, the first interconnection bus adopts a non-cache coherent design.

[0046] Among them, the CXL upstream port control logic unit is an upstream port control logic unit that supports the Compute Express Link (CXL) protocol, that is, Figure 1 The CXL upstream port controller logic shown in can connect to a CXL master device (such as a CPU) and determine the device memory to be accessed by the CXL master device according to the system configuration and address.

[0047] In the embodiments of the present disclosure, the number k of CXL upstream port control logic units in the memory access control chip can be set according to the number of CPUs that need to be connected actually, and k is a positive integer. For example, in Figure 1 In the shown chip, k is 2, and the two CXL upstream port control logic units can be respectively marked as CXL upstream port controller logic 0 and CXL upstream port controller logic 1.

[0048] Among them, the CXL downstream port control logic unit, that is, Figure 1 The CXL downstream port controller logic shown in can connect to a CXL device (such as a CXL memory card with a pooling function).

[0049] In the embodiments of the present disclosure, the number f of CXL downstream port control logic units in the memory access control chip can be set according to the memory size that needs to be expanded actually, f is a positive integer, and f can be the same as k. For example, in Figure 1 In the shown chip, f is 2, and the two CXL downstream port control logic units can be respectively marked as CXL downstream port controller logic 0 and CXL downstream port controller logic 1.

[0050] Among them, the second interconnection bus, that is, Figure 1 The Cache coherence interconnection bus shown in. Because the memory is shared among multiple-core CPUs, when multiple cores access the same memory address, it is necessary to ensure that the cache data seen by all cores is consistent. Therefore, the second interconnection bus adopts a Cache coherence design.

[0051] In the embodiments of the present disclosure, the second interconnection bus can provide a full-connection data path between the CXL upstream port control logic unit and the CXL downstream port control logic unit.

[0052] Among them, the protocol conversion logic unit is connected to the first interconnection bus and the second interconnection bus, and is used to perform the conversion between the CXL protocol (that is, the CPU high-speed interconnection protocol) and the AI protocol, so as to realize high-speed data exchange between the CPU and the AI chip in the AI server, and apply CXL in the AI server.

[0053] In this embodiment, by designing a protocol conversion logic unit in the memory access control chip, the interconnection bus providing the data path between the CXL uplink and downlink ports is connected to the interconnection bus providing the data path for accessing data between AI chips, enabling the memory access control chip to integrate the CXL Switch function and the AI Switch function. While implementing the sharing and high-speed transmission of data between CPUs using the CXL technology, the CXL technology is also applied to AI chips, improving the data transmission rate between the CPU and the AI chip, facilitating the memory expansion and pooling of the AI chip, and optimizing the performance of the AI server.

[0054] Optionally, the CXL uplink port control logic unit can first be used to determine whether the target address in the memory access request is the address of the AI chip according to the configuration information when receiving a data memory access request sent by the connected CXL chip.

[0055] Among them, the CXL chip can be a Central Processing Unit (CPU) chip based on the CXL technology and can include one or more CXL master controllers.

[0056] In the embodiments of the present disclosure, the CXL chip can request to access the memory to perform operations such as reading and writing data. Therefore, the CXL uplink port control logic unit connected to the CXL chip can receive the data memory access request sent by the connected CXL chip. The configuration information contains the correspondence between the address and the memory. From the target address in the memory access request, it can be queried in the configuration information whether the memory to be accessed by the target address is the memory of the AI chip or other memories, such as the CPU memory, the CXL expansion card memory, or the system cache, etc.

[0057] Then, when the target address is the address of the AI chip, the memory access request can be sent to the protocol conversion logic unit to convert the memory access request into a memory access request conforming to the AI protocol through the protocol conversion logic unit and send it to the target AI chip corresponding to the target address.

[0058] In the embodiments of the present disclosure, the protocol conversion logic unit can send the converted memory access request to the target AI chip corresponding to the target address through the first interconnection bus. After receiving the memory access request, taking the memory read request as an example, the target AI chip can read the data from the AI chip memory and then send the data to the protocol conversion logic unit through the connected AI interconnection control logic unit and the first interconnection bus. Then, the protocol conversion logic unit converts the read data into the data format under the CXL protocol and then sends it to the CXL chip that issued the request through the second interconnection bus and the CXL uplink port control logic unit.

[0059] In the embodiments of the present disclosure, the CXL upstream port control logic unit can determine whether the target memory access address in the received memory access request is the address of the AI chip. If it is the address of the AI chip, it is converted into the correct protocol through the protocol conversion logic unit, so that the memory access request sent by the CXL chip can be routed to the AI chip, realizing data exchange between the CPU and the AI chip, and further improving the performance of data transmission.

[0060] Optionally, in Figure 1 the chip shown, a buffer and a control logic unit connected to the second interconnection bus may also be included.

[0061] Among them, the buffer is the Figure 1 system cache (Cache) in. The buffer can be used to cache the frequently used data in the CXL memory card to reduce the latency of the CXL master device accessing the CXL memory.

[0062] Among them, the control logic unit, that is, the Figure 1 cache (Cache) coherence control logic unit in, is used to store the data information stored in the buffer and the storage information of the data in the CXL memory card connected to the chip in the connected CXL chip, that is, the cache situation and cache state.

[0063] It should be noted that the memory access control chip proposed in the present disclosure can be connected to multiple CXL chips at the same time. Therefore, there may be multiple CPU cores performing read and write operations on the same memory address. If the Cache data is inconsistent, it may cause system errors or crashes. Therefore, the control logic unit should conform to Cache coherence.

[0064] It should be noted that in Figure 1 the chip shown, there is only one cache coherence control logic unit, but in actual use, multiple ones can be set according to needs. Different control logic units can record the storage information of different CXL memory data.

[0065] In the embodiments of the present disclosure, by setting a buffer in the memory access control chip to store frequently used data, the data access speed can be increased, the access latency can be reduced, and by setting a control logic unit in the memory access control chip to perform partition management on the memory address space, the memory access efficiency can be further improved.

[0066] Optionally, in Figure 1 the case where the chip shown includes a control logic unit, in order to improve the efficiency and accuracy of memory access request routing, the second interconnection bus can also be used to receive the data memory access requests sent by any CXL upstream port control logic unit or protocol conversion logic unit, and send the data memory access requests to the control logic unit.

[0067] In the embodiments of the present disclosure, since both the CXL chip and the AI chip can read and write the memory in the system, the data access request may be initiated by the CXL chip or the AI chip. The second interconnect bus can receive the data access request sent by any CXL upstream port control logic unit or protocol conversion logic unit, and send the request to the control logic unit to further route and judge the data access request through the control logic unit.

[0068] Then, the control logic unit can be used to determine the response mode of the data access request according to at least one of the target address, data information, and storage information in the data access request.

[0069] In the embodiments of the present disclosure, the control logic unit can query the stored data information or storage information of itself to determine the storage location of the target data corresponding to the target address in the data access request, whether it is in the AI chip, the CXL chip, or the CXL memory card, etc. Then, the corresponding response mode can be determined according to the storage location.

[0070] In the embodiments of the present disclosure, the response mode may include: in the case where the storage location is another CXL chip, sending a listen command to notify the CXL chip to write back the data; in the case where the storage location is the buffer, directly obtaining the data from the buffer; or in the case where the storage location is the CXL memory card, the access request can be sent to the CXL memory card via the second interconnect bus and the CXL downstream port control logic unit connected to the CXL memory card to obtain the target data of the access request.

[0071] In the embodiments of the present disclosure, the second interconnect bus sends the data access request to the control logic unit, and the control logic unit determines the storage location of the target data corresponding to the target address in the data access request according to the stored data information, and then determines the response mode of the data access request, which can further improve the efficiency of data access.

[0072] Optionally, when the data access request is a data read request, the control logic unit can be used to determine the storage location of the target data corresponding to the target address according to the data information and storage information.

[0073] It should be noted that this data read request may be initiated by a certain CXL chip or the AI chip.

[0074] In the embodiments of the present disclosure, the target data corresponding to the target access address is the latest data. If the data information and storage information may include the storage time of the data, the storage location of the target data corresponding to the target address can be determined to be in the buffer area, or in the CXL chip or the CXL memory card according to the data information and storage information.

[0075] Then, when the storage location of the target data is the first CXL chip, a data read request is sent to the first CXL chip.

[0076] Herein, the first CXL chip is different from the CXL chip that initiates the data read request.

[0077] In the embodiments of the present application, the control logic unit needs to send a listening command to the first CXL chip through the second interconnection bus and the CXL upstream port control logic unit associated with the first CXL chip, and the listening command includes the target address.

[0078] After that, when the target data returned by the first CXL chip is received, the target data is sent to the second CXL chip or the AI chip that initiates the data read request.

[0079] Herein, the second CXL chip is the CXL chip that initiates the data read request.

[0080] In the embodiments of the present disclosure, the first CXL chip that receives the listening command can deliver the target data to the control logic unit via the CXL upstream port control logic unit and the second interconnection bus. Thus, the control logic unit can send the target data to the CXL upstream port control logic unit or the protocol conversion logic unit associated with the second CXL chip via the second interconnection bus, and then send the target data to the second CXL chip or the AI chip that initiates the data read request.

[0081] In the embodiments of the present disclosure, the memory access control chip can read data by using the CXL upstream port control logic unit connected to the other CXL chip when the storage location of the target data is the other CXL chip, realizing memory sharing among multiple CPUs and optimizing resource utilization.

[0082] Optionally, after obtaining the target data, the control logic unit can also write the target data into the buffer area and update the data information based on the target data and the target address.

[0083] In the embodiments of the present disclosure, the obtained target data may need to be frequently accessed. Since the access speed of the cache is generally much faster than that of the main memory or the disk, the target data obtained from the CXL chip is written into the buffer area, i.e., the system cache. Subsequently, when reading the target data again, there is no need to access the CXL chip, thereby effectively reducing the read and write latency of the CXL memory pool. Moreover, when writing the target data into the buffer area, the data information can be updated by using the target data and the target address, thereby ensuring the accuracy and real-time nature of the data information.

[0084] It should be noted that when writing target data into the cache area, but the cache area is full, the target data and target address can be used to replace the data with the lowest access frequency in the current cache area and its corresponding memory access address to complete the update of data information. This can improve the resource utilization of the cache area and ensure the accuracy of the control logic unit in determining the response method based on the stored data information.

[0085] Alternatively, when the storage location of the target data is within any CXL memory card, the target control logic unit may send the data read request to the CXL downstream port control logic unit associated with any CXL memory card, and then upon receiving the target data returned by the associated first CXL downstream port control logic unit, send the target data to the second CXL chip or AI chip that initiated the data read request.

[0086] In the disclosed embodiment, the control logic unit can send a data read request to the CXL downstream port control logic unit associated with any CXL memory card through the second interconnect bus, so that the CXL downstream port control logic unit can read the target data from the connected first CXL memory card, and then send the target data to the second CXL chip that initiates the data read request via the second interconnect bus and the CXL upstream port control logic unit associated with the second CXL chip that initiates the data read request, or send the target data to the AI ​​chip that initiates the data read request via the second interconnect bus, the protocol conversion logic unit, the first interconnect bus and the AI ​​interconnect control logic unit.

[0087] In the disclosed embodiment, the memory access control chip can use the CXL downstream port control logic unit connected to the CXL memory card to read data when the storage location of the target data is a CXL memory card, so that the pooled memory can be expanded using a memory card that supports the CXL pooling function, thereby expanding the computing bandwidth, greatly improving the performance of computing tasks running on the pooled memory, and realizing high-speed access of the AI ​​chip to the CXL memory pool.

[0088] Alternatively, when the storage location of the target data is a cache area, the control logic unit may obtain the target data from the cache area, and then send the target data to the second CXL chip or AI chip that initiates the data read request.

[0089] In the disclosed embodiment, the control logic unit may directly obtain the target data from the cache area, and then send the target data to the CXL uplink port control logic unit or the protocol conversion logic unit associated with the second CXL chip via the second interconnect bus, and then send it to the second CXL chip or the AI ​​chip.

[0090] In the embodiments of the present disclosure, when the storage location of the target data is the buffer, the memory access control chip can directly read the data in the buffer, thereby improving the efficiency of data memory access, further enhancing the performance of the computing tasks running on the pooled memory, and realizing the high-speed access of the AI chip to the CXL memory pool.

[0091] It should be noted that in Figure 1 the memory access control chip shown, it may further include an FM management logic unit, which is connected to the second interconnection bus and manages and configures the binding relationship between the internal upstream port and the downstream port of the memory access control chip.

[0092] For the memory access control chip described in the above embodiments, the present disclosure also proposes a data memory access method to implement reading, writing, etc. of data by using the memory access control chip.

[0093] Figure 2 It is a schematic flowchart of the data memory access method proposed in an embodiment of the present disclosure.

[0094] As Figure 2 shown, the data memory access method includes:

[0095] S301: Receive a first data memory access request sent by the connected first chip.

[0096] Among them, the first data memory access request includes a target address, and the first chip is a CXL chip or an AI chip.

[0097] In the embodiments of the present disclosure, the memory access control chip for implementing this data memory access method can be connected to multiple CXL chips and AI chips to receive the first data memory access request sent by the chips. The target address included in the first data memory access request can facilitate the memory access control chip to determine the storage location of the target accessed data, improving the accuracy and routing efficiency of data memory access.

[0098] S302: Determine the second chip where the target address is located according to the configuration information.

[0099] In the embodiments of the present disclosure, the memory access control chip can determine whether the second chip where the target address is located is a CXL chip or an AI chip according to the corresponding relationship between the address and the chip included in the configuration information. Furthermore, according to the type of the second chip, it can be determined whether the steps are executed by the CXL upstream port control logic unit or the AI interconnection control logic unit when processing the first data memory access request.

[0100] S303: When the type of the second chip is different from that of the first chip, convert the first data memory access request into a second data memory access request that conforms to the protocol corresponding to the second chip, so as to perform data memory access on the second chip based on the second data memory access request.

[0101] In the embodiments of the present disclosure, when the type of the second chip is different from that of the first chip, it can be known that the first data access request sent by the first chip cannot be directly routed to the second chip for processing due to different protocols. Therefore, the protocol conversion logic unit in the memory access control chip can be used to convert the first data access request into a second data access request that conforms to the corresponding protocol of the second chip, so as to perform data access on the second chip based on the second data access request. The specific process of data access can refer to the description in the above embodiments.

[0102] In the embodiments of the present disclosure, since the data access method can be implemented by using the memory access control chip, for a detailed description of the data access method, reference can be made to the description of the memory access control chip in the above embodiments of the present disclosure, which will not be elaborated here.

[0103] In this embodiment, by determining the chip type corresponding to the memory access address in the data access request, when the chip type of the target access is different from the chip type of the sending request, the request is protocol-converted, so that the converted request can be routed to the target access chip for data access, which can implement the application of the CXL technology in the AI chip, improve the data transmission rate between the CPU and the AI chip, realize the memory expansion and pooling of the AI chip, and optimize the performance of the AI server.

[0104] Optionally, in the case where the second chip is a CXL chip and the first data access request is a read request, the target data read from the second chip can be stored in the buffer area, and then the data information stored in the buffer area can be updated based on the target data and the target address. Thus, the efficiency of data access can be improved, and the performance of the computing tasks running on the pooled memory can be further enhanced.

[0105] The present disclosure also proposes a data access system. Figure 3 It is a schematic structural diagram of the data access system.

[0106] As Figure 3 shown, the data access system may include the memory access control chip in the above embodiments, m AI chips respectively connected to the memory access control chip, k CXL chips respectively connected to the memory access control chip, and f CXL memory cards respectively connected to the memory access control chip.

[0107] By Figure 3It can be known that each AI chip can be connected to a memory access control chip by connecting to an AI interconnection control logic unit. Therefore, the number of AI chips is the same as the number of AI interconnection control logic units, both being m, and each AI chip has a corresponding AI chip memory. For example, when there are 2 AI interconnection control logic units in the memory access control chip, labeled as AI interconnection control logic 0 and AI interconnection control logic 1 respectively, the connected AI chips can be labeled as AI chip 0 and AI chip 1 respectively, as Figure 3 shown.

[0108] Each CXL chip (i.e., the Figure 3 CPU chip in it) can be connected to the memory access control chip by connecting to a CXL upstream port control logic unit. Therefore, the number of CXL chips is the same as the number of CXL upstream port control logic units, both being k, and each CXL chip has a corresponding CPU memory. For example, when there are 2 CXL upstream port control logic units in the memory access control chip, labeled as CXL upstream port control logic 0 and CXL upstream port control logic 1 respectively, the connected CXL chips can be labeled as CPU chip 0 and CPU chip 1 respectively, as Figure 3 shown.

[0109] Each CXL memory card can be connected to the memory access control chip by connecting to a CXL downstream port control logic unit. Therefore, the number of CXL memory cards is the same as the number of CXL downstream port control logic units, both being f, and each CXL memory card is an extended memory with a pooling function. For example, when there are 2 CXL downstream port control logic units in the memory access control chip, labeled as CXL downstream port control logic 0 and CXL downstream port control logic 1 respectively, the connected CXL memory cards can be labeled as CXL memory card 0 and CXL memory card 1 respectively, as Figure 3 shown.

[0110] It should be noted that in the data memory access system provided by the present disclosure, the CPU performs unified addressing on the memories in the system, and both the CPU chip and the AI chip can perform read and write access to the memories in the system.

[0111] In the embodiments of the present disclosure, by providing a data memory access system including a memory access control chip, m AI chips, k CXL chips, and f CXL memory cards, high-speed data transmission can be achieved between the CPU and the AI, as well as high-speed access of the AI chip to the CXL memory pool, and the memory can be extended by connecting CXL memory cards, improving the computing performance of the AI server.

[0112] According to the embodiments of the present disclosure, the present disclosure also provides a readable storage medium and a computer program product.

[0113] The various embodiments of the systems and techniques described above in this specification can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that receives data and instructions from, and transmits data and instructions to, a storage system, at least one input device, and at least one output device.

[0114] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions / operations specified in the flowchart and / or block diagram to be implemented. The program code can be executed entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine, or entirely on the remote machine or server.

[0115] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0116] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and a pointing device (e.g., a mouse or a trackball), by which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and the input received from the user can be in any form (including acoustic input, voice input, or tactile input).

[0117] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), the Internet, and blockchain network.

[0118] A computer system can include a client and a server. The client and the server are generally far from each other and usually interact through a communication network. The relationship between the client and the server is generated by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system, and solves the defects of difficult management and weak business scalability existing in traditional physical hosts and VPS services ("Virtual Private Server", or simply "VPS"). The server can also be a server of a distributed system, or a server combined with blockchain.

[0119] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and no limitation is imposed herein.

[0120] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined. In the description of the present disclosure, the words "if" and "when" may be interpreted as "when...", "while...", "in response to determining", or "in the case of...".

[0121] The above specific embodiments do not constitute a limitation on the protection scope of the present disclosure. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present disclosure should be included within the protection scope of the present disclosure.

Claims

1. A memory access control chip, comprising: m AI interconnected control logic units; A first interconnection bus for connecting the m AI interconnection control logic units; k CXL upstream port control logic units; f CXL downstream port control logic units; a second interconnect bus for connecting all CXL upstream port control logic units and CXL downstream port control logic units; A protocol conversion logic unit for connecting the first interconnect bus and the second interconnect bus, wherein the protocol conversion logic unit is used to perform conversion between the CXL protocol and the AI ​​protocol; Wherein, m, k and f are positive integers respectively.

2. The memory access control chip according to claim 1, wherein: The CXL upstream port control logic unit is used to: Upon receiving a data memory access request sent by a connected CXL chip, determining, according to the configuration information, whether a target address in the memory access request is an address of the AI ​​chip; When the target address is the address of the AI ​​chip, the memory access request is sent to the protocol conversion logic unit, so that the memory access request is converted into a memory access request that complies with the AI ​​protocol through the protocol conversion logic unit, and sent to the target AI chip corresponding to the target address.

3. The memory access control chip according to claim 1 or 2, wherein: The memory access control chip also includes a cache area and a control logic unit connected to the second interconnect bus; The control logic unit is used to store the data information stored in the cache area and the storage information of the data in the CXL memory card connected to the chip in the connected CXL chip.

4. The memory access control chip as claimed in claim 3, wherein: The second interconnect bus is used to receive a data access request sent by any one of the CXL uplink port control logic unit or the protocol conversion logic unit, and send the data access request to the control logic unit; The control logic unit is further used to determine a response mode of the data memory access request according to at least one of a target address in the data memory access request, the data information and the storage information.

5. The memory access control chip as claimed in claim 4, wherein: The data access request is a data read request, and the control logic unit is further used for: Determine the storage location of the target data corresponding to the target address according to the data information and the storage information; In a case where the storage location of the target data is a first CXL chip, sending the data read request to the first CXL chip; When receiving the target data returned by the first CXL chip, the target data is sent to the second CXL chip or the AI ​​chip that initiated the data read request.

6. The memory access control chip as claimed in claim 4, wherein: The control logic unit is further used for: In a case where the storage location of the target data is in any CXL memory card, sending the data read request to a CXL downstream port control logic unit associated with any CXL memory card; In case of receiving the target data returned by the associated first CXL downstream port control logic unit, the target data is sent to the second CXL chip or the AI ​​chip that initiated the data read request.

7. The memory access control chip according to claim 4, wherein: The target control logic unit is further used for: Writing the target data into the buffer area; The data information is updated based on the target data and the target address.

8. The memory access control chip as claimed in claim 4, wherein: The target control logic unit is further used for: In a case where the storage location of the target data is a cache area, acquiring the target data from the cache area; The target data is sent to the second CXL chip or the AI ​​chip that initiates the data read request.

9. A data access method, comprising: receiving a first data memory access request sent by a connected first chip, wherein the first data memory access request includes a target address, and the first chip is a CXL chip or an AI chip; Determine, according to the configuration information, the second chip where the target address is located; In the case that the type of the second chip is different from that of the first chip, the first data access request is converted into a second data access request that complies with a protocol corresponding to the second chip, so as to perform data access on the second chip based on the second data access request.

10. The method of claim 9, wherein: Also includes: In a case where the second chip is a CXL chip and the first data access request is a read request, storing the target data read from the second chip into a cache area; Based on the target data and the target address, the data information stored in the buffer is updated.

11. A data memory access system, comprising the memory access control chip according to any one of claims 1 to 9, m AI chips respectively connected to the memory access control chip, k CXL chips respectively connected to the memory access control chip, and f CXL memory cards respectively connected to the memory access control chip.

12. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to claim 9 or 10.

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