Logic board fault positioning device and method

Abstract

The invention relates to the technical field of electronic testing, in particular to a logic board fault positioning device and method. Firstly, dominant physical faults on the surface of the logic board are detected and positioned through an image recognition model, and the fault detection precision and speed are improved; secondly, the detection points of the logic board are evaluated by introducing the weighted Euclidean distance, the relative importance of different signals on fault judgment is more accurately considered, the most critical signal for fault diagnosis is preferentially concerned, and the sensitivity of fault positioning is improved; and finally, through combination of the fault knowledge graph and the Bayesian network, comprehensive tracking and reasoning of component faults are realized, and potential fault components are accurately positioned by dynamically updating the posterior probability, so that the accuracy and reliability of fault diagnosis are improved. Through combination of the scheme, high-intelligence and high-efficiency logic board fault detection and positioning are realized.

Description

Technical Field

[0001] The present invention relates to the field of electronic testing technologies, and particularly to a logic board fault location device and method. Background Art

[0002] The logic board is a crucial component in electronic devices and is widely used in various complex electronic products and systems, such as computers, communication devices, automated control systems, etc. With the high integration and complexity of electronic devices, faults in the logic board have a profound impact on the performance and stability of the entire system. Therefore, accurately and timely locating faults in the logic board is of great significance. Through efficient fault location technologies, fault points on the logic board can be quickly discovered and diagnosed, thereby shortening the repair time, reducing maintenance costs, and improving the reliability of the device and the operating efficiency of the system.

[0003] However, existing logic board fault location technologies still have certain deficiencies. Traditional fault location methods mainly rely on manual inspection or experience-based diagnosis, often with low efficiency, poor accuracy, and difficulty in adapting to diverse fault modes in complex systems. Current automated detection means, although using technologies such as image recognition and electrical signal analysis, can often only detect obvious surface faults and have limited diagnostic capabilities for hidden component faults or complex multi-point faults. In addition, existing technologies also have problems in the accuracy of fault path tracing and component fault location, especially when dealing with signal interference and the fusion of multiple signal data, it is easy to produce false judgments and missed judgments. Therefore, how to improve the comprehensiveness, accuracy, and real-time nature of fault location has become a challenge that needs to be urgently solved in current technologies.

[0004] Therefore, a logic board fault location device and method are proposed. Summary of the Invention

[0005] The purpose of the present invention is to provide a logic board fault location device and method. By using an image recognition model to accurately detect the physical fault types and locations on the surface of the logic board, rapid location of obvious faults is achieved; by introducing the weighted Euclidean distance to evaluate the detection points of the logic board, the relative importance of different signals for fault judgment is more accurately considered, and priority is given to focusing on the voltage signals that are most critical for fault diagnosis; through the combination of a fault knowledge graph and a Bayesian network, in-depth reasoning and location of potential component faults are realized, the most likely faulty components are output based on the posterior probability criterion, and high-confidence fault diagnosis results are provided.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A logic board fault location device, comprising:

[0008] A physical fault detection module, which is used to obtain the surface image data of the logic board by using a high-definition camera device, perform physical fault detection on the surface image data through an image recognition model, and map the physical fault points to the corresponding points on the logic board topology diagram;

[0009] A component fault detection module, including:

[0010] A data acquisition sub-module, which is used to collect the real-time electrical signal data of the test points on the logic board through an electrical signal probe;

[0011] A fault analysis sub-module, which is used to calculate the weighted Euclidean distance between the real-time electrical signal data and the pre-stored historical electrical signal data, and determine the abnormal signal nodes based on a preset fluctuation threshold;

[0012] A fault location sub-module, which is used to track the faulty components according to the topological positions of the abnormal signal nodes, combined with a pre-constructed fault knowledge graph and a Bayesian network, to obtain the confidence levels of each component inside the area of the abnormal signal nodes; output the component with the highest confidence level as the faulty component and determine the fault type, and map the fault points of the faulty component to the corresponding points on the logic board topology diagram;

[0013] A fault report generation module, which is used to collect the fault points and fault types, generate fault repair suggestions in combination with a fault knowledge base, and print a fault report.

[0014] Further, the physical fault detection of the surface image data includes:

[0015] Using a high-definition camera device to capture the surface image data of the logic board; preprocessing the surface image data to obtain preprocessed data; inputting the preprocessed data into a pre-trained image recognition model; the image recognition model outputs the physical fault type and physical fault points.

[0016] Further, the electrical signal data includes voltage signals, current signals, and frequency signals, and the calculation formula for the weighted Euclidean distance is:

[0017]

[0018] Where D represents the weighted Euclidean distance, U r 、I r and f r are the real-time voltage signal, real-time current signal, and real-time frequency signal respectively, U h 、I h and f h are the historical voltage signal, historical current signal, and historical frequency signal respectively, and α represents the voltage distance weight, and β represents the composite distance weight.

[0019] Further, the component fault tracking process includes:

[0020] According to the position of the abnormal signal node in the logic board topology diagram, generate an upstream power supply path and a downstream load path along the signal transmission direction as candidate fault paths;

[0021] Based on the pre-constructed fault knowledge graph, track the candidate fault paths and locate potential fault components;

[0022] Use a Bayesian network to calculate the confidence of each potential fault component and output it.

[0023] Further, the calculation process of the Bayesian network includes:

[0024] Construct Bayesian network nodes, which include abnormal signal nodes, potential fault components, and fault types;

[0025] Based on the fault knowledge graph, set the initial prior probability of component failure;

[0026] Use the weighted Euclidean distance as the observation evidence to update the node posterior probability;

[0027] According to the maximum posterior probability criterion, output the confidence of the potential fault component.

[0028] The present invention also proposes a logic board fault location method, including:

[0029] Use a high-definition camera device to obtain the surface image data of the logic board, perform physical fault detection on the surface image data through an image recognition model, and map the physical fault points to the corresponding points on the logic board topology diagram;

[0030] Collect the real-time electrical signal data of the test points on the logic board through an electrical signal probe;

[0031] Calculate the weighted Euclidean distance between the real-time electrical signal data and the pre-stored historical electrical signal data, and determine the abnormal signal node based on a preset fluctuation threshold;

[0032] According to the topological position of the abnormal signal node, combine the pre-constructed fault knowledge graph and Bayesian network to perform fault component tracking to obtain the confidence of each component inside the abnormal signal node area; output the component with the highest confidence as the fault component and determine the fault type, and map the fault points of the fault component to the corresponding points on the logic board topology diagram;

[0033] Collect the fault points and fault types, generate fault repair suggestions in combination with the fault knowledge base, and print a fault report.

[0034] Further, the physical fault detection of the surface image data includes:

[0035] Use a high-definition camera device to capture the surface image data of the logic board; preprocess the surface image data to obtain preprocessed data; input the preprocessed data into a pre-trained image recognition model; the image recognition model outputs the physical fault type and the physical fault location.

[0036] Further, the electrical signal data includes voltage signals, current signals, and frequency signals, and the calculation formula for the weighted Euclidean distance is:

[0037]

[0038] where D represents the weighted Euclidean distance, U r , I r and f r are the real-time voltage signal, real-time current signal, and real-time frequency signal respectively, U h , I h and f h are the historical voltage signal, historical current signal, and historical frequency signal respectively, and α represents the voltage distance weight, and β represents the composite distance weight.

[0039] Further, the component fault tracing process includes:

[0040] According to the position of the abnormal signal node in the logic board topology diagram, generate an upstream power supply path and a downstream load path along the signal transmission direction as candidate fault paths;

[0041] Based on a pre-constructed fault knowledge graph, trace the candidate fault paths and locate potential fault components;

[0042] Use a Bayesian network to calculate the confidence of each potential fault component and output it.

[0043] Further, the calculation process of the Bayesian network includes:

[0044] Construct Bayesian network nodes, and the Bayesian network nodes include abnormal signal nodes, potential fault components, and fault types;

[0045] Based on the fault knowledge graph, set the initial prior probability of component failure;

[0046] Use the weighted Euclidean distance as the observed evidence to update the posterior probability of the node;

[0047] Output the confidence of the potential fault component according to the maximum posterior probability criterion.

[0048] The beneficial effects of the present invention are:

[0049] 1. The present invention introduces the weighted Euclidean distance to evaluate the detection points of the logic board. Compared with the traditional Euclidean distance, the weighted Euclidean distance can more accurately consider the relative importance of different signals for fault judgment. By assigning different weights to different signals, the weighted Euclidean distance can give more priority to the voltage signals that are most critical for fault diagnosis. Thus, in the case of large signal fluctuations or interference from multiple signals, it can still effectively identify the most influential fault features, avoid the overall judgment being affected by the instability or noise of a certain signal, and improve the accuracy and reliability of fault location.

[0050] 2. The present invention uses a Bayesian network to reason and locate the faulty components of abnormal signal nodes. By combining the observed evidence of real-time signals and prior fault knowledge, it dynamically updates the posterior probabilities of each potential faulty component, thereby accurately judging the faulty components and their fault modes. This process can output the most likely faulty component based on the maximum posterior probability criterion and give the corresponding confidence level, improving the accuracy, reliability, and decision support ability of fault diagnosis.

[0051] 3. The present invention detects and locates the obvious physical faults on the surface of the logic board through an image recognition model, and detects and locates the hidden component faults in the logic board components through the weighted Euclidean distance, fault knowledge graph, and Bayesian network. By combining physical faults and component faults, more comprehensive and accurate fault diagnosis can be achieved. This method can not only identify the visible faults on the surface, but also locate potential component problems through electrical signal analysis and probability reasoning, thereby improving the accuracy of fault location, reducing the probability of missed detection, and accelerating the speed of fault troubleshooting and repair, ultimately improving the reliability and maintenance efficiency of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention, but do not constitute a limitation to the present invention. In the drawings:

[0053] Figure 1 is a schematic structural diagram of a logic board fault location device provided by the present invention;

[0054] Figure 2 is a calculation flow chart of a Bayesian network provided by the present invention;

[0055] Figure 3 is a flow chart of a logic board fault location method provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0056] The following describes the preferred embodiments of the present invention with reference to the drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0057] Example 1

[0058] A logic board fault location device, as Figure 1 shown, includes:

[0059] A physical fault detection module, which is used to obtain the surface image data of the logic board by using a high-definition camera device, perform physical fault detection on the surface image data through an image recognition model, and map the physical fault points to the corresponding points on the logic board topology diagram;

[0060] Further, the physical fault detection of the surface image data includes:

[0061] Using a high-definition camera device to capture the surface image data of the logic board; preprocessing the surface image data to obtain preprocessed data; inputting the preprocessed data into a pre-trained image recognition model; the image recognition model outputs the physical fault type and physical fault points.

[0062] Specifically, the resolution of the high-definition camera device is not less than 20 million pixels, and it is equipped with a circularly polarized light source. The image acquisition covers the entire surface of the logic board, including all components, welding points, and circuits and other key areas; the preprocessing of the surface image data includes using filtering algorithms (such as Gaussian filtering, mean filtering, etc.) to remove the noise in the image and adjust the contrast of the image to make physical faults (such as pin breaks, component burns, or solder joint drops, etc.) more prominent; the pre-trained model is an object detection model, which can be a detection model of the ResNet, VIT, or YOLO series. In this embodiment, the YOLO v5 model is preferably used, and the pre-trained model has completed the training of the logic board physical fault data.

[0063] This solution accurately identifies the physical fault type and fault points on the logic board by collecting the surface image of the logic board and combining image preprocessing technology and a pre-trained object detection model, and then realizes the troubleshooting and location of obvious physical faults on the surface of the logic board.

[0064] A component fault detection module, including:

[0065] A data acquisition sub-module, which is used to collect the real-time electrical signal data of the test points on the logic board through an electrical signal probe;

[0066] Further, the electrical signal probe is a multi-channel probe array, which supports the detection of voltage (0 - 50V), current (0 - 10A), and frequency (0 - 100MHz) ranges; the test points include the gate drive circuit, source drive circuit, timing control circuit, DC-DC conversion circuit, and gamma correction circuit.

[0067] A fault analysis sub-module, which is used to calculate the weighted Euclidean distance between the real-time electrical signal data and the pre-stored historical electrical signal data, and determine abnormal signal nodes based on a preset fluctuation threshold;

[0068] Further, the electrical signal data includes voltage signals, current signals and frequency signals, and the calculation formula of the weighted Euclidean distance is:

[0069]

[0070] where D represents the weighted Euclidean distance, U r 、I r and f r are the real-time voltage signal, real-time current signal and real-time frequency signal respectively, U h 、I h and f h are the historical voltage signal, historical current signal and historical frequency signal respectively, α represents the voltage distance weight, and β represents the composite distance weight.

[0071] Specifically, α and β will change with the change of the test point. In a feasible implementation manner, in the gate drive circuit, α = 0.75 and β = 0.25; U h 、I h and f h are the means of the data in the historical electrical signal database respectively, and the fluctuation threshold Wt satisfies the following formula:

[0072]

[0073] By calculating the weighted Euclidean distance between the real-time electrical signal data and the pre-stored historical electrical signal data, the abnormal degree of the current voltage, current and frequency signals can be accurately evaluated. By setting the fluctuation threshold, abnormal signal nodes can be effectively determined, and potential faults existing in the system can be identified in time. This measurement method based on the weighted Euclidean distance can consider the relative importance of different signals and improve the accuracy and sensitivity of fault detection.

[0074] A fault location sub-module, which is used to track fault components according to the topological position of the abnormal signal node, in combination with a pre-constructed fault knowledge graph and a Bayesian network, so as to obtain the confidence of each component inside the abnormal signal node area; output the component with the highest confidence as the fault component and judge the fault type, and map the fault point of the fault component to the corresponding point on the logic board topology diagram;

[0075] Further, the component fault tracking process is as Figure 2 shown, including:

[0076] Generate an upstream power supply path and a downstream load path along the signal transmission direction as candidate fault paths according to the position of the abnormal signal node in the logic board topology diagram;

[0077] Based on a pre-constructed fault knowledge graph, trace the candidate fault paths and locate potential fault components;

[0078] Use a Bayesian network to calculate the confidence levels of each potential fault component and output them.

[0079] Specifically, the upstream power supply path is the source of signal transmission, usually a power module, and the downstream load path is the final output end of the signal, usually a load or an execution component. The fault knowledge graph contains the dependency relationships, fault modes, fault paths, and component parameter ranges among components; in a feasible implementation, the detected abnormal signal node is a timing control circuit. After detection, it is determined that the downstream load path is the candidate fault path. Combining with the pre-constructed fault knowledge graph, the potential fault components located include a program memory, a signal processor, and a capacitor; use a Bayesian network to calculate the confidence levels of each potential fault component and output them.

[0080] By generating an upstream power supply path and a downstream load path along the signal transmission path according to the position of the abnormal signal node in the logic board topology diagram, the candidate fault paths can be accurately traced. This process, combined with the pre-constructed fault knowledge graph, can effectively locate potential fault components, calculate the fault confidence levels of each component through a Bayesian network, and finally output the most likely fault components and their confidence levels. This method improves the accuracy and efficiency of fault location, can quickly and accurately identify the fault source, reduce the time for fault troubleshooting, and optimize the maintenance decision-making.

[0081] Furthermore, the calculation process of the Bayesian network includes:

[0082] Construct Bayesian network nodes, where the Bayesian network nodes include abnormal signal nodes, potential fault components, and fault types;

[0083] Set the initial prior probability of component failure based on the fault knowledge graph;

[0084] Use the weighted Euclidean distance as the observed evidence to update the node posterior probability;

[0085] Output the confidence level of the potential fault component according to the maximum posterior probability criterion.

[0086] Furthermore, Bayesian nodes are established with abnormal signal nodes, potential fault components, and fault types; based on the fault knowledge graph and historical data, an initial prior probability of failure is set for each component. For example, if a capacitor has a higher probability of failure under certain high-load conditions, a relatively high prior probability can be set for it; the weighted Euclidean distance is used to measure the deviation between real-time electrical signal data and historical data, and these distance values can be used as the observed evidence of the Bayesian network to update the posterior probability of the nodes. According to Bayes' theorem, the posterior probability update formula for each potential fault component is as follows:

[0087]

[0088] Among them, P(C|E) represents the posterior probability of component C failing given the observed evidence E, P(E|C) represents the probability of observing the evidence E (i.e., the weighted Euclidean distance) under the condition that component C fails, P(C) is the prior probability of component C, and P(E) is the marginal probability of evidence E; according to the maximum posterior probability criterion, the potential fault component with the maximum posterior probability is selected, and the confidence level of this component is output.

[0089] By constructing Bayesian network nodes, abnormal signal nodes, potential fault components, and fault types are effectively connected, and the initial prior probability of component failure is set using the fault knowledge graph. By introducing the weighted Euclidean distance as the observed evidence, the posterior probability of the nodes can be dynamically updated to reflect the changes in the system state in real time. Finally, based on the maximum posterior probability criterion, the confidence level of the potential fault component is accurately output, thereby improving the accuracy and reliability of fault diagnosis, helping to quickly locate the problem source, and supporting more targeted maintenance decisions.

[0090] The fault report generation module is used to collect the fault location and fault type, generate fault repair suggestions in combination with the fault knowledge base, and print the fault report.

[0091] Embodiment 2

[0092] A certain electronic equipment R & D company adopted a logic board fault location method proposed by the present invention to achieve intelligent and efficient motherboard fault location, as Figure 3 shown, including:

[0093] Using a high-definition camera device to obtain the surface image data of the logic board, performing physical fault detection on the surface image data through an image recognition model, and mapping the physical fault points to the corresponding points on the logic board topology diagram;

[0094] Collecting the real-time electrical signal data of the test points on the logic board through an electrical signal probe;

[0095] Calculate the weighted Euclidean distance between the real-time electrical signal data and the pre-stored historical electrical signal data, and determine the abnormal signal nodes based on a preset fluctuation threshold;

[0096] According to the topological position of the abnormal signal nodes, combine the pre-constructed fault knowledge graph and Bayesian network to track the faulty components, so as to obtain the confidence levels of each component inside the area of the abnormal signal nodes; Output the component with the highest confidence level as the faulty component and determine the fault type, and map the fault points of the faulty component to the corresponding points on the logic board topology diagram;

[0097] Collect the fault points and fault types, generate fault repair suggestions in combination with the fault knowledge base, and print a fault report.

[0098] Furthermore, the physical fault detection of the surface image data includes:

[0099] Use a high-definition camera device to capture the surface image data of the logic board; preprocess the surface image data to obtain preprocessed data; input the preprocessed data into a pre-trained image recognition model; The image recognition model outputs the physical fault type and physical fault points.

[0100] Furthermore, the electrical signal data includes voltage signals, current signals, and frequency signals, and the calculation formula for the weighted Euclidean distance is:

[0101]

[0102] where D represents the weighted Euclidean distance, U r 、I r and f r are the real-time voltage signal, real-time current signal, and real-time frequency signal respectively, U h 、I h and f h are the historical voltage signal, historical current signal, and historical frequency signal respectively, and α represents the voltage distance weight, and β represents the composite distance weight.

[0103] Furthermore, the component fault tracking process includes:

[0104] According to the position of the abnormal signal nodes in the logic board topology diagram, generate an upstream power supply path and a downstream load path along the signal transmission direction as candidate fault paths;

[0105] Based on the pre-constructed fault knowledge graph, track the candidate fault paths and locate the potential faulty components;

[0106] Use the Bayesian network to calculate the confidence levels of each potential faulty component and output them.

[0107] Furthermore, the calculation process of the Bayesian network includes:

[0108] Construct Bayesian network nodes, where the Bayesian network nodes include abnormal signal nodes, potential failure components, and failure types;

[0109] Set the initial prior probability of component failure based on the fault knowledge graph;

[0110] Use the weighted Euclidean distance as the observed evidence to update the node posterior probability;

[0111] Output the confidence of the potential failure component according to the maximum posterior probability criterion.

[0112] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A logic board fault location device, characterized in that: include: A physical fault detection module is used to obtain surface image data of the logic board using a high-definition camera device, perform physical fault detection on the surface image data through image recognition model detection, and map the physical fault point to the corresponding point of the logic board topology map; Component fault detection module, including: A data acquisition submodule, used to collect real-time electrical signal data of test points on the logic board through an electrical signal probe; A fault analysis submodule, used to calculate the weighted Euclidean distance between the real-time electrical signal data and the pre-stored historical electrical signal data, and determine abnormal signal nodes based on a preset fluctuation threshold; The fault location submodule is used to track the fault component according to the topological position of the abnormal signal node, combined with the pre-built fault knowledge graph and Bayesian network, to obtain the confidence of each component inside the abnormal signal node area; output the component with the highest confidence as the fault component and determine the fault type, and map the fault point of the fault component to the corresponding point of the logic board topology map; The fault report generation module is used to collect fault locations and fault types, generate fault repair suggestions based on the fault knowledge base, and print fault reports.

2. A logic board fault location device according to claim 1, characterized in that: The surface image data is used to perform physical fault detection, including: Use a high-definition camera to capture surface image data of the logic board; preprocess the surface image data to obtain preprocessed data; input the preprocessed data into a pre-trained image recognition model; and the image recognition model outputs a physical fault type and a physical fault location.

3. A logic board fault location device according to claim 1, characterized in that: The electrical signal data includes a voltage signal, a current signal and a frequency signal, and the calculation formula of the weighted Euclidean distance is: Wherein, D represents the weighted Euclidean distance, U r ,I r and f r They are real-time voltage signal, real-time current signal and real-time frequency signal, U h ,I h and f h are historical voltage signal, historical current signal and historical frequency signal respectively, α represents voltage distance weight, and β represents composite distance weight.

4. A logic board fault location device according to claim 1, characterized in that: The component failure tracing process includes: According to the position of the abnormal signal node in the logic board topology diagram, an upstream power supply path and a downstream load path are generated along the signal transmission direction as candidate fault paths; Based on the pre-built fault knowledge graph, it tracks candidate fault paths and locates potential faulty components. The confidence of each potential fault component is calculated and output using a Bayesian network.

5. A logic board fault location device according to claim 4, characterized in that: The calculation process of the Bayesian network includes: Constructing a Bayesian network node, wherein the Bayesian network node includes an abnormal signal node, a potential fault component, and a fault type; Set the initial prior probability of component failure based on the fault knowledge graph; Use the weighted Euclidean distance as observation evidence to update the node posterior probability; The confidence level of the potential faulty component is output according to the maximum a posteriori probability criterion.

6. A logic board fault location method, characterized in that: include: Using a high-definition camera to obtain surface image data of the logic board, performing physical fault detection on the surface image data through image recognition model detection, and mapping the physical fault points to corresponding points in the logic board topology map; Collect real-time electrical signal data of test points on the logic board through electrical signal probes; Calculating the weighted Euclidean distance between the real-time electrical signal data and the pre-stored historical electrical signal data, and determining abnormal signal nodes based on a preset fluctuation threshold; According to the topological position of the abnormal signal node, the fault component is tracked in combination with the pre-built fault knowledge graph and the Bayesian network to obtain the confidence of each component inside the abnormal signal node area; the component with the highest confidence is output as the faulty component and the fault type is determined, and the fault point of the faulty component is mapped to the corresponding point of the logic board topology map; Collect fault locations and fault types, generate fault repair suggestions based on the fault knowledge base, and print fault reports.

7. A logic board fault location method according to claim 6, characterized in that: The surface image data is used to perform physical fault detection, including: Use a high-definition camera to capture surface image data of the logic board; preprocess the surface image data to obtain preprocessed data; input the preprocessed data into a pre-trained image recognition model; and the image recognition model outputs a physical fault type and a physical fault location.

8. A logic board fault location method according to claim 6, characterized in that: The electrical signal data includes a voltage signal, a current signal and a frequency signal, and the calculation formula of the weighted Euclidean distance is: Wherein, D represents the weighted Euclidean distance, U r ,I r and f r They are real-time voltage signal, real-time current signal and real-time frequency signal, U h ,I h and f h are historical voltage signal, historical current signal and historical frequency signal respectively, α represents voltage distance weight, and β represents composite distance weight.

9. A logic board fault location method according to claim 6, characterized in that: The component failure tracing process includes: According to the position of the abnormal signal node in the logic board topology diagram, an upstream power supply path and a downstream load path are generated along the signal transmission direction as candidate fault paths; Based on the pre-built fault knowledge graph, it tracks candidate fault paths and locates potential faulty components. The confidence of each potential fault component is calculated and output using a Bayesian network.

10. A logic board fault location method according to claim 9, characterized in that: The calculation process of the Bayesian network includes: Constructing a Bayesian network node, wherein the Bayesian network node includes an abnormal signal node, a potential fault component, and a fault type; Set the initial prior probability of component failure based on the fault knowledge graph; Use the weighted Euclidean distance as observation evidence to update the node posterior probability; The confidence level of the potential faulty component is output according to the maximum a posteriori probability criterion.

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