Gate drive circuit, power-on startup method, display panel, and display device

Abstract

The present application discloses a gate drive circuit, a power-on startup method, a display panel, and a display device. The gate drive circuit includes: a GOA module, a level conversion module, and a timing control module. The pull-up unit of the timing control module is used to provide a second clock signal of a first frequency to the level conversion module before the level conversion module is powered on; and is used to provide a second clock signal of a second frequency to the level conversion module after the level conversion module is powered on. By firstly making the timing control module provide the second clock signal of the first frequency to the level conversion module before the level conversion module is powered on and after the level conversion module is powered on, it is possible to enable the level conversion module to output an inverted third clock signal and a fourth clock signal according to the second clock signal of the first frequency within a short period of time after the level conversion module is powered on, thereby avoiding the situation where the third clock signal and the fourth clock signal are both high or both low.

Description

Technical Field

[0001] The present application belongs to the technical field of display devices, and in particular relates to a gate drive circuit, a power-on startup method, a display panel, and a display device. Background Art

[0002] Liquid crystal panels are a key component of liquid crystal display devices. These panels consist of rows and columns of pixel units. During operation, a row driver circuit provides gate drive signals to the corresponding pixel circuits for each row of pixels, completing row scanning and enabling the display of images. Common row driver circuits include gate-on-array (GOA) and chip-on-film (COF) driver circuits. GOA driver circuits are widely used in display devices due to their narrow bezels and low cost.

[0003] However, the level conversion chip used in the existing GOA drive circuit may have abnormal output when powered on, causing some switching devices to be mis-conducted and triggering overcurrent protection. Summary of the Invention

[0004] The purpose of the present application is to provide a gate drive circuit, a power-on startup method, a display panel and a display device, aiming to solve the problem of false triggering of overcurrent protection in traditional display panels.

[0005] A first aspect of an embodiment of the present application provides a gate drive circuit, the gate drive circuit comprising: a GOA module, the GOA module comprising an output unit and a pull-down maintenance unit, the output unit being configured to generate and output a scan signal based on a first clock signal when a voltage at a charging node of the GOA module is greater than or equal to a preset threshold, the pull-down maintenance unit being connected between the charging node and a low-level wiring connection; a timing control module being connected to a level conversion module, and being configured to provide a second clock signal of a first frequency to the level conversion module from before the level conversion module is powered on to after the level conversion module is powered on; and being configured to adjust the frequency of the second clock signal from the first frequency to a second frequency after the level conversion module is powered on, the second frequency being lower than the first frequency; the level conversion module being connected to the pull-down maintenance unit via a half-bridge switching circuit of the GOA module, the level conversion module being configured to output an inverted third clock signal and a fourth clock signal to the pull-down maintenance unit based on the second clock signal, the third clock signal and the fourth clock signal being configured to control the on and off of the pull-down maintenance unit via the half-bridge switching circuit.

[0006] In one embodiment, the half-bridge switching circuit includes a first switching device and a second switching device, and the pull-down maintaining unit includes a third switching device; the first end of the first switching device is connected to the high-level wiring, the second end of the first switching device is connected to the control end of the third switching device, the first end of the second switching device is connected to the control end of the third switching device, the second end of the second switching device is connected to the low-level wiring, and the control end of the first switching device and the control end of the second switching device are both connected to the level conversion module to respectively access the third clock signal and the fourth clock signal; the first end of the third switching device is connected to the charging node, and the second end of the third switching device is connected to the low-level wiring.

[0007] In one embodiment, the output unit includes a fourth switching device and a bootstrap capacitor; the first end of the bootstrap capacitor is connected to the charging node, the first end of the fourth switching device is used to access the first clock signal, the second end of the fourth switching device is connected to the second end of the bootstrap capacitor, the control end of the fourth switching device is connected to the charging node, and the second end of the fourth switching device is used to output the scan signal.

[0008] In one embodiment, the GOA module further includes a pull-up unit, which is connected between the charging node and the high-level trace, and is used to pull up the voltage of the charging node to a high level before the output unit generates a high-level pulse of the scanning signal according to the high-level pulse of the first clock signal.

[0009] In one embodiment, the gate driving circuit further includes a pull-down unit; the pull-down unit is configured to pull down the voltage of the output end of the output unit to a low level before the next rising edge of the first clock signal following the falling edge of the scan signal.

[0010] In one embodiment, the timing control module is further configured to output a fifth clock signal to the level conversion module after outputting the second clock signal of the second frequency, and the level conversion module is configured to output the first clock signal according to the fifth clock signal.

[0011] In one embodiment, the level conversion module includes a level conversion unit and an enable control unit; the enable control unit is connected to the level conversion unit and the timing control module, and is used to output an enable signal after the timing control module outputs the second clock signal of the second frequency and the input voltage of the gate drive circuit is greater than a first preset voltage; the level conversion unit is used to power on and start after receiving the enable signal.

[0012] A second aspect of an embodiment of the present application provides a power-on startup method, which is applied to a gate drive circuit. The gate drive circuit includes: a GOA module, the GOA module including an output unit and a pull-down maintenance unit, the output unit being configured to generate and output a scan signal based on a first clock signal when a voltage at a charging node of the GOA module is greater than or equal to a preset threshold, the pull-down maintenance unit being connected to the charging node and a low-level trace; a level conversion module being connected to the pull-down maintenance unit via a half-bridge switch circuit, the level conversion module being configured to generate and output an inverted third clock signal and a fourth clock signal to the pull-down maintenance unit based on a second clock signal, the third clock signal and the fourth clock signal being configured to control the on and off of the pull-down maintenance unit via the half-bridge switch circuit; the power-on startup method comprising: providing the second clock signal of a first frequency to the level conversion module before the level conversion module is powered on and after the level conversion module is powered on; adjusting the frequency of the second clock signal from the first frequency to a second frequency after the level conversion module is powered on; the second frequency being lower than the first frequency.

[0013] A third aspect of an embodiment of the present application provides a display panel, comprising a plurality of cascaded gate drive circuits as described above, wherein the gate drive circuit of the nth level is used to generate and output a scanning signal applied to the nth row of pixel circuits in the display panel based on a first clock signal within a corresponding scanning period.

[0014] In one embodiment, the display panel also includes a power supply circuit, which is used to generate and output an operating voltage and a high-level voltage based on an input voltage; the gate drive circuit also includes a feedback module, which is connected to the timing control module of the gate drive circuit, and the feedback module is used to provide a feedback voltage to the timing control module based on the operating voltage, and the timing control module is used to output a second clock signal after the feedback voltage is greater than a second preset voltage; the time node when the feedback voltage reaches the second preset voltage is prior to the first rising edge of the high-level voltage.

[0015] A fourth aspect of the embodiments of the present application provides a display device, comprising the display panel as described above.

[0016] Compared with the prior art, the embodiments of the present application have the following advantages: by firstly providing the second clock signal of the first frequency to the level conversion module before the level conversion module is powered on and after the level conversion module is powered on, the level conversion module can be enabled to output the inverted third clock signal and the fourth clock signal according to the second clock signal of the first frequency in a short time after the level conversion module is powered on, thereby avoiding the situation where the third clock signal and the fourth clock signal are both high or both low, thereby avoiding the situation where the two switching devices of the half-bridge switching circuit are turned on at the same time, resulting in triggering the overcurrent protection of the gate drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a gate drive circuit provided in one embodiment of the present application;

[0018] Figure 2 Waveform diagrams of a high-level voltage, a low-level voltage, a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, and a fifth clock signal provided in an embodiment of the present application;

[0019] Figure 3 A specific circuit diagram of the GOA module provided in one embodiment of the present application;

[0020] Figure 4 A specific circuit diagram of a level conversion module and a feedback module provided in one embodiment of the present application;

[0021] Figure 5 A flowchart of a power-on startup method provided in one embodiment of the present application;

[0022] Figure 6 A schematic diagram of a display panel provided in one embodiment of the present application;

[0023] Figure 7 A schematic diagram of a display device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0025] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0026] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0028] At present, a display panel generally includes multiple gate drive circuits. One gate drive circuit can be connected to a row of pixel circuits. One gate drive circuit can be used to generate and output a scan signal applied to the corresponding pixel circuit based on a clock signal within a corresponding scan cycle. The scan cycle specifically corresponds to the scan signal that each gate drive circuit needs to output. Within the scan cycle, the corresponding clock signal only includes one high-level pulse. The gate drive circuit generally needs to output a scan signal with the same high-level pulse based on a high-level pulse of the clock signal within the corresponding scan cycle. There is a phase difference between the scan signals output by different gate drive circuits. When the corresponding pixel circuit receives the scan signal, the pixel circuit will obtain the corresponding part of the Data signal from the continuous Data signal when the voltage of the scan signal is greater than the set threshold, thereby ultimately realizing the row-by-row scanning of the display panel.

[0029] Figure 1 A schematic diagram of a gate drive circuit provided in an embodiment of the present application is shown. For ease of explanation, only the portion related to this embodiment is shown, which is described in detail as follows:

[0030] A gate driving circuit 10 is applied to a display panel. The display panel includes a plurality of gate driving circuits 10 .

[0031] The gate driving circuit 10 includes a GOA module 100 , a level conversion module 200 and a timing control module 300 .

[0032] The GOA module 100 includes an output unit 110 and a pull-down maintenance unit 120. The output unit 110 is used to generate and output a scan signal based on a first clock signal when the voltage of the charging node PU of the GOA module 100 is greater than or equal to a preset threshold. The pull-down maintenance unit 120 is connected between the charging node PU and the low-level trace.

[0033] The level conversion module 200 is connected to the pull-down maintenance unit 120 via the half-bridge switch circuit 130. The level conversion module 200 is configured to output inverted third and fourth clock signals LC1 and LC2 to the pull-down maintenance unit 120 based on the second clock signal LC_In. The third and fourth clock signals LC1 and LC2 are used to control the on and off states of the pull-down maintenance unit 120 via the half-bridge switch circuit 130. When the pull-down maintenance unit 120 is off, the charging node PU is disconnected from the low-level trace. When the pull-down maintenance unit 120 is on, the charging node PU is connected to the low-level trace, thereby pulling the voltage of the charging node PU down to a low level.

[0034] The timing control module 300 is connected to the level conversion module 200 and is configured to provide the second clock signal LC_In of the first frequency to the level conversion module 200 from before the level conversion module 200 is powered on to after the level conversion module 200 is powered on; and to provide the second clock signal LC_In of the second frequency to the level conversion module 200 after the level conversion module 200 is powered on; the second frequency is lower than the first frequency.

[0035] Specifically, the timing control module 300 may provide the second clock signal LC_In of the second frequency to the level conversion module 200 after the level conversion module 200 is powered on for a certain period of time.

[0036] In some embodiments, the timing control module 300 can be configured to provide the second clock signal LC_In at a second frequency to the level shifter module 200 after providing the second clock signal LC_In at a first frequency with a preset duration to the level shifter module 200. The frequency switching time node of the second clock signal LC_In can be adaptively set based on the actual situation and requirements of the gate driver circuit 10.

[0037] The specific waveforms of the high-level voltage VGH on the high-level trace, the low-level voltage VGL on the low-level trace, the first clock signal CK, the second clock signal LC_In, the third clock signal LC1, the fourth clock signal LC2 and the fifth clock signal CPV are as follows: Figure 2 shown.

[0038] At time T1 , the level conversion module 200 is powered on and starts up, and outputs a corresponding third clock signal LC1 and a fourth clock signal LC2 according to the second clock signal LC_In of the first frequency.

[0039] At time T2 , the frequency of the second clock signal LC_In is switched from the first frequency to the second frequency. Accordingly, the level conversion module 200 outputs the corresponding third clock signal LC1 and fourth clock signal LC2 according to the second clock signal LC_In of the second frequency.

[0040] The level conversion module 200 may specifically include a level conversion chip. The timing control module 300 may specifically include a logic control unit, such as a microcontroller such as a chip or a single chip microcomputer.

[0041] It should be noted that the third clock signal LC1 and the fourth clock signal LC2 can be used to provide the two switching devices of the half-bridge switch circuit 130 connected between the high-level trace and the low-level trace, respectively, to generate corresponding square wave signals at the connection point of the two switching devices to further control the other switching devices. When the level conversion module 200 is powered on and started, some level conversion chips may output the third clock signal LC1 and the fourth clock signal LC2 in phase when they do not recognize the second clock signal LC_In. If the third clock signal LC1 and the fourth clock signal LC2 are both high or low, this may cause the two switching devices to be turned on simultaneously, causing the high-level trace and the low-level trace to be connected, triggering the overcurrent protection of the gate drive circuit 10.

[0042] By first ordering the timing control module 300 to provide the second clock signal LC_In of the first frequency to the level conversion module 200 before the level conversion module 200 is powered on and after the level conversion module 200 is powered on, the level conversion module 200 can output the inverted third clock signal LC1 and the fourth clock signal LC2 according to the second clock signal LC_In of the first frequency within a short period of time after the level conversion module 200 is powered on, thereby avoiding the situation where the third clock signal LC1 and the fourth clock signal LC2 are both high or both low, thereby avoiding the situation where the two switching devices of the half-bridge switch circuit 130 are turned on at the same time, resulting in triggering the overcurrent protection of the gate drive circuit 10.

[0043] It should be noted that during the process of the gate drive circuit 10 receiving the input voltage and generating the corresponding operating voltage, the actual power-on startup time of the level conversion module 200 is affected by various factors, making it difficult to determine the actual power-on startup time of the level conversion module 200. The second clock signal LC_In of the first frequency needs to be continuously output for a period of time to cover all possible power-on startup times of the level conversion module 200. Therefore, the duration of the second clock signal LC_In of the first frequency needs to be determined based on actual conditions.

[0044] At the same time, if device performance permits, the higher the first frequency, the faster the level conversion module 200 will be taken over after the level conversion module 200 is powered on and started, so as to adjust the third clock signal LC1 and the fourth clock signal LC2 to an inverted state in the shortest time. Therefore, in some embodiments, the first frequency is the maximum frequency of the signal that the timing control module 300 can output.

[0045] It is understandable that the second frequency needs to be determined according to the refresh rate of the display panel, which is not limited in this embodiment.

[0046] In some embodiments, the high level voltage of the second clock signal LC_In is equal to the operating voltage of the gate driving circuit 10 , and the high level voltages of the third clock signal LC1 and the fourth clock signal LC2 are equal to the voltage of the high level wiring.

[0047] In one embodiment, the structures of the gate driving circuits 10 are the same. Figure 3 The GOA module 100 of the n-th stage gate driver circuit 10 is shown. For ease of explanation, the n-th stage gate driver circuit 10 is used as an example in the following embodiments. The half-bridge switch circuit 130 includes a first switch device Q1 and a second switch device Q2, and the pull-down maintenance unit 120 includes a third switch device Q3.

[0048] A first end of the first switching device Q1 is connected to a high-level wiring, a second end of the first switching device Q1 is connected to a control end of the third switching device Q3 of the GOA module 100, a first end of the second switching device Q2 is connected to a control end of the third switching device Q3, a second end of the second switching device Q2 is connected to a low-level wiring, and the control end of the first switching device Q1 and the control end of the second switching device Q2 are both connected to the level conversion module 200 to receive the third clock signal LC1 and the fourth clock signal LC2, respectively.

[0049] A first end of the third switch device Q3 is connected to the charging node PU, and a second end of the third switch device Q3 is connected to the low level wiring.

[0050] Since the third clock signal LC1 and the fourth clock signal LC2 are in phase with each other under normal operation, only one of the first switching device Q1 and the second switching device Q2 is turned on at the same time. When the first switching device Q1 is turned on and the second switching device Q2 is turned off, the half-bridge switching circuit 130 can provide a high level to the control end of the third switching device Q3. When the first switching device Q1 is turned off and the second switching device Q2 is turned on, the half-bridge switching circuit 130 can provide a low level to the control end of the third switching device Q3.

[0051] Specifically, in some embodiments, the first switching device Q1 , the second switching device Q2 , and the third switching device Q3 may all be N-type transistors.

[0052] In one embodiment, if Figure 3 As shown, the output unit 110 includes a fourth switching device Q4 and a bootstrap capacitor C1.

[0053] A first end of the bootstrap capacitor C1 is connected to the charging node PU, a first end of the fourth switch device Q4 is used to access the first clock signal CK, a second end of the fourth switch device Q4 is connected to the second end of the bootstrap capacitor C1, a control end of the fourth switch device Q4 is connected to the charging node PU, and a second end of the fourth switch device Q4 is used to output a scan signal.

[0054] Specifically, the fourth switching device Q4 is configured to be turned on when a voltage difference between a voltage at the control terminal of the fourth switching device Q4 and the first terminal of the fourth switching device Q4 is greater than a turn-on threshold.

[0055] It is understandable that, in the corresponding scan cycle, before the output unit 110 outputs the corresponding scan signal according to a high-level pulse of the first clock signal CK, it is necessary to charge the charging node PU to turn on the fourth switch device Q4.

[0056] In one embodiment, if Figure 3 As shown, the GOA module 100 also includes a pull-up unit 140, which is connected between the charging node PU and the high-level trace. The pull-up unit 140 is used to pull up the voltage of the charging node PU to a high level before the output unit 110 generates a high-level pulse of the scanning signal according to the high-level pulse of the first clock signal in the scanning cycle.

[0057] The pull-up unit 140 may be configured to charge the charging node PU in a corresponding scanning period to output a scanning signal.

[0058] Specifically, the pull-up unit 140 may include a fifth switching device Q5, a first end of the fifth switching device Q5 is connected to the high-level wiring, a second end of the fifth switching device Q5 is connected to the charging node PU, and a control end of the fifth switching device Q5 can be connected to a scan signal or a cascade control signal output by other gate drive circuits 10. The signal connected to the control end of the fifth switching device Q5 can be determined according to the timing and waveform of the scan signal or cascade control signal output by each actual gate drive circuit 10.

[0059] In some embodiments, in a plurality of cascaded gate driving circuits 10 , the pull-up unit 140 of the nth stage may be connected to the gate driving circuit 10 of the n-1th stage to control the pull-up unit 140 of the nth stage according to the scan signal G(n-1) output by the gate driving circuit 10 of the n-1th stage.

[0060] In one embodiment, if Figure 3 As shown, the gate driving circuit 10 further includes a pull-down unit 150 .

[0061] The pull-down unit 150 is configured to pull down the voltage of the output terminal of the output unit 110 to a low level before the next rising edge of the first clock signal following the falling edge of the scan signal.

[0062] Since the pixel circuit connected to the gate driving circuit 10 generally has a certain capacitance, the pull-down unit 150 is used to quickly release the charge at the output end of the output unit 110 to avoid abnormal scanning signals.

[0063] Specifically, the pull-down unit 150 includes a sixth switching device Q6, a first end of the sixth switching device Q6 is connected to the output end of the output unit 110, a second end of the sixth switching device Q6 is connected to the low-level wiring, and the control end of the sixth switching device Q6 can be connected to the scan signal or cascade control signal output by other gate drive circuits 10. The signal connected to the control end of the sixth switching device Q6 can be determined according to the timing and waveform of the scan signal or cascade control signal output by each actual gate drive circuit 10.

[0064] In some embodiments, in a plurality of cascaded gate driving circuits 10 , the pull-down unit 150 of the nth stage may be connected to the gate driving circuit 10 of the n+1th stage to control the pull-down unit 150 of the nth stage according to the scan signal G(n+1) output by the gate driving circuit 10 of the n+1th stage.

[0065] In one embodiment, the timing control module 300 is further configured to output a fifth clock signal CPV to the level conversion module 200 after outputting the second clock signal LC_In of the second frequency. The level conversion module 200 is configured to output the first clock signal CK according to the fifth clock signal CPV.

[0066] like Figure 2 As shown, at time T3, the timing control module 300 starts to output the fifth clock signal CPV, and the level conversion module 200 is configured to output the first clock signal CK according to the fifth clock signal CPV.

[0067] After the power-on startup of the level conversion module 200 is completed, the level conversion module 200 starts to work smoothly, and then the first clock signal CK can be outputted by the level conversion module 200 to generate the scan signal.

[0068] Specifically, after the timing control module 300 can control the pull-down holding module to pull down the voltage of the charging node PU to a low level through the corresponding second clock signal LC_In, the fifth clock signal CPV is output to avoid the first clock signal CK causing the voltage of the charging node PU to be abnormal through the coupling capacitor between the first end of the fourth switching device Q4 and the charging node PU, thereby causing the fourth switching device Q4 to be mis-turned on.

[0069] In one embodiment, if Figure 4 As shown, the level conversion module 200 includes a level conversion unit 210 and an enable control unit 220. The level conversion unit 210 is configured to power on and start after receiving an enable signal. The enable control unit 220 is connected to the level conversion unit 210 and the timing control module 300, and is configured to output an enable signal after the timing control module 300 outputs a second clock signal LC_In of a second frequency and the input voltage VIN is greater than a first preset voltage.

[0070] It is understandable that the timing control module 300 may provide a control signal to the enable control unit 220 when outputting the second clock signal LC_In of the second frequency, and the enable control unit 220 may output the enable signal according to the control signal.

[0071] In some embodiments, the enabling control unit 220 includes a first resistor R1 , a second resistor R2 , a third resistor R3 , a fourth resistor R4 , a fifth resistor R5 , a seventh switching device Q7 , an eighth switching device Q8 , a ninth switching device Q9 and a voltage detection unit 221 .

[0072] A first end of the first resistor R1 is connected to the input voltage VIN. A second end of the first resistor R1 is connected to the first end of the second resistor R2 and the input end of the voltage detection unit 221, respectively. A second end of the second resistor R2 is grounded. An output end of the voltage detection unit 221 is connected to the control end of the seventh switching device Q7. A first end of the seventh switching device Q7 is connected to the first end of the ninth switching device Q9, the first end of the fifth resistor R5, and the first end of the third resistor R3, respectively. A second end of the seventh switching device Q7 is grounded. A second end of the fifth resistor R5 is connected to the operating voltage VCC. A second end of the third resistor R3 is connected to the control end of the ninth switching device Q9 and the first end of the fourth resistor R4, respectively. A second end of the ninth switching device Q9 is connected to the level shifting unit 210. A second end of the fourth resistor R4 is connected to the first end of the eighth switching device Q8. A second end of the eighth switching device Q8 is grounded. The control end of the eighth switching device Q8 is connected to the timing control module 300.

[0073] The seventh and eighth switching devices Q7 and Q8 are both N-type transistors, and the ninth switching device Q9 is a P-type transistor. The voltage detection unit 221 is configured to control the seventh switching device Q7 to be conductive when the input voltage VIN is less than or equal to a first predetermined voltage. The eighth switching device Q8 is turned on or off according to a control signal from the timing control module 300.

[0074] When the seventh switching device Q7 is turned off and the eighth switching device Q8 and the ninth switching device Q9 are both turned on, the enable control unit 220 may output a corresponding enable signal.

[0075] In some embodiments, the gate drive circuit 10 further includes a feedback module 400, which is connected to the timing control module 300 and is configured to provide a feedback voltage to the timing control module 300 based on the operating voltage VCC. The timing control module 300 may be configured to output a second clock signal after the feedback voltage is greater than a second preset voltage.

[0076] It is understandable that the second preset voltage can be set according to the first preset voltage, or the specific parameters of the feedback module 400 can be configured according to the first preset voltage, so that the timing control module 300 is powered on and started before the level conversion module 200, ensuring that the second clock signal LC_In of the first frequency can be received when the level conversion module 200 is powered on and started.

[0077] In some embodiments, current limiting resistors are provided on both the high-level trace and the low-level trace to limit the current when the first switching device Q1 and the second switching device Q2 are turned on at the same time, thereby avoiding triggering overcurrent protection.

[0078] Figure 5A flowchart of a power-on startup method provided by an embodiment of the present application is shown. For ease of explanation, only the portion related to this embodiment is shown, which is described in detail as follows:

[0079] A power-on startup method is applied to the gate drive circuit 10 as in any of the above embodiments, such as Figure 1 As shown, the gate driving circuit 10 includes a GOA module 100 and a level conversion module 200 .

[0080] The GOA module 100 includes an output unit 110 and a pull-down maintenance unit 120. The output unit 110 is configured to generate and output a scan signal based on a first clock signal CK when the voltage of a charging node PU of the GOA module 100 is greater than or equal to a preset threshold. The pull-down maintenance unit 120 is connected to the charging node PU and a low-level trace.

[0081] The level conversion module 200 is connected to the pull-down maintenance unit 120 through the half-bridge switch circuit 130, and is used to generate and output the inverted third clock signal LC1 and fourth clock signal LC2 to the pull-down maintenance unit 120 according to the second clock signal LC_In. The third clock signal LC1 and the fourth clock signal LC2 are used to control the conduction and cut-off of the pull-down maintenance unit 120 through the half-bridge switch circuit 130;

[0082] The power-on startup method includes: steps S100 to S200.

[0083] Step S100 : before the level conversion module 200 is powered on and after the level conversion module 200 is powered on, providing the second clock signal LC_In of the first frequency to the level conversion module 200 .

[0084] Step S200: After the level conversion module 200 is powered on, a second clock signal LC_In with a second frequency is provided to the level conversion module 200. The second frequency is lower than the first frequency.

[0085] Specifically, in step S200 , after the level conversion module 200 is powered on for a certain period of time, a second clock signal LC_In with a second frequency may be provided to the level conversion module 200 .

[0086] In some embodiments, step S200 may also be configured to provide the second clock signal LC_In of the second frequency to the level conversion module 200 after providing the second clock signal LC_In of the first frequency with a preset duration to the level conversion module 200 .

[0087] It is understandable that the power-on startup method can be specifically implemented by the timing control module 300 of the gate driving circuit 10 .

[0088] By first ordering the timing control module 300 to provide the second clock signal LC_In of the first frequency to the level conversion module 200 before the level conversion module 200 is powered on and after the level conversion module 200 is powered on, the level conversion module 200 can output the inverted third clock signal LC1 and the fourth clock signal LC2 according to the second clock signal LC_In of the first frequency within a short period of time after the level conversion module 200 is powered on, thereby avoiding the situation where the third clock signal LC1 and the fourth clock signal LC2 are both high or both low, thereby avoiding the situation where the two switching devices of the half-bridge switch circuit 130 are turned on at the same time, resulting in triggering the overcurrent protection of the gate drive circuit 10.

[0089] Figure 6 A schematic diagram of a display panel provided in an embodiment of the present application is shown. For ease of explanation, only the portion related to this embodiment is shown, which is described in detail as follows:

[0090] A display panel 20 includes a plurality of cascaded gate drive circuits 10 as in any of the above embodiments and a plurality of pixel circuits 21 corresponding one-to-one to each gate drive circuit 10, wherein the gate drive circuit 10 is connected to the corresponding pixel circuit 21, and the n-th level gate drive circuit 10 is used to generate and output a scanning signal applied to the n-th row pixel circuit 21 based on a first clock signal within a corresponding scanning cycle.

[0091] Since the display panel 20 includes the gate driving circuit 10 of any of the above embodiments, the display panel 20 has the beneficial effects of the gate driving circuit 10 of any of the above embodiments, which will not be described in detail here.

[0092] In some embodiments, the display panel 20 may specifically be a liquid crystal display panel.

[0093] In one embodiment, the display panel 20 further includes a power supply circuit 22, which is used to generate and output an operating voltage VCC, a high-level voltage VGH, and a low-level voltage VGL based on an input voltage VIN. The high-level voltage VGH and the low-level voltage VGL are provided to the gate drive circuit 10 via a high-level line and a low-level line, respectively.

[0094] In one embodiment, the time node at which the feedback voltage output by the feedback module 400 reaches the second preset voltage is earlier than the first rising edge of the high-level voltage VGH.

[0095] It is understood that the feedback module 400 can be configured to adjust the conversion coefficient between the operating voltage VCC and the feedback voltage, thereby controlling the time point at which the feedback voltage reaches the second preset voltage. This allows the timing control module 300 to output the second clock signal before other modules operating based on the high-level voltage VGH (e.g., the level conversion module 200) are powered on.

[0096] Figure 7 A schematic diagram of a display device provided in an embodiment of the present application is shown. For ease of explanation, only the portion related to this embodiment is shown, which is described in detail as follows:

[0097] A display device 30 includes the display panel 20 according to any one of the above embodiments.

[0098] Since the display device 30 includes the display panel 20 of any of the above embodiments, the display device 30 has the beneficial effects of the display panel 20 of any of the above embodiments, which will not be described in detail here.

[0099] In some embodiments, the display device 30 may specifically be a smart device such as a mobile phone or a computer.

[0100] Through the description of the above embodiments, those skilled in the art will understand that for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0101] It should be understood that the devices and methods disclosed in the several embodiments provided in this application can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device. In addition, some features can be ignored or not performed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0102] Units described as separate components may or may not be physically separate. Components shown as units may be one physical unit or multiple physical units. That is, they may be located in one place or distributed across multiple locations. Depending on actual needs, some or all of the units may be selected to achieve the objectives of this solution.

[0103] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit; may also exist physically separately; or some units may be integrated into a single unit, while some units may exist physically separately. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0104] It should be noted that all or part of the above-mentioned embodiments provided in this application (for example, part or all of any feature) can be arbitrarily combined or used in conjunction with each other.

[0105] The above content is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A gate drive circuit, characterized in that: The gate drive circuit includes: A GOA module, the GOA module comprising an output unit and a pull-down maintenance unit, the output unit being configured to generate and output a scan signal based on a first clock signal when a voltage of a charging node of the GOA module is greater than or equal to a preset threshold, the pull-down maintenance unit being connected between the charging node and a low-level wiring connection; a timing control module connected to the level conversion module, configured to provide a second clock signal of the first frequency to the level conversion module from before the level conversion module is powered on to after the level conversion module is powered on; and to adjust the frequency of the second clock signal from the first frequency to a second frequency after the level conversion module is powered on; the second frequency is lower than the first frequency; The level conversion module is connected to the pull-down maintenance unit through the half-bridge switch circuit of the GOA module. The level conversion module is used to output an inverted third clock signal and a fourth clock signal to the pull-down maintenance unit according to the second clock signal. The third clock signal and the fourth clock signal are used to control the conduction and cutoff of the pull-down maintenance unit through the half-bridge switch circuit.

2. The gate drive circuit according to claim 1, wherein: The half-bridge switching circuit includes a first switching device and a second switching device, and the pull-down maintaining unit includes a third switching device; A first end of the first switching device is connected to the high-level wiring, a second end of the first switching device is connected to the control end of the third switching device, a first end of the second switching device is connected to the control end of the third switching device, and a second end of the second switching device is connected to the low-level wiring, and the control end of the first switching device and the control end of the second switching device are both connected to the level conversion module to receive the third clock signal and the fourth clock signal, respectively; A first end of the third switch device is connected to the charging node, and a second end of the third switch device is connected to the low level trace.

3. The gate drive circuit according to claim 1, wherein: The output unit includes a fourth switching device and a bootstrap capacitor; The first end of the bootstrap capacitor is connected to the charging node, the first end of the fourth switching device is used to access the first clock signal, the second end of the fourth switching device is connected to the second end of the bootstrap capacitor, the control end of the fourth switching device is connected to the charging node, and the second end of the fourth switching device is used to output the scan signal.

4. The gate drive circuit according to claim 1, wherein: The GOA module also includes a pull-up unit, which is connected between the charging node and the high-level trace, and is used to pull up the voltage of the charging node to a high level before the output unit generates a high-level pulse of the scan signal according to the high-level pulse of the first clock signal.

5. The gate driving circuit according to claim 1, wherein: The gate driving circuit further includes a pull-down unit; The pull-down unit is configured to pull down the voltage of the output terminal of the output unit to a low level before the next rising edge of the first clock signal following the falling edge of the scan signal.

6. The gate drive circuit according to any one of claims 1 to 5, wherein: The timing control module is further configured to output a fifth clock signal to the level conversion module after outputting the second clock signal of the second frequency, and the level conversion module is configured to output the first clock signal according to the fifth clock signal.

7. The gate drive circuit according to any one of claims 1 to 5, wherein: The level conversion module includes a level conversion unit and an enabling control unit; The enable control unit is connected to the level conversion unit and the timing control module, and is configured to output an enable signal after the timing control module outputs the second clock signal of the second frequency and the input voltage of the gate drive circuit is greater than a first preset voltage; The level conversion unit is configured to be powered on and started after receiving the enable signal.

8. The power-on startup method is characterized in that: Applicable to a gate drive circuit, the gate drive circuit comprising: A GOA module, the GOA module including an output unit and a pull-down maintenance unit, the output unit being configured to generate and output a scan signal based on a first clock signal when a voltage of a charging node of the GOA module is greater than or equal to a preset threshold, the pull-down maintenance unit being connected to the charging node and a low-level trace; a level conversion module connected to the pull-down maintaining unit via a half-bridge switch circuit, the level conversion module being configured to generate and output an inverted third clock signal and a fourth clock signal to the pull-down maintaining unit according to the second clock signal, the third clock signal and the fourth clock signal being configured to control the on and off state of the pull-down maintaining unit via the half-bridge switch circuit; The power-on startup method includes: providing the second clock signal of the first frequency to the level conversion module before the level conversion module is powered on and after the level conversion module is powered on; After the level conversion module is powered on, the frequency of the second clock signal is adjusted from the first frequency to a second frequency; the second frequency is lower than the first frequency.

9. A display panel, characterized in that Comprising a plurality of cascaded gate drive circuits as described in any one of claims 1 to 7, wherein the gate drive circuit of the nth stage is used to generate and output a scanning signal applied to the nth row of pixel circuits in the display panel based on a first clock signal within a corresponding scanning period.

10. The display panel according to claim 9, wherein: The display panel further includes a power supply circuit, the power supply circuit being configured to generate and output an operating voltage and a high-level voltage based on an input voltage; The gate drive circuit further includes a feedback module, the feedback module being connected to the timing control module of the gate drive circuit, the feedback module being configured to provide a feedback voltage to the timing control module based on the operating voltage, the timing control module being configured to output a second clock signal after the feedback voltage is greater than a second preset voltage; The time node at which the feedback voltage reaches the second preset voltage is earlier than the first rising edge of the high-level voltage.

11. A display device, characterized in that Comprising the display panel according to claim 9 or 10.

Images