Semiconductor structure, manufacturing method thereof and memory

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a memory. Wherein the semiconductor structure comprises a semiconductor layer; an auxiliary structure in the semiconductor layer; the semiconductor layer comprises a first type of material, the auxiliary structure comprises a second type of material, and the hardness of the second type of material is greater than that of the first type of material.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor structure, a manufacturing method thereof, and a memory. Background Art

[0002] As memories develop towards higher integration densities, the sizes of memories are also changing. However, when scaling down the sizes of memories, it may lead to degradation of the electrical and reliable performance of the memories.

[0003] Therefore, the structures and performances of current memories both need to be further improved. Summary of the Invention

[0004] To solve one or more of the related technical problems, embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a memory. On the one hand, a semiconductor structure provided by embodiments of the present disclosure includes: a semiconductor layer; an auxiliary structure located in the semiconductor layer; wherein, the semiconductor layer includes a first type of material, the auxiliary structure includes a second type of material, and the hardness of the second type of material is greater than the hardness of the first type of material.

[0005] In some embodiments, the projected shape of the auxiliary structure on a first surface includes: annular, rectangular, square, U-shaped; the first surface is parallel to the top surface of the semiconductor layer.

[0006] In some embodiments, the auxiliary structure includes a plurality of grating structures with the same shape and arranged periodically; the plurality of grating structures are spaced apart in the semiconductor layer.

[0007] In some embodiments, the semiconductor structure further includes: a photolithography layer covering the top surface of the auxiliary structure and the top surface of the semiconductor layer; the photolithography layer contains alignment marks.

[0008] In some embodiments, the projected area of the auxiliary structure on the first surface overlaps with the projected area of the alignment mark on the first surface; or, the projected area of the auxiliary structure on the first surface is located around the projected area of the alignment mark on the first surface.

[0009] In some embodiments, the shape of the grating structure is strip-shaped; the shape of the alignment mark includes a plurality of strip-shaped main alignment marks arranged in sequence, and a plurality of strip-shaped auxiliary alignment marks arranged in sequence and perpendicularly intersecting the main alignment marks; wherein, the extending direction of the grating structure intersects with the extending directions of the main alignment mark and the auxiliary alignment mark.

[0010] In some embodiments, the period width of the alignment grating in the alignment mark is different from the period width of the grating structure.

[0011] In some embodiments, the semiconductor layer includes a device region and a peripheral region surrounding the device region; wherein, the auxiliary structure is located in the peripheral region.

[0012] In some embodiments, the semiconductor layer further includes an image mark; the image mark is located in the device region.

[0013] In some embodiments, the first type of material includes silicon; the second type of material includes silicon oxide.

[0014] On the other hand, a memory provided by an embodiment of the present disclosure includes: the semiconductor structure as described in the above embodiments of the present disclosure.

[0015] On the other hand, a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure includes: providing a substrate, the substrate including a first type of material; forming a dielectric layer in the substrate, the dielectric layer including a second type of material; performing a polishing process on the substrate and the dielectric layer to form a semiconductor layer and an auxiliary structure located in the semiconductor layer; wherein, the hardness of the second type of material is greater than the hardness of the first type of material.

[0016] In some embodiments, the forming a dielectric layer in the substrate includes: forming a plurality of grooves in the substrate; filling the second type of material in the grooves to form the dielectric layer.

[0017] In some embodiments, the performing a polishing process on the substrate and the dielectric layer to form a semiconductor layer and an auxiliary structure located in the semiconductor layer includes: performing chemical mechanical polishing (CMP) on the top surface of the substrate and the top surface of the dielectric layer to remove part of the substrate and remove part of the dielectric layer, and the remaining substrate constitutes the semiconductor layer, and the remaining dielectric layer constitutes the auxiliary structure.

[0018] In some embodiments, the projected shape of the auxiliary structure on a first surface includes: annular, rectangular, square, U-shaped; the first surface is parallel to the top surface of the semiconductor layer.

[0019] In some embodiments, the auxiliary structure includes a plurality of grating structures having the same shape and arranged periodically; the plurality of grating structures are spaced apart and disposed in the semiconductor layer.

[0020] In some embodiments, the method further includes: forming a photolithography layer covering the top surface of the auxiliary structure and the top surface of the semiconductor layer; and forming alignment marks in the photolithography layer.

[0021] In some embodiments, the projected area of the auxiliary structure on the first surface overlaps with the projected area of the alignment marks on the first surface; or, the projected area of the auxiliary structure on the first surface is located around the projected area of the alignment marks on the first surface.

[0022] In some embodiments, the grating structure is in a long strip shape; the shapes of the alignment marks include a plurality of strip-shaped main alignment marks arranged in sequence and a plurality of strip-shaped auxiliary alignment marks arranged in sequence perpendicular to the main alignment marks; wherein, the extending direction of the grating structure intersects with the extending directions of the main alignment marks and the auxiliary alignment marks.

[0023] In some embodiments, the period width of the alignment grating in the alignment marks is different from the period width of the grating structure.

[0024] In some embodiments, the semiconductor layer includes a device region and a peripheral region located around the device region; the auxiliary structure is located in the peripheral region; the method further includes: forming image marks in the device region.

[0025] Embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a memory. Among them, the manufacturing method of the semiconductor structure includes: providing a substrate, the substrate including a first type of material; forming a dielectric layer in the substrate, the dielectric layer including a second type of material; polishing the substrate and the dielectric layer to form a semiconductor layer and an auxiliary structure located in the semiconductor layer; wherein, the hardness of the second type of material is greater than the hardness of the first type of material. In the embodiments of the present disclosure, by forming a dielectric layer in the substrate and making the hardness of the dielectric layer greater than that of the semiconductor layer, in this way, when polishing the substrate and the dielectric layer, the consumption rate of the substrate can be slowed down to reduce the removal amount of the substrate by the grinding process, thereby improving the conformal ability of the semiconductor layer topography. In other words, by forming a dielectric layer in the substrate, the ability of the substrate to resist destructive manufacturing processes can be stronger, thereby improving the reliability of the semiconductor layer. Description of the Drawings

[0026] Figure 1 It is a schematic structural diagram of a storage unit circuit adopting a 1T1C architecture provided by an embodiment of the present disclosure;

[0027] Figure 2 It is a schematic cross-sectional view of a substrate structure including a device region and a peripheral region provided by an embodiment of the present disclosure;

[0028] Figure 3 Schematic flow chart of a method for fabricating a semiconductor structure provided by an embodiment of the present disclosure;

[0029] Figures 4a - 4h Schematic cross-sectional view of a manufacturing process of a semiconductor structure provided by an embodiment of the present disclosure;

[0030] Figure 5a Schematic diagram of the relative positions of an auxiliary structure and alignment marks in a semiconductor structure provided by an embodiment of the present disclosure;

[0031] Figure 5b Another schematic diagram of the relative positions of an auxiliary structure and alignment marks in a semiconductor structure provided by an embodiment of the present disclosure;

[0032] Figure 6 Schematic diagram of the test results of alignment marks in a semiconductor structure with an auxiliary structure provided by an embodiment of the present disclosure. Detailed implementation manners

[0033] To make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further elaborated in detail below in conjunction with the drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0034] In the following paragraphs, the present disclosure will be described more specifically by way of example with reference to the drawings. The advantages and features of the present disclosure will be clearer according to the following description and the claims. It should be noted that the drawings are all in very simplified forms and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present disclosure.

[0035] It can be understood that the meanings of "on...", "above...", and "over..." in the present disclosure should be interpreted in the broadest manner, so that "on..." not only means "on" something "without any intermediate features or layers (i.e., directly on something)", but also includes the meaning of being "on" something with intermediate features or layers.

[0036] In addition, for ease of description, spatial relative terms such as "on", "above", "over", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another element or feature. Except for the orientation depicted in the drawings, spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein can be interpreted accordingly.

[0037] In the embodiments of the present disclosure, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0038] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entirety of a structure below or above, or may have a scope smaller than the scope of the structure below or above. In addition, the layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of a continuous structure, or the layer may be between any horizontal planes at the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and / or along an inclined surface. The layer may include multiple sub-layers. For example, an interconnect layer may include one or more conductor and contact sub-layers (wherein interconnect lines and / or via contacts are formed), and one or more dielectric sub-layers.

[0039] In the embodiments of the present disclosure, terms such as "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0040] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be elaborated in detail below with reference to the accompanying drawings. The attached drawings are for reference and illustration purposes only and are not used to limit the embodiments of the present disclosure.

[0041] The semiconductor structure involved in the embodiments of the present disclosure is at least a part that will be used in subsequent processes to form a final device structure. Here, the final device may include a memory, and the memory includes but is not limited to dynamic random access memory. Only dynamic random access memory will be taken as an example for illustration below. However, it should be noted that the following description of dynamic random access memory in the embodiments is only used to illustrate the present disclosure and does not limit the scope of the present disclosure.

[0042] With the development of dynamic random access memory technology, its array architecture has changed from 8F2 to 6F 2 then to 4F 2 ; In addition, based on the requirements for ions and leakage current in dynamic random access memory, the architecture of the memory has evolved from Planar Array Transistor to Recess Gate Array Transistor, then from Recess Gate Array Transistor to Buried Channel Array Transistor, and finally from Buried Channel Array Transistor to Vertical Channel Array Transistor.

[0043] It should be understood that whether it is a planar transistor or a buried transistor, a dynamic random access memory includes a peripheral circuit and a memory cell array; among them, the peripheral circuit may include any suitable digital, analog, and / or mixed-signal circuits configured to facilitate various operations such as read operations, write operations, and erase operations of the memory. For example, the peripheral circuit may include control logic (such as a control circuit or a controller), a data buffer, a decoder (the decoder may also be referred to as a demultiplexer), a driver, and a read / write circuit, etc. When the control logic receives a read / write operation command and address data, under the action of the control logic, the decoder can apply a corresponding voltage obtained from the driver to the corresponding bit line and word line based on the decoded address to achieve data read / write, and perform data interaction with the outside through the data buffer. The memory cell array may include a plurality of memory cells; each memory cell may include a transistor and a capacitor, that is, the dynamic random access memory has a 1 transistor (T, Transistor) and 1 capacitor (C, Capacitor) (1T1C) architecture; its working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0044] Exemplarily, referring to Figure 1 , Figure 1 is a schematic diagram of a memory cell circuit structure adopting a 1T1C architecture provided in an embodiment of the present disclosure. As Figure 1 shown, the drain of the transistor T is electrically connected to the bit line (BL, Bit Line), the source of the transistor T is electrically connected to one electrode plate of the capacitor C, the other electrode plate of the capacitor C may be connected to a reference voltage, the reference voltage may be a ground voltage or other voltages, and the gate of the transistor T is connected to the word line (WL, Word Line); by applying different voltages to the word line WL to control the conduction or cutoff of the transistor T, the bit line BL is used to perform read or write operations on the transistor T when the transistor T is conducting.

[0045] In some embodiments, the memory cell array may also be divided into an active area (AA), a shallow trench isolation area (STI), a dicing street area (sometimes also referred to as a scribe line area), etc. according to different structural functions. Among them, the active area AA can be used to form multiple memory cells; the shallow trench isolation area STI can be used to separate two adjacent active device areas; the dicing street area can be used to form a scribe line (i.e., a cutting channel) and form alignment marks.

[0046] With the great progress of lithography technology and advanced resolution enhancement technology, the semiconductor industry has successfully reduced the device size. At the same time, the overlay error measurement required for lithography, including the accuracy of overlay and the alignment accuracy between alignment marks, has an important impact on the yield of the final product. In some embodiments, new designs and processes have greatly improved the performance of integrated circuits, resulting in an increasing difference in the environments of the chip active area AA, shallow trench isolation area STI, and dicing street area. In particular, the error of alignment marks (sometimes also referred to as measurement marks) on the dicing street area caused by deposition processes and chemical mechanical polishing processes, etc., is becoming increasingly prominent and is a common but difficult problem to solve in the industry.

[0047] Exemplarily, referring to Figure 2 , the substrate 200 includes a device area 201 and a peripheral area 202 surrounding the device area; in subsequent processes, multiple stacked layers are formed on the substrate through deposition processes, etc.; the area corresponding to the device area 201 in the multiple stacked layers includes the active area AA, which can be used to form memory cells; the area corresponding to the peripheral area 202 in the multiple stacked layers includes the dicing street area, which can be used to form a scribe line and alignment marks. In order to ensure the flatness of the surface of each stacked layer, the surface of the substrate needs to be polished before forming the stacked layer, for example, polished by chemical mechanical polishing process. However, due to the process loading during the polishing process, the topography of the peripheral area 202 may change, such as over-polishing during the polishing process, resulting in a bowl-shaped depression 203 in the peripheral area 202; thus, problems such as height difference and color difference appear between the surface of the peripheral area 202 and the device area 201; in this case, after forming a stacked layer including alignment marks above the peripheral area 202, it affects the use of the alignment marks.

[0048] Based on this, in order to solve at least some of the above problems, embodiments of the present disclosure provide a method for manufacturing a semiconductor; wherein, Figure 3 is a schematic flow chart of the implementation of the method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure. As Figure 3As shown, the method includes the following steps: S301: Provide a substrate, where the substrate includes a first type of material. S302: Form a dielectric layer in the substrate, where the dielectric layer includes a second type of material, and the hardness of the second type of material is greater than that of the first type of material. S303: Polish the substrate and the dielectric layer to form a semiconductor layer and an auxiliary structure located in the semiconductor layer.

[0049] Figures 4a - 4h This is an example of a cross-sectional view of the manufacturing process of a semiconductor structure provided by an embodiment of the present disclosure. It should be understood that Figure 3 the operations shown are not exclusive, and other operations can also be performed before, after, or between any of the shown operations; and it should be understood that Figure 3 among the multiple specific operation steps shown, it is not necessary to complete them in the order Figure 3 shown, and other operation steps can also be performed before, after, or between any specific operation step. The following will describe the method for forming the semiconductor structure according to various embodiments of the present disclosure in conjunction with Figure 3 and Figures 4a - 4h the figures.

[0050] Referring to Figure 4a , perform S301 to provide a substrate 401. In practical applications, the substrate 401 can be formed by processes such as physical vapor deposition (PVD, Physical Vapor Deposition), chemical vapor deposition (CVD, Chemical Vapor Deposition), atomic layer deposition (ALD, Atomic Layer Deposition), or a combination thereof, and can also be obtained by other means, which will not be elaborated here one by one. The substrate 401 includes a first type of material, and the constituent materials of the first type of material can include silicon (Si), but are not limited thereto. As Figure 4a shown, the substrate 401 can be divided into a device region 402 and a peripheral region 403 located around the device region. It should be noted that Figure 4a only an exemplary relative position schematic diagram of a part of the device region 402 and a part of the peripheral region 403 is shown in the figure.

[0051] Here, the thickness direction of the substrate 401 can be defined as the Z-axis direction, and the X-axis direction and the Y-axis direction are defined on the bottom surface or the top surface perpendicular to the Z-axis direction, where the X-axis direction and the Y-axis direction intersect. In some embodiments, the X-axis direction and the Y-axis direction can be perpendicular to each other.

[0052] Referring to Figure 4b and Figure 4c , perform S302 to form a dielectric layer in the substrate 401.

[0053] It should be understood that the dielectric layer can be formed in the peripheral region of the substrate or in the device region of the substrate. In the embodiments of the present disclosure, the case where the dielectric layer is formed in the peripheral region of the substrate is taken as an example for illustration. Based on this, as Figure 4b shown, a plurality of grooves 404 are formed in the peripheral region 403 of the substrate; the shapes of the plurality of grooves 404 can be selected according to actual situations. For example, the projected shapes of the plurality of grooves 404 on the first surface include: circular, rectangular, square, U-shaped, etc., and the first surface is parallel to the top surface 401a / bottom surface 401b of the substrate 401. Here, the case where the shapes of the plurality of grooves 404 are a plurality of long strip-shaped grooves with equal width and equal spacing and arranged in a certain periodic pattern is taken as an example for illustration. The method for forming the grooves 404 includes but is not limited to etching, such as plasma dry etching, etc.

[0054] It should be noted that before forming the grooves 404, a patterned mask layer needs to be formed on the top surface of the peripheral region 403. Forming the patterned mask layer involves a series of process steps. For example, first deposit a mask layer, coat a photoresist on the mask layer, then perform exposure and development, and then remove the photoresist by dissolution or ashing, and finally form the patterned mask layer. The material of the mask layer can be, for example, silicon nitride. It can be understood that the pattern of the mask layer can include a series of preset patterns. Here, the preset pattern is a plurality of long strip-shaped patterns.

[0055] As Figure 4c shown, a second type of material is filled in the grooves to form the dielectric layer 405. The consumption rate of the second type of material is less than the consumption rate of the first type of material.

[0056] It should be noted that for different manufacturing processes, the manifestation characteristics of the consumption rate are different; for example, when the first type of material and the second type of material are polished by chemical mechanical polishing process, the consumption rate can be manifested as the polishing rate, that is, the polishing rate of the chemical mechanical polishing process for the first type of material is less than its polishing rate for the second type of material. For example, when the first type of material and the second type of material are etched by an etching process, the consumption rate can be manifested as the etching rate, that is, the etching rate of the etching process for the first type of material is less than its etching rate for the second type of material; in other embodiments, the consumption rate can also be understood as the removal rate, etc., which will not be elaborated here one by one.

[0057] Exemplarily, to meet the above requirements, the hardness of the second type of material is greater than that of the first type of material; thus, when chemically mechanically polishing the first type of material and the second type of material, the polishing rate of the second type of material is smaller than that of the first type of material; in other words, under the same polishing conditions, the dielectric layer is less likely to be removed compared to the substrate. Exemplarily, the constituent materials of the second type of material include, but are not limited to, silicon dioxide (SiO2); the dielectric layer 405 can be formed by PVD, CVD, ALD, or a combination thereof.

[0058] Reference Figure 4d , the method further includes: polishing the substrate and the dielectric layer to form a semiconductor layer and an auxiliary structure located in the semiconductor layer. Exemplarily, chemically mechanically polishing the top surface of the peripheral region 403 and the top surface of the dielectric layer 405 to remove a part of the peripheral region 403 and a part of the dielectric layer 405, and the remaining peripheral region 403 constitutes the semiconductor layer 406, and the remaining dielectric layer 405 constitutes the auxiliary structure 407.

[0059] It should be understood that the dielectric layer is located in the substrate, and the hardness of the second type of material in the dielectric layer is greater than that of the first type of material in the substrate. Therefore, during the chemical mechanical polishing process, the harder dielectric layer can slow down the polishing rate of the substrate by the polishing process, so as to reduce the removal amount of the substrate by the polishing process and improve the conformal ability of the semiconductor layer topography. In other words, forming a dielectric layer in the substrate can make the substrate more resistant to destructive process technologies, thereby improving the reliability of the semiconductor layer.

[0060] Based on the different shapes of the multiple grooves, the shape of the auxiliary structure is also different. In some embodiments, the projected shape of the auxiliary structure on the first surface includes: annular, rectangular, square, U-shaped, etc. Exemplarily, reference Figure 4d, a plurality of grooves have the same width and the same spacing and are arranged in parallel according to a certain periodic pattern. The auxiliary structures formed in the plurality of grooves are a plurality of grating structures with the same shape, the same size and periodic arrangement. Here, the plurality of grating structures are arranged at intervals in the semiconductor layer 406. In some embodiments, the top surface of the auxiliary structure 407 is substantially flush with the top surface of the semiconductor layer 406; in other embodiments, the chemical mechanical polishing process can also polish the device region 402 of the substrate so that the top surface of the auxiliary structure 407, the top surface of the semiconductor layer 406, and the top surface of the device region 402 of the substrate are all substantially flush. Substantially flush can be understood as that after the chemical mechanical polishing process, the top surface of the formed auxiliary structure, the top surface of the semiconductor layer, and the top surface of the device region 402 in the substrate are flush on the same plane, and during the chemical mechanical polishing process, within the process error range, the situation where the top surfaces of the auxiliary structure 407, the semiconductor layer 406, and the device region 402 in the substrate are not flush on the same plane.

[0061] In some embodiments, referring to Figure 4e and Figure 4f , the method further includes: forming an image mark 408 in the device region 402 of the substrate. The image mark 408 can be any suitable circuit pattern. The process of forming the image mark may include forming a mask layer and a photoresist on the top surface of the device region 402, and projecting the pattern on the mask layer onto the photoresist through an exposure system, etc. Among them, during the process of exposing and projecting the pattern, due to the imperfection of the optical system and the diffraction effect, the pattern on the photoresist is not completely consistent with the pattern on the mask layer. And the auxiliary structure 407 shown in the embodiments of the present disclosure can be used for optical proximity correction (OPC, Optical Proximity Correction) of the image mark 408 during the exposure process, so that the pattern on the photoresist is consistent with the pattern on the mask layer, thereby ensuring the accuracy of the image mark 408.

[0062] In some embodiments, referring to Figure 4g and Figure 4h, the method further includes: forming a photolithography layer 409 covering the top surface of the auxiliary structure and the top surface of the semiconductor layer; and forming alignment marks 410 in the photolithography layer 409. Here, the photolithography layer 409 may also cover the top surface of the device region 402. It should be noted that during the fabrication of the memory, alignment marks are used to ensure the correct positioning, alignment, monitoring, and adjustment between the substrate, the photolithography layer, and the subsequent formed stacked layers. It should be understood that during the fabrication of the memory, the memory needs to go through multiple processing and treatment steps, such as photolithography, etching, deposition, etc. Each processing requires positioning and aligning the stacked layers to ensure that the patterns in each layer are in the correct position relative to the previous step. Alignment marks can be used to provide an accurate reference. To ensure the accuracy of the positions between the layers, corresponding alignment marks are formed in each layer.

[0063] The photolithography layer formed on the top surface of the auxiliary structure and the top surface of the semiconductor layer by the above method has good flatness, thereby reducing the unevenness of the top surface of the photolithography layer caused by the depression of the top surface of the semiconductor layer, thus improving the accuracy of the alignment marks in the photolithography layer and the usability of the alignment marks. On the other hand, due to the relatively high hardness of the auxiliary structure, the process load has less impact on the top surfaces of the auxiliary structure and the semiconductor layer. Thus, there is no height difference between the top surface of the auxiliary structure, the top surface of the semiconductor layer, and the top surface of the device region of the substrate, that is, the uniformity and consistency of the top surface are good. Furthermore, the alignment marks in the photolithography layer can better accurately position the circuit structure formed above the device region, improving the accuracy and precision of alignment.

[0064] In some embodiments, the projection area of the auxiliary structure on the first surface overlaps with the projection area of the alignment mark on the first surface; or, the projection area of the auxiliary structure on the first surface is located around the projection area of the alignment mark on the first surface.

[0065] The size of the auxiliary structure 407 can be set arbitrarily. Therefore, the projection area of the auxiliary structure 407 on the first surface can be larger than, smaller than, or equal to the projection area of the alignment mark 410 on the first surface. Refer to Figure 5a , the projection area of the auxiliary structure 407 on the first surface can be larger than the projection area of the alignment mark 410 on the first surface. Figure 5a The projection area of the auxiliary structure 407 on the first surface shown in Figure 5b, the projection area of the auxiliary structure 407 on the first surface is annular and located around the projection area of the alignment mark 410 on the first surface. In some other embodiments, the projection area of the auxiliary structure on the first surface may partially overlap with the projection area of the alignment mark on the first surface, and the projection area of the auxiliary structure on the first surface and the projection area of the alignment mark on the first surface may also be arranged in any other suitable relative positions, which will not be elaborated here one by one.

[0066] In some embodiments, the shape of the grating structure is strip-shaped; the shape of the alignment mark includes a plurality of strip-shaped main alignment marks arranged in sequence and a plurality of strip-shaped auxiliary alignment marks arranged in sequence and perpendicular to the main alignment marks; wherein, the extending direction of the grating structure intersects with the extending directions of the main alignment marks and the auxiliary alignment marks.

[0067] Reference Figure 5a and Figure 5b , the alignment mark 410 includes a plurality of main alignment marks 4101 and a plurality of auxiliary alignment marks 4102 perpendicular to the plurality of main alignment marks 4101. Among them, the plurality of main alignment marks 4101 and the plurality of auxiliary alignment marks 4102 are both strip-shaped. A part of the main alignment marks 4101 among the plurality of main alignment marks 4101 are evenly arranged in the first direction (such as the X-axis direction) and extend along the second direction (such as the Y-axis direction); another part of the main alignment marks 4101 are evenly arranged in the second direction (such as the Y-axis direction) and extend along the first direction (such as the X-axis direction). A part of the auxiliary alignment marks 4102 among the plurality of auxiliary alignment marks 4102 are evenly arranged in the first direction (such as the X-axis direction) and extend along the second direction (such as the Y-axis direction); another part of the auxiliary alignment marks 4102 are evenly arranged in the second direction (such as the Y-axis direction) and extend along the first direction (such as the X-axis direction). The main alignment marks 4101 extending along the first direction are perpendicular to the auxiliary alignment marks 4102 extending along the second direction, and the main alignment marks 4101 extending along the second direction are perpendicular to the auxiliary alignment marks 4102 extending along the first direction.

[0068] The shapes of the plurality of grating structures are all strip-shaped, and the extending direction of each grating structure intersects with the extending directions of the main alignment marks and the auxiliary alignment marks. In this way, when the main alignment marks 4101 and the auxiliary alignment marks 4102 perform alignment and measurement operations, the grating structure will not have any influence on the measurement and alignment of the main alignment marks 4101 and the auxiliary alignment marks 4102.

[0069] In some embodiments, the alignment mark includes an alignment grating; the alignment grating can be understood as the main alignment mark 4101 and / or the auxiliary alignment mark 4102 in the above embodiments. The period width of the alignment grating in the alignment mark is different from the period width of the grating structure. ReferenceFigure 4h The alignment marks 410 include a plurality of alignment gratings, the width period of each alignment grating being a first width W1, and the auxiliary structure 407 includes a plurality of grating structures, the period width of each grating structure being a second width W2, with the first width W1 being greater than the second width W2. It should be understood that the period width of the grating structures in the auxiliary structure is different from the period width of the alignment gratings in the alignment marks, which is beneficial to the measurement and alignment of the alignment marks. In other words, the grating structures in the auxiliary structure do not have any impact on the measurement and alignment of the alignment marks. For example, during the exposure process, the grating structures do not have a diffraction impact on the measurement and alignment of the alignment marks.

[0070] In some embodiments, at least one stacked layer may also be formed on the top surface of the photolithography layer 409 and the top surface of the alignment marks. Corresponding alignment marks may be provided in each layer of the at least one stacked layer for positioning, alignment, monitoring, and adjustment, which will not be elaborated here.

[0071] Based on this, in the embodiments of the present disclosure, by forming a dielectric layer in the substrate and making the hardness of the dielectric layer greater than that of the semiconductor layer, in this way, when polishing the substrate and the dielectric layer, the consumption rate of the substrate can be slowed down to reduce the removal amount of the substrate by the grinding process, thereby improving the conformal ability of the semiconductor layer topography. In other words, by forming a dielectric layer in the substrate, the substrate can have a stronger ability to resist destructive manufacturing processes, thereby improving the reliability of the semiconductor layer.

[0072] Reference Figure 6 , Figure 6 is a schematic diagram of the test results of the alignment marks in the semiconductor structure with an auxiliary structure provided by the embodiments of the present disclosure. Figure 6 In [the figure], the abscissa is the size of the alignment marks (mark size), and S1, S2, and S3 are used to characterize different numerical requirements. As can be seen from Figure 6 [the figure], by testing the contrast marks in the semiconductor layer formed by using the manufacturing method described in the above embodiments of the present disclosure, the sizes of the alignment marks are all below 500 micrometers (um), and the Dishing test values are all within the process window range. In other words, by setting an auxiliary structure in the semiconductor layer, the conformal ability of the semiconductor layer topography is improved, making the flatness of the photolithography layer formed on the semiconductor layer better and the integrity of the alignment marks formed in the photolithography layer higher, thereby improving the usability of the alignment marks.

[0073] Based on the above manufacturing method of the semiconductor structure, the embodiments of the present disclosure also provide a semiconductor structure. Reference Figure 4e 、 Figure 4g 、 Figure 4h 、 Figure 5a 、Figure 5b , the semiconductor structure includes: a semiconductor layer 406; and an auxiliary structure 407 located in the semiconductor layer 406; wherein, the semiconductor layer 406 includes a first type of material, and the auxiliary structure 407 includes a second type of material, and the consumption rate of the second type of material is less than the consumption rate of the first type of material. Exemplarily, the hardness of the second type of material is greater than the hardness of the first type of material.

[0074] In actual operation, various different manufacturing processes can be used to form the semiconductor layer and the auxiliary structure; compared with only forming the semiconductor layer, in the embodiments of the present disclosure, referring to Figure 4g , the auxiliary structure 407 is disposed in the semiconductor layer 406, and the hardness of the auxiliary structure 407 is set to be greater than the hardness of the semiconductor layer 406, so that the consumption rate of the harder auxiliary structure by different manufacturing processes is reduced, that is, the influence of the manufacturing process on the semiconductor layer is reduced, and the conformal ability of the semiconductor layer topography is improved. In other words, by disposing the auxiliary structure in the semiconductor layer, the ability of the semiconductor layer to resist destructive manufacturing processes can be stronger, thereby improving the reliability of the semiconductor layer.

[0075] It should be noted that for different manufacturing processes, the consumption rate of the auxiliary structure 407 is less than the consumption rate of the semiconductor layer 406; for example, in the process of removing part of the first type of material by chemical mechanical polishing to form the auxiliary structure and removing part of the second type of material to form the semiconductor layer, the polishing rate of the chemical mechanical polishing process for the second type of material is less than its polishing rate for the first type of material; for example, in the process of removing part of the first type of material by etching to form the auxiliary structure and removing part of the second type of material to form the semiconductor layer, the etching rate of the etching process for the second type of material is less than its etching rate for the first type of material; in other embodiments, the consumption rate can also be reflected as the removal rate, etc., which will not be elaborated here one by one. In the embodiments of the present disclosure, in order to meet the above requirements, the hardness of the first type of material in the auxiliary structure 407 is set to be greater than the hardness of the second type of material in the semiconductor layer 406. Exemplarily, the first type of material may include silicon; the second type of material may include silicon oxide. The first type of material and the second type of material can also be any other suitable materials.

[0076] The shape of the auxiliary structure 407 can be selected and set according to actual needs. Exemplarily, the projected shape of the auxiliary structure on the first surface includes: annular, rectangular, square, U-shaped; the first surface is parallel to the top surface of the semiconductor layer.

[0077] In some specific embodiments, the auxiliary structure includes a plurality of grating structures with the same shape and arranged periodically; the plurality of grating structures are spaced apart in the semiconductor layer. It should be noted that the plurality of grating structures have the same width and the same spacing and are arranged in parallel according to a certain periodic law.

[0078] In some embodiments, the semiconductor structure further includes: a lithography layer covering the top surface of the auxiliary structure and the top surface of the semiconductor layer; the lithography layer contains alignment marks. Refer to Figure 4g , the lithography layer 409 can be one of the multiple stacked layers described in the foregoing embodiments, and the alignment mark 410 is located in the lithography layer 409. As described above, the alignment mark 410 is used to ensure the correct positioning, alignment, monitoring, and adjustment between the substrate, the lithography layer, the subsequently formed stacked layers, and the patterns provided on each layer during the manufacturing process of the memory.

[0079] In some embodiments, the projection area of the auxiliary structure on the first surface overlaps with the projection area of the alignment mark on the first surface; or, the projection area of the auxiliary structure on the first surface is located around the projection area of the alignment mark on the first surface. In some other embodiments, the projection area of the auxiliary structure on the first surface may partially overlap with the projection area of the alignment mark on the first surface, and the projection area of the auxiliary structure on the first surface may also be arranged in any suitable relative position with respect to the projection area of the alignment mark on the first surface, which will not be elaborated here one by one.

[0080] In some embodiments, the shape of the grating structure is elongated; the shape of the alignment mark includes a plurality of sequentially arranged strip-shaped main alignment marks and a plurality of sequentially arranged strip-shaped auxiliary alignment marks that intersect perpendicularly with the main alignment marks; wherein, the extending direction of the grating structure intersects with the extending directions of both the main alignment marks and the auxiliary alignment marks. Refer to Figure 5a and Figure 5b , the alignment mark includes a plurality of main alignment marks 4101 and a plurality of auxiliary alignment marks 4102 that intersect perpendicularly with the plurality of main alignment marks 4101. Among them, the plurality of main alignment marks 4101 and the plurality of auxiliary alignment marks 4102 are both elongated. A part of the plurality of main alignment marks 4101 is uniformly arranged in the first direction (such as the X-axis direction) and extends in the second direction (such as the Y-axis direction); another part of the main alignment marks 4101 is uniformly arranged in the second direction (such as the Y-axis direction) and extends in the first direction (such as the X-axis direction). A part of the plurality of auxiliary alignment marks 4102 is uniformly arranged in the first direction (such as the X-axis direction) and extends in the second direction (such as the Y-axis direction); another part of the auxiliary alignment marks 4102 is uniformly arranged in the second direction (such as the Y-axis direction) and extends in the first direction (such as the X-axis direction). The main alignment marks 4101 extending in the first direction are perpendicular to the auxiliary alignment marks 4102 extending in the second direction, and the main alignment marks 4101 extending in the second direction are perpendicular to the auxiliary alignment marks 4102 extending in the first direction.

[0081] The shapes of multiple grating structures are all strip-shaped, and the extending direction of each grating structure intersects with the extending direction of the main alignment mark and the extending direction of the auxiliary alignment mark. In this way, when performing alignment and measurement operations on the main alignment mark 4101 and the auxiliary alignment mark 4102, the grating structures do not have any influence on the measurement and alignment of the main alignment mark 4101 and the auxiliary alignment mark 4102.

[0082] In some embodiments, the period width of the alignment grating in the alignment mark is different from the period width of the grating structure. Refer to Figure 4h , the alignment mark 410 includes multiple alignment gratings, the width period of each alignment grating is the first width W1, the auxiliary structure 407 includes multiple grating structures, the period width of each grating structure is the second width W2, and the first width W1 is greater than the second width W2. It should be understood that the difference in the period width of the grating structure in the auxiliary structure and the period width of the alignment grating in the alignment mark is beneficial to the measurement and alignment of the alignment mark. In other words, the grating structures in the auxiliary structure do not have any influence on the measurement and alignment of the alignment mark. For example, during the exposure process, the grating structures do not have a diffraction effect on the measurement and alignment of the alignment mark. It should be noted that the alignment grating can be understood as the main alignment mark 4101 and / or the auxiliary alignment mark 4102 in the above embodiments.

[0083] In some embodiments, the semiconductor layer includes a device region and a peripheral region located around the device region; wherein, the auxiliary structure is located in the peripheral region. In other embodiments, the auxiliary structure can also be located in the device region.

[0084] In some embodiments, an image mark is further included in the semiconductor layer; the image mark is located in the device region. Refer to Figure 4e , the auxiliary structure 407 can be used to perform optical proximity correction OPC on the image mark 408 during the exposure process, so that the pattern on the photoresist is consistent with the pattern on the mask layer, thereby ensuring the accuracy of the image mark 408.

[0085] Based on the above semiconductor structure, an embodiment of the present disclosure further provides a memory, including: the semiconductor structure as described in the above embodiments of the present disclosure.

[0086] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict. The above is only a preferred embodiment of the present disclosure, and is not used to limit the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, Comprising: A semiconductor layer; An auxiliary structure located in the semiconductor layer; wherein, the semiconductor layer comprises a first type of material, the auxiliary structure comprises a second type of material, and the hardness of the second type of material is greater than the hardness of the first type of material.

2. The semiconductor structure according to claim 1, wherein The projected shape of the auxiliary structure on a first surface includes: circular, rectangular, square, U-shaped; the first surface is parallel to the top surface of the semiconductor layer.

3. The semiconductor structure according to claim 2, wherein The auxiliary structure comprises a plurality of grating structures with the same shape and arranged periodically; the plurality of grating structures are spaced apart and arranged in the semiconductor layer.

4. The semiconductor structure according to claim 3, wherein The semiconductor structure further comprises: A photolithography layer covering the top surface of the auxiliary structure and the top surface of the semiconductor layer; the photolithography layer contains alignment marks.

5. The semiconductor structure according to claim 4, characterized in that, The projected area of the auxiliary structure on the first surface overlaps with the projected area of the alignment marks on the first surface; Or, The projected area of the auxiliary structure on the first surface is located around the projected area of the alignment marks on the first surface.

6. The semiconductor structure according to claim 4, characterized in that, The shape of the grating structure is strip-shaped; the shape of the alignment marks includes a plurality of strip-shaped main alignment marks arranged in sequence, and a plurality of strip-shaped auxiliary alignment marks arranged in sequence and perpendicularly intersecting the main alignment marks; Wherein, the extending direction of the grating structure intersects with the extending direction of the main alignment marks and the extending direction of the auxiliary alignment marks.

7. The semiconductor structure according to claim 4, wherein The periodic width of the alignment grating in the alignment marks is different from the periodic width of the grating structure.

8. The semiconductor structure according to claim 1, wherein The semiconductor layer comprises a device region and a peripheral region located around the device region; wherein, the auxiliary structure is located in the peripheral region.

9. The semiconductor structure according to claim 8, wherein, The semiconductor layer further comprises an image mark; the image mark is located in the device region.

10. The semiconductor structure according to claim 1, characterized in that, The first type of material comprises silicon; the second type of material comprises silicon oxide.

11. A memory, characterized in that, Comprising: The semiconductor structure according to any one of claims 1 to 10.

12. A method for fabricating a semiconductor structure, characterized in that, The method comprises: Providing a substrate, the substrate comprising a first type of material; Forming a dielectric layer in the substrate, the dielectric layer comprising a second type of material; Performing a polishing process on the substrate and the dielectric layer to form a semiconductor layer and an auxiliary structure located in the semiconductor layer; wherein, the hardness of the second type of material is greater than the hardness of the first type of material.

13. The manufacturing method according to claim 12, characterized in that, The forming the dielectric layer in the substrate comprises: Forming a plurality of grooves in the substrate; Filling the second type of material in the grooves to form the dielectric layer.

14. The manufacturing method according to claim 13, characterized in that, The performing a polishing process on the substrate and the dielectric layer to form a semiconductor layer and an auxiliary structure located in the semiconductor layer comprises: Performing chemical mechanical polishing on the top surface of the substrate and the top surface of the dielectric layer to remove part of the substrate and remove part of the dielectric layer, and the remaining substrate constitutes the semiconductor layer, and the remaining dielectric layer constitutes the auxiliary structure.

15. The manufacturing method according to claim 14, characterized in that, The projected shape of the auxiliary structure on a first surface includes: circular, rectangular, square, U-shaped; the first surface is parallel to the top surface of the semiconductor layer.

16. The manufacturing method according to claim 15, wherein The auxiliary structure includes a plurality of grating structures having the same shape and arranged periodically; the plurality of grating structures are spaced apart and disposed in the semiconductor layer.

17. The manufacturing method according to claim 16, characterized in that, The method further includes: forming a photolithography layer covering the top surface of the auxiliary structure and the top surface of the semiconductor layer; and forming alignment marks in the photolithography layer.

18. The manufacturing method according to claim 17, characterized in that, The projected area of the auxiliary structure on the first surface overlaps with the projected area of the alignment marks on the first surface; or the projected area of the auxiliary structure on the first surface is located around the projected area of the alignment marks on the first surface.

19. The manufacturing method according to claim 17, wherein, The shape of the grating structure is strip-shaped; the shape of the alignment marks includes a plurality of strip-shaped main alignment marks arranged in sequence and a plurality of strip-shaped auxiliary alignment marks arranged in sequence perpendicular to the main alignment marks; wherein, the extending direction of the grating structure intersects with the extending direction of the main alignment marks and the extending direction of the auxiliary alignment marks.

20. The manufacturing method according to claim 18, characterized in that, The period width of the alignment grating in the alignment marks is different from the period width of the grating structure.

21. The manufacturing method according to claim 12, wherein The semiconductor layer includes a device region and a peripheral region located around the device region; the auxiliary structure is located in the peripheral region; The method further includes: forming image marks in the device region.

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