200Gbps CWDM EML laser and preparation method thereof

Abstract

The invention provides a 200Gbps CWDM EML laser and a preparation method thereof, the EML is composed of four butt joint areas, specifically, a PQ waveguide is in butt joint with one end of a DFB laser diode to form a first butt joint area, the other end of the DFB laser diode is in butt joint with an isolation area PQ waveguide to form a second butt joint area, the isolation area PQ waveguide is in butt joint with one end of an EA modulator to form a third butt joint area, and the other end of the EA modulator is in butt joint with the other end of the DFB laser diode to form a fourth butt joint area. The other end of the EA modulator is in butt joint with the PQ waveguide to form a fourth butt joint area. The four butt joint areas are integrated on one EML laser, and the PQ waveguide, the DFB laser diode and the EA modulator are designed on the same ridge waveguide. According to the technical scheme, the integrated chip is manufactured through design of epitaxial PL, grating period, chip process and the like, the structural design gives play to the temperature advantage of the AlGaInAs active material, the active area is protected through PQ waveguide butt joint, and the reliability of the product is further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed EML lasers, in particular to a 200Gbps CWDM EML laser and a preparation method thereof. Background Art

[0002] Driven by market demands such as the growth of global AI computing power and the domestic "East Data West Computing" project, the demand for data center modules continues to grow, with a CAGR of about 10%. In particular, high-speed modules such as 400G / 800G are the growth focus in the next 3 to 5 years (about 10 million to 15 million pieces). The demand is mainly from North America, and domestic DCs adopt a follow-up strategy.

[0003] From the information in industry reports, the demand for 400G / 800G high-end modules in the Chinese region mainly comes from Alibaba, Tencent, Baidu, ByteDance, Huawei, etc. The generational switch of domestic data centers is at least 1 to 2 years later than that in North America. The demand for 400G has gradually increased since 2023, and the total demand for specifications above 400G to 800G is expected to be about 500,000 pieces in 2024 (relatively conservative data), and the demand growth in recent years has been about 100%.

[0004] From the perspective of high-end module solutions, silicon photonics solutions and the upcoming commercially available 200G PAM4 CWDM EML will replace part of the market of 100G PAM4 EML. Currently, the estimated shipment proportion of silicon photonics modules does not exceed 30%, and it is expected not to exceed 50% in the next 1 to 2 years. The shipment of 200G PAM4 EML is relatively less due to maturity and other issues. Therefore, there is still a large market space for the demand of 200G PAM4 EML in the future. The reliability of the existing 200G PAM4 EML in applications needs to be improved. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a 200Gbps CWDM EML laser and a preparation method thereof. By designing the epitaxial PL, grating period, chip process, etc., an integrated chip is fabricated. This structural design gives full play to the temperature advantage of the AlGaInAs active material and protects the active region through PQ waveguide butt joint, further improving the reliability of the product.

[0006] To achieve the above object, the present invention adopts the following technical solutions: A 200Gbps CWDM EML laser, the EML is composed of 4 butt-joint regions, specifically: One end of the PQ waveguide is butt-jointed with one end of the DFB laser diode to form the first butt-joint region, the other end of the DFB laser diode is butt-jointed with the PQ waveguide of the isolation region to form the second butt-joint region, one end of the PQ waveguide of the isolation region is butt-jointed with one end of the EA modulator to form the third butt-joint region, and the other end of the EA modulator is butt-jointed with the PQ waveguide to form the fourth butt-joint region; A total of 4 butt-joint regions are integrated on an EML laser, and the PQ waveguide, DFB laser diode, and EA modulator are designed on the same ridge waveguide.

[0007] In a preferred embodiment: One end of the DFB laser diode and one end of the EA modulator are both provided with a section of PQ waveguide for butt-joint; and there is a common PQ waveguide of the isolation region between the DFB laser diode and the EA modulator; The length of the DFB is 300 - 400um, and the length of the EA is 50 - 150um.

[0008] In a preferred embodiment: The lengths of the sections of PQ waveguide provided at one end of the DFB laser diode and one end of the EA modulator are both 15 - 30um.

[0009] In a preferred embodiment: The length of the common PQ waveguide of the isolation region provided between the DFB laser diode and the EA modulator is 30 - 80um.

[0010] In a preferred embodiment: The width of the ridge waveguide is 2.0 - 3.0um.

[0011] The present invention also provides a preparation method of a 200Gbps CWDM EML laser, for preparing the above-mentioned 200Gbps CWDM EML laser, including the following steps: Step 1: Grow a Base Wafer on an InP substrate by MOCVD, including an N-InP buffer layer, an InGaAlAs lower waveguide layer, an AlGaInAs active layer, an InGaAlAs upper waveguide layer, a P-InAlAs electron blocking layer, a P-InP Spacer layer, a P-InGaAsP etch stop layer, a P-InP Spacer layer, a P-InGaAsP grating layer, and a P-InP protection layer; Step 2: Fabricate a grating on the Base Wafer. After using holographic exposure to create a uniform part of the grating, send it for epitaxial burial. P-InP spacer layer is buried as a landfill protection layer for the grating. Then grow a SiO2 mask layer on its surface, and prepare the LD region through photolithography and etching. For the remaining regions, use ICP etching and wet etching to etch down to below the active region, and then send it for epitaxial growth for the docking growth of the EA structure. The EA growth includes an N-InP buffer layer, an N-InAlAs layer, an InGaAlAs lower waveguide layer, an AlGaInAs active layer, an InGaAlAs upper waveguide layer, a P-InAlAs electron blocking layer, a P-InP Spacer layer, a P-InGaAsP etch stop layer, and a P-InP protection layer. Step 3: After removing the SiO2 mask layer, grow a new SiO2 mask layer, and prepare a new LD region and EA structure through photolithography and etching. For the remaining regions, use ICP etching and wet etching to etch down to below the active region, and then send it for epitaxial growth for the docking growth of the PQ waveguide. The PQ waveguide includes a U-InP buffer layer, a U-InGaAsP waveguide layer, a U-InP protection layer, a U-InGaAsP etch stop layer, and a U-InP protection layer. After wet removing the SiO2 mask layer, send it for final burial, which includes a P-InP spacer layer, a P-InGaAsP transition layer, a P-InGaAs ohmic contact layer, and a P-InP protection layer, to form the final epitaxial wafer. Step 4: Perform chip fabrication on the epitaxial wafer. First, grow a SiO2 mask layer, then prepare the ridge waveguide layer through photolithography and wet etching. After removing all SiO2 mask layers, grow another SiO2 mask layer, and through photolithography and etching, perform isolation region etching on the isolation waveguide layer where the DFB laser diode is connected to the EA modulator to prepare the isolation resistance region. After removing the SiO2 mask layer, then grow Si3N4, and make openings on the ridge, including the DFB laser diode and EA modulator regions, and then perform thin gold evaporation and alloying on the ridge. Next, prepare the BCB region in the EA pad area, and after curing, make openings on the ridge on the BCB. Then grow another layer of Si3N4, continue to make openings on the ridge for the DFB and EA regions, and then perform P-side metal evaporation plating, and then arrange for thinning, thinning to a thickness of 90 - 120um, N-side metal GeAu-Ni-Au and N-side alloying, and then strip plating the optical film, and the chip fabrication is completed.

[0012] In a preferred embodiment: In step 1, the thickness of the N-InP buffer layer is 500 - 900 nm, the thickness of the InGaAlAs lower waveguide layer is 50 - 80 nm, the thickness of the AlGaInAs active layer is 80 - 110 nm, the thickness of the InGaAlAs upper waveguide layer is 30 - 50 nm, the thickness of the P-InAlAs electron blocking layer is 30 - 60 nm, the thickness of the P-InP Spacer layer is 30 - 60 nm, the thickness of the P-InGaAsP etch stop layer is 10 - 20 nm, the thickness of the P-InP Spacer layer is 40 - 60 nm, the thickness of the P-InGaAsP grating layer is 20 - 30 nm, and the thickness of the P-InP protective layer is 20 - 50 nm, thus completing the growth of the Base Wafer.

[0013] In a preferred embodiment: In step 2, on the Base Wafer, by holographic exposure and partial grating etching technology, a grating is fabricated only in the DFB region, and the grating occupies 40 - 70% of the DFB region. Then, epitaxial growth is arranged for InP burial, and the burial thickness is 130 - 170 nm. Then, the EA butt growth is carried out, and the thicknesses of each layer are respectively: N-InP buffer layer 50 - 200 nm, N-InAlAs layer 20 - 30 nm, InGaAlAs lower waveguide layer 20 - 30 nm, AlGaInAs active layer 140 - 170 nm, InGaAlAs upper waveguide layer 20 - 30 nm, P-InAlAs electron blocking layer 20 - 30 nm, P-InP Spacer layer 40 - 70 nm, P-InGaAsP etch stop layer 20 - 30 nm (required to be flush with the DFB etch stop layer), and P-InP protective layer 200 - 300 nm (required to be flush with the DFB surface layer).

[0014] In a preferred embodiment: In step 3, for the PQ waveguide butt growth, the thicknesses of each layer are respectively: U-InP buffer layer 50 - 200 nm, U-InGaAsP waveguide layer 200 - 250 nm, U-InP protective layer 40 - 70 nm, U-InGaAsP etch stop layer 20 - 30 nm (required to be flush with the DFB etch stop layer), and U-InP protective layer burial 200 - 300 nm (required to be flush with the DFB surface layer); the final burial thickness: P-InP spacer layer 1600 - 2000 nm, P-InGaAsP transition layer 40 - 70 nm, P-InGaAs ohmic contact layer 200 - 300 nm, and P-InP protective layer 20 - 30 nm.

[0015] In a preferred embodiment: In step 4, first grow a SiO2 mask layer on the epitaxial wafer, and then prepare the ridge waveguide layer by photolithography and wet etching. The width of the ridge waveguide is 2.0 - 3.0 um; after removing all SiO2, grow another layer of SiO2 with a thickness of 200 - 400 nm, perform ridge opening and shallow etching at the junction of DFB and EA, and etch until the remaining thickness of P-InP is 2 / 3 of the original thickness, thus completing the process of the isolation region; remove SiO2, grow 150 - 250 nm of Si3N4, then perform ridge opening and ID metal lithography on DFB and EA and arrange for evaporation of metal Ti-Au (50 - 100 nm) on the P side and alloying; then arrange for the BCB process, and retain 2 - 3 um thick BCB in the EA region; grow another 150 - 250 nm of Si3N4, and perform ridge opening on DFB and EA, evaporation of metal Ti-Pt-Au (50 - 100 - 100 nm) on the P side and plating of thick gold Au (1500 nm); then arrange for thinning, thin the thickness to 90 - 120 um, deposit metal GeAu-Ni-Au on the N side and perform N-side alloying, and then strip and plate the optical film, thus completing the fabrication of the chip.

[0016] Compared with the prior art, the present invention has the following beneficial effects: Compared with solutions such as Identical and SAG, it not only gives full play to the temperature advantage of the AlGaInAs active material, but also protects the active region through PQ waveguide butt-joint, further improving the reliability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is the epitaxial layer structure diagram of the 200Gbps CWDM EML laser of the embodiment of the present invention; Figure 2 is the chip schematic diagram of the 200Gbps CWDM EML laser of the embodiment of the present invention; Figure 3 is the 3D schematic diagram of the chip of the 200Gbps CWDM EML laser of the embodiment of the present invention; Figure 4 is the LIV test data of the 200Gbps CWDM EML laser of the embodiment of the present invention; Figure 5 is the bandwidth test data of the 200Gbps CWDM EML laser of the embodiment of the present invention; Figure 6 is the eye diagram test data of the 200Gbps CWDM EML laser of the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0019] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs.

[0020] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application; as used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should also be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0021] The present invention provides a 200 Gbps CWDM EML laser. Referring to Figures 1-6 , it is designed for the butt-joint integration of a DFB laser diode, an EA modulator, and a PQ waveguide. The structures of the three are different. By designing the epitaxial PL, grating period, chip process, etc., an integrated chip is fabricated.

[0022] The gist lies in: the PQ waveguide is butt-jointed with the DFB laser diode, the other end of the DFB is butt-jointed with the PQ waveguide in the isolation region, then the PQ waveguide in the isolation region is butt-jointed with the EA modulator, and the other end of the EA is butt-jointed with the PQ waveguide. A total of 5 sections are butt-jointed and integrated on an EML laser, and the PQ waveguide, DFB laser diode, and EA modulator are all designed on the same ridge waveguide.

[0023] As a design scheme for the butt-joint structure, it includes 4 butt-joint regions: the PQ waveguide is butt-jointed with the DFB laser diode, the other end of the DFB is butt-jointed with the PQ waveguide in the isolation region, then the PQ waveguide in the isolation region is butt-jointed with the EA modulator, and the other end of the EA is butt-jointed with the PQ waveguide. There is a section of PQ waveguide butt-jointed at both ends of the DFB laser diode and the EA modulator, and the waveguide length of both is 15 - 30 um; and there is a common PQ waveguide in the isolation region between the DFB and the EA, and the isolation region length of both is 30 - 80 um; the DFB length is 300 - 400 um, the EA length is 50 - 150 um, and the ridge waveguide width is 2.0 - 3.0 um.

[0024] On this basis, the design structure of the 200Gbps CWDM EML laser is grown in the following order. A Base Wafer is grown on an InP substrate by MOCVD, including an N-InP buffer layer (500 - 900 nm), an InGaAlAs lower waveguide layer (50 - 80 nm), an AlGaInAs active layer (80 - 110 nm), an InGaAlAs upper waveguide layer (30 - 50 nm), a P-InAlAs electron blocking layer (30 - 60 nm), a P-InP Spacer layer (30 - 60 nm), a P-InGaAsP etch stop layer (10 - 20 nm), a P-InP Spacer layer (40 - 60 nm), a P-InGaAsP grating layer (20 - 30 nm), and a P-InP protective layer (20 - 50 nm).

[0025] Furthermore, on the Base Wafer, a grating is fabricated only in the DFB region through holographic exposure and partial grating etching techniques, with the grating occupying 40 - 70% of the DFB region. Then, InP burial is arranged for epitaxy, with a burial thickness of 130 - 170 nm. Then, a 100 - 300 nm SiO2 mask layer is grown on its surface, and the LD region is prepared by photolithography and etching. The remaining regions are etched by ICP and wet etching to 50 - 200 nm below the lower waveguide, and then sent for epitaxial butt growth of the EA structure. The EA growth includes an N-InP buffer layer (50 - 200 nm, compensated according to the depth etched to the lower waveguide previously), an N-InAlAs layer (20 - 30 nm), an InGaAlAs lower waveguide layer (20 - 30 nm), an AlGaInAs active layer (140 - 170 nm), an InGaAlAs upper waveguide layer (20 - 30 nm), a P-InAlAs electron blocking layer (20 - 30 nm), a P-InP Spacer layer (40 - 70 nm), a P-InGaAsP etch stop layer (20 - 30 nm, required to be flush with the DFB etch stop layer), and a P-InP protective layer (200 - 300 nm, required to be flush with the DFB surface layer).

[0026] Further, after removing SiO2, a SiO2 mask layer of 100 - 300 nm is regrown. New LD and EA regions are fabricated by photolithography and etching. For the remaining regions, ICP etching and wet etching are used to etch to a depth of 50 - 200 nm below the lower waveguide, and then it is sent to epitaxy for the butt-joint growth of the PQ waveguide; the PQ waveguide includes a U-InP buffer layer (50 - 200 nm, compensated according to the depth of etching to the lower waveguide in the previous step), a U-InGaAsP waveguide layer (200 - 250 nm), a U-InP protective layer (40 - 70 nm), a U-InGaAsP etch stop layer (20 - 30 nm, which needs to be flush with the DFB etch stop layer), and a U-InP protective layer (200 - 300 nm, which needs to be flush with the DFB surface layer); after wet-etching the SiO2 layer, it is sent to epitaxy for final burial, which buries a P-InP spacer layer (1600 - 2000 nm), a P-InGaAsP transition layer (40 - 70 nm), a P-InGaAs ohmic contact layer (200 - 300 nm), and a P-InP protective layer (20 - 30 nm) to form the final epitaxial wafer.

[0027] Further, for the epitaxial wafer, a SiO2 mask layer of 100 - 300 nm is grown first, and then a ridge waveguide layer is fabricated by photolithography and wet etching, with the ridge waveguide width being 2.0 - 3.0 μm; after removing all SiO2, a layer of SiO2 of 200 - 400 nm is regrown. Ridge opening and shallow etching are performed at the junction of DFB and EA, and etching is carried out until the remaining thickness of P-InP is 2 / 3 of the original thickness, thus completing the process of the isolation region; after removing SiO2, 150 - 250 nm of Si3N4 is grown, and then ridge opening and ID metal lithography are performed on DFB and EA, and metal Ti-Au (50 - 100 nm) is arranged for P-side evaporation and alloying; then the BCB process is arranged, and a 2 - 3 μm thick BCB is retained in the EA region; 150 - 250 nm of Si3N4 is regrown, and ridge opening is performed on DFB and EA, and metal Ti-Pt-Au (50 - 100 - 100 nm) is evaporated on the P side and thick gold plating Au (1500 nm) is carried out; then thinning is arranged, and the thickness is thinned to 90 - 120 μm, metal GeAu-Ni-Au is plated on the N side and alloying is carried out on the N side, and then optical films are stripped and plated, thus completing the fabrication of the chip, as Figure 2 、 Figure 3 。

[0028] Specifically, the design structure of the 200 Gbps CWDM EML laser is as Figure 1As shown, first grow an N-InP buffer layer 1 (500 - 900 nm) on the InP sub-layer 0; then grow an InGaAlAs lower waveguide layer 2 (50 - 80 nm); then grow an AlGaInAs active layer 3 (80 - 110 nm); then grow an InGaAlAs upper waveguide layer 4 (30 - 50 nm); then is a P-InAlAs electron blocking layer 5 (30 - 60 nm); then grow a P-InP Spacer layer 6 (30 - 60 nm); then grow a P-InGaAsP etch stop layer 7 (10 - 20 nm); then grow a P-InP Spacer layer 8 (40 - 60 nm); then grow a P-InGaAsP grating layer 9 (20 - 30 nm) and a P-InP protection layer 10 (20 - 50 nm).

[0029] Next, by arranging holographic exposure and partial grating etching techniques, make a grating only in the DFB region, with the grating duty cycle controlled at 40 - 70% and occupying 40 - 70% of the DFB region. After that, arrange for epitaxial growth to bury the InP layer 11 with a burial thickness of 130 - 170 nm; then grow a 100 - 300 nm SiO2 mask layer on its surface, and prepare the LD region through photolithography and etching; for the remaining region, use ICP etching and wet etching to reach 50 - 200 nm below the lower waveguide layer 2, and then send it for epitaxial butt-joint growth of the EA structure; the EA growth sequentially includes an N-InP buffer layer (50 - 200 nm, compensated according to the previous etching depth to the lower waveguide), an N-InAlAs layer (20 - 30 nm), an InGaAlAs lower waveguide layer (20 - 30 nm), an AlGaInAs active layer (140 - 170 nm), an InGaAlAs upper waveguide layer (20 - 30 nm), a P-InAlAs electron blocking layer (20 - 30 nm), a P-InP Spacer layer (40 - 70 nm), a P-InGaAsP etch stop layer (20 - 30 nm, required to be flush with the DFB etch stop layer 7), and a P-InP protection layer (200 - 300 nm, required to be flush with the DFB surface InP layer 11).

[0030] Next, after removing SiO2, a SiO2 mask layer of 100 - 300 nm is grown again. New LD and EA regions are prepared by photolithography and etching. For the remaining regions, ICP etching and wet etching are used to etch to a depth of 50 - 200 nm below the lower waveguide layer 2, and then it is sent to epitaxy for the butt growth of the PQ waveguide. The PQ waveguide successively includes a U-InP buffer layer (50 - 200 nm, compensated according to the previously etched depth of the lower waveguide), a U-InGaAsP waveguide layer (200 - 250 nm), a U-InP protective layer (40 - 70 nm), a U-InGaAsP etch stop layer (20 - 30 nm, which needs to be flush with the DFB etch stop layer 7), and a U-InP protective layer (200 - 300 nm, which needs to be flush with the DFB surface InP layer 11). After wet-etching the SiO2 layer, it is sent to epitaxy for final burial, which buries a P-InP spacer layer 12 (1600 - 2000 nm), a P-InGaAsP transition layer 13 (40 - 70 nm), a P-InGaAs ohmic contact layer 14 (200 - 300 nm), and a P-InP protective layer 15 (20 - 30 nm) to form the final epitaxial wafer.

[0031] After the 200Gbps CWDM EML laser is fabricated, as Figure 3 shown, the specific fabrication steps are as follows: 1) First, a SiO2 mask layer of 100 - 300 nm is grown on the epitaxial wafer, and then a ridge waveguide layer is prepared by photolithography and wet etching, with the ridge waveguide width being 2.0 - 3.0 um. After removing all SiO2, a layer of SiO2 of 200 - 400 nm is grown again. 2) For the junction of DFB and EA, openings are made on the ridge and shallow etching is carried out until the thickness of P-InP remains 2 / 3 of its original thickness, thus completing the process of the isolation region. SiO2 is removed and a Si3N4 layer 16 of 150 - 250 nm is grown. 3) Then, openings are made on the ridge of DFB and EA, ID metal photolithography is arranged, and a P-side metal Ti-Au layer 17 (50 - 100 nm) is evaporated and alloyed. 4) Next, the BCB process is arranged, and a BCB layer 18 with a thickness of 2 - 3 um is retained in the EA region. Then a Si3N4 layer 19 of 150 - 250 nm is grown. 5) Again, openings are made on the ridge of DFB and EA, a P-side metal Ti-Pt-Au (50 - 100 - 100 nm) is evaporated, and thick gold Au (1500 nm) is electroplated. The DFB gold layer 20 and the EA gold layer 21 are formed. 6) Then, thinning is arranged to a thickness of 90 - 120 um, N-side metal GeAu-Ni-Au and N-side alloying are carried out, and then the optical film is strip-plated, thus completing the fabrication of the chip, as Figure 2 、 Figure 3 shown.

[0032] In subsequent chip LIV tests, at T = 50 °C, the Pf power reaches 13.85 mW @ 80 mA (as Figure 4 shown); the bandwidth test of the COC-level chip (as Figure 5 shown) reaches above 67 GHz (using a 67 GHz network analyzer, which has exceeded the upper limit of the test instrument); and good results are obtained in the 200 Gbps PAM4 COC-level eye diagram test (as Figure 6 shown).

[0033] This patent is not limited to the best implementation mode. Anyone inspired by this patent can obtain various other forms of 200 Gbps (and lower rate) CWDM EML lasers and their preparation methods. All equivalent changes and modifications made according to the scope of the patent application of this invention shall fall within the scope covered by this patent.

Claims

1. A 200Gbps CWDM EML laser, characterized in that: The EML consists of four docking areas, specifically: the PQ waveguide is docked with one end of the DFB laser diode to form a first docking area, the other end of the DFB laser diode is docked with the isolation area PQ waveguide to form a second docking area, the isolation area PQ waveguide is docked with one end of the EA modulator to form a third docking area, and the other end of the EA modulator is docked with the PQ waveguide to form a fourth docking area; a total of four docking areas are integrated on an EML laser, and the PQ waveguide, DFB laser diode, and EA modulator are designed on the same ridge waveguide.

2. A 200Gbps CWDM EML laser according to claim 1, characterized in that: One end of the DFB laser diode and the EA modulator are both provided with a section of PQ waveguide for docking; and a common isolation area PQ waveguide is provided between the DFB laser diode and the EA modulator; the DFB length is 300-400um, and the EA length is 50-150um.

3. A 200Gbps CWDM EML laser according to claim 1, characterized in that: The length of a PQ waveguide provided at one end of the DFB laser diode and the EA modulator is 15-30um.

4. The 200Gbps CWDM EML laser according to claim 1, characterized in that: The length of the common isolation region PQ waveguide provided between the DFB laser diode and the EA modulator is 30-80 um.

5. The 200Gbps CWDM EML laser according to claim 1, characterized in that: The ridge waveguide width is 2.0-3.0um.

6. A method for preparing a 200Gbps CWDM EML laser, characterized in that: The preparation of a 200 Gbps CWDM EML laser as claimed in any one of claims 1 to 5 comprises the following steps: Step 1: growing a Base Wafer on an InP substrate by MOCVD, including an N-InP buffer layer, an InGaAlAs lower waveguide layer, an AlGaInAs active layer, an InGaAlAs upper waveguide layer, a P-InAlAs electron blocking layer, a P-InP Spacer layer, a P-InGaAsP etching stop layer, a P-InP Spacer layer, a P-InGaAsP grating layer and a P-InP protective layer; Step 2: Make a grating on the Base Wafer. After making a uniform partial grating by holographic exposure, send it to epitaxy for burial. The buried P-InP space layer is used as the grating burial protection layer; then grow a SiO2 mask layer on its surface, and prepare the LD area by photolithography and etching; the remaining area is etched by ICP and wet etching to below the active area, and then sent to epitaxy for docking growth of EA structure; EA growth includes N-InP buffer layer, N-InAlAs layer, InGaAlAs lower waveguide layer, AlGaInAs active layer, InGaAlAs upper waveguide layer, P-InAlAs electron blocking layer, P-InP Spacer layer, P-InGaAsP etching stop layer, and P-InP protective layer; Step 3: After removing the SiO2 mask layer, grow a new SiO2 mask layer, prepare a new LD area and EA structure by photolithography and etching, use ICP etching and wet etching for the remaining areas, etch below the active area, and then send the epitaxy for docking growth of PQ waveguide; the PQ waveguide includes U-InP buffer layer, U-InGaAsP waveguide layer, U-InP protective layer, U-InGaAsP etching stop layer, and U-InP protective layer; after removing the SiO2 mask layer by wet method, send the epitaxy for final burial, which is buried with P-InP space layer, P-InGaAsP transition layer, P-InGaAs ohmic contact layer, and P-InP protective layer to form the final epitaxial wafer; Step 4: Chip production is carried out on the epitaxial wafer. First, a SiO2 mask layer is grown, and then a ridge waveguide layer is prepared by wet photolithography. After removing all SiO2 mask layers, another SiO2 mask layer is grown. By photolithography and etching, an isolation area is etched on the isolation waveguide layer connecting the DFB laser diode and the EA modulator to prepare an isolation resistor area. After removing the SiO2 mask layer, Si3N4 is grown to open windows on the ridge, including the DFB laser diode and the EA modulator area, and then a thin gold vapor deposition and alloy is performed on the ridge. Next, a BCB area is prepared in the EA pad area, and a hole is opened on the ridge on the BCB after solidification. Then another Si3N4 layer is grown, and windows are continued to be opened on the ridge of the DFB and EA areas, and then P-side metal vapor deposition and chemical plating are performed, and then thinning is arranged to reduce the thickness to 90-120um, N-side metal GeAu-Ni-Au and N-side alloy, and then strip-plating of optical film is performed to complete the chip production.

7. The method for preparing a 200Gbps CWDM EML laser according to claim 6, characterized in that: In step 1, the thickness of the N-InP buffer layer is 500-900nm, the thickness of the InGaAlAs lower waveguide layer is 50-80nm, the thickness of the AlGaInAs active layer is 80-110nm, the thickness of the InGaAlAs upper waveguide layer is 30-50nm, the thickness of the P-InAlAs electron blocking layer is 30-60nm, the thickness of the P-InP Spacer layer is 30-60nm, the thickness of the P-InGaAsP corrosion stop layer is 10-20nm, the thickness of the P-InP Spacer layer is 40-60nm, the thickness of the P-InGaAsP grating layer is 20-30nm, and the thickness of the P-InP protective layer is 20-50nm, and the growth of the Base Wafer is completed.

8. The method for preparing a 200Gbps CWDM EML laser according to claim 6, characterized in that: In step 2, on the base wafer, a grating is made only in the DFB area through holographic exposure and partial grating etching technology, and the grating occupies 40-70% of the DFB area, and then epitaxy is arranged to bury InP with a buried thickness of 130-170nm; then the EA is butt-grown, and the thickness of each layer is: N-InP buffer layer 50-200nm, N-InAlAs layer 20-30nm, InGaAlAs lower waveguide layer 20-30nm, AlGaInAs active layer 140-170nm, InGaAlAs upper waveguide layer 20-30nm, P-InAlAs electron blocking layer 20-30nm, P-InP Spacer layer 40-70nm, P-InGaAsP etching stop layer 20-30nm, P-InP protective layer 200-300nm.

9. The method for preparing a 200Gbps CWDM EML laser according to claim 6, characterized in that: In step 3, the PQ waveguide is butt-grown, and the thickness of each layer is: U-InP buffer layer 50-200nm, U-InGaAsP waveguide layer 200-250nm, U-InP protective layer 40-70nm, U-InGaAsP corrosion stop layer 20-30nm, U-InP protective layer buried 200-300nm; the final buried thickness is: P-InP space layer 1600-2000nm, P-InGaAsP transition layer 40-70nm, P-InGaAs ohmic contact layer 200-300nm, P-InP protective layer 20-30nm.

10. The method for preparing a 200Gbps CWDM EML laser according to claim 6, characterized in that: In step 4, a SiO2 mask layer is first grown on the epitaxial wafer, and then a ridge waveguide layer is prepared by wet photolithography, and the ridge waveguide width is 2.0-3.0um; after removing all SiO2, a layer of 200-400nm SiO2 is grown, and holes are opened on the ridge and shallow etching is performed at the junction of DFB and EA, and the thickness of P-InP is etched to 2 / 3 of the thickness, and the isolation area process is completed; SiO2 is removed, 150-250nm Si3N4 is grown, and then holes are opened on the ridge and ID metal is photolithography is performed on DFB and EA, and Ti-Au is evaporated on the P surface and alloyed; then a BCB process is arranged, and a 2-3um thick BCB is retained on the EA area; 150-250nm Si3N4 is grown again, and holes are opened on the ridges of DFB and EA, and Ti-Pt-Au is evaporated on the P surface and thick gold Au is plated; Then arrange thinning, reduce the thickness to 90-120um, N-side metal GeAu-Ni-Au and N-side alloy, and then strip-plate optical film to complete the chip production.

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