Slope protection circuit

Abstract

A power integrated circuit includes: at least one group III nitride high voltage high electron mobility transistor (power HEMT), the power HEMT including a heterojunction formed between a GaN layer and an AlGaN layer; and a slope protection circuit. The slope protection circuit includes a clamp transistor electrically connected between a gate terminal and a source terminal of the power HEMT, and a detection circuit. The detection circuit is electrically connected between the drain terminal and the source terminal of the power HEMT, wherein the output terminal of the detection circuit is electrically connected with the gate terminal of the clamping transistor. The detection circuit is configured to output a signal to turn on the clamp transistor when the transient voltage is observed to be greater than a threshold transient voltage between the drain and source of the power HEMT.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. More specifically, but not limited thereto, the present invention relates to heterostructure A1GaN / GaN high electron mobility transistors or rectifiers. Background Art

[0002] Gallium nitride (GaN) is a wide-bandgap material with properties that make it an ideal choice for a number of application areas that require or benefit from solid-state devices, such as radio-frequency electronics, optoelectronics, and power electronics.

[0003] GaN technology allows transistors with high electron mobility and saturation velocity to be designed. These properties of GaN make it an ideal choice for high-power and high-temperature microwave applications, such as radar and cellular communication systems.

[0004] In addition, GaN has a wide bandgap and thus has the potential to emit light at higher frequencies, such as in the green (about 495 nm - 570 nm), blue (about 450 nm - 495 nm), violet (about 380 nm - 450 nm), and ultraviolet (about 100 nm - 400 nm) parts of the electromagnetic spectrum.

[0005] Gallium nitride (GaN) has recently been recognized as a very promising material for use in the field of power devices. Application areas include portable consumer electronics, solar inverters, electric vehicles, and power supplies. This material has a wide bandgap (Eg = 3.39 eV) and thus a relatively high critical electric field (Ec = 3.3 MV / cm), which helps in designing devices with shorter drift regions, thereby reducing the on-resistance and providing better performance compared to silicon-based devices with the same breakdown voltage.

[0006] Using an aluminum gallium nitride (AlGaN) / gallium nitride heterostructure, a two-dimensional electron gas (2DEG) can also be formed at the heterointerface, where the mobility of the carriers can reach very high values (μ = 2000 cm 2 / (Vs)). In addition, the piezoelectric polarization charges in the A1GaN / GaN heterostructure result in a very high electron density in the 2DEG layer (e.g., 1x10 13 cm -2 ). These properties make high electron mobility transistors (HEMTs) and Schottky barrier diodes have highly competitive performance parameters. A commonly used parameter for comparing power semiconductor transistors is the specific on-resistance or specific Rds(ON). Specific Rds(ON) is typically the product of the device resistance and the device area on the wafer. A large amount of research has focused on using A1GaN / GaN heterostructures to develop power devices.

[0007] In addition, the use of GaN devices can reduce switching losses, thereby increasing the switching frequency, and further increasing the power density and efficiency of power conversion devices. For the same on-state Rds(0N) resistance, the input and output capacitances of GaN power devices are generally lower than those of silicon IGBTs and MOSFETs, resulting in a higher dV / dt signal across the device and enabling faster switching speeds. While this is beneficial in many applications, the presence of parasitic elements in the device and circuit can lead to unwanted oscillations. To avoid oscillations, it is recommended to add an external gate resistor to the device to reduce the observed dV / dt and dI / dt rates (L. Efthymiou et al, 0n the Source of 0scillatory Behaviour during Switching of Power Enhancement Mode GaN HEMTs, Energies, vol. 10, no. 3, 2017). However, adding an external gate resistor may increase the switching cycle and the overall switching losses of the device.

[0008] The dV / dt value (also known as the voltage slew rate) of a power switching device is caused by the interaction between various parasitic capacitances and the impedance of the gate drive circuit, and is determined by the charging and discharging rates of the power device capacitance and any capacitance in the circuit in which the power device operates. High slew rates are typically common in bridge topologies with high voltage buses, and the high switching speed of gallium nitride technology exacerbates this phenomenon. Multiple strategies for improving dV / dt immunity have been proposed in the prior art.

[0009] One solution for improving dV / dt immunity is monolithic integrated active Miller clamping. An active Miller clamp is a transistor connected between the gate and source of a power device. The combination of the power transistor and other monolithic integrated components is designed to provide sensing and protection functions and is commonly referred to as a power integrated circuit (IC). In operation, when the power device is in the off state, the active Miller clamp is in the on state to provide a low impedance path between the gate and source of the power device. This ensures that any parasitic conduction effects are limited during the off state or turn-off of the power device. The active Miller clamp is also designed to be in the off state when the power device is in the on state to establish a gate drive voltage between the gate and source of the power device. Therefore, the active Miller clamp needs to switch between the on and off states, typically requiring a switching drive signal to be applied to its gate. The active Miller clamp driver is usually powered by a fixed voltage supply. The driver is typically an inverter, and the control signal (or a level-shifted version of the control signal) is used as an input to drive the power device.

[0010] U.S. Patent Application Publication No. 2023 / 0131602 proposes a heterojunction power device that incorporates an auxiliary gate region and an auxiliary two-dimensional carrier (e.g., 2DEG) region. The heterojunction power device may further include an active Miller clamp to provide an additional pull-down network for the active (high-voltage) device gate terminal during device turn-off transients. However, in general, the active Miller clamp circuit can operate more effectively when a voltage (Vdd) is established to power the active Miller clamp drive circuit. In the absence of Vdd, high dV / dt values during device switching transients can cause false turn-on of the transistor. In a typical half-bridge topology, this can lead to breakdown (R. Xie, H. Wang, G. Tang, X. Yang and K. J. Chen, "An Analytical Model for False Turn-0n Evaluation of High-Voltage Enhancement-Mode GaN Transistor in Bridge-Leg Configuration," in IEEE Transactions on Power Electronics, vol. 32, no. 8, pp. 6416-6433, Aug. 2017, doi: 10.1109 / TPEL.2016.2618349).

[0011] Accordingly, the applicant has recognized the need for an alternative solution to help provide dV / dt robustness during periods when the Miller clamp is not operative. SUMMARY OF THE INVENTION

[0012] An object of the present invention is to provide a slew rate protection circuit that can provide the same or better protection against false turn-on as a monolithically integrated active Miller clamp transistor without the need to establish a voltage source (VDD) to do so. The slew rate protection circuit can protect power devices in a power integrated circuit (IC) from false triggering due to rapid transients at the output terminals (e.g., drain, source).

[0013] The slew rate protection circuit (or a portion thereof) operates only for a short period of time before a voltage source (VDD) is established that can power the active Miller clamp driver. The VDD can be an externally applied voltage or a regulated voltage generated on the power integrated circuit. Once the voltage source for the active Miller clamp driver is established, the slew rate protection circuit can be turned off.

[0014] Overall, this can result in a device that has a higher resistance to false triggering during all operating periods, including start-up periods before the voltage and / or regulated voltage is established in a power electronic circuit.

[0015] According to a first aspect of the present invention, there is provided a power integrated circuit, comprising:

[0016] at least one group III nitride high-voltage high electron mobility transistor (i.e., a power HEMT), the power HEMT including a heterojunction formed between a GaN layer and an AlGaN layer; and

[0017] a slope protection circuit, comprising:

[0018] a clamping transistor electrically connected between the gate terminal and the source terminal of the power HEMT, and

[0019] a detection circuit electrically connected between the drain terminal and the source terminal of the power HEMT, wherein an output terminal of the detection circuit is electrically connected to the gate terminal of the clamping transistor.

[0020] Wherein, when a transient voltage greater than a threshold transient voltage is observed between the drain terminal and the source terminal of the power HEMT, the detection circuit is configured to output a signal to turn on the clamping transistor.

[0021] Thus, a power integrated circuit is described herein, which includes a first main terminal, a second main terminal, and a control terminal. The power integrated circuit further includes a semiconductor switch, the semiconductor switch including:

[0022] a group III nitride high-voltage high electron mobility transistor (HEMT), having at least three terminals, namely a source terminal, a drain terminal, and a gate terminal, and having at least one GaN layer and at least one AlGaN layer, and at least one heterojunction formed between the at least one GaN layer and the at least one AlGaN layer; and

[0023] a slope protection circuit. The slope protection circuit further includes:

[0024] an enhancement or depletion mode clamping transistor connected between the gate terminal and the source terminal of the power HEMT,

[0025] an (edge) detection circuit connected between the drain terminal and the source terminal of the power HEMT, wherein an output terminal of the edge detection circuit is connected to the gate terminal of the enhancement mode clamping transistor.

[0026] Wherein, the detection circuit is configured to turn on the enhancement mode clamping transistor when a fast positive dv / dt is observed between the terminals of the power HEMT.

[0027] The detection circuit can be configured to turn on the enhancement-mode clamping transistor only when there is no voltage supply. For example, the slope protection circuit can further include a disabling circuit that can disable the operation of the detection circuit when there is a voltage supply. The disabling circuit can include a disabling transistor connected between the gate terminal and the source terminal of the enhancement-mode clamping transistor.

[0028] For example, the detection circuit includes a passive differentiator, namely a capacitor and a resistor connected in series, and the midpoint between them is the output terminal of the edge detection circuit. Alternatively, the detection circuit includes a source-gate connected transistor and a resistor in series, and the midpoint between them is the output terminal of the edge detection circuit.

[0029] The output terminal of the detection circuit can be connected to the gate of the enhancement-mode clamping transistor through a high-voltage diode.

[0030] For example, the power integrated circuit is a group-III nitride power integrated circuit, and all components are monolithically integrated. Alternatively, the slope protection circuit can be integrated on a silicon chip co-packaged with a group-III nitride chip, and the group-III nitride chip includes a power HEMT and a clamping transistor (such as a Miller clamp).

[0031] For example, the power integrated circuit further includes an interface circuit operatively connected between the control terminal of the power integrated circuit and the gate terminal of the power HEMT. The interface circuit can be part of the power integrated circuit or part of a separate group-III nitride or silicon circuit.

[0032] The power integrated circuit can further include a drive circuit for the clamping transistor, such as an inverter circuit, which is operatively connected to the gate terminal of the clamping transistor. The drive circuit can be operated / powered by an (external) voltage source. Alternatively, the power integrated circuit can include a second clamping transistor (such as a Miller clamp), which is also connected between the gate terminal and the source terminal of the power HEMT, and the drive circuit can be the drive circuit of the second clamping transistor.

[0033] In either case, the control terminal of the power integrated circuit can be operatively connected to the drive circuit through a signal conditioning circuit. The signal conditioning circuit can include one or more of a level shifter, a buffer circuit, a filter, a logic circuit, and / or a timing circuit.

[0034] The power integrated circuit can further include any one or more of the following components or circuits:

[0035] Miller clamp HEMT;

[0036] Pull-down circuit;

[0037] Voltage regulator;

[0038] Current source;

[0039] Detect the load resistance;

[0040] Short - circuit detection circuit;

[0041] Detection and protection circuit;

[0042] Over - current protection circuit;

[0043] Over - temperature protection circuit;

[0044] Driver circuit;

[0045] Startup circuit;

[0046] Electro - static discharge circuit;

[0047] Logic circuit;

[0048] Capacitor;

[0049] Resistor; and / or

[0050] Diode.

[0051] It will be appreciated that the diode used herein may refer to any component configured to facilitate the forward flow of current and block the reverse flow of current. For example, the diode in the present invention may include or be replaced by any one or more of a p - n junction diode, a Schottky diode, a source - gate - connected transistor, or any other suitable device.

[0052] According to a second aspect of the present invention, there is provided a system, the system comprising:

[0053] A power integrated circuit, comprising:

[0054] At least one group - III nitride high - voltage high - electron - mobility transistor (i.e., power HEMT), the power HEMT comprising a heterojunction formed between a GaN layer and an AlGaN layer; and

[0055] A clamping transistor electrically connected between the gate terminal and the source terminal of the power HEMT; A silicon chip co - packaged with the power integrated circuit, the silicon chip comprising:

[0056] A detection circuit electrically connected between the drain terminal and the source terminal of the power HEMT

[0057] wherein the output of the detection circuit is electrically connected to the gate terminal of the clamping transistor; and

[0058] wherein the detection circuit is configured to output a signal to turn on the clamping transistor when a transient voltage greater than a threshold transient voltage is observed between the drain terminal and the source terminal of the power HEMT.

[0059] The silicon chip may further include one or more of the following:

[0060] A voltage regulator;

[0061] An inductive load resistor;

[0062] A short - circuit detection circuit;

[0063] An inductive and protection circuit;

[0064] An over - current protection circuit;

[0065] An over - temperature protection circuit;

[0066] A drive circuit;

[0067] A startup circuit;

[0068] An electrostatic discharge circuit; and / or

[0069] A logic circuit.

[0070] The above - mentioned power integrated circuit may be the power integrated circuit according to the first aspect of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The content of the present invention can be more comprehensively understood through the drawings, but the drawings should not be regarded as limiting the present invention to the specific embodiments shown. Instead, the drawings are only for explanation and understanding.

[0072] Figure 1 The circuit schematic diagram of the active Miller clamp circuit is shown.

[0073] Figure 2 A bridge - arm circuit is shown, which includes two power HEMTs and related active Miller clamp HEMTs.

[0074] Figure 3 Another example of the half - bridge configuration of the power device is shown.

[0075] Figure 4 The circuit schematic diagram of an example slope protection circuit according to the present invention is shown.

[0076] Figure 5 The circuit schematic diagram of another example slope protection circuit according to the present invention is shown.

[0077] Figure 6 The circuit schematic diagram of another example slope protection circuit according to the present invention is shown.

[0078] Figure 7 The circuit schematic diagram of another example slope protection circuit according to the present invention is shown.

[0079] Figure 8Shows a circuit schematic diagram of another exemplary slope protection circuit according to the present invention.

[0080] Figure 9 Shows a circuit schematic diagram of an exemplary detection protection circuit according to the present invention.

[0081] Figure 10 Shows a circuit schematic diagram of another exemplary detection protection circuit according to the present invention.

[0082] Figure 11 Shows a circuit schematic diagram of another exemplary slope protection circuit according to the present invention.

[0083] Figure 12 Shows a schematic diagram of an exemplary chipset according to the present invention. Detailed implementation

[0084] Figure 1 Shows a circuit schematic diagram of an active Miller clamp circuit. Figure 1 Includes a first transistor with its source 16, drain 12, and gate 15 connected, a second transistor 34, and an active Miller clamp circuit. The active Miller clamp circuit includes a resistor 52, an active switch low-voltage enhancement-mode transistor 50, and an active switch depletion-mode transistor 51. The active Miller clamp circuit is used to provide an additional pull-down network for the device gate terminal 10 during the device turn-off transient period. In operation, the active Miller clamp uses the voltage bias of an external gate terminal (i.e., the terminal connected to the gate driver) to adjust the resistance of the active switch transistor 51 so as to provide a low-resistance pull-down path when the main power device is being turned off or is in the off state. When the gate driver signal is high, the gate of the active switch transistor 51 in the Miller clamp is biased low (so its resistance is high), and vice versa.

[0085] However, when the voltage (Vdd) is established to power the drive circuit of the active Miller clamp circuit, the active Miller clamp circuit can work more effectively. Without Vdd, the high dV / dt value during the device switching transient may cause the transistor to turn on erroneously. In a typical half-bridge topology, this may lead to breakdown.

[0086] During power-up, it may happen that the active Miller clamp is needed during the operation of a safety power integrated circuit (IC), but the necessary voltage supply has not been established yet. Figure 2 Shows an example of a power electronic circuit where this may occur.

[0087] Figure 2Shows a circuit schematic of a bridge arm circuit. The circuit includes two power HEMTs connected in a bridge arm structure, their associated Miller clamps, Miller clamp drive circuits, and associated interface circuits. These circuits can be integrated as part of a power integrated circuit (IC). The power integrated circuit can be driven by a controller / driver circuit. Both the power integrated circuit and the controller / driver circuit require a voltage supply to operate (VDDL for the low-side circuit, VDDH for the high-side circuit), so the drivers of the power HEMTs are powered by VDDL and VDDH of the low-side (LS) and high-side (HS) respectively. The Miller clamp HEMT is driven by an inverter, which can also be powered by the low VDDL and high VDDH respectively. The low-side power supply can be provided by a DC voltage rail through a startup circuit. The high-side power supply can be provided by the low-side power supply through a bootstrap diode.

[0088] As shown in the figure, there may be an interface circuit (or auxiliary gate circuit) between the driver and the power HEMT. During circuit startup, the low-side power supply VDDL can be charged from the DC link through the startup circuit. In this way, the low-side power HEMT can start switching according to the control signal of the controller / driver. In the first few switching cycles, the high-side voltage VDDH may not have been established through the bootstrap diode D1 yet. Therefore, in this case, due to the switching of the low-side device, a fast slope may be observed at the midpoint of the bridge arm, while the Miller clamp of the high-side device has not been powered by VDDH yet. This may cause the high-side device to conduct erroneously and breakdown of the bridge arm to occur.

[0089] In other words, when Figure 2 the power electronic circuit starts up, the low-voltage power supply VDDL may be established before the high-voltage power supply VDDH. Therefore, the low-side (LS) power HEMT may start switching before the high-voltage power supply VDDH is established. Therefore, fast dv / dt transients may occur at the drain-source terminals of the high-side (HS) power HEMT. For example, during the conduction of the low-side power HEMT, since there is no high-voltage power supply VDDH, the active Miller clamp shown in the figure cannot fully operate, which may cause the device to conduct erroneously. If the low-side and high-side power HEMTs conduct simultaneously, breakdown may also occur during this period.

[0090] Figure 3Shows another example of a half - bridge configuration of a power device. When the gate of the high - side power device starts to conduct, the high drain voltage of the HS device is converted at the source, which in turn pulls up the drain of the LS device. The Miller capacitance between the gate and the drain of the low - side switch starts to charge and injects current into the gate of the LS. If the current injected into the gate is large enough to make the gate voltage of the LS device higher than the device threshold voltage, parasitic conduction will occur, resulting in reduced efficiency or even device failure. As described above, using an active Miller clamp between the gate and the source of the power device is one of the techniques to mitigate or avoid such spurious conduction. However, in the case where the voltage source (VDD) of the inverter driving the Miller clamp has not been established, the active Miller clamp cannot conduct, and when current passes through the Miller capacitance, the Miller clamp cannot maintain the gate voltage below the required threshold.

[0091] Figure 4 Shows a circuit schematic example of a slope protection circuit 200 connected to a power HEMT device 101 and its associated circuits according to the content of the present invention. These circuits can be monolithically integrated as part of a power integrated circuit (such as power IC 100) having at least three terminals, which are a high - voltage terminal (T2), a low - voltage terminal (T1), and a control terminal. The power integrated circuit 100 can be driven by a controller / driver circuit, which can be connected to the control terminal. The power HEMT 101 can be connected to the control terminal through an associated interface circuit 300. In one embodiment of the present invention, the power HEMT 101 is a high - side GaN HEMT. The interface circuit 300 is placed in front of the gate of the high - side GaN HEMT (e.g., connected between the control terminal and the gate of the power HEMT 101) to match the drive voltage of the control terminal with the drive voltage of the GaN HEMT. For example, the drive voltage range of the gate terminal can be 0V to 20V, while the drive voltage output by the interface circuit 300 (and thus directly seen by the gate terminal of the high - side GaN HEMT) remains in the range of 0 to 7V.

[0092] The shown slope protection circuit 200 can operate without a voltage source VDD. The slope protection circuit includes a detection circuit (including capacitor 201 and resistor 203) and transistor 202. Transistor 202 can be connected to the Miller clamp transistor in a similar manner, that is, it is connected between the gate and the source of the power HEMT 101 to facilitate a low - parasitic connection between the two terminals when needed. Transistor 202 is driven by the detection circuit, which in this case includes a passive differentiator circuit. If a fast transient (e.g., > 100V / ns) is observed between the drain and the source of the power HEMT 101, the passive differentiator circuit will output the derivative of the transient signal as an output. Thus, if a fast positive transient (e.g., > 100V / ns) is observed (at Figure 2Or Figure 3 In the circuit of Figure 3 , this may trigger mis - conduction of the power HEMT through the Miller capacitance. The passive differentiator will output a positive peak to the gate of the dv / dt clamping transistor 202. This can turn on the dv / dt clamping transistor 202 and provide a low - parasitic path to suppress the mis - turn - on event. Therefore, the slope protection circuit 200 can also be referred to as a dv / dt hold - off circuit.

[0093] In practical applications, it may be necessary to disable the slope protection circuit. This can be achieved by a disabling circuit as shown in Figure 5 The disabling circuit includes a transistor 204 whose gate terminal is connected to the voltage source VDD. When enabled, the disabling circuit enables the power integrated circuit 100 to "turn off" the function of the slope protection circuit 200. Thus, when the voltage source VDD is established (and thus when the active Miller clamp is in normal operation), the power integrated circuit 100 can operate without interference from the slope protection circuit 200. Disabling the slope protection circuit 200 can promote more stable overall operation of the power integrated circuit 100 because any potential false triggering of the slope protection circuit 200 (e.g., due to noise or other parasitic signals) can be reduced or avoided. Although the disabling circuit is described in several embodiments hereinbelow, it should be understood that in all these embodiments, this remains an optional feature.

[0094] Figure 6 Another circuit schematic of the slope protection circuit 200 is shown. In this example, the detection circuit includes a resistor 203 and a high - voltage enhancement - mode transistor 205.

[0095] In this embodiment, the high - voltage enhancement - mode transistor 205 is a source - gate - connected HEMT, which forms a detection circuit in series with the resistor 203, and the mid - point is used as the output of the circuit detection circuit. The source - gate - connected HEMT has an output capacitance C oss , which operates in a similar manner to the capacitor 201 shown in the previous embodiment. Compared with a metal - insulator - metal (MIM) capacitor, the source - gate - connected HEMT may have higher area efficiency.

[0096] Advantageously, the source - gate - connected transistor 205 can be a scaled - down version (in terms of gate width or area) of the power HEMT 101. In this case, the HEMT 205 has a voltage - dependent capacitance similar to that of the power HEMT 101. Therefore, the output peak of the detection circuit can better match the peak of the stray voltage on the gate of the power HEMT 101. In addition, the scaled HEMT 205 can have the same high - voltage rating as the power HEMT 101.

[0097] In another example, the Miller capacitance of HEMT 205 can be designed to produce sufficient output to trigger the dv / dt clamping circuit before a drain-source dV / dt related spike is observed on the gate-source terminal of power HEMT 101 through the Miller capacitance. This can be achieved by device cross-section engineering to increase the Miller capacitance of HEMT 205 at low drain-gate voltage Vgd (e.g., Vgd < 50V). For example, for Vgd less than 50V, the Miller capacitance per unit width of HEMT 205 may be approximately or substantially equal to twice the Miller capacitance per unit width of power HEMT 101.

[0098] Figure 7 A circuit schematic of the present invention is shown, in which a slope protection circuit 200 composed of a detection circuit, a dv / dt clamping transistor 202, and an optional disabling circuit is configured. The detection circuit includes a capacitor 201 and a resistor 203. The series combination of the capacitor 201 and the resistor 203 forms a detection circuit, and the midpoint is connected to the gate of the dv / dt clamping transistor 202.

[0099] In addition, Figure 7 A Miller clamping transistor 102 driven by an inverter circuit 301 powered by a voltage source VDD is also shown. The inverter circuit 301 can be operated by a regulated gate signal by passing the gate signal through a signal conditioning module or circuit 302. The signal conditioning module 302 can include one or more level converters, buffer circuits, filters, and / or logic circuits. The entire circuit can be part of a GaN power integrated circuit 100, as shown in the previous embodiments.

[0100] The dv / dt clamping transistor 202 and the Miller clamping transistor 102 can be enhancement-mode transistors. Alternatively, they can be depletion-mode transistors, such as the transistors described in U.S. Patent No. 11658236.

[0101] In Figure 7In the case where the power HEMT 101 in [the circuit] is a low-side device in a half-bridge configuration, when it is turned off, if the high-side device is turned on, the rapid voltage transient at the drain of the low-side power HEMT 101 will charge the parasitic capacitance between the gate and the drain and may erroneously turn on the power HEMT 101. If VDD does not exist for some reason, the Miller clamp 102 will not conduct, and thus cannot provide a low-resistance path for the incoming current. As a result, the gate voltage of the power HEMT 101 may increase, leading to mis-conduction and breakdown of the low-side power HEMT 101. However, in this case, the slope protection circuit 200 can help reduce or avoid the mis-conduction of the low-side power HEMT 101. For example, the rapid voltage transient between the drain and source of the power HEMT 101 can pull up node A through the capacitance C1 of the capacitor 201. This increases the voltage applied to the gate of the dv / dt clamp transistor 202 and can turn on the transistor 202. This in turn provides a low-resistance path for the current from the Miller capacitance of the power HEMT 101, thus avoiding the spike on the gate of the power HEMT 101. Therefore, the mis-conduction event of the power HEMT 101 may be able to be limited or completely avoided.

[0102] The slope protection circuit 200 is also equipped with a disabling circuit including the transistor 204, which can be modulated by the same voltage source VDD that powers the drive circuit of the Miller clamp transistor. When VDD is established (i.e., when the Miller clamp can operate), the transistor 204 turns on and the voltage at node A is pulled low, thus turning off the slope protection circuit 200. Alternatively, the transistor 204 can be modulated by a gate signal from a control port instead of the voltage source VDD. When the transistor 204 is modulated by the gate signal, under normal operation, the dv / dt clamp transistor 202 and the Miller clamp 102 may have stronger dv / dt immunity.

[0103] Figure 8 Another schematic diagram of the circuit principle of the present invention is shown. As Figure 6 shown, in this example, the detection circuit includes a resistor 203 and a high-voltage enhancement-mode transistor 205 with its source and gate connected in place of the capacitor 201, and a Miller clamp transistor 102 and a signal conditioning block or circuit 302 driven by an inverter circuit 301, as described above with reference to Figure 7 the above.

[0104] Figure 9 Another example of the detection circuit is shown, which is applicable to any slope protection circuit. Therefore, it can be understood that Figure 9 the detection circuit shown in [the figure] can replace the above-mentioned Figures 4 - 8The detection circuit shown in []. The detection circuit may include a threshold multiplier circuit to replace resistor 203, as shown in the previous embodiment. The threshold multiplier circuit helps limit the maximum spike observed at the output of the detection circuit. This can further protect the transistor gate connected to the output of the detection circuit (e.g., dv / dt claim 202).

[0105] Figure 10 Another additional example of the detection circuit is shown, which is applicable to any example of the slope protection circuit. Therefore, it can be understood that Figure 10 the detection circuit shown in []. can replace any of the detection circuits shown above Figures 4 - 8 In this example, a series of source-gate or drain-gate connected HEMTs are connected in parallel with a resistor (e.g., resistor 203) to help limit the maximum spike observed at the output of the detection circuit. Only two HEMTs are shown in this embodiment, but in other embodiments, more (e.g., 3, 4, or more HEMTs in series) or fewer (e.g., a single HEMT) HEMTs can be used depending on the maximum allowable voltage required at the output of the detection circuit.

[0106] As Figure 11 shown, the slope protection circuit 200 of the present invention can be integrated with the existing Miller clamp 102. In this configuration, the Miller clamp 102 can act as a dv / dt clamp. Therefore, compared with the configurations of Figure 7 and Figure 8 , the overall circuit configuration described in Figure 11 can have one less transistor, which is beneficial for saving chip area. A diode 206 can be provided to facilitate the slope protection circuit 200 to control the Miller clamp 102. In this example, the Miller clamp 102 conducts only when the voltage at node A is higher than the output voltage of the inverter 301. Therefore, when VDD cannot be established for some reason and a high voltage dv / dt transient appears at the drain of the power HEMT 101 (causing the inverter 301 to be unable to activate the Miller clamp 102), the slope protection circuit 200 may activate the Miller clamp 102. Once VDD is established, the transistor 204 is turned on, thereby pulling down node A and reverse biasing the diode 206. Therefore, the slope protection circuit 200 is disabled, and the Miller clamp 102 operates according to the input of the drive circuit / control port.

[0107] Compared with the diode 206, the area of the dv / dt clamp transistor 202 may be larger. Therefore, using the diode 206 is beneficial for saving chip area. In addition, when the slope protection circuit 200 is disabled, the diode 206 can avoid or reduce the power dissipated by the Miller clamp 102 in the slope protection circuit 200.

[0108] It will be understood that diode 206 can be any element configured to facilitate forward current flow and block reverse current flow. For example, diode 206 can include or be replaced by any one or more of a p-n junction diode, a Schottky diode, a source-gate connected transistor, or any other suitable device.

[0109] Figure 12 A silicon companion chip 1000 is shown, which can be co-packaged with a power HEMT, such as power HEMT 101. A Miller clamp 102, as a driver low-side component, can be monolithically integrated with the power HEMT 101. A slope protection circuit 200 can be integrated in the silicon companion chip 1000. Additionally, the companion chip 1000 can provide various other functions, such as voltage regulation 1008, voltage clamping action, under-voltage lockout 1005, high-side drive 1001, current sensing 1002, bandgap reference (1003), over-current protection 1004, over-temperature detection / protection 1007, level shifting 1009, electrostatic discharge (ESD) protection circuit 1010, logic circuit 1011, and startup circuit 1012, as well as other sensing and protection functions. It can have programmable functions and can be fabricated using a mixed-signal process, thus allowing digital and analog components to be integrated together.

[0110] Those skilled in the art will understand that in the foregoing description and the appended claims, positional terms are defined with reference to the conceptual diagrams (as shown in the drawings). These terms are used for ease of reference but are not intended to limit their meaning. Accordingly, these terms should be understood to refer to the positions of the components shown in the drawings.

[0111] Although the present invention has been described in accordance with the above preferred embodiments, it should be understood that these embodiments are for illustrative purposes only and the claims are not limited to these embodiments. Those skilled in the art can make modifications and substitutions based on the present invention, and these modifications and substitutions fall within the scope of the appended claims. Each feature disclosed or illustrated in this specification can be incorporated into this specification alone or in any suitable combination with any other feature disclosed or illustrated in this specification.

[0112] Those skilled in the art will also think of many other effective alternatives. It should be understood that this specification is not limited to the described embodiments but includes all modifications that are consistent with the spirit and scope of this specification.

Claims

1. A power integrated circuit, comprising: at least one Group III-nitride HEMT including a heterojunction formed between a GaN layer and an AlGaN layer; as well as Slope protection circuit, including: a first clamp transistor electrically connected between a gate terminal and a source terminal of the III-nitride HEMT; a detection circuit electrically connected between a drain terminal and a source terminal of the III-nitride HEMT; wherein an output of the detection circuit is electrically connected to a gate terminal of the first clamp transistor; and The detection circuit is configured to output a signal to turn on the first clamp transistor when a transient voltage greater than a threshold transient voltage is observed between the drain terminal and the source terminal of the III-nitride HEMT. 2 . The power integrated circuit of claim 1 , wherein the first clamp transistor is an enhancement mode transistor.

3. The power integrated circuit according to claim 1 or 2, wherein the slope protection circuit comprises a disabling circuit electrically connected to a voltage supply terminal, wherein when a voltage applied to the voltage supply terminal is greater than a threshold voltage, the disabling circuit is configured to disable the slope protection circuit.

4. The power integrated circuit according to claim 3, wherein: The inhibit circuit comprises an inhibit transistor, wherein: The source terminal of the inhibit transistor is electrically connected to the source terminal of the first clamp transistor; A drain terminal of the inhibit transistor is electrically connected to a gate terminal of the first clamp transistor; and A gate terminal of the inhibiting transistor is electrically connected to the voltage supply terminal.

5. The power integrated circuit according to any one of claims 1-2, wherein the detection circuit comprises a resistance element and a capacitance element connected in series, and a midpoint between the resistance element and the capacitance element is electrically connected to the gate terminal of the first clamp transistor.

6. The power integrated circuit according to claim 5, wherein the capacitive element comprises: A transistor having a source-gate connection; or Capacitor.

7. The power integrated circuit of claim 6, wherein the capacitive element comprises a source-gate connected transistor, and wherein the source-gate connected transistor has substantially the same structure as a III-nitride HEMT, and wherein an area or gate perimeter of the source-gate connected transistor is X times smaller than an area or gate perimeter of the III-nitride HEMT, where X is a scaling factor and X is greater than 1.

8. The power integrated circuit according to any one of claims 1 to 2, wherein the resistance element comprises one or more of the following: Resistors; and Threshold multiplier circuit.

9. The power integrated circuit of claim 8, wherein the prime resistance element comprises a resistor, and the detection circuit further comprises one or more transistors connected in parallel with the resistor, wherein the one or more transistors comprise a series of source-gate connected or drain-gate connected transistors.

10. The power integrated circuit of any one of claims 1-2, comprising a component electrically connected between the output of the detection circuit and the gate terminal of the first clamp transistor, wherein the component is configured to block or limit reverse flow of current. The power integrated circuit of claim 10 , wherein the component is a diode.

12. The power integrated circuit according to any one of claims 1 to 2, further comprising: An interface circuit is electrically connected between a control terminal of the power integrated circuit and the gate terminal of the III-nitride HEMT.

13. The power integrated circuit of claim 12, wherein the interface circuit is an external circuit connected to the power integrated circuit.

14. The power integrated circuit of claim 12, wherein the interface circuit is monolithically integrated with the power integrated circuit. 15 . The power integrated circuit of claim 1 , further comprising a drive circuit electrically connected to the gate terminal of the first clamp transistor.

16. The power integrated circuit according to claim 1, further comprising: a second clamp transistor electrically connected between the gate terminal and the source terminal of the III-nitride HEMT; as well as A drive circuit is electrically connected to the gate terminal of the second clamp transistor.

17. A power integrated circuit according to claim 15, wherein the slope protection circuit includes a disabling circuit electrically connected to a voltage supply terminal, wherein when a voltage applied to the voltage supply terminal is greater than a threshold voltage, the disabling circuit is configured to disable the slope protection circuit; and wherein the drive circuit is operated or powered by the voltage applied to the voltage supply terminal.

18. The power integrated circuit according to any one of claims 15 to 17, wherein the driving circuit is an inverter circuit.

19. The power integrated circuit according to any one of claims 15 to 17, wherein the drive circuit is electrically connected to a control terminal of the power integrated circuit through a signal conditioning circuit.

20. The power integrated circuit of claim 19, wherein the signal conditioning circuit comprises one or more of: a level shifter, a buffer circuit, a filter, a logic circuit, and / or a timing circuit.

21. The power integrated circuit of any one of claims 1-2, wherein the threshold transient voltage is 100 volts per nanosecond.

22. The power integrated circuit of claim 1, comprising one or more of the following: Miller clamped HEMT; Pull-down circuit; Voltage stabilizer; Current source; Detect load resistance; Short circuit detection circuit; Detection and protection circuits; Overcurrent protection circuit; Over temperature protection circuit; Driving circuit; Start circuit; Electrostatic discharge circuits; Logic circuits; Capacitors; Resistors; and / or diode.

23. The power integrated circuit according to any one of claims 1 to 2, wherein: The slope protection circuit is monolithically integrated with the power integrated circuit.

24. A system comprising: Power integrated circuits, including: at least one Group III-nitride HEMT including a heterojunction formed between a GaN layer and an AlGaN layer; and a clamp transistor electrically connected between a gate terminal and a source terminal of the III-nitride HEMT; A silicon chip packaged together with the power integrated circuit, the silicon chip comprising: a detection circuit electrically connected between a drain terminal and a source terminal of the III-nitride HEMT; wherein an output of the detection circuit is electrically connected to a gate terminal of the clamp transistor; and Wherein, when a transient voltage greater than a threshold transient voltage is observed between the drain terminal and the source terminal of the III-nitride HEMT, the detection circuit is configured to output a signal to turn on the clamp transistor.

25. The system of claim 24, wherein: The silicon chip further comprises one or more of the following: Voltage regulator; Inductive load resistance; Short circuit detection circuit; Detection and protection circuits; Overcurrent protection circuit; Over temperature protection circuit; Driving circuit; Start circuit; Electrostatic discharge circuits; and / or Logic circuit.

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