Photovoltaic input port coupling voltage suppression circuit and photovoltaic system

Abstract

The present invention discloses a photovoltaic input port coupling voltage suppression circuit and a photovoltaic system, comprising a plurality of resistors, a plurality of operational amplifiers, a plurality of switching tubes, a diode, and a relay. Among the plurality of resistors, one end of a resistor R1 is connected to a coupling voltage V2 and a common end of a relay K1, and the other end is connected to a non-inverting end of an operational amplifier U1; the output end of the operational amplifier U1 is connected to an inverting end and one end of a resistor R4; the other end of the resistor R4 is connected to one end of a resistor R6 and a non-inverting end of an operational amplifier U3; the inverting end of the operational amplifier U3 is connected to one end of a resistor R5 and one end of a resistor R8, and the output end is connected to the other end of the resistor R8 and a gate of a MOS tube Q1; the source of the MOS tube Q1 is connected to one end of a CE1 circuit or a CE2 circuit; the other ends of the CE1 circuit and the CE2 circuit are connected to a normally closed contact of a relay K1; the output end of the operational amplifier U2 is connected to an inverting end and the other end of the resistor R5, and a reference voltage of a conduction voltage difference of the MOS tube Q1 is set at the non-inverting end of the operational amplifier U2; the normally open contact of the relay K1 is connected to a photovoltaic terminal input voltage V1 and one end of a resistor R10.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a photovoltaic input port coupling voltage suppression circuit and a photovoltaic system. Background Art

[0002] The function of a photovoltaic inverter is to convert the direct current (DC) generated by photovoltaic panels into alternating current (AC) to meet the power needs of the grid or load. A typical photovoltaic inverter is equipped with multiple input terminals, each of which can be connected to one or more photovoltaic panel assemblies. To address the voltage coupling problem during the photovoltaic inverter process, Patent Publication No. CN118783384A proposes a photovoltaic input port coupling voltage suppression circuit and photovoltaic system solution. This solution effectively reduces the coupling voltage on the non-input line by setting a precise threshold voltage. However, the output voltage of the photovoltaic panel fluctuates with changes in light intensity and temperature. These fluctuations are further amplified through the inversion and coupling processes, forming a dynamic coupling voltage that is difficult to accurately predict. This can cause the driving voltage of the switching transistor to deviate from the optimal operating range. When the deviation exceeds the VGS breakdown threshold of the switching transistor, it can easily cause device burnout or startup failure. Furthermore, because the switching transistor has a turn-on threshold voltage, when the coupling voltage approaches but does not reach this threshold, the switching transistor will be in the off state, resulting in a residual voltage that is difficult to eliminate. Summary of the Invention

[0003] In view of the deficiencies in the prior art, the present invention provides a photovoltaic input port coupling voltage suppression circuit and a photovoltaic system, which solve the problems mentioned in the background art.

[0004] To achieve the above objectives, the present invention is implemented through the following technical solutions: a photovoltaic input port coupling voltage suppression circuit, including a plurality of resistors, a plurality of operational amplifiers, a plurality of switching tubes, a diode, and a relay, wherein one end of the resistor R1 among the plurality of resistors is connected to the coupling voltage V2 and the common end of the relay K1, and the other end is connected to the in-phase end of the operational amplifier U1; the output end of the operational amplifier U1 is connected to the inverting end and one end of the resistor R4; the other end of the resistor R4 is connected to one end of the resistor R6 and the in-phase end of the operational amplifier U3; the inverting end of the operational amplifier U3 is connected to one end of the resistor R5 and one end of the resistor R8, and the output end is connected to the other end of the resistor R8 and the gate of the MOS tube Q1; the source of the MOS tube Q1 is connected to one end of the CE1 line or the CE2 line ; The other ends of the CE1 and CE2 lines are connected to the normally closed contact of relay K1; the output end of op amp U2 is connected to the inverting end and the other end of resistor R5, and the non-inverting end of op amp U2 sets the MOS tube Q1 conduction voltage difference reference voltage; the normally open contact of relay K1 is connected to the photovoltaic input voltage V1 and one end of resistor R10; the other end of resistor R10 is connected to the non-inverting end of op amp U4; the output end of op amp U4 is connected to the base of transistor Q2; the collector of transistor Q2 is connected to one end of resistor R11; the other end of resistor R11 is connected to the anode of D1 and one end of the relay K1 coil; the other end of the relay K1 coil, the cathode of D1 and the power supply are connected; the drain of MOS tube Q1, the emitter of transistor Q2 and the ground are connected;

[0005] In order to solve the burning and startup failure caused by the driving voltage deviating beyond the breakdown threshold when the coupling voltage changes, and the residual discharge generated when the coupling voltage approaches but does not reach the threshold value, the scheme controls the VGS voltage of the MOS tube Q1 to always be at the optimal working point by sampling the coupling voltage V2, where the input voltage of the photovoltaic input end is marked as V1, and the coupling voltage on the line is marked as V2. Resistor R1 first samples and detects the coupling voltage V2 on the photovoltaic input end, and the sampled voltage is fed back to the non-inverting end of the operational amplifier U1. The inverting end of the operational amplifier U1 is connected to the output end of the operational amplifier U1. The operational amplifier U1 isolates the output coupling voltage V2, and the output signal of the operational amplifier U1 is passed through resistors R4 and resistor After the R6 loop, it is fed back to the non-inverting terminal of the operational amplifier U3. At the same time, the non-inverting terminal of the operational amplifier U2 inputs the optimal voltage difference parameter signal from the gate to the source of the MOS tube Q1 and is isolated by the resistor R5 from the output terminal of the operational amplifier U2 and input to the inverting terminal of the operational amplifier U3. After the output terminal of the operational amplifier U3 forms feedback with the inverting terminal of the operational amplifier U3 through the resistor R8, the voltage difference between the non-inverting terminal of the operational amplifier U3 and the inverting terminal of the operational amplifier U3 is output based on the current V2 voltage to the gate of the MOS tube Q1 to avoid the driving voltage VGS of the MOS tube Q1 from deviating beyond the breakdown threshold when the coupling voltage V2 changes. When the output of the operational amplifier U3 is to the MOS tube Q1, the MOS tube Q1 is turned on and the MOS tube Q1 is turned on. The source of the S tube Q1 discharges the coupled voltage V2 through the CE1 or CE2 post-stage circuit, and discharges along with the coupled voltage V2. When the V2 voltage is lower than the VGS conduction threshold of the MOS tube Q1, the output of the operational amplifier U3 compensates the negative voltage to the gate of the MOS tube Q1 to keep the MOS tube Q1 at the optimal working point to discharge the residual voltage. The resistor R10 is a sampling resistor, which is used to sample the input voltage V1 of the photovoltaic input terminal and input it to the non-inverting terminal of the operational amplifier U4. When the operational amplifier uses a non-rail device, the inverting terminal of the operational amplifier U4 is set by the resistor R7 and the resistor R9 or the power supply to set the reference voltage. The voltage parameter is greater than the offset voltage. When a rail operational amplifier is used, the operational amplifier U4 output is The output is the ground terminal potential. At this time, the resistor R7 can be removed. When the photovoltaic input terminal input voltage V1 is true, the operational amplifier U4 compares the voltages of the inverting terminal and the non-inverting terminal of the operational amplifier U4 and outputs a signal to the base of the transistor Q2. The transistor Q2 is turned on, and the power supply at one end of the relay K1 coil passes through the resistor R11, the collector of the transistor Q2, the emitter of the transistor Q2, and the ground terminal circuit. The relay K1 coil is closed, and the auxiliary contact of the relay K1 turns to normally open, disconnecting V2 from the source of the MOS tube Q1. When the photovoltaic input terminal input voltage V1 is false, the relay K1 is reset to the state shown in the figure. V2 can be connected to the source of the MOS tube Q1 via the CE1 line or the CE2 line to limit the current.

[0006] Preferably, it also includes a plurality of resistors, a plurality of operational amplifiers, capacitors, an inverter, and a digital potentiometer. Among the plurality of resistors, one end of the resistor R15, the 3-pin of the digital potentiometer, and the other end of the CE2 line are connected, and the other end is connected to one end of the resistor R16 and the non-inverting end of the operational amplifier U7; the inverting end of the operational amplifier U7 is connected to one end of the capacitor C1 and one end of the resistor R17, and the output end is connected to the other end of the resistor R16, the other end of the resistor R17, and the inverting end of the operational amplifier U6; the non-inverting end of the operational amplifier U6 is set with a reference voltage of the voltage drop change point of the resistor R15 and the resistor R16; the 1-pin of the digital potentiometer U5 is connected to the output end of the operational amplifier U6, the 5-pin is connected to the 6-pin and one end of the CE2 line, the 2-pin is connected to the output end of the inverter U8, and the 7-pin is connected to the ground end; the input end of the inverter U8 is connected to the output end of the operational amplifier U4; the other end of the capacitor C1 is connected to the ground end;

[0007] Among them, it is to be provided that when the coupling voltage V2 fluctuates too much, CE2 can be connected to the source of the MOS tube Q1 to keep the discharge rate of the MOS tube Q1 consistent when the coupling voltage V2 changes, so as to avoid overcurrent and slow discharge voltage accumulation. The resistance input terminal of the digital potentiometer U5 is connected to the normally closed auxiliary contact of the relay K1 as a current limiter, and the cursor and the resistance output terminal are connected to the source of the MOS tube Q1 in parallel. When the seventh pin of the digital potentiometer U5 has no upper control, it is connected to the ground by default. The second pin of the digital potentiometer U5 is controlled by the output terminal of the inverter U8. When the input voltage V1 of the photovoltaic input terminal is false, the inverting terminal of the operational amplifier U4 is greater than the voltage of the non-inverting terminal of the operational amplifier U4, and the operational amplifier U 4 When the output offset voltage is cut off or off-rail, the voltage potential is lower than the positive conduction voltage of the NMOS tube inside the inverter U8. The inverter U8 still inverts the output signal to the second pin of the digital potentiometer U5. When there is an input to the second pin of the digital potentiometer U5, the digital potentiometer U5 is ready to be adjusted from high resistance to low resistance. The adjustment signal is input to the first pin of the digital potentiometer U5 by the operational amplifier U6. At the same time, the coupling voltage is sampled by the resistor R15 and input to the non-inverting terminal of the operational amplifier U7. The other way is input to the output terminal of the operational amplifier U7 through the resistor R16. The voltage at the connection terminal of the sampling capacitor C1 and the resistor R17 at the inverting terminal of the operational amplifier U7 is greater than that at the inverting terminal. Phase terminal voltage, the output signal of the operational amplifier U7 is fed back to the capacitor C1 through the resistor R17. When the voltage at the inverting terminal of the operational amplifier U7 increases as the voltage of the resistor R17 and the capacitor C1 integration is greater than the non-inverting terminal of the operational amplifier U7, the operational amplifier U7 has no output. The coupling voltage V2 at the resistor R15 terminal is fed back to the output terminal of the operational amplifier U7 through the resistor R16. The voltage at the connection terminal of the resistor R15 and the resistor R16 drops. At the same time, the voltage at the capacitor C1 terminal is fed back to the output terminal of the operational amplifier U7 through the resistor R17. The voltage of the capacitor C1 gradually decreases. When the voltage at the capacitor C1 terminal is lower than the non-inverting terminal of the operational amplifier U7, the operational amplifier U7 outputs again to pull up the voltage at the connection terminal of the resistor R15 and the resistor R16. The resistor R17 and the capacitor C1 are integrated again. When the coupling voltage V2 changes, the voltage The voltage drop at the connection end of resistor R15 and resistor R16 increases. During the voltage drop period of resistor R15 and resistor R16, the output end of operational amplifier U7 feeds back a signal to the inverting end of operational amplifier U6. The non-inverting end of U6 sets the reference voltage of the voltage drop change point of resistor R15 and resistor R16. The operational amplifier U6 outputs a signal to the first pin of the digital potentiometer U5, which controls the digital potentiometer U5 to gradually decrease from high resistance to low resistance, so that the discharge rate of MOS tube Q1 is consistent when the coupling voltage V2 changes. Until the input voltage V1 of the photovoltaic input end is true, the coil of relay K1 is closed and the connection between V2 and the source of MOS tube Q1 is disconnected again. The reference voltage of the non-inverting end of operational amplifier U6 and operational amplifier U2 can be set by resistor voltage divider or power supply.

[0008] Preferably, a resistor is further included, and a resistor R12 is connected in series at both ends of the CE1 line;

[0009] Among them, when the coupling voltage V2 is connected to the source of the MOS tube Q1 through the CE1 line, the loop of V2 passes through the normally closed contact of the relay K1, the resistor R12, the source of the MOS tube Q1, and the drain of the MOS tube Q1 to be grounded, and the resistor R12 is used to limit the current.

[0010] Preferably, the in-phase terminal of the operational amplifier U2 is connected to one end of the resistor R2 and one end of the resistor R3; the other end of the resistor R3 is connected to the power supply; the other end of the resistor R2 is connected to the ground;

[0011] Among them, the reference voltage of the op amp U2 non-inverting terminal can be set by resistor voltage division or power supply.

[0012] Preferably, a resistor is further included, wherein one end of the resistor R9 is connected to the inverting end of the operational amplifier U4, and the other end is connected to the ground end;

[0013] Among them, the inverting terminal of the operational amplifier U4 is set with a reference voltage by resistors R7 and R9 or a power supply when the operational amplifier adopts a non-rail device, and the voltage parameter is greater than the offset voltage. When a rail operational amplifier is used, when there is no input at the non-inverting terminal of the operational amplifier U4, the output of the operational amplifier U4 is the ground terminal potential. At this time, only resistor R9 can be used.

[0014] Preferably, a resistor is further included, wherein one end of the resistor R7 is connected to the inverting terminal of the operational amplifier U4, and the other end is connected to the power supply;

[0015] Among them, the inverting terminal of the operational amplifier U4 is set with a reference voltage by resistors R7 and R9 or a power supply when the operational amplifier adopts a non-rail device, and the voltage parameter is greater than the offset voltage.

[0016] Preferably, it further comprises a plurality of resistors, wherein one end of the resistor R14 is connected to one end of the resistor R13 and the in-phase terminal of the operational amplifier U6, and the other end is connected to the ground terminal; the other end of the resistor R13 is connected to the power supply;

[0017] Among them, the reference voltage of the op amp U6 and the op amp U2 in-phase terminal can be set by resistor voltage division or power supply.

[0018] The present invention further provides a photovoltaic system comprising any of the above-mentioned photovoltaic input port coupling voltage suppression circuits.

[0019] The photovoltaic input port coupling voltage suppression circuit and photovoltaic system provided by the present invention have the following beneficial effects:

[0020] The drive voltage VGS can be kept in the optimal operating range when the coupling voltage changes, avoiding malfunctions caused by deviations exceeding the breakdown threshold. Compensation is also performed to remove residual voltage when the coupling voltage falls below the conduction threshold. The discharge rate can be controlled when the coupling voltage fluctuates significantly, avoiding overcurrent and voltage accumulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the structure of a photovoltaic input port coupling voltage suppression circuit of the present invention. DETAILED DESCRIPTION

[0022] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0023] The present invention provides a photovoltaic input port coupling voltage suppression circuit, comprising a plurality of resistors, a plurality of operational amplifiers, a plurality of switching tubes, a diode, and a relay. Among the plurality of resistors, one end of a resistor R1 is connected to a coupling voltage V2 and a common end of a relay K1, and the other end is connected to a non-inverting end of an operational amplifier U1; the output end of the operational amplifier U1 is connected to an inverting end and one end of a resistor R4; the other end of the resistor R4 is connected to one end of a resistor R6 and a non-inverting end of an operational amplifier U3; the inverting end of the operational amplifier U3 is connected to one end of a resistor R5 and one end of a resistor R8, and the output end is connected to the other end of the resistor R8 and a gate of a MOS tube Q1; the source of the MOS tube Q1 is connected to one end of a CE1 line or a CE2 line; the CE1 line is connected to the CE2 The other end of the line is connected to the normally closed contact of relay K1; the output end of op amp U2 is connected to the inverting end and the other end of resistor R5, and the non-inverting end of op amp U2 sets the MOS tube Q1 conduction voltage difference reference voltage; the normally open contact of relay K1 is connected to the photovoltaic input voltage V1 and one end of resistor R10; the other end of resistor R10 is connected to the non-inverting end of op amp U4; the output end of op amp U4 is connected to the base of transistor Q2; the collector of transistor Q2 is connected to one end of resistor R11; the other end of resistor R11 is connected to the anode of D1 and one end of the relay K1 coil; the other end of the relay K1 coil, the cathode of D1 and the power supply are connected; the drain of MOS tube Q1, the emitter of transistor Q2 and the ground end are connected.

[0024] Specifically, it also includes several resistors, several operational amplifiers, capacitors, inverters, and digital potentiometers. Among the several resistors, one end of resistor R15, pin 3 of the digital potentiometer, and the other end of CE2 are connected, and the other end is connected to one end of resistor R16 and the non-inverting end of operational amplifier U7; the inverting end of operational amplifier U7 is connected to one end of capacitor C1 and one end of resistor R17, and the output end is connected to the other end of resistor R16, the other end of resistor R17, and the inverting end of operational amplifier U6; pin 1 of digital potentiometer U5 is connected to the output end of operational amplifier U6, pin 5 is connected to pin 6 and one end of CE2, pin 2 is connected to the output end of inverter U8, and pin 7 is connected to the ground end; the input end of inverter U8 is connected to the output end of operational amplifier U4; the other end of capacitor C1 is connected to the ground end.

[0025] Specifically, a resistor R12 is further included, and two ends of the CE1 line are connected in series.

[0026] Specifically, the non-inverting terminal of the operational amplifier U2 is connected to one end of the resistor R2 and one end of the resistor R3; the other end of the resistor R3 is connected to the power supply; and the other end of the resistor R2 is connected to the ground.

[0027] Specifically, a resistor is also included, wherein one end of the resistor R9 is connected to the inverting end of the operational amplifier U4, and the other end is connected to the ground end.

[0028] Specifically, a resistor is also included, wherein one end of the resistor R7 is connected to the inverting end of the operational amplifier U4, and the other end is connected to the power supply.

[0029] Specifically, it also includes several resistors, among which one end of the resistor R14 is connected to one end of the resistor R13 and the in-phase terminal of the operational amplifier U6, and the other end is connected to the ground terminal; the other end of the resistor R13 is connected to the power supply.

[0030] The present invention further provides a photovoltaic system, comprising any one of the photovoltaic input port coupling voltage suppression circuits described above.

[0031] See Figure 1In one embodiment, the problem to be solved is the burnout and startup failure caused by the driving voltage deviating beyond the breakdown threshold when the coupling voltage changes, as well as the residual discharge generated when the coupling voltage approaches but does not reach the threshold value. In this embodiment, the VGS voltage of the MOS tube Q1 is controlled to always be at the optimal operating point by sampling the coupling voltage V2, wherein the input voltage of the photovoltaic input terminal is labeled V1, and the coupling voltage on the line is labeled V2. Resistor R1 first samples and detects the coupling voltage V2 on the photovoltaic input terminal, and the sampled voltage is fed back to the non-inverting terminal of the operational amplifier U1. The inverting terminal of the operational amplifier U1 is connected to the output terminal of the operational amplifier U1. The operational amplifier U1 isolates the output coupling voltage V2, and the output signal of the operational amplifier U1 is fed back to the non-inverting terminal of the operational amplifier U3 after passing through the circuit of resistors R4 and R6. The op amp U3 output terminal is connected to the inverting terminal of the MOS tube Q1, and the op amp U3 output terminal is isolated by the resistor R5 and then input to the inverting terminal of the MOS tube Q1. After the op amp U3 output terminal forms feedback with the inverting terminal of the MOS tube U3 through the resistor R8, the voltage difference between the op amp U3 inverting terminal and the op amp U3 inverting terminal is output to the gate of the MOS tube Q1 based on the current V2 voltage to avoid the drive voltage VGS of the MOS tube Q1 from shifting beyond the breakdown threshold when the coupling voltage V2 changes. When the op amp U3 outputs to the MOS tube Q1, the MOS tube Q1 is turned on, and the source of the MOS tube Q1 discharges the coupling voltage V2 through the CE1 or CE2 post-stage circuit. As the coupling voltage V2 changes, the optimal driving voltage VGS is output. Discharge, when the V2 voltage is lower than the VGS conduction threshold of the MOS tube Q1, the output end of the operational amplifier U3 compensates the negative voltage to the gate of the MOS tube Q1 to make the MOS tube Q1 still at the optimal working point to discharge the residual voltage. The resistor R10 is a sampling resistor, which is used to sample the input voltage V1 of the photovoltaic input end and input it to the non-inverting end of the operational amplifier U4. When the operational amplifier uses a non-rail device, the reference voltage of the inverting end of the operational amplifier U4 is set by the resistor R7 and the resistor R9 or the power supply. The voltage parameter is greater than the offset voltage. When the rail operational amplifier is used, when there is no input at the non-inverting end of the operational amplifier U4, the output of the operational amplifier U4 is the ground terminal potential. At this time, the resistor R7 can be removed. When the input voltage V1 of the photovoltaic input end is true, the operational amplifier U4 compares the voltage of the inverting end and the non-inverting end of the operational amplifier U4 and outputs the signal to the three The base of transistor Q2 is connected, and transistor Q2 is turned on. The power supply at one end of the relay K1 coil is connected through the resistor R11, the collector of transistor Q2, the emitter of transistor Q2, and the ground terminal. The relay K1 coil is closed, and the auxiliary contact of relay K1 turns normally open, disconnecting V2 from the source of MOS tube Q1. When the input voltage V1 at the photovoltaic input end is false, relay K1 is reset to the state shown in the figure. V2 can be connected to the source of MOS tube Q1 via the CE1 line or the CE2 line to limit the current. When the coupling voltage V2 is connected to the source of MOS tube Q1 via the CE1 line, the circuit of V2 passes through the normally closed contact of relay K1, the resistor R12, the source of MOS tube Q1, and the drain of MOS tube Q1 to ground, and the current is limited by resistor R12.

[0032] See Figure 1In one embodiment, the problem to be solved is that when the coupling voltage V2 fluctuates too widely, CE2 can be connected to the source of the MOS transistor Q1 to maintain a consistent discharge rate of the MOS transistor Q1 when the coupling voltage V2 changes, avoiding overcurrent and slow discharge voltage accumulation. The resistance input terminal of the digital potentiometer U5 is connected to the normally closed auxiliary contact of the relay K1 as a current limiter. The cursor and resistance output terminals are connected in parallel to the source of the MOS transistor Q1. The seventh pin of the digital potentiometer U5 is connected to ground by default when there is no upper control. The second pin of the digital potentiometer U5 is controlled by the output terminal of the inverter U8. When the photovoltaic input voltage V1 is false, the voltage at the inverting terminal of the op amp U4 is greater than the voltage at the non-inverting terminal of the op amp U4. When the op amp U4 is cut off or off-rail, it outputs an offset voltage, and the voltage potential is lower than the positive conduction voltage of the NMOS tube inside the inverter U8. The inverter U8 still inverts the output signal to the second pin of the digital potentiometer U5. When there is an input to the second pin of the digital potentiometer U5, the digital potentiometer U5 is ready to be adjusted from high resistance to low resistance. The adjustment signal is input to the first pin of the digital potentiometer U5 by the op amp U6. At the same time, the coupled voltage is sampled by the resistor R15 and input to the op amp U7 non-inverting terminal one way, and the other way is input to the op amp U7 output terminal through the resistor R16. The op amp U7 inverting terminal samples the voltage at the connection terminal of the capacitor C1 and the resistor R17. When powered on, the resistor R17 and the capacitor C1 are integrated, and the voltage at the non-inverting terminal of the op amp U7 is large. At the inverting terminal voltage, the output signal of the operational amplifier U7 is fed back to the capacitor C1 through the resistor R17. When the voltage at the inverting terminal of the operational amplifier U7 increases as the voltage of the integrated resistor R17 and the capacitor C1 is greater than the inverting terminal of the operational amplifier U7, the operational amplifier U7 has no output. The coupling voltage V2 at the resistor R15 terminal is fed back to the output terminal of the operational amplifier U7 through the resistor R16. The voltage at the connection terminal of the resistor R15 and the resistor R16 drops. At the same time, the voltage at the capacitor C1 terminal is fed back to the output terminal of the operational amplifier U7 through the resistor R17. The voltage of the capacitor C1 gradually decreases. When the voltage at the capacitor C1 terminal is lower than the inverting terminal of the operational amplifier U7, the operational amplifier U7 outputs again to pull up the voltage at the connection terminal of the resistor R15 and the resistor R16. The resistor R17 and the capacitor C1 are integrated again. When the coupling voltage V2 changes The voltage drop at the connection end of resistor R15 and resistor R16 increases. The output end of operational amplifier U7 feeds back a signal to the inverting end of operational amplifier U6 during the voltage drop period of resistor R15 and resistor R16. The non-inverting end of U6 sets the reference voltage of the voltage drop change point of resistor R15 and resistor R16. The operational amplifier U6 outputs a signal to the first pin of the digital potentiometer U5, which controls the digital potentiometer U5 to gradually decrease from high resistance to low resistance, so that the discharge rate of MOS tube Q1 is consistent when the coupling voltage V2 changes. Until the input voltage V1 of the photovoltaic input end is true, the coil of relay K1 is closed and the connection between V2 and the source of MOS tube Q1 is disconnected again. The reference voltage of the non-inverting end of operational amplifier U6 and operational amplifier U2 can be set by resistor voltage divider or power supply.

[0033] While the embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that various changes, modifications, substitutions, and alterations can be made to the embodiments without departing from the principles and spirit of the invention.

Claims

1. A photovoltaic input port coupling voltage suppression circuit, characterized in that: It includes a resistor R1, a resistor R4, a resistor R5, a resistor R6, a resistor R8, a resistor R10, a resistor R11, an op amp U1, an op amp U2, an op amp U3, an op amp U4, a MOS tube Q1, a transistor Q2, a diode D1, and a relay K1. One end of the resistor R1 is connected to the coupling voltage V2 and the common end of the relay K1, and the other end is connected to the non-inverting end of the op amp U1; the output end of the op amp U1 is connected to the inverting end and one end of the resistor R4; the other end of the resistor R4 is connected to one end of the resistor R6 and the non-inverting end of the op amp U3; the inverting end of the op amp U3 is connected to one end of the resistor R5 and one end of the resistor R8, and the output end is connected to the other end of the resistor R8 and the gate of the MOS tube Q1; the source of the MOS tube Q1 is connected to one end of the CE1 line or the CE2 line; the other ends of the CE1 line and the CE2 line are connected to the normally closed contact of the relay K1; The output terminal of op amp U2 is connected to the inverting terminal and the other end of resistor R5, and the non-inverting terminal of op amp U2 sets the reference voltage of the conduction voltage difference of MOS tube Q1; the normally open contact of relay K1 is connected to the photovoltaic input voltage V1 and one end of resistor R10; the other end of resistor R10 is connected to the non-inverting terminal of op amp U4; the output terminal of op amp U4 is connected to the base of transistor Q2; the collector of transistor Q2 is connected to one end of resistor R11; the other end of resistor R11 is connected to the anode of D1 and one end of the coil of relay K1; the other end of the coil of relay K1, the cathode of D1 and the power supply are connected; the drain of MOS tube Q1, the emitter of transistor Q2 and the ground terminal are connected.

2. The photovoltaic input port coupling voltage suppression circuit according to claim 1, characterized in that: It also includes resistor R15, resistor R16, resistor R17, capacitor C1, operational amplifier U6, operational amplifier U7, inverter U8, and digital potentiometer U5. One end of the resistor R15, pin 3 of the digital potentiometer and the other end of the CE2 line are connected; the other end of the resistor R15 is connected to one end of the resistor R16 and the non-inverting end of the operational amplifier U7; the inverting end of the operational amplifier U7 is connected to one end of the capacitor C1 and one end of the resistor R17; the output end of the operational amplifier U7 is connected to the other end of the resistor R16, the other end of the resistor R17 and the inverting end of the operational amplifier U6; the non-inverting end of the operational amplifier U6 sets the reference voltage through a resistor divider or a power supply; pin 1 of the digital potentiometer U5 is connected to the output end of the operational amplifier U6, pin 5 is connected to pin 6 and one end of the CE2 line, pin 2 is connected to the output end of the inverter U8, and pin 7 is connected to the ground end; the input end of the inverter U8 is connected to the output end of the operational amplifier U4; and the other end of the capacitor C1 is connected to the ground end.

3. The photovoltaic input port coupling voltage suppression circuit according to claim 1, characterized in that: The circuit further includes a resistor R12, which is connected in series in the CE1 circuit.

4. The photovoltaic input port coupling voltage suppression circuit according to claim 1, characterized in that: The non-inverting terminal of the operational amplifier U2 is connected to one end of the resistor R2 and one end of the resistor R3; the other end of the resistor R3 is connected to the power supply; and the other end of the resistor R2 is connected to the ground.

5. The photovoltaic input port coupling voltage suppression circuit according to claim 1, characterized in that: A resistor R9 is also included, one end of the resistor R9 is connected to the inverting end of the operational amplifier U4, and the other end is connected to the ground end.

6. The photovoltaic input port coupling voltage suppression circuit according to claim 5, characterized in that: The device further includes a resistor R7 , one end of which is connected to the inverting terminal of the operational amplifier U4 , and the other end of which is connected to the power supply.

7. The photovoltaic input port coupling voltage suppression circuit according to claim 2, characterized in that: It also includes a resistor R13 and a resistor R14. One end of the resistor R14 is connected to one end of the resistor R13 and the in-phase terminal of the operational amplifier U6, and the other end is connected to the ground terminal; the other end of the resistor R13 is connected to the power supply.

8. A photovoltaic system, characterized in that: The photovoltaic input port coupling voltage suppression circuit comprises the photovoltaic input port coupling voltage suppression circuit according to any one of claims 1 to 7.

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