LDPC (Low Density Parity Check) decoding method based on H matrix column effective QC mutual exclusion and related equipment

Abstract

The invention provides an H matrix column effective QC mutual exclusion-based LDPC decoding method and related equipment, and the method comprises the steps: designing an H matrix, enabling the effective QC positions of two adjacent columns to be mutually exclusive, and guaranteeing the independent processing of each column; at least one stage of delay unit is inserted into the key path of the decoding module through an insertion beat processing technology so as to reduce half path delay; a single parallel decoding mode is adopted, and column decoding operation is completed based on a mutually exclusive H matrix. The method has the beneficial effects that the decoding parallelism degree can be improved, the key path delay is reduced, and the hardware resource consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of decoding of low-density parity-check (LDPC) codes, and particularly to an LDPC decoding single-parallel method and related devices based on column-effective QC exclusive design of an H matrix, which are used to improve decoding parallelism, reduce critical path delay, and reduce hardware resource consumption. Background Art

[0002] As an efficient error-correcting code, LDPC (Low-Density Parity-Check) codes are widely used in fields such as data transmission and storage. It realizes error detection and correction by constructing a sparse parity-check (H) matrix. In current LDPC decoding technologies, the design of the H matrix has an important impact on decoding efficiency and performance. In traditional H matrix designs, the number of QC (Quantized Cube) and the sparsity of each row need to be constrained, and there are also constraints on the effective QC positions of adjacent columns. This results in the effective QC positions of adjacent columns of the LDPCH matrix being able to point to the same syndrome. This design causes the need to wait for the syndrome updated by the previous column decoding during the column decoding process, resulting in the operations of EV_CALC (Edge Value Calculation), FLIP_FLOP (Flip and Trigger), and SYND_UPD (Syndrome Update) in the entire column decoding all need to be synchronized, resulting in poor critical path timing performance, and only being able to converge to a working frequency of about 400 MHz, which cannot meet the requirements of the read bandwidth of modern SSDs (Solid State Drives). Therefore, double-parallel column decoding needs to be used to compensate for the problem of insufficient bandwidth. Summary of the Invention

[0003] The technical problems to be solved by the present invention are: critical path delay and large hardware resource consumption of double-parallel column decoding.

[0004] To solve the above technical problems, the technical solution adopted by the present invention is: an LDPC decoding method based on column-effective QC exclusivity of an H matrix, including:

[0005] Design an H matrix such that the effective QC positions of adjacent columns are mutually exclusive, ensuring that each column decoding is processed independently;

[0006] Insert at least one stage of delay unit in the critical path of the decoding module through an interleave processing technique to halve the path delay;

[0007] Adopt a single-parallel decoding mode to complete column decoding operations based on the mutually exclusive H matrix.

[0008] Further, the design of the H matrix specifically includes:

[0009] Divide the QC area by column, and constrain the QC positions of adjacent columns not to overlap;

[0010] Optimize the QC distribution through a sparsification algorithm to ensure that the number of valid QCs in each column meets the preset threshold.

[0011] Furthermore, the critical path includes the data paths of EV_CALC, FLIP_FLOP, and SYND_UPD.

[0012] Furthermore, the interlaced processing technology includes:

[0013] Insert a first-level delay unit between the EV_CALC module and the FLIP_FLOP module;

[0014] Insert a second-level delay unit at the output of the SYND_UPD module to achieve timing synchronization.

[0015] Furthermore, the single-parallel decoding mode is implemented through the following steps:

[0016] Perform the decoding operations for all columns in parallel without waiting for the syndrome update results of adjacent columns;

[0017] Independently update the syndrome values of each column based on the mutually exclusive H matrix.

[0018] Furthermore, the LDPC decoding method based on the mutual exclusion of valid QCs in the columns of the H matrix further includes:

[0019] Optimize the timing control of the decoding module through logic gate configuration;

[0020] Adopt dynamic voltage and frequency regulation technology to maintain stability at an operating frequency of 800 MHz.

[0021] Furthermore, the method is applicable to the read channel error correction scenario of a solid-state drive.

[0022] The present invention also provides an LDPC decoding device based on the mutual exclusion of valid QCs in the columns of the H matrix, including:

[0023] An H matrix generation module for designing an H matrix such that the positions of valid QCs in adjacent columns are mutually exclusive to ensure independent processing of each column during decoding;

[0024] A decoding processing module for inserting at least one level of delay unit in the critical path of the decoding module through interlaced processing technology to halve the path delay;

[0025] A single-parallel control module for performing column decoding operations based on the mutually exclusive H matrix using the single-parallel decoding mode.

[0026] The present invention also provides a computer device, which includes a memory and a processor. A computer program is stored on the memory, and when the processor executes the computer program, the LDPC decoding method based on column-valid QC mutual exclusion of the H matrix described in any one of the above is implemented.

[0027] The present invention also provides a storage medium, characterized in that: the storage medium stores a computer program, and when the computer program is executed by a processor, the LDPC decoding method based on column-valid QC mutual exclusion of the H matrix described in any one of the above can be implemented.

[0028] The beneficial effects of the present invention are as follows: the working frequency is increased to 800 MHz, meeting the SSD read bandwidth requirements; the decoding area is reduced by 50%, and the hardware cost is reduced; the system stability is enhanced, and the timing control is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The specific structure of the present invention will be described in detail below with reference to the drawings.

[0030] Figure 1 It is a flowchart of the LDPC decoding method based on column-valid QC mutual exclusion of the H matrix according to an embodiment of the present invention;

[0031] Figure 2 It is a comparison diagram of the QC distribution of the H matrix according to an embodiment of the present invention;

[0032] Figure 3 It is a circuit schematic diagram of the key path interception processing technology according to an embodiment of the present invention;

[0033] Figure 4 It is a block diagram of the LDPC decoding device based on column-valid QC mutual exclusion of the H matrix according to an embodiment of the present invention;

[0034] Figure 5 It is a schematic block diagram of the computer device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0036] It should be understood that when used in this specification and the appended claims, the terms "comprises" and "comprising" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0037] It should also be understood that the terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms.

[0038] It should be further understood that the term "and / or" used in the specification of the present invention and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0039] As Figures 1-3 shown, the first embodiment of the present invention is: a LDPC decoding method based on column - effective QC mutual exclusion of the H matrix, including the steps of:

[0040] S10. Design the H matrix such that the effective QC positions of adjacent columns are mutually exclusive, ensuring that each column is decoded independently.

[0041] In a specific embodiment, the design of the H matrix specifically includes:

[0042] Divide the QC area by columns, and constrain the QC positions of adjacent columns not to overlap;

[0043] Optimize the QC distribution through a sparsification algorithm to ensure that the number of effective QCs in each column meets a preset threshold.

[0044] This embodiment details the design process of the H matrix:

[0045] QC area division: Divide the H matrix into multiple QC areas by columns, and each area contains QC units of several rows and columns.

[0046] Mutual exclusion constraint: Ensure that the QC positions of adjacent columns do not overlap through a constraint algorithm. For example, the effective QC distribution of the i - th column is in the row number set S_i, and the effective QC distribution of the (i + 1)-th column is in the row number set S_{i + 1}, and

[0047] Sparsification processing: Use a greedy algorithm or a random search algorithm to optimize the QC distribution, ensure that the number of QCs in each column does not exceed a preset threshold (such as 4 QCs per column), and at the same time meet the error - correction performance requirements.

[0048] S20. Insert at least one - stage delay unit in the critical path of the decoding module through the inter - snapshot processing technology to halve the path delay.

[0049] In a specific embodiment, the critical path includes the data paths of EV_CALC (edge value calculation), FLIP_FLOP (flip trigger), and SYND_UPD (syndrome update).

[0050] In a specific embodiment, the snapshot processing technology includes:

[0051] Insert a first-stage delay unit between the EV_CALC module and the FLIP_FLOP module;

[0052] Insert a second-stage delay unit at the output end of the SYND_UPD module to achieve timing synchronization.

[0053] The hardware implementation steps for critical path optimization are as follows:

[0054] Path analysis: Identify that the path delay from EV_CALC to FLIP_FLOP is T1, and the path delay of SYND_UPD is T2.

[0055] Snapshot design: Insert a first-stage D flip-flop (delay T1 / 2) at the output of EV_CALC, and insert a second-stage D flip-flop (delay T2 / 2) at the output of SYND_UPD.

[0056] Timing synchronization: Generate two-stage synchronous clock signals through a clock divider to ensure that the inserted delay units are synchronized with the main clock.

[0057] S30. Adopt a single-parallel decoding mode to complete column decoding operations based on the mutually exclusive H matrix.

[0058] In a specific embodiment, the single-parallel decoding mode is implemented through the following steps:

[0059] Perform decoding operations on all columns in parallel without waiting for the syndrome update results of adjacent columns;

[0060] Based on the mutually exclusive H matrix, independently update the syndrome values of each column.

[0061] The hardware architecture of single-parallel decoding includes the following modules:

[0062] Column decoding unit array: Each column corresponds to an independent decoding unit, which includes EV_CALC, FLIP_FLOP, and SYND_UPD sub-modules.

[0063] Global controller: Schedule the start and stop of each column decoding unit to avoid resource conflicts.

[0064] Syndrome memory: Store the syndrome values of each column, and use a dual-port RAM to achieve parallel reading and writing.

[0065] In a specific embodiment, the LDPC decoding method based on column-valid QC mutual exclusion of the H matrix further includes:

[0066] Optimizing the timing control of the decoding module through logic gate configuration;

[0067] Adopting dynamic voltage and frequency regulation technology to maintain stability at an operating frequency of 800 MHz.

[0068] In a specific embodiment, the method is applicable to the read channel error correction scenario of a solid-state drive (SSD).

[0069] Performance testing to verify the technical effects of the present invention on an FPGA platform:

[0070] Operating frequency test: The critical path delay is reduced from 2.5 ns to 1.25 ns, and the operating frequency is stable at 800 MHz.

[0071] Resource occupancy comparison: Compared with traditional double-parallel row-column decoding, the number of logic gates is reduced by 40%, and the memory occupancy is reduced by 35%.

[0072] Error correction performance test: When the bit error rate (BER) is 1e-5, the decoding throughput is increased to 12 Gbps, meeting the SSD read bandwidth requirements.

[0073] For the application scenario, the present solution can be integrated into the SSD controller chip, and the specific implementation process is as follows:

[0074] Data reception: Reading data from the NAND flash and caching it into the input buffer.

[0075] Single-parallel decoding: Invoking the decoding device of the present invention to perform real-time error correction on the data.

[0076] Data output: Transmitting the error-corrected data to the host interface.

[0077] By implementing the technical solution of the present invention, the LDPC decoder can meet the SSD read bandwidth requirements in the single-parallel working mode, while halving the decoding area, improving the data processing speed and reducing the hardware cost. The specific technical effects are as follows:

[0078] Improving work efficiency: The operating frequency is increased from 400 MHz to 800 MHz, greatly improving the decoding efficiency.

[0079] Reducing the decoding area: Changing from double-parallel row-column decoding to single-parallel decoding effectively reduces the hardware resource occupancy and the overall area of the decoder.

[0080] Improving system stability: By optimizing the timing control and path delay, the system stability and the reliability of data processing are improved.

[0081] Such asFigure 4 As shown in Figure 4 , the present invention also provides an LDPC decoding device based on column - effective QC mutual exclusion of the H matrix, including:

[0082] An H - matrix generation module 10, configured to design an H matrix such that the effective QC positions of two adjacent columns are mutually exclusive, ensuring that each column is decoded independently;

[0083] A decoding processing module 20, configured to insert at least one - stage delay unit through an inter - shot processing technique in the critical path of the decoding module to halve the path delay;

[0084] A single - parallel control module 30, configured to adopt a single - parallel decoding mode to complete column - decoding operations based on the mutually - exclusive H matrix.

[0085] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the above - mentioned LDPC decoding device based on column - effective QC mutual exclusion of the H matrix can refer to the corresponding description in the foregoing method embodiments. For the sake of convenience and brevity of description, it will not be elaborated herein.

[0086] The above - mentioned LDPC decoding device based on column - effective QC mutual exclusion of the H matrix can be implemented in the form of a computer program, and this computer program can run on a computer device as shown in Figure 5 As shown in Figure 5 .

[0087] Please refer to Figure 5 , Figure 5 which is a schematic block diagram of a computer device provided by an embodiment of the present application. The computer device 500 can be a terminal or a server. Among them, the terminal can be an electronic device with communication functions such as a smart phone, a tablet computer, a notebook computer, a desktop computer, a personal digital assistant, and a wearable device. The server can be an independent server or a server cluster composed of multiple servers.

[0088] Refer to Figure 5 , the computer device 500 includes a processor 502, a memory, and a network interface 505 connected through a system bus 501. Among them, the memory can include a non - volatile storage medium 503 and an internal memory 504.

[0089] The non - volatile storage medium 503 can store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions, and when the program instructions are executed, the processor 502 can execute an LDPC decoding method based on column - effective QC mutual exclusion of the H matrix.

[0090] The processor 502 is used to provide computing and control capabilities to support the operation of the entire computer device 500.

[0091] The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can be caused to execute an LDPC decoding method based on column-valid QC mutual exclusion of the H matrix.

[0092] The network interface 505 is used for network communication with other devices. Those skilled in the art can understand that Figure 5 the structure shown in is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device 500 to which the solution of this application is applied. The specific computer device 500 may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0093] Among them, the processor 502 is used to run the computer program 5032 stored in the memory to implement the LDPC decoding method based on column-valid QC mutual exclusion of the H matrix as described above.

[0094] It should be understood that in the embodiments of this application, the processor 502 may be a central processing unit (CPU), and the processor 502 may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0095] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program includes program instructions, and the computer program can be stored in a storage medium, and the storage medium is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0096] Therefore, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by the processor, the processor is caused to execute the LDPC decoding method based on column-valid QC mutual exclusion of the H matrix as described above.

[0097] The storage medium may be a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk, an optical disk, or other computer-readable storage media that can store program codes.

[0098] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of the examples have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0099] In several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of each unit is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0100] The steps in the method embodiments of the present invention can be adjusted, combined, and deleted according to actual needs. The units in the device embodiments of the present invention can be combined, divided, and deleted according to actual needs. In addition, the functional units in various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.

[0101] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention.

[0102] As described above, the above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. An LDPC decoding method based on H matrix column effective QC mutual exclusion, characterized in that: include: Design the H matrix so that the valid QC positions of two adjacent columns are mutually exclusive, ensuring that each column is decoded independently; Inserting at least one level of delay unit in the critical path of the decoding module by using the beat insertion processing technology to reduce the path delay by half; A single parallel decoding mode is adopted to complete the column decoding operation based on the mutually exclusive H matrix.

2. The LDPC decoding method based on H matrix column effective QC mutual exclusion according to claim 1, characterized in that: The design of the H matrix specifically includes: Divide the QC area by column, and constrain the QC positions of adjacent columns to not overlap; The QC distribution is optimized through the sparseness algorithm to ensure that the number of valid QCs in each column meets the preset threshold.

3. The LDPC decoding method based on H matrix column effective QC mutual exclusion according to claim 1, characterized in that: The critical path includes data paths of EV_CALC, FLIP_FLOP, and SYND_UPD.

4. The LDPC decoding method based on H matrix column effective QC mutual exclusion according to claim 1, characterized in that: The interpolation processing technology includes: Insert the first-stage delay unit between the EV_CALC module and the FLIP_FLOP module; Insert the second-stage delay unit at the output of the SYND_UPD module to achieve timing synchronization.

5. The LDPC decoding method based on H matrix column effective QC mutual exclusion according to claim 1, characterized in that: The single parallel decoding mode is implemented by the following steps: Process decoding operations of all columns in parallel without waiting for the syndrome update results of adjacent columns; Based on the mutually exclusive H matrix, the syndrome value of each column is updated independently.

6. The LDPC decoding method based on H matrix column effective QC mutual exclusion according to claim 1, characterized in that: Also includes: Optimize the timing control of the decoding module through logic gate configuration; Dynamic voltage and frequency adjustment technology is used to maintain stability at 800MHz operating frequency.

7. The LDPC decoding method based on H matrix column effective QC mutual exclusion according to claim 1, characterized in that: The method is applicable to the read channel error correction scenario of a solid state drive.

8. An LDPC decoding device based on H matrix column effective QC mutual exclusion, characterized in that: include: H matrix generation module, used to design the H matrix so that the valid QC positions of two adjacent columns are mutually exclusive, ensuring that each column is decoded independently; A decoding processing module, used for inserting at least one level of delay unit in the critical path of the decoding module through an insertion processing technology to reduce the path delay by half; The single parallel control module is used to adopt a single parallel decoding mode and complete the column decoding operation based on the mutually exclusive H matrix.

9. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the LDPC decoding method based on H matrix column effective QC mutual exclusion as claimed in any one of claims 1 to 7 when executing the computer program.

10. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the LDPC decoding method based on H matrix column effective QC mutual exclusion as described in any one of claims 1 to 7 can be implemented.

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