Column memory circuits, chips, image sensors and imaging devices

Abstract

This invention provides a column memory circuit, a chip, an image sensor, and an imaging device. The column memory circuit includes M×N memory modules, N readout modules, and a data transmission module. A correlated double sampling unit of the column memory circuit is disposed in the data transmission module. Each memory module receives a first data signal, and the second terminal of each memory module is coupled to the first terminal of its corresponding readout module. The second terminal of each readout module is coupled to the data transmission module. The memory module converts the received first data signal into a second data signal. The readout modules send the received second data signal to the data transmission module. The data transmission module performs correlated double sampling processing on the second data signal using the correlated double sampling unit to obtain and output a third data signal. This invention can significantly reduce the area of ​​the column memory circuit while maintaining good circuit performance, and it can significantly reduce the cost of the image sensor.

Description

Technical Field

[0001] This invention relates to the field of image processing technology, and in particular to a column memory circuit, chip, image sensor, and imaging device. Background Technology

[0002] An image sensor is a device that converts optical images into electrical signals, and typically includes components such as a pixel array, an analog-to-digital converter, and column memory circuitry. For an example, please refer to... Figure 1 It schematically illustrates the flow of data signals during the imaging process. From Figure 1 It can be seen that the pixel array 110 ( Figure 1 Not shown in the text, see below. Figure 6 The pixel unit 111 is responsible for converting the acquired image light signal into a voltage signal and outputting the voltage signal to the analog-to-digital converter 120 (ADC). The ADC 120 is responsible for comparing the received voltage signal with the ramp signal and generating a pulse signal when the two signals are equal. The column memory circuit 130 latches the counter data when it receives the pulse signal, processes the data in a certain way, and then serially outputs it to the image signal processing (ISP) 150. The image processor 150 extracts and optimizes the received image data (such as color correction, gamma correction, etc.) to obtain an image that can be displayed, stored, and / or further processed, and outputs it through the interface circuit 160.

[0003] Research has shown that current column memory circuits have a large area and high power consumption. Although they have been well applied in high-performance image sensors, they are difficult to apply in low-cost image sensors.

[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] To address the technical problems of large area and high power consumption in the column memory circuit of image sensors in the prior art, the present invention provides a column memory circuit, chip, image sensor and imaging device. The present invention can significantly reduce the area of ​​the column memory circuit while ensuring circuit performance. Using the column memory circuit provided by the present invention can significantly reduce the cost of image sensors.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a column memory circuit for an image sensor, comprising M×N memory modules, N readout modules, and a data transmission module, wherein a related dual sampling unit of the column memory circuit is disposed in the data transmission module; a first end of each memory module is configured to receive a first data signal, a second end of each memory module is coupled to the first end of the corresponding readout module, and a second end of the readout module is coupled to the data transmission module, wherein M≥2;

[0007] The storage module is configured to convert the received first data signal into a second data signal, the readout module is configured to send the received second data signal to the data transmission module, and the data transmission module is configured to perform correlation double sampling processing on the second data signal through the correlation double sampling unit to obtain and output a third data signal.

[0008] Optionally, the correlated dual sampling unit includes a plurality of first transistors.

[0009] Optionally, each of the memory modules includes a first latch and a buffer unit coupled in sequence, each of the read modules includes a trigger and a multiplexer coupled in sequence, and the data transmission module includes a transcoding unit, a second latch, the correlated double sampling unit, and a data interface unit coupled in sequence.

[0010] The first latch is configured to latch the first data signal when it receives the first control signal from the image sensor and send the latched first data signal to the buffer unit. The buffer unit is configured to buffer the first data signal to obtain the second data signal and send the second data signal to the trigger.

[0011] When the trigger receives the second control signal from the image sensor, it sends the second data signal to the multiplexer. The multiplexer is configured to select the corresponding second data signal to send to the transcoding unit according to the third control signal from the image sensor. The transcoding unit is configured to transcode the second data signal to obtain a first set of fourth data signals for sending to the second latch, and after obtaining the first set of fourth data signals, to transcode the subsequently received second data signals to obtain a second set of fourth data signals for sending to the correlated double sampling unit. The second latch is configured to latch the first set of fourth data signals when it receives the fourth control signal. The correlated double sampling unit is configured to perform correlated double sampling processing based on the first set of fourth data signals and the second set of fourth data signals to obtain the third data signal.

[0012] Optionally, the transcoding unit includes a plurality of second transistors.

[0013] Optionally, the second data signal adopts Gray code encoding, and the first group of fourth data signals, the second group of fourth data signals, and the third data signal adopt binary encoding.

[0014] To achieve the above objectives, the present invention also provides a chip for an image sensor, wherein the chip integrates the column memory circuit described in any of the preceding claims.

[0015] To achieve the above objectives, the present invention also provides an image sensor, which includes the column memory circuit described in any of the above claims or the chip described above.

[0016] Optionally, the image sensor further includes a digital circuit area and a pixel array, and the data transmission module of the column memory circuit is disposed in the digital circuit area;

[0017] The pixel array is configured to convert the acquired image light signal into the first data signal, the column memory circuit is configured to convert the first data signal into the second data signal and convert the second data signal into the third data signal through the data transmission module located in the digital circuit area, and the image processor is configured to process the third data signal to obtain the target image of the object to be acquired.

[0018] Optionally, the data transmission module is installed in the digital circuit area using digital chip design tools.

[0019] To achieve the above objectives, the present invention also provides an imaging device, the imaging device comprising the column memory circuit described in any one of the above claims, the chip described in the above claims, or the image sensor described in any one of the above claims.

[0020] Compared with the prior art, the column memory circuit, chip, image sensor, and imaging device provided by the present invention have the following advantages:

[0021] The present invention provides a column memory circuit for an image sensor, comprising M×N memory modules, N readout modules, and a data transmission module. A correlated double sampling unit of the column memory circuit is disposed in the data transmission module. A first terminal of each memory module is configured to receive a first data signal, and a second terminal of each memory module is coupled to the first terminal of its corresponding readout module. The second terminal of each readout module is coupled to the data transmission module, where M≥2. Further, each memory module is configured to convert the received first data signal into a second data signal, each readout module is configured to send the received second data signal to the data transmission module, and the data transmission module is configured to perform correlated double sampling processing on the second data signal through the correlated double sampling unit to obtain and output a third data signal. Therefore, the column memory circuit provided by this invention abandons the design method of setting the correlated double sampling unit in the storage module in the prior art. It makes full use of the objective fact that the number of data transmission modules is much smaller than the number of storage modules. By setting the correlated double sampling unit in the data transmission module, the number of correlated double sampling units can be significantly reduced. This not only saves costs but also reduces the circuit area occupied by the correlated double sampling unit, thereby significantly reducing the circuit area of ​​the column memory while ensuring good circuit performance. The column memory circuit provided by this invention can significantly reduce the cost of image sensors and can be well applied to low-cost image sensors.

[0022] Since the chip, image sensor, and imaging device for image sensors provided by this invention belong to the same inventive concept as the column memory circuit provided by this invention, the chip, image sensor, and imaging device for image sensors provided by this invention have at least all the advantages of the column memory circuit provided by this invention. For details on the beneficial effects of the chip, image sensor, and imaging device for image sensors provided by this invention, please refer to the above description of the beneficial effects of the column memory circuit provided by this invention, which will not be repeated here. Attached Figure Description

[0023] Figure 1 This is a schematic diagram illustrating the flow of data signals during the imaging process;

[0024] Figure 2 This is a schematic diagram showing the flow of data signals in the column memory circuit of an image sensor.

[0025] Figure 3 This is a schematic diagram of the topology of a column memory circuit for an image sensor in the prior art;

[0026] Figure 4A block diagram of the column memory circuit provided by the present invention;

[0027] Figure 5 A schematic diagram of the topology of a specific example of the column memory circuit provided by the present invention;

[0028] Figure 6 A schematic diagram of the block structure of the imaging device provided by the present invention;

[0029] The accompanying figure is labeled as follows:

[0030] Pixel array-110, pixel unit-111, analog-to-digital converter-120, column memory circuit-130, 140, image processor-150, interface circuit-160;

[0031] Storage modules - Bank0, Bank1, Bank2, Bank3, 130A, 141, 141A; Read modules - R01, R23, 130B, 142, 142A; Data transmission modules - 170, 143.

[0032] First latch - 131, 141A1, transcoding unit - 132, 1431, second latch - 133, 1432, correlated double sampling unit - 134, 1433, buffer unit - 135, 141A2, flip-flop - 136, 142A1, multiplexer - 137, 142A2, data interface unit - 1434;

[0033] Gray code data - GC, binary data - BC, comparator data - CMP, black level enable signal - BLK_EN, adjacent readout module output signal terminal - GBL;

[0034] First data signal - D1, second data signal - D2, third data signal - D3, fourth data signal - D4;

[0035] First control signal -T1, second control signal -T2, third control signal -T3, fourth control signal -T4;

[0036] Digital circuit area -180. Detailed Implementation

[0037] The following detailed description, in conjunction with the accompanying drawings, provides a further detailed account of the column memory circuit, chip, image sensor, and imaging device proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of the invention. Please refer to the drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes and to enable those skilled in the art to understand and read them, and are not intended to limit the implementation conditions of this invention. Any modifications to the structure, changes in proportions, or adjustments to the size, provided they produce the same or similar effects and achieve the same objectives as this invention, should still fall within the scope of the technical content disclosed in this invention. Specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and usage environment. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, omitting repeated descriptions. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it need not be discussed further in subsequent figures. Furthermore, if the methods described herein involve a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, some of the described steps may be omitted and / or other steps not described herein may be added to the method.

[0038] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The singular forms “a,” “an,” and “the” include plural objects. The term “or” is generally used to mean “and / or,” the term “several” is generally used to mean “at least one,” and the term “at least two” is generally used to mean “two or more.” Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0039] It should be understood that when a component is referred to as "connected," "connected to," or "coupled to" other components, it may be directly connected to other components, or there may be intermediary components. Conversely, when a component is referred to as "directly connected" or "directly connected to" other components, there are no intermediary components.

[0040] To facilitate understanding and explanation of the present invention, before describing the specific implementation methods of the column memory circuit, image sensor, and imaging device provided by the present invention, the main research process of the present invention will be described first.

[0041] First, please see Figure 2 This schematically illustrates the flow of data signals within the column memory circuit of an image sensor. For example... Figure 2 As shown, Figure 2 An example of a columnar memory circuit includes four bank modules (Bank0, Bank1, Bank2, and Bank3), two readout modules (R01 and R23), and one data I / O module 170. Bank modules Bank0 and Bank1 share readout module R01, and bank modules Bank2 and Bank3 share readout module R23; that is, every two bank modules share one readout module. The data signal processing flow of the columnar memory circuit is roughly as follows: from the analog-to-digital converter 120... Figure 2 Not shown in the image, please refer to [the image / reference]. Figure 1Gray code data GC and comparator data CMP (understanding) enter the storage modules Bank0, Bank1, Bank2 and Bank3 from the outside. Storage modules Bank0 and Bank1 send the processed data to the corresponding read module R01 and then transmit it to the data transmission module 170. Storage modules Bank2 and Bank3 send the processed data to the corresponding read module R23 and then send it to the data transmission module 170 through the read module R01. All read modules R01 and R23 together form a shift read function. The data transmission module 170 receives the data processed by the read modules R01 and R23 and outputs the data from the column memory circuit 130.

[0042] Please see Figure 3 , Figure 3 This is a schematic diagram of the topology of a column memory circuit in an image processor in the prior art. For example... Figure 3 As shown, in this example, the column memory circuit 130 includes M×N memory modules ( Figure 3 The diagram shows the i-th storage module 130A, where 1 ≤ i ≤ (M × N), and N read modules ( Figure 3 The diagram illustrates the j-th readout module 130B (1≤j≤N) and one data transmission module 170. The data signal processing is roughly as follows: Gray code data GC is latched into the first latch 131 on the falling edge of the comparator data CMP signal. The transcoding unit 132 converts the latched Gray code data GC into binary data BC. The second latch 133 stores the black level signal of the image sensor when the black level enable signal BLK_EN is high. The Correlated Double Sampling (CDS) unit 134 implements the CDS function based on the stored black level signal and pixel level data when the black level enable signal BLK_EN is low. The buffer unit 135 sends the completed CDS data signal BIT_OUT from the storage module 130A to the corresponding readout module 130B. As mentioned above, N readout modules together form a shift register function. Furthermore, the read module 130A first uses a flip-flop 136 (e.g., a D flip-flop, DFF) and a multiplexer 137 to connect the memory module 130A and the memory modules sharing the read module 130A with the memory module 130A. Figure 3 (not shown in the image) (e.g.) Figure 2 The data in the storage modules bank0 and bank1 of the read module R01 is sent out. Then, the multiplexer 137 is switched to the output signal terminal GBL of the adjacent read module. The read module 130B then sends the data from other storage modules through the multiplexer 137 (e.g., ...). Figure 2The data from the storage modules bank2 and bank3 of the read module R23 are first sent to the read module R23, then transmitted to the read module R01 for output, and then output from the column memory circuit 130 through the data transmission module 170.

[0043] It should be noted that this article only describes the part of the column memory circuit that is relevant to the present invention. For more detailed information about the column memory circuit not mentioned in this article, please refer to the relevant technical adaptations known to those skilled in the art.

[0044] Depend on Figure 3 As can be seen, existing column memory circuits typically include a data transmission module 170, N readout modules 130B, and M×N storage modules 130A (the specific values ​​of M and N are related to the resolution of the image sensor). Most functions are implemented in the storage modules 130A. Through extensive research, the inventors discovered that circuits with complex functions such as the transcoding unit 132 and the associated dual sampling unit 134 are typically composed of a large number of transistors. The complex functions combined with a large number of storage modules 130A result in the column memory circuit 130 occupying a large circuit area, making it difficult to apply to low-cost image sensor products.

[0045] Based on the above research, the core idea of ​​this invention is to provide a column memory circuit, an image sensor, and an imaging device. This invention can significantly reduce the area of ​​the column memory circuit while ensuring circuit performance. Using the column memory circuit provided by this invention can significantly reduce the cost of the image sensor.

[0046] It should be noted that the column memory circuit and chip for image sensors provided by this invention can be applied to the image sensors and imaging devices provided by this invention. The image sensors provided by this invention can be applied to the imaging devices provided by this invention. It should be understood that the term "imaging device" or "imaging equipment" or other similar terms as used herein include general imaging devices, such as, but not limited to, cameras, camcorders, mobile phones, tablets, educational devices, and medical imaging devices with image sensors.

[0047] To achieve the above-mentioned goals, this invention provides a columnar memory circuit. For an example, please refer to... Figure 4 The diagram illustrates a block structure schematic of the column memory circuit provided by the present invention. Figure 4As can be seen, the column memory circuit for image sensors provided by the present invention includes M×N memory modules 141, N readout modules 142, and a data transmission module 143. The correlated double sampling unit 1433 of the column memory circuit is disposed in the data transmission module 143. The first end of each memory module 141 is configured to receive a first data signal D1. The second end of each memory module 141 is coupled to the first end of its corresponding readout module 142. The second end of each readout module 142 is coupled to the data transmission module 143, where M≥2. Further, each memory module 141 is configured to convert the received first data signal D1 into a second data signal D2. Each readout module 142 is configured to send the received second data signal D2 to the data transmission module 143. The data transmission module 143 is configured to perform correlated double sampling processing on the second data signal D2 through the correlated double sampling unit 1433 to obtain and output a third data signal D3.

[0048] Therefore, the column memory circuit provided by this invention abandons the design method of setting the correlated double sampling units in the storage module in the prior art. It makes full use of the objective fact that the number of data transmission modules 143 is much smaller than the number of storage modules 141. By setting the correlated double sampling units 1433 in the data transmission module 143, the number of correlated double sampling units 1433 can be significantly reduced. This not only saves costs but also reduces the circuit area occupied by the correlated double sampling units 1433. As a result, the circuit area of ​​the column memory can be significantly reduced while ensuring circuit performance. The column memory circuit provided by this invention can significantly reduce the cost of image sensors. The column memory circuit provided by this invention can be well applied to low-cost image sensors.

[0049] Specifically, compared with the prior art design that places the relevant double sampling unit in the storage module, the column memory circuit provided by the present invention places the relevant double sampling unit 1433 in the data transmission module 143, which can save M×N-1 relevant double sampling units 1433.

[0050] Preferably, in some exemplary embodiments, the correlated dual sampling unit 1433 includes a plurality of first transistors ( Figure 4(Not shown in the image). Therefore, the design of implementing the correlated double sampling unit 1433 using several first transistors is easy to implement. It should be noted that those skilled in the art should understand that the above-described implementation of the correlated double sampling unit 1433 using first transistors is merely an exemplary description of a preferred embodiment and not a limitation of the present invention. The present invention does not limit the specific implementation of the correlated double sampling unit 1433. For more detailed information on the correlated double sampling unit 1433, please refer to related technologies known to those skilled in the art; due to space limitations, this will not be elaborated upon further here.

[0051] For example, taking the related dual sampling unit 1433 as an example, which includes P first transistors, the prior art design of setting the related dual sampling unit in the memory module 141 requires a total of M×N×P first transistors. However, the column memory circuit provided by the present invention only requires P first transistors. It can be seen that compared with the prior art, the present invention can save at least (M×N-1)×P transistors.

[0052] For example, please see Figure 5 The diagram illustrates a topology of one specific example of the column memory circuit provided by the present invention. Figure 5 The example uses the i-th storage module 141A and the j-th read module 142A. From... Figure 5As can be seen, in the column memory circuit provided by the present invention, each of the memory modules 141A includes a first latch 141A1 and a buffer unit 141A2 coupled in sequence, each of the read modules 142A includes a flip-flop 142A1 and a multiplexer 142A2 coupled in sequence, and the data transmission module 143 includes a transcoding unit 1431, a second latch 1432, a correlated double sampling unit 1433, and a data interface unit 1434 coupled in sequence. Further, the first latch 141A1 is configured to latch the first data signal D1 (e.g., a Gray code voltage signal representing the pixel's output voltage value) when it receives the first control signal T1 (e.g., comparator data CMP) from the image sensor, and send the latched first data signal D1 to the buffer unit 141A2. The buffer unit 141A2 is configured to buffer the first data signal D1 to obtain the second data signal D2 (e.g., a Gray code voltage signal representing the pixel's output voltage value), and send the second data signal D2 to the trigger 142A1. When the trigger 142A1 receives the second control signal T2 (e.g., a readout clock signal) from the image sensor, it sends the second data signal D2 to the multiplexer 142A2. The multiplexer 142A2 is configured to select the corresponding second data signal according to the third control signal T3 (e.g., a memory module selection signal) from the image sensor. Signal D2 is sent to the transcoding unit 1431; the transcoding unit 1431 is configured to transcode the second data signal D2 to obtain a first group of fourth data signals D41 (e.g., a binary voltage signal representing the voltage value of a black level signal) for sending to the second latch 1432, and after obtaining the first group of fourth data signals D41, transcode the subsequently received second data signal D2 to obtain a second group of fourth data signals D42 (a binary voltage signal representing the voltage value of an image pixel) for sending to the correlated double sampling unit 1433; the second latch 1432 is configured to latch the first group of fourth data signals D41 when a fourth control signal T4 (e.g., a black level enable signal) is received; the correlated double sampling unit 1433 is configured to perform correlated double sampling processing based on the first group of fourth data signals D41 and the second group of fourth data signals D42 to obtain the third data signal D3 (a binary voltage signal).

[0053] The column memory circuit provided by this invention includes a memory module 141A comprising a first latch 141A1 and a buffer unit 141A2. The first latch 141A1 ensures the stability of the first data signal D1, and the buffer unit 141A2 buffers the first data signal D1 to ensure the stable transmission of the second data signal D2 from multiple memory modules connected to the read module 142A to the trigger 142A1. Furthermore, the read module 142A of the column memory circuit includes the trigger 142A1 and the multiplexer 142A2 sequentially coupled. The trigger 142A1 synchronizes the switching and readout timing of the multiplexers 142A2 among the various read modules 142, thereby enabling the multiplexers 142A2 to select the second data signal from the corresponding read module 142. The output signal D2 is selected (for example, the second signal data D2 of the readout module 142A or the second signal data D2 of the readout module 142B can be selected through the multiplexer 142A2); furthermore, the data transmission module 143 includes the transcoding unit 1431, the second latch 1432, the correlated double sampling unit 1433, and the data interface unit 1434. Thus, the transcoding module 1431 converts the second data signal D2 into the first group of fourth data signals D41 and the second group of fourth data signals D42, which lays a solid foundation for the second latch 1432 to perform efficient processing of the data signal. The second latch 1432 can also help the correlated double sampling unit 1433 to suppress fixed-mode noise and reset noise in the data signal to obtain the third data signal, thereby improving the image quality.

[0054] Preferably, taking read module 142A as an example again, one input terminal of its multiplexer 142A2 is coupled to the output terminal of the flip-flop 142A1 of read module 142A, and the other input terminal of its multiplexer 142A2 is coupled to the multiplexer of another read module 142B adjacent to read module 142A. Figure 5 The output terminal (not shown in the diagram). Furthermore, most of the read modules 142 are coupled to the data transmission module 143 through multiplexers of other adjacent read modules 142, and for the last read module 142, the output terminal of its multiplexer is directly connected to the data transmission module 143.

[0055] Exemplary examples, in some exemplary embodiments, the second data signal D2 is encoded using Gray code, while the first group of fourth data signals D41, the second group of fourth data signals D42, and the third data signal D3 are encoded using binary code. Therefore, using Gray code for the first data signal D1 effectively reduces transmission errors, and using binary code for the first group of fourth data signals D41, the second group of fourth data signals D42, and the third data signal D3 facilitates efficient processing by the subsequent readout module. It should be noted that those skilled in the art should understand that the present invention does not impose excessive limitations on the specific format of the binary encoding used for the first data signal D1, the first group of fourth data signals D41, the second group of fourth data signals D42, and the third data signal D3; the format should be reasonably set according to actual needs when implementing the present invention.

[0056] Exemplary examples include, but are not limited to, D flip-flops in some exemplary embodiments. Thus, the column memory circuit provided by the present invention, in which the flip-flop 142A1 of its read module 142A is designed as a D flip-flop, can effectively guarantee the serial transmission of the second data signal D2.

[0057] Preferably, in some exemplary embodiments, the transcoding unit 1431 includes a plurality of second transistors ( Figure 6 (Not shown in the image). Therefore, the transcoding unit 1431 employs a design using several second transistors, resulting in simple logic and ease of implementation. It should be noted that those skilled in the art should understand that using second transistors to implement the transcoding unit 1431 is merely an exemplary description of a preferred embodiment and not a limitation of the invention. The invention does not limit the specific implementation of the transcoding unit 1431. For more detailed information on the transcoding unit 1431, please refer to relevant technologies known to those skilled in the art; due to space limitations, this will not be elaborated upon further here.

[0058] For example, taking the related dual sampling unit 1433 as having P first transistors and the transcoding unit 1431 as having Q second transistors, in the prior art, both the transcoding unit 1431 and the related dual sampling unit 1433 are located in the memory module 141. These two units require a total of M×N×P first transistors and M×N×Q second transistors. However, using the column memory circuit provided by the present invention, these two units require a total of P first transistors and Q second transistors. Therefore, compared with the prior art, the present invention can save (M×N-1)×(P+Q) transistors.

[0059] As can be understood from the above description, compared with the prior art, the column memory circuit provided by the present invention sets both the transcoding unit 1431 and the related dual sampling unit 1433 in the data transmission module 143, which will result in an increase in the amount of data output by the storage module 141A. If it is necessary to further improve the performance of the column memory circuit, although the performance requirements of the buffer unit 141A2 of the column memory circuit may be increased and a larger data bit width needs to be supported, the column memory circuit provided by the present invention still has a good cost performance overall.

[0060] It should be noted that, as those skilled in the art will understand, the present invention does not impose excessive limitations on the specific type of the image sensor. For example, the image sensor may be, but is not limited to, a CMOS image sensor. Furthermore, the present invention does not impose excessive limitations on the specific values ​​of M, N, P, and Q. Preferably, the values ​​of M and N are preferably related to the resolution of the image sensor, and should be reasonably set according to actual needs when implementing the present invention.

[0061] A second embodiment of the present invention provides a chip for an image sensor, wherein the chip integrates a column memory circuit as described in any of the above embodiments. Therefore, by using a chip integrating the column memory circuit provided by the present invention, not only can the cost of the image sensor be reduced, but the integration level of the image sensor can also be further improved.

[0062] A third embodiment of the present invention provides an image sensor, which includes the column memory circuit or the chip described in any of the above embodiments. For example, please refer to... Figure 6 , Figure 6 This is a block diagram illustrating the structure of an imaging device according to one exemplary embodiment of the present invention. Figure 6 As can be seen, the image sensor also includes a digital circuit area 180 and a pixel array 110. The data transmission module 143 of the column memory circuit 140 is disposed in the digital circuit area 180. The digital circuit area 180 is typically composed of digital circuit modules designed and implemented using hardware description languages ​​such as Verilog. Further, the pixel array 110 is configured to convert the acquired image light signal into the first data signal, the column memory circuit is configured to convert the first data signal into the second data signal and then convert the second data signal into the third data signal through the data transmission module 143 located in the digital circuit area 180. The image processor is configured to process the third data signal to obtain the target image of the object to be acquired.

[0063] The image sensor provided by this invention employs a design in which the data transmission module 143 is located in the digital circuit area 180. Since the digital circuit area typically uses programming to implement circuit functions, this design simplifies the process and improves flexibility. Furthermore, since the image sensor provided by this invention belongs to the same inventive concept as the column memory circuit provided by this invention, the image sensor provided by this invention possesses at least all the advantages of the column memory circuit provided by this invention. For detailed information on the beneficial effects of the image sensor provided by this invention, please refer to the above description of the beneficial effects of the column memory circuit provided by this invention; further details will not be repeated here.

[0064] It should be noted that, as mentioned above (e.g., in conjunction with...), Figure 1 The image sensor may further include an analog-to-digital converter 120 coupled between the pixel array 110 and the column memory circuit 140, and an image processor for further processing the third data signal. Figure 6 (not shown in the image). For more detailed information on image sensors, please refer to relevant technologies known to those skilled in the art; however, due to space limitations, this will not be elaborated upon here.

[0065] Preferably, in some exemplary embodiments, the data transmission module 143 is configured in the digital circuit area using digital chip design tools. It should be noted that those skilled in the art should understand that the present invention does not limit the specific type of the digital chip design tools. For example, the digital chip design tools include, but are not limited to, RTL and APR tools. For instance, the transcoding unit 1431 and the correlated double sampling unit 1433 may be implemented in the digital circuit area 180 using RTL and APR tools.

[0066] A fourth embodiment of the present invention provides an imaging device. The imaging device provided in this embodiment includes the column memory circuit provided in any of the above embodiments, or the chip provided in the embodiments herein, or the image sensor provided by the present invention. Since the imaging device provided in this embodiment and the image sensor provided by the present invention belong to the same inventive concept, and the image sensor provided by the present invention and the column memory circuit provided by the present invention belong to the same inventive concept, the imaging device provided in this embodiment at least has all the advantages of the column memory circuit provided by the present invention. For details, please refer to the above description of the beneficial effects of the column memory circuit; further elaboration will not be provided here.

[0067] Compared with the prior art, the column memory circuit, chip, image sensor, and imaging device provided by the present invention have the following beneficial effects: The column memory circuit provided by the present invention abandons the design method of setting the correlated double sampling units in the storage module in the prior art. It makes full use of the objective fact that the number of data transmission modules is much smaller than the number of storage modules. By setting the correlated double sampling units in the data transmission module, the number of correlated double sampling units can be significantly reduced, which not only saves costs but also reduces the circuit area occupied by the correlated double sampling units. This significantly reduces the circuit area of ​​the column memory while ensuring circuit performance. The column memory circuit provided by the present invention can significantly reduce the cost of image sensors and can be well applied to low-cost image sensors.

[0068] In addition, the functional modules in the various embodiments of this article can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0069] The above description is merely a description of preferred embodiments of the column memory circuit, chip, image sensor, and imaging device provided by the present invention, and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A column memory circuit for an image sensor, characterized in that, It includes M×N storage modules, N readout modules, and a data transmission module. The data transmission module includes a transcoding unit, a second latch, a correlated double sampling unit, and a data interface unit that are coupled in sequence. The first end of each storage module is configured to receive a first data signal. The second end of each storage module is coupled to the first end of the corresponding readout module. The second end of each readout module is coupled to the transcoding unit of the data transmission module. M≥2. The storage module is configured to convert the received first data signal into a second data signal. The readout module is configured to send the received second data signal to the transcoding unit. The transcoding unit is configured to transcode the second data signal to obtain a first set of fourth data signals for transmission to the second latch. After obtaining the first set of fourth data signals, it transcodes the subsequently received second data signals to obtain a second set of fourth data signals for transmission to the correlated double sampling unit. The second latch is configured to latch the first set of fourth data signals when a fourth control signal is received. The correlated double sampling unit is configured to perform correlated double sampling processing based on the first set of fourth data signals and the second set of fourth data signals to obtain a third data signal. The data interface unit is configured to output the third data signal.

2. The column memory circuit according to claim 1, characterized in that, The correlated dual sampling unit includes several first transistors.

3. The column memory circuit according to claim 1, characterized in that, Each of the memory modules includes a first latch and a buffer unit coupled in sequence, and each of the read modules includes a trigger and a multiplexer coupled in sequence. The first latch is configured to latch the first data signal when it receives the first control signal from the image sensor and send the latched first data signal to the buffer unit. The buffer unit is configured to buffer the first data signal to obtain the second data signal and send the second data signal to the trigger. When the trigger receives the second control signal from the image sensor, it sends the second data signal to the multiplexer. The multiplexer is configured to select the corresponding second data signal to send to the transcoding unit according to the third control signal from the image sensor.

4. The column memory circuit according to claim 3, characterized in that, The transcoding unit includes several second transistors.

5. The column memory circuit according to claim 3, characterized in that, The second data signal uses Gray code encoding, while the first group of fourth data signals, the second group of fourth data signals, and the third data signal use binary encoding.

6. A chip for an image sensor, characterized in that, The chip integrates a column memory circuit as described in any one of claims 1 to 5.

7. An image sensor, characterized in that, Includes the column memory circuit as described in any one of claims 1 to 5 or the chip as described in claim 6.

8. The image sensor according to claim 7, characterized in that, The image sensor also includes a digital circuit area, a pixel array, and an image processor, and the data transmission module of the column memory circuit is disposed in the digital circuit area; The pixel array is configured to convert the acquired image light signal into the first data signal, the column memory circuit is configured to convert the first data signal into the second data signal and convert the second data signal into the third data signal through the data transmission module located in the digital circuit area, and the image processor is configured to process the third data signal to obtain the target image of the object to be acquired.

9. The image sensor according to claim 8, characterized in that, The data transmission module is installed in the digital circuit area using digital chip design tools.

10. An imaging device, characterized in that, It includes the column memory circuit as described in any one of claims 1 to 5, the chip as described in claim 6, or the image sensor as described in any one of claims 7 to 9.

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