Semiconductor structure, memory and manufacturing method thereof, and electronic equipment

Abstract

The invention relates to a memory cell, a memory and a manufacturing method thereof, and electronic equipment, and relates to the technical field of semiconductors. The memory cell comprises a substrate, a write transistor and a read transistor. The write transistor includes a first gate and a first semiconductor layer. The read transistor includes a second gate and a second semiconductor layer. The first gate extends in a first direction parallel to the substrate. The first semiconductor layer at least partially surrounds the periphery of the first grid electrode in an insulating mode and comprises a first source / drain electrode and a second source / drain electrode which are oppositely arranged in the second direction. The second grid electrode is located on the side, away from the first grid electrode, of the first semiconductor layer, and the second semiconductor layer comprises a third source / drain electrode which at least partially surrounds the extension part in the circumferential direction in an insulating mode and a fourth source / drain electrode which covers the end face of the extension part in an insulating mode. According to the invention, the process cost can be greatly reduced. Therefore, the wide production and application of the high-performance memory are promoted.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a memory and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] Based on this, the embodiments of the present disclosure provide a semiconductor structure, a memory and a manufacturing method thereof, and an electronic device, which are conducive to reducing the process complexity of the horizontal ring channel transistor, thereby significantly reducing the process cost of the horizontal ring channel memory, thereby promoting the widespread production and application of high-performance memory.

[0005] According to some embodiments, the present disclosure provides a semiconductor structure on one hand, including: a substrate, and at least one memory cell disposed on the substrate; the memory cell includes: a write transistor and a read transistor arranged in a direction parallel to the substrate. The write transistor includes a first gate and a first semiconductor layer. The read transistor includes a second gate and a second semiconductor layer. The first gate extends in a first direction parallel to the substrate. The first semiconductor layer is at least partially insulated and surrounds the circumference of the first gate, and the first semiconductor layer includes a first source / drain and a second source / drain arranged oppositely in a second direction. The second direction is parallel to the substrate and intersects with the first direction. The second gate is located on a side of the first semiconductor layer away from the first gate, and includes a connecting portion electrically connected to the first semiconductor layer, and an extension portion located on a side of the connecting portion away from the first semiconductor layer and extending in the second direction. The second semiconductor layer includes a third source / drain at least partially insulated and surrounds the circumference of the extension portion, and a fourth source / drain insulatingly covering the end face of the extension portion.

[0006] According to some embodiments, a second channel is further included, and the third source / drain, the fourth source / drain and the second channel are integrally connected.

[0007] According to some embodiments, a dimension of the connecting portion in a direction perpendicular to the substrate is larger than a dimension of at least a portion of the extending portion in a direction perpendicular to the substrate.

[0008] According to some embodiments, on the other hand, the present disclosure provides a memory, including: a semiconductor structure as described in the above embodiments, a write word line, a write bit line, a read word line, and a read bit line. The write word line is electrically connected to the first gate. The write bit line is located on a side of the first semiconductor layer away from the connection portion and is electrically connected to the first semiconductor layer. The read word line at least partially surrounds the third source / drain and is electrically connected to the third source / drain. The read bit line is located on a side of the fourth source / drain away from the second gate, is electrically connected to the fourth source / drain, and is insulated from the write bit line.

[0009] According to some embodiments, the write word line and the read bit line extend in a first direction, and the write bit line and the read word line extend in a direction perpendicular to the substrate, respectively.

[0010] According to some embodiments, the connection portion between the read bit line and the second gate is a pattern of the same conductive layer in different regions and insulated from each other.

[0011] According to some embodiments, on yet another aspect, the present disclosure further provides a method for manufacturing a memory, including the following steps:

[0012] Providing a substrate and forming one or more memory cells on the substrate; wherein,

[0013] Forming the memory cells includes:

[0014] Forming a write transistor; the write transistor includes a first gate and a first semiconductor layer; the first gate extends in a first direction parallel to the substrate; the first semiconductor layer at least partially insulates and surrounds the circumference of the first gate, and the first semiconductor layer includes a first source / drain and a second source / drain oppositely arranged in a second direction; the second direction is parallel to the substrate and intersects the first direction;

[0015] Forming a read transistor; the read transistor includes a second gate and a second semiconductor layer; the second gate is located on a side of the first semiconductor layer away from the first gate and includes a connection portion electrically connected to the first semiconductor layer, and an extension portion located on a side of the connection portion away from the first semiconductor layer and extending in the second direction; the second semiconductor layer includes a third source / drain at least partially insulating and surrounding the circumference of the extension portion, and a fourth source / drain insulating and covering the end face of the extension portion;

[0016] The method for manufacturing the memory further includes:

[0017] Forming a write word line electrically connected to the first gate;

[0018] Forming a write bit line electrically connected to the first semiconductor layer;

[0019] Forming a read word line electrically connected to the third source / drain;

[0020] Forming a read bit line electrically connected to the fourth source / drain.

[0021] According to some embodiments, forming a memory cell, a write word line, a write bit line, a read word line, and a read bit line further includes:

[0022] Providing a substrate, and forming a stacked structure on the substrate; the stacked structure includes a plurality of first conductive material layers and a plurality of first insulating material layers alternately stacked in a direction perpendicular to the substrate;

[0023] Etching the stacked structure to form a write word line pre-groove and a read transistor pre-groove in the first conductive material layer, and making the retained first conductive material layer form a connection portion of the read bit line and the second gate, respectively; wherein the write word line pre-groove extends along a first direction, the connection portion is located between the write word line pre-groove and the read transistor pre-groove, and the read bit line is located on a side of the read transistor pre-groove away from the connection portion along a second direction; the second direction and the first direction are parallel to the substrate and intersect;

[0024] A semiconductor material layer, a dielectric material layer and a second conductive material layer are sequentially deposited in the write word line pre-groove and the read transistor pre-groove, and the semiconductor material layer, the dielectric material layer and the second conductive material layer are patterned so that the second conductive material layer, the dielectric material layer and the semiconductor material layer retained in the write word line pre-groove form a write word line and a first dielectric layer and a first semiconductor layer sequentially surrounding the write word line, and the second conductive material layer, the dielectric material layer and the semiconductor material layer retained in the read transistor pre-groove form an extension of the second gate and a second dielectric layer and a second semiconductor layer sequentially covering the extension; the extension is electrically connected to the connection portion and extends along the second direction; the second semiconductor layer includes a third source / drain surrounding the extension, and a fourth source / drain electrically connected to the third source / drain and the read bit line;

[0025] forming a write word line electrically connected to the first gate and extending along a first direction;

[0026] A write bit line is formed on a side of the first semiconductor layer away from the connecting portion; the write bit line extends in a direction perpendicular to the substrate;

[0027] Etching the stack structure to expose the circumferential surface of the third source / drain;

[0028] A read word line is formed to cover the peripheral surface of the third source / drain and extend in a direction perpendicular to the substrate.

[0029] According to some embodiments, etching the stacked structure to form a write word line pre-groove and a read transistor pre-groove in the first conductive material layer, and making the retained first conductive material layer form a connection portion of the read bit line and the second gate, respectively, includes the following steps:

[0030] Etch the stacked structure along the direction perpendicular to the substrate to form at least one first etch groove and a plurality of first etch holes penetrating the stacked structure; the first etch groove extends along a first direction; the plurality of first etch holes are distributed on both sides of the corresponding first etch groove and are arranged at intervals along the first direction;

[0031] Based on the first etch groove and the first etch holes, etch the corresponding sidewalls of each first conductive material layer to form a write line pre-etch groove and a read transistor pre-etch groove, and make the remaining first conductive material layers respectively form read bit lines and connection parts.

[0032] According to some embodiments, before sequentially depositing a semiconductor material layer, a dielectric material layer, and a second conductive material layer in the write line pre-etch groove and the read transistor pre-etch groove, the manufacturing method of the memory further includes the following steps:

[0033] Fill the sacrificial material in the first etch groove, the first etch holes, and the removal area of the first conductive material layer;

[0034] Remove the sacrificial material in the first etch groove and between the read transistor pre-etch grooves adjacent in the first direction;

[0035] Fill a third conductive material layer in the removal area of the sacrificial material;

[0036] Etch the third conductive material layer to form a second etch hole exposing the sacrificial material in the write line pre-etch groove and a third etch hole exposing the sacrificial material in the read transistor pre-etch groove;

[0037] Based on the second etch hole and the third etch hole, remove the remaining sacrificial material, and sequentially deposit a semiconductor material layer, a dielectric material layer, and a second conductive material layer in the removal area of the remaining sacrificial material.

[0038] According to some embodiments, the sacrificial material includes a spin-on insulating dielectric or a hard mask material.

[0039] According to some embodiments, patterning the semiconductor material layer, the dielectric material layer, and the second conductive material layer includes the following steps:

[0040] Etch the third etch hole, and the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the third etch hole to form a fourth etch hole;

[0041] Based on the fourth etch hole, etch the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the read transistor pre-etch groove close to the connection part along the first direction, and correspondingly form an initial second semiconductor layer, an initial second dielectric layer, an initial extension part, and a first interval between the initial extension part and the connection part;

[0042] Fill a fourth conductive material layer in the fourth etch hole and the first interval; the fourth conductive material layer in the first interval and the initial extension part together constitute an extension part;

[0043] Fifth etching holes are respectively formed on two opposite sides of the writing line preset groove along the first direction, and the second conductive material layer remaining in the writing line preset groove forms a writing line; the fifth etching holes are located in the region between adjacent connection parts in the first direction, and the fifth etching holes expose partial side walls of the writing line;

[0044] Based on the fifth etching holes, the first insulating material layer, the semiconductor material layer and the dielectric material layer are wet-etched, and the semiconductor material layer and the dielectric material layer remaining in the writing line preset groove correspondingly form a first semiconductor layer and a first dielectric layer. Meanwhile, the initial second semiconductor layer and the initial second dielectric layer correspondingly form a second semiconductor layer and a second dielectric layer;

[0045] A second insulating material layer is filled in the fifth etching holes and the etching regions of the first insulating material layer, the semiconductor material layer and the dielectric material layer.

[0046] According to some embodiments, patterning the semiconductor material layer, the dielectric material layer and the second conductive material layer includes the following steps:

[0047] Seventh etching holes are respectively formed on two opposite sides of the writing line preset groove along the first direction, and the second conductive material layer remaining in the writing line preset groove forms a writing line; the seventh etching holes are located in the region between adjacent connection parts in the first direction, and the seventh etching holes expose partial side walls of the writing line;

[0048] Based on the seventh etching holes, the semiconductor material layer and the dielectric material layer are wet-etched, and the semiconductor material layer and the dielectric material layer remaining in the writing line preset groove correspondingly form a first semiconductor layer and a first dielectric layer;

[0049] A fourth insulating material layer is filled in the seventh etching holes and the etching regions of the semiconductor material layer and the dielectric material layer;

[0050] The semiconductor material layer, the dielectric material layer, the second conductive material layer and the fourth insulating material layer in the third etching holes are etched to form eighth etching holes;

[0051] Based on the eighth etching holes, the semiconductor material layer, the dielectric material layer and the second conductive material layer in the read transistor preset groove close to the connection part are etched along the first direction, correspondingly forming an initial second semiconductor layer, an initial second dielectric layer, an initial extension part and a second interval located between the initial extension part and the connection part;

[0052] A sixth conductive material layer is filled in the eighth etching holes and the second interval; the sixth conductive material layer in the second interval and the initial extension part together constitute an extension part;

[0053] The sixth conductive material layer in the eighth etching holes is removed;

[0054] Based on the eighth etching hole, wet-etch the first insulating material layer, the initial second semiconductor layer, and the initial second dielectric layer to form the second semiconductor layer and the second dielectric layer corresponding to the initial second semiconductor layer and the initial second dielectric layer;

[0055] Fill the eighth etching hole and the etching regions of the first insulating material layer, the initial second semiconductor layer, and the initial second dielectric layer with a fifth insulating material layer.

[0056] According to some embodiments, etching the stacked structure to expose the circumferential surface of the third source / drain, and forming a read word line that covers the circumferential surface of the third source / drain and extends in a direction perpendicular to the substrate, includes the following steps:

[0057] Etch the third conductive material layer between the read transistor preset grooves adjacent in the first direction to form a sixth etching hole; the sixth etching hole exposes the sidewalls of the third source / drain;

[0058] Based on the sixth etching hole, etch each first insulating material layer to expose the circumferential surface of the third source / drain;

[0059] Fill the sixth etching hole and the etching region of the first insulating material layer with a fifth conductive material layer;

[0060] Etch the fifth conductive material layer to form a read word line isolation hole, and make the remaining fifth conductive material layer form a read word line;

[0061] Fill the read word line isolation hole with a third insulating material.

[0062] According to some embodiments, forming a write transistor further includes the following steps:

[0063] Provide a substrate, and form a stacked structure on the substrate; the stacked structure includes multiple layers of first conductive material layers and multiple layers of first insulating material layers alternately stacked in a direction perpendicular to the substrate;

[0064] Etch the stacked structure in a direction perpendicular to the substrate to form at least one first etching groove penetrating the stacked structure; the first etching groove extends in the first direction;

[0065] Based on the first etching groove, etch the corresponding sidewalls of each first conductive material layer to form a write word line preset groove;

[0066] Fill the first etching groove and the removal regions of the first conductive material layers with a sacrificial material;

[0067] Remove the sacrificial material in the first etching groove;

[0068] Fill the first etching groove with a third conductive material layer;

[0069] Etch the third conductive material layer to form a second etching hole that exposes the sacrificial material in the write word line preset groove;

[0070] Based on the second etching holes, the remaining sacrificial material is removed, and a semiconductor material layer, a dielectric material layer, and a second conductive material layer are sequentially deposited on the removal area of the remaining sacrificial material;

[0071] Fifth etching holes are respectively formed on opposite sides of the write line preset groove along the first direction, and the second conductive material layer remaining in the write line preset groove forms a first gate; the fifth etching holes are located in the area between adjacent connection parts in the first direction, and the fifth etching holes expose partial side walls of the first gate;

[0072] Based on the fifth etching holes, the first insulating material layer, the semiconductor material layer, and the dielectric material layer are wet-etched, and the semiconductor material layer and the dielectric material layer remaining in the write line preset groove correspondingly form a first semiconductor layer and a first dielectric layer;

[0073] A second insulating material layer is filled in the fifth etching holes and the etching areas of the first insulating material layer, the semiconductor material layer, and the dielectric material layer.

[0074] According to some embodiments, forming a read transistor further includes:

[0075] Providing a substrate, and forming a stacked structure on the substrate; the stacked structure includes multiple layers of first conductive material layers and multiple layers of first insulating material layers alternately stacked along the direction perpendicular to the substrate;

[0076] Etching the stacked structure along the direction perpendicular to the substrate to form a plurality of first etching holes penetrating the stacked structure; the plurality of first etching holes are arranged at intervals along the first direction;

[0077] Based on the first etching holes, the corresponding side walls of each first conductive material layer are etched to form a read transistor preset groove, and the remaining first conductive material layer forms a connection part of a second gate;

[0078] A sacrificial material is filled in the first etching holes and the removal areas of the first conductive material layers;

[0079] The sacrificial material between adjacent read transistor preset grooves in the first direction is removed;

[0080] A third conductive material layer is filled in the removal area of the sacrificial material;

[0081] The third conductive material layer is etched to form third etching holes exposing the sacrificial material in the read transistor preset groove;

[0082] Based on the third etching holes, the remaining sacrificial material is removed, and a semiconductor material layer, a dielectric material layer, and a second conductive material layer are sequentially deposited on the removal area of the remaining sacrificial material;

[0083] Etch the semiconductor material layer, dielectric material layer, and second conductive material layer within the third etch hole to form a fourth etch hole;

[0084] Based on the fourth etch hole, etch the semiconductor material layer, dielectric material layer, and second conductive material layer within the read transistor preset groove near the connection portion along the first direction, and correspondingly form an initial second semiconductor layer, an initial second dielectric layer, an initial extension portion, and a first spacer located between the initial extension portion and the connection portion;

[0085] Fill the fourth conductive material layer within the fourth etch hole and the first spacer; the fourth conductive material layer within the first spacer and the initial extension portion together constitute the extension portion;

[0086] Form a fifth etch hole to correspondingly form a second semiconductor layer and a second dielectric layer for the initial second semiconductor layer and the initial second dielectric layer; the fifth etch hole is located in the region between the connection portions adjacent in the first direction;

[0087] Fill the second insulating material layer within the fifth etch hole and the etched regions of the first insulating material layer, semiconductor material layer, and dielectric material layer.

[0088] According to some embodiments, forming a read transistor further includes:

[0089] Provide a substrate and form a stacked structure on the substrate; the stacked structure includes multiple layers of first conductive material layers and multiple layers of first insulating material layers alternately stacked along the direction perpendicular to the substrate;

[0090] Etch the stacked structure along the direction perpendicular to the substrate to form multiple first etch holes penetrating the stacked structure; the multiple first etch holes are arranged at intervals along the first direction;

[0091] Based on the first etch hole, etch the corresponding sidewalls of each first conductive material layer to form a read transistor preset groove, and make the remaining first conductive material layer form the connection portion of the second gate;

[0092] Fill the sacrificial material within the first etch hole and the removed region of the first conductive material layer;

[0093] Remove the sacrificial material between the read transistor preset grooves adjacent in the first direction;

[0094] Fill the third conductive material layer within the removed region of the sacrificial material;

[0095] Etch the third conductive material layer to form a third etch hole exposing the sacrificial material within the read transistor preset groove;

[0096] Based on the third etch hole, remove the remaining sacrificial material, and sequentially deposit a semiconductor material layer, a dielectric material layer, and a second conductive material layer within the removed region of the remaining sacrificial material;

[0097] Form a seventh etching hole, the seventh etching hole being located in a region between connection parts adjacent in a first direction;

[0098] Fill a fourth insulating material layer in the seventh etching hole;

[0099] Etch the semiconductor material layer, the dielectric material layer, the second conductive material layer, and the fourth insulating material layer in the third etching hole to form an eighth etching hole;

[0100] Based on the eighth etching hole, etch the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the read transistor preset groove near the connection part in the first direction, and correspondingly form an initial second semiconductor layer, an initial second dielectric layer, an initial extension part, and a second gap located between the initial extension part and the connection part;

[0101] Fill a sixth conductive material layer in the eighth etching hole and the second gap; the sixth conductive material layer in the second gap and the initial extension part together constitute an extension part;

[0102] Remove the sixth conductive material layer in the eighth etching hole;

[0103] Based on the eighth etching hole, wet-etch the first insulating material layer, the initial second semiconductor layer, and the initial second dielectric layer to make the initial second semiconductor layer and the initial second dielectric layer correspondingly form a second semiconductor layer and a second dielectric layer;

[0104] Fill a fifth insulating material layer in the eighth etching hole and the etching regions of the first insulating material layer, the initial second semiconductor layer, and the initial second dielectric layer.

[0105] According to some embodiments, another aspect of the present disclosure further provides an electronic device, including: one or more memories as described in any one of the foregoing embodiments.

[0106] The embodiments of the present disclosure may / at least have the following advantages:

[0107] In the embodiments of the present application, by forming a write line preset groove and a read transistor preset groove, and then patterning the first conductive material layer deposited in the write line preset groove and the read transistor preset groove, the connection part between the read bit line and the second gate can be correspondingly formed. After patterning the semiconductor material layer, the dielectric material layer, and the second conductive material layer deposited in the write line preset groove and the read transistor preset groove, the extension parts of the first gate and the second gate can be correspondingly formed. In this way, the connection part between the read bit line and the second gate can be formed by a synchronous process, and the extension parts of the first gate and the second gate can be formed by a synchronous process. Therefore, the process complexity is significantly reduced, the manufacturing of the 2T0C memory is completed with fewer steps, and the process cost is greatly reduced. Thus, it promotes the wide production and application of high-performance memories.

[0108] In addition, by forming a read transistor preset groove, the preparation of a horizontal loop-channel read word line can also be realized. The read word line wraps around the circumferential surface of the third source / drain and extends in the direction perpendicular to the substrate. In this way, the second semiconductor layer surrounding the third source / drain can have a larger channel area and channel width, enabling better control ability of the read transistor, thereby improving the performance of the memory. Description of the Drawings

[0109] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0110] Figure 1 A top view structural schematic diagram of a memory provided in some embodiments; Figure 1 (a) is Figure 1 A cross-sectional schematic diagram of the memory shown in a cross-section along aa' perpendicular to the substrate; Figure 1 (b) is Figure 1 A cross-sectional schematic diagram of the memory shown in a cross-section along bb' perpendicular to the substrate; Figure 1 (c) is Figure 1 A cross-sectional schematic diagram of the memory shown in a cross-section along cc' perpendicular to the substrate; Figure 1 (d) is Figure 1 A cross-sectional schematic diagram of the memory shown in a cross-section along dd' perpendicular to the substrate;

[0111] Figure 2 A flowchart of a manufacturing method of a memory provided in some embodiments;

[0112] Figure 3 A flowchart of step S20 in a manufacturing method of a memory provided in some embodiments;

[0113] Figure 4 A flowchart of forming a semiconductor material layer, a dielectric material layer, and a second conductive material layer in a manufacturing method of a memory provided in some embodiments;

[0114] Figure 5 A flowchart of one implementation of step S30 in a manufacturing method of a memory provided in some embodiments;

[0115] Figure 6 A flowchart of another implementation of step S30 in a manufacturing method of a memory provided in some embodiments;

[0116] Figure 7A schematic flow chart of step S50 in a method for manufacturing a memory provided in some embodiments;

[0117] FIG. 8(a) is a schematic cross-sectional view of the structure obtained in step S10 in a method for manufacturing a memory provided in some embodiments on the aa' cross-section perpendicular to the substrate; FIG. 8(b) is a schematic cross-sectional view of the structure obtained in step S10 in a method for manufacturing a memory provided in some embodiments on the bb' cross-section perpendicular to the substrate; FIG. 8(c) is a schematic cross-sectional view of the structure obtained in step S10 in a method for manufacturing a memory provided in some embodiments on the cc' cross-section perpendicular to the substrate; FIG. 8(d) is a schematic cross-sectional view of the structure obtained in step S10 in a method for manufacturing a memory provided in some embodiments on the dd' cross-section perpendicular to the substrate;

[0118] FIG. 9(a) is a schematic cross-sectional view of the structure obtained in step S21 in a method for manufacturing a memory provided in some embodiments on the aa' cross-section perpendicular to the substrate; FIG. 9(b) is a schematic cross-sectional view of the structure obtained in step S21 in a method for manufacturing a memory provided in some embodiments on the bb' cross-section perpendicular to the substrate; FIG. 9(c) is a schematic cross-sectional view of the structure obtained in step S21 in a method for manufacturing a memory provided in some embodiments on the cc' cross-section perpendicular to the substrate; FIG. 9(d) is a schematic cross-sectional view of the structure obtained in step S21 in a method for manufacturing a memory provided in some embodiments on the dd' cross-section perpendicular to the substrate;

[0119] FIG. 10(a) is a schematic cross-sectional view of the structure obtained in step S22 in a method for manufacturing a memory provided in some embodiments on the aa' cross-section perpendicular to the substrate; FIG. 10(b) is a schematic cross-sectional view of the structure obtained in step S22 in a method for manufacturing a memory provided in some embodiments on the bb' cross-section perpendicular to the substrate; FIG. 10(c) is a schematic cross-sectional view of the structure obtained in step S22 in a method for manufacturing a memory provided in some embodiments on the cc' cross-section perpendicular to the substrate; FIG. 10(d) is a schematic cross-sectional view of the structure obtained in step S22 in a method for manufacturing a memory provided in some embodiments on the dd' cross-section perpendicular to the substrate;

[0120] FIG. 11(a) is a schematic cross-sectional view of the structure obtained in step S251 of a method for manufacturing a memory provided in some embodiments in the aa' cross-section perpendicular to the substrate; FIG. 11(b) is a schematic cross-sectional view of the structure obtained in step S251 of a method for manufacturing a memory provided in some embodiments in the bb' cross-section perpendicular to the substrate; FIG. 11(c) is a schematic cross-sectional view of the structure obtained in step S251 of a method for manufacturing a memory provided in some embodiments in the cc' cross-section perpendicular to the substrate; FIG. 11(d) is a schematic cross-sectional view of the structure obtained in step S251 of a method for manufacturing a memory provided in some embodiments in the dd' cross-section perpendicular to the substrate;

[0121] FIG. 12(a) is a schematic cross-sectional view of the structure obtained in step S252 of a method for manufacturing a memory provided in some embodiments in the aa' cross-section perpendicular to the substrate; FIG. 12(b) is a schematic cross-sectional view of the structure obtained in step S252 of a method for manufacturing a memory provided in some embodiments in the bb' cross-section perpendicular to the substrate; FIG. 12(c) is a schematic cross-sectional view of the structure obtained in step S252 of a method for manufacturing a memory provided in some embodiments in the cc' cross-section perpendicular to the substrate; FIG. 12(d) is a schematic cross-sectional view of the structure obtained in step S252 of a method for manufacturing a memory provided in some embodiments in the dd' cross-section perpendicular to the substrate;

[0122] FIG. 13(a) is a schematic cross-sectional view of the structure obtained in step S253 of a method for manufacturing a memory provided in some embodiments in the aa' cross-section perpendicular to the substrate; FIG. 13(b) is a schematic cross-sectional view of the structure obtained in step S253 of a method for manufacturing a memory provided in some embodiments in the bb' cross-section perpendicular to the substrate; FIG. 13(c) is a schematic cross-sectional view of the structure obtained in step S253 of a method for manufacturing a memory provided in some embodiments in the cc' cross-section perpendicular to the substrate; FIG. 13(d) is a schematic cross-sectional view of the structure obtained in step S253 of a method for manufacturing a memory provided in some embodiments in the dd' cross-section perpendicular to the substrate;

[0123] FIG. 14(a) is a schematic cross-sectional view of the structure obtained in step S254 of a method for manufacturing a memory provided in some embodiments in the aa' cross-section perpendicular to the substrate; FIG. 14(b) is a schematic cross-sectional view of the structure obtained in step S254 of a method for manufacturing a memory provided in some embodiments in the bb' cross-section perpendicular to the substrate; FIG. 14(c) is a schematic cross-sectional view of the structure obtained in step S254 of a method for manufacturing a memory provided in some embodiments in the cc' cross-section perpendicular to the substrate; FIG. 14(d) is a schematic cross-sectional view of the structure obtained in step S254 of a method for manufacturing a memory provided in some embodiments in the dd' cross-section perpendicular to the substrate;

[0124] FIG. 15(a) is a schematic cross-sectional view of the structure obtained after forming a removal region in a method for manufacturing a memory provided in some embodiments, taken along the aa' cross-section perpendicular to the substrate; FIG. 15(b) is a schematic cross-sectional view of the structure obtained after forming a removal region in a method for manufacturing a memory provided in some embodiments, taken along the bb' cross-section perpendicular to the substrate; FIG. 15(c) is a schematic cross-sectional view of the structure obtained after S255 in a method for manufacturing a memory provided in some embodiments, taken along the cc' cross-section perpendicular to the substrate; FIG. 15(d) is a schematic cross-sectional view of the structure obtained after S255 in a method for manufacturing a memory provided in some embodiments, taken along the dd' cross-section perpendicular to the substrate;

[0125] FIG. 16(a) is a schematic cross-sectional view of the structure obtained in step S255 in a method for manufacturing a memory provided in some embodiments, taken along the aa' cross-section perpendicular to the substrate; FIG. 16(b) is a schematic cross-sectional view of the structure obtained in step S255 in a method for manufacturing a memory provided in some embodiments, taken along the bb' cross-section perpendicular to the substrate; FIG. 16(c) is a schematic cross-sectional view of the structure obtained in step S255 in a method for manufacturing a memory provided in some embodiments, taken along the cc' cross-section perpendicular to the substrate; FIG. 16(d) is a schematic cross-sectional view of the structure obtained in step S255 in a method for manufacturing a memory provided in some embodiments, taken along the dd' cross-section perpendicular to the substrate;

[0126] FIG. 17(a) is a schematic cross-sectional view of the structure obtained in step S31 in a method for manufacturing a memory provided in some embodiments, taken along the aa' cross-section perpendicular to the substrate; FIG. 17(b) is a schematic cross-sectional view of the structure obtained in step S31 in a method for manufacturing a memory provided in some embodiments, taken along the bb' cross-section perpendicular to the substrate; FIG. 17(c) is a schematic cross-sectional view of the structure obtained in step S31 in a method for manufacturing a memory provided in some embodiments, taken along the cc' cross-section perpendicular to the substrate; FIG. 17(d) is a schematic cross-sectional view of the structure obtained in step S31 in a method for manufacturing a memory provided in some embodiments, taken along the dd' cross-section perpendicular to the substrate;

[0127] FIG. 18(a) is a schematic cross-sectional view of the structure obtained in step S32 in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 18(b) is a schematic cross-sectional view of the structure obtained in step S32 in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 18(c) is a schematic cross-sectional view of the structure obtained in step S32 in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 18(d) is a schematic cross-sectional view of the structure obtained in step S32 in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0128] FIG. 19(a) is a schematic cross-sectional view of the structure obtained in step S33 in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 19(b) is a schematic cross-sectional view of the structure obtained in step S33 in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 19(c) is a schematic cross-sectional view of the structure obtained in step S33 in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 19(d) is a schematic cross-sectional view of the structure obtained in step S33 in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0129] FIG. 20(a) is a schematic cross-sectional view of the structure obtained in step S34 in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 20(b) is a schematic cross-sectional view of the structure obtained in step S34 in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 20(c) is a schematic cross-sectional view of the structure obtained in step S34 in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 20(d) is a schematic cross-sectional view of the structure obtained in step S34 in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0130] FIG. 21(a) is a schematic cross-sectional view of the structure obtained in step S35 in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 21(b) is a schematic cross-sectional view of the structure obtained in step S35 in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 21(c) is a schematic cross-sectional view of the structure obtained in step S35 in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 21(d) is a schematic cross-sectional view of the structure obtained in step S35 in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0131] FIG. 22(a) is a schematic cross-sectional view of the structure obtained in step S36 in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 22(b) is a schematic cross-sectional view of the structure obtained in step S36 in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 22(c) is a schematic cross-sectional view of the structure obtained in step S36 in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 22(d) is a schematic cross-sectional view of the structure obtained in step S36 in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0132] FIG. 23(a) is a schematic cross-sectional view of a structure obtained in step S61 in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 23(b) is a schematic cross-sectional view of a structure obtained in step S61 in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 23(c) is a schematic cross-sectional view of a structure obtained in step S61 in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 23(d) is a schematic cross-sectional view of a structure obtained in step S61 in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0133] FIG. 24(a) is a schematic cross-sectional view of a structure obtained in step S62 in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 24(b) is a schematic cross-sectional view of a structure obtained in step S62 in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 24(c) is a schematic cross-sectional view of a structure obtained in step S62 in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 24(d) is a schematic cross-sectional view of a structure obtained in step S62 in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0134] FIG. 25(a) is a schematic cross-sectional view of a structure obtained in step S63 in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 25(b) is a schematic cross-sectional view of a structure obtained in step S63 in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 25(c) is a schematic cross-sectional view of a structure obtained in step S63 in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 25(d) is a schematic cross-sectional view of a structure obtained in step S63 in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0135] FIG. 26(a) is a schematic cross-sectional view of a resulting structure in an aa'-section perpendicular to the substrate in step S64 of a method for manufacturing a memory provided in some embodiments; FIG. 26(b) is a schematic cross-sectional view of a resulting structure in a bb'-section perpendicular to the substrate in step S64 of a method for manufacturing a memory provided in some embodiments; FIG. 26(c) is a schematic cross-sectional view of a resulting structure in a cc'-section perpendicular to the substrate in step S64 of a method for manufacturing a memory provided in some embodiments; FIG. 26(d) is a schematic cross-sectional view of a resulting structure in a dd'-section perpendicular to the substrate in step S64 of a method for manufacturing a memory provided in some embodiments;

[0136] FIG. 27(a) is a schematic cross-sectional view of a resulting structure in an aa'-section perpendicular to the substrate in step S65 of a method for manufacturing a memory provided in some embodiments; FIG. 27(b) is a schematic cross-sectional view of a resulting structure in a bb'-section perpendicular to the substrate in step S65 of a method for manufacturing a memory provided in some embodiments; FIG. 27(c) is a schematic cross-sectional view of a resulting structure in a cc'-section perpendicular to the substrate in step S65 of a method for manufacturing a memory provided in some embodiments; FIG. 27(d) is a schematic cross-sectional view of a resulting structure in a dd'-section perpendicular to the substrate in step S65 of a method for manufacturing a memory provided in some embodiments;

[0137] FIG. 28(a) is a schematic cross-sectional view of a resulting structure in an aa'-section perpendicular to the substrate in step S31' of a method for manufacturing a memory provided in some embodiments; FIG. 28(b) is a schematic cross-sectional view of a resulting structure in a bb'-section perpendicular to the substrate in step S31' of a method for manufacturing a memory provided in some embodiments; FIG. 28(c) is a schematic cross-sectional view of a resulting structure in a cc'-section perpendicular to the substrate in step S31' of a method for manufacturing a memory provided in some embodiments; FIG. 28(d) is a schematic cross-sectional view of a resulting structure in a dd'-section perpendicular to the substrate in step S31' of a method for manufacturing a memory provided in some embodiments;

[0138] FIG. 29(a) is a schematic cross-sectional view of the structure obtained in step S32' in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 29(b) is a schematic cross-sectional view of the structure obtained in step S32' in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 29(c) is a schematic cross-sectional view of the structure obtained in step S32' in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 29(d) is a schematic cross-sectional view of the structure obtained in step S32' in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0139] FIG. 30(a) is a schematic cross-sectional view of the structure obtained in step S33' in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 30(b) is a schematic cross-sectional view of the structure obtained in step S33' in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 30(c) is a schematic cross-sectional view of the structure obtained in step S33' in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 30(d) is a schematic cross-sectional view of the structure obtained in step S33' in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0140] FIG. 31(a) is a schematic cross-sectional view of the structure obtained in step S34' in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 31(b) is a schematic cross-sectional view of the structure obtained in step S34' in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 31(c) is a schematic cross-sectional view of the structure obtained in step S34' in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 31(d) is a schematic cross-sectional view of the structure obtained in step S34' in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0141] FIG. 32(a) is a schematic cross-sectional view of the structure obtained in step S35' in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 32(b) is a schematic cross-sectional view of the structure obtained in step S35' in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 32(c) is a schematic cross-sectional view of the structure obtained in step S35' in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 32(d) is a schematic cross-sectional view of the structure obtained in step S35' in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0142] FIG. 33(a) is a schematic cross-sectional view of the structure obtained in step S36' in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 33(b) is a schematic cross-sectional view of the structure obtained in step S36' in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 33(c) is a schematic cross-sectional view of the structure obtained in step S36' in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 33(d) is a schematic cross-sectional view of the structure obtained in step S36' in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0143] FIG. 34(a) is a schematic cross-sectional view of the structure obtained in step S37' in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 34(b) is a schematic cross-sectional view of the structure obtained in step S37' in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 34(c) is a schematic cross-sectional view of the structure obtained in step S37' in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 34(d) is a schematic cross-sectional view of the structure obtained in step S37' in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0144] FIG. 35(a) is a schematic cross-sectional view of the structure obtained in step S38' in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 35(b) is a schematic cross-sectional view of the structure obtained in step S38' in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 35(c) is a schematic cross-sectional view of the structure obtained in step S38' in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 35(d) is a schematic cross-sectional view of the structure obtained in step S38' in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0145] FIG. 36(a) is a schematic cross-sectional view of the structure obtained in step S39' in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 36(b) is a schematic cross-sectional view of the structure obtained in step S39' in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 36(c) is a schematic cross-sectional view of the structure obtained in step S39' in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 36(d) is a schematic cross-sectional view of the structure obtained in step S39' in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0146] FIG. 37(a) is a schematic cross-sectional view of another structure obtained in step S61 in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 37(b) is a schematic cross-sectional view of another structure obtained in step S61 in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 37(c) is a schematic cross-sectional view of another structure obtained in step S61 in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 37(d) is a schematic cross-sectional view of another structure obtained in step S61 in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0147] FIG. 38(a) is a schematic cross-sectional view of another structure obtained in step S62 in a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 38(b) is a schematic cross-sectional view of another structure obtained in step S62 in a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 38(c) is a schematic cross-sectional view of another structure obtained in step S62 in a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 38(d) is a schematic cross-sectional view of another structure obtained in step S62 in a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0148] FIG. 39(a) is a schematic cross-sectional view of another resulting structure in step S63 of a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 39(b) is a schematic cross-sectional view of another resulting structure in step S63 of a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 39(c) is a schematic cross-sectional view of another resulting structure in step S63 of a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 39(d) is a schematic cross-sectional view of another resulting structure in step S63 of a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0149] FIG. 40(a) is a schematic cross-sectional view of another resulting structure in step S64 of a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 40(b) is a schematic cross-sectional view of another resulting structure in step S64 of a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 40(c) is a schematic cross-sectional view of another resulting structure in step S64 of a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 40(d) is a schematic cross-sectional view of another resulting structure in step S64 of a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate;

[0150] FIG. 41(a) is a schematic cross-sectional view of another resulting structure in step S65 of a manufacturing method of a memory provided in some embodiments on an aa' cross-section perpendicular to the substrate; FIG. 41(b) is a schematic cross-sectional view of another resulting structure in step S65 of a manufacturing method of a memory provided in some embodiments on a bb' cross-section perpendicular to the substrate; FIG. 41(c) is a schematic cross-sectional view of another resulting structure in step S65 of a manufacturing method of a memory provided in some embodiments on a cc' cross-section perpendicular to the substrate; FIG. 41(d) is a schematic cross-sectional view of another resulting structure in step S65 of a manufacturing method of a memory provided in some embodiments on a dd' cross-section perpendicular to the substrate.

[0151] Description of reference numerals:

[0152] 1 - Substrate; L11 - First conductive material layer; L12 - Second conductive material layer; L13 - Third conductive material layer; L14 - Fourth conductive material layer; L15 - Fifth conductive material layer; L16 - Sixth conductive material layer; L2 - Insulating material layer; L21 - First insulating material layer; L22 - Second insulating material layer; L23 - Third insulating material layer; L24 - Fourth insulating material layer; L25 - Fifth insulating material layer; L3 - Sacrificial material;

[0153] L20 - Semiconductor material layer; 21 - First semiconductor layer; 211 - First source / drain; 212 - Second source / drain; 22 - Second semiconductor layer; 221 - Third source / drain; 222 - Fourth source / drain; 220 - Initial second semiconductor layer; L40 - Dielectric material layer; 41 - First dielectric layer; 42 - Second dielectric layer; 420 - Initial second dielectric layer;

[0154] D - Stacked structure; G - Second channel; 11 - First gate; 12 - Second gate; A - Connection part; B - Extension part; B0 - Initial extension part; Y1 - First mask layer; Y2 - Second mask layer; T R - Read transistor; T W - Write transistor; WL1 - Write word line; WL2 - Read word line; BL1 - Write bit line; BL2 - Read bit line;

[0155] C1 - First etching groove; C2 - Write word line pre - setting groove; C3 - Read transistor pre - setting groove;

[0156] K1 - First etching hole; K2 - Second etching hole; K3 - Third etching hole; K4 - Fourth etching hole; K5 - Fifth etching hole; K6 - Sixth etching hole; K7 - Seventh etching hole; K8 - Eighth etching hole; KR - Read word line isolation hole; J1 - First spacer. Detailed implementation manners

[0157] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present disclosure is more thorough and comprehensive.

[0158] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used in the description of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0159] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0160] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "overlying", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the figures is flipped, an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can include both an upper and a lower orientation. In addition, the device may also have additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0161] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / include" or "has" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0162] As used herein, the "deposition" process includes but is not limited to Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD).

[0163] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown are to be expected, for example, due to manufacturing techniques and / or tolerances. Thus, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0164] With the development of communication technology and digital technology, people continuously pursue products with lower power consumption, lighter weight and better performance. Memories are prone to have higher integration density and larger storage capacity, and have gradually become one of the important research directions in the current storage field.

[0165] Based on this, the present disclosure provides a storage cell, a memory, a manufacturing method thereof, and an electronic device, which can help reduce the process complexity of the horizontal annular channel transistor and complete the manufacturing of the 2T0C memory with fewer steps, thereby significantly reducing the process cost.

[0166] Some embodiments of the present disclosure provide a semiconductor structure. Please refer to Figure 1 and Figure 1 (a), Figure 1 (b), Figure 1 (c) and Figure 1 (d). The semiconductor structure includes: a substrate 1, and at least one storage cell disposed on the substrate 1; the storage cell includes: a write transistor T W and a read transistor T R . The write transistor T W includes a first gate 11 and a first semiconductor layer 21. The read transistor T R includes a second gate 12 and a second semiconductor layer 22. Wherein, the first gate 11 extends along a first direction (for example, the X direction) parallel to the substrate 1. The first semiconductor layer 21 at least partially insulates and surrounds the circumference of the first gate 11, and the first semiconductor layer 21 includes a first source / drain 211 and a second source / drain 212 disposed opposite to each other in a second direction (for example, the Y direction). The second direction (for example, the Y direction) is parallel to the substrate 1 and intersects the first direction (for example, the X direction). The second gate 12 is located on a side of the first semiconductor layer 21 facing away from the first gate 11, and includes a connection portion A electrically connected to the first semiconductor layer 21, and an extension portion B located on a side of the connection portion A facing away from the first semiconductor layer 21 and extending along the second direction (for example, the Y direction). The second semiconductor layer 22 includes a third source / drain 221 that at least partially insulates and surrounds the circumference of the extension portion B, and a fourth source / drain 222 that insulates and covers the end face of the extension portion B.

[0167] In some embodiments, it further includes a second channel G, and the third source / drain 221, the fourth source / drain 222 and the second channel are integrally connected. In this way, the manufacturing process of the source / drain can be simplified.

[0168] In some embodiments, the size of the connection portion A in the direction perpendicular to the substrate 1 is greater than the size of at least a part of the extension portion B in the direction perpendicular to the substrate 1. In this way, the connection resistance between the read transistor T R and the write transistor T W can be reduced, and the write and read speeds can be increased.

[0169] Some embodiments of the present disclosure also provide a memory. Please continue to refer to Figure 1 and Figure 1 (a), Figure 1 (b), Figure 1(c) and Figure 1 (d), the memory includes: a semiconductor structure as described in the above embodiments, and a write word line WL1, a write bit line BL1, a read word line WL2, and a read bit line BL2. The write word line WL1 is electrically connected to the first gate 11. The write bit line BL1 is located on a side of the first semiconductor layer 21 away from the connection portion A and is electrically connected to the first semiconductor layer 21. The read word line WL2 at least partially surrounds the third source / drain 221 and is electrically connected to the third source / drain 221. The read bit line BL2 is located on a side of the fourth source / drain 222 away from the second gate 12 and is electrically connected to the fourth source / drain 222 and is insulated from the write bit line BL1.

[0170] In the embodiment of the present application, the first semiconductor layer 21 is insulatingly surrounded by the circumferential direction of the first gate 11, the second gate 12 is located on a side of the first semiconductor layer 21 away from the first gate 11, and the read bit line BL2 is located on the surface of the fourth source / drain 222 away from the second gate 12. The second gate 12 and the read bit line BL2 can be fabricated simultaneously, and the first gate 11 and the second gate 12 can also be fabricated simultaneously. Thus, the process complexity is significantly reduced, thereby greatly reducing the process cost. Furthermore, it promotes the wide production and application of high-performance memories.

[0171] In addition, the read word line WL2 covers the circumferential surface of the third source / drain 221 and extends along the direction perpendicular to the substrate 1, so that the second semiconductor layer 22 surrounding the third source / drain 221 can have a higher channel area and channel width, making the control ability of the read transistor T R better, thereby improving the performance of the memory.

[0172] Exemplarily, the materials of the write word line WL1, the write bit line BL1, the read word line WL2, the read bit line BL2, the connection portion A, and the extension portion B all include but are not limited to a metal layer, such as a tungsten metal layer.

[0173] Exemplarily, the first semiconductor layer 21 and the second semiconductor layer 22 include but are not limited to a metal oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) layer. Here, by using the relatively high current switching ratio of IGZO, the three-dimensionalization of the 2T0C structure memory can be achieved.

[0174] In some embodiments, the write word line WL1 and the read bit line BL2 extend along a first direction (e.g., the X direction), and the write bit line BL1 and the read word line WL2 extend along the direction perpendicular to the substrate 1, respectively.

[0175] In some embodiments, the connection portion A between the read bit line BL2 and the second gate 12 is a pattern of the same conductive layer in different regions and insulated from each other.

[0176] In some embodiments, please refer to Figure 1 and Figure 1 (a) Figure 1 (b) Figure 1 (c) and Figure 1 (d) further includes an insulating material layer L2.

[0177] By way of example, the insulating material layer L2 includes, but is not limited to, a silicon oxide layer.

[0178] In some embodiments, the memory further includes a first dielectric layer 41 and a second dielectric layer 42. The first dielectric layer 41 is located between the first semiconductor layer 21 and the write word line WL1. The second dielectric layer 42 is located between the second semiconductor layer 22 and the extension B.

[0179] Some embodiments of the present disclosure also provide a method for manufacturing a memory. Figure 1 , Figure 1 (a) Figure 1 (b) Figure 1 (c) and Figure 1 (d) It is understood that the manufacturing method includes steps S1 to S5.

[0180] S1: providing a substrate, and forming one or more memory cells on the substrate.

[0181] The forming of the storage unit includes steps S11 to S12.

[0182] S11: forming a write transistor; the write transistor comprises a first gate and a first semiconductor layer; the first gate extends along a first direction parallel to the substrate; the first semiconductor layer is at least partially insulated and surrounds the first gate, and the first semiconductor layer comprises a first source / drain and a second source / drain arranged opposite to each other in a second direction; the second direction is parallel to the substrate and intersects with the first direction.

[0183] S12: forming a read transistor; the read transistor comprises a second gate and a second semiconductor layer; the second gate is located on a side of the first semiconductor layer away from the first gate, and comprises a connecting portion electrically connected to the first semiconductor layer, and an extending portion located on a side of the connecting portion away from the first semiconductor layer and extending along a second direction; the second semiconductor layer comprises a third source / drain electrode at least partially insulated and surrounding the circumference of the extending portion, and a fourth source / drain electrode insulated and covering an end surface of the extending portion;

[0184] The method for manufacturing the memory further includes:

[0185] S2: forming a write word line electrically connected to the first gate;

[0186] S3: forming a write bit line electrically connected to the first semiconductor layer;

[0187] S4: forming a read word line electrically connected to the third source / drain;

[0188] S5: forming a read bit line electrically connected to the fourth source / drain.

[0189] In some embodiments, see Figure 2 Combined with Figure 1 , Figure 1 (a) Figure 1 (b) Figure 1 (c) and Figure 1 (d) It is understood that forming a memory cell, a write word line, a write bit line, a read word line and a read bit line also includes steps S10 to S50.

[0190] S10: providing a substrate 1, and forming a stacked structure on the substrate 1; the stacked structure includes a plurality of first conductive material layers and a plurality of first insulating material layers L21 alternately stacked in a direction perpendicular to the substrate 1.

[0191] S20: Etching the stacked structure to form a write word line WL1 pre-groove and a read transistor pre-groove in the first conductive material layer L11, and making the retained first conductive material layer form a connection portion A of the read bit line BL2 and the second gate 12 respectively; wherein the write word line pre-groove extends along a first direction (e.g., X direction), the connection portion A is located between the write word line pre-groove and the read transistor pre-groove, and the read bit line BL2 is located on a side of the read transistor pre-groove away from the connection portion A along a second direction (e.g., Y direction); the second direction (e.g., Y direction) and the first direction (e.g., X direction) are parallel to the substrate and intersect.

[0192] S30: sequentially depositing a semiconductor material layer, a dielectric material layer and a second conductive material layer in the write word line pre-groove and the read transistor pre-groove, and patterning the semiconductor material layer, the dielectric material layer and the second conductive material layer, so that the second conductive material layer, the dielectric material layer and the semiconductor material layer retained in the write word line pre-groove form the write word line WL1 and the first dielectric layer and the first semiconductor layer sequentially surrounding the write word line WL1, and the second conductive material layer, the dielectric material layer and the semiconductor material layer retained in the read transistor pre-groove form the extension B of the second gate 12 and the second dielectric layer and the second semiconductor layer sequentially covering the extension B; the extension B is electrically connected to the connecting portion A and extends along the second direction (for example, the Y direction); the second semiconductor layer includes a third source / drain 221 surrounding the extension B, and a fourth source / drain 222 electrically connecting the third source / drain 221 and the read bit line BL2.

[0193] S40 : forming a write word line WL1 electrically connected to the first gate 11 and extending along a first direction (eg, X direction).

[0194] S50 : forming a write bit line BL1 on a side of the first semiconductor layer away from the connecting portion.

[0195] S60: Etch the stacked structure to expose the circumferential surface of the third source / drain 221; form a read word line WL2 that covers the circumferential surface of the third source / drain 221 and extends in a direction perpendicular to the substrate 1.

[0196] In the embodiments of the present application, by forming a write word line WL1 pre - groove and a read transistor pre - groove, and then patterning the first conductive material layer L11 deposited in the write word line WL1 pre - groove and the read transistor pre - groove, a connection portion A between the read bit line BL2 and the second gate 12 can be correspondingly formed. After patterning the semiconductor material layer, dielectric material layer, and second conductive material layer deposited in the write word line WL1 pre - groove and the read transistor pre - groove, an extension portion B of the first gate 11 and the second gate 12 can be correspondingly formed. In this way, the connection portion A between the read bit line BL2 and the second gate 12 can be formed by a synchronous process, and the extension portion B of the first gate 11 and the second gate 12 can be formed by a synchronous process. Therefore, the process complexity is significantly reduced, the manufacturing of the 2T0C memory is completed with fewer steps, and the process cost is greatly reduced. Thus, it promotes the wide production and application of high - performance memories.

[0197] In addition, by forming a read transistor pre - groove, the preparation of a horizontal - direction ring - channel read word line WL2 can also be realized. The read word line WL2 covers the circumferential surface of the third source / drain 221 and extends in a direction perpendicular to the substrate 1. In this way, the second semiconductor layer surrounding the third source / drain 221 can have a larger channel area and channel width, so that the control ability of the read transistor T R is better, thereby improving the performance of the memory.

[0198] In some embodiments, please refer to Figure 3 and in combination with Figure 1 、 Figure 1 (a)、 Figure 1 (b)、 Figure 1 (c) and Figure 1 (d) for understanding. In step S20, the stacked structure is etched to form a write word line pre - groove and a read transistor pre - groove in the first conductive material layer, and the remaining first conductive material layer forms a connection portion between the read bit line and the second gate 12, including steps S21 - S22:

[0199] S21: Etch the stacked structure in a direction perpendicular to the substrate 1 to form at least one first etching groove and a plurality of first etching holes penetrating the stacked structure; the first etching groove extends in a first direction (for example, the X direction); the plurality of first etching holes are distributed on both sides of the corresponding first etching groove and are arranged at intervals in the first direction (for example, the X direction);

[0200] S22: Based on the first etching groove and the first etching hole, etch the corresponding sidewalls of each first conductive material layer to form a writing line pre-etching groove and a read transistor pre-etching groove, and make the remaining first conductive material layers respectively form a read bit line BL2 and a connection part A.

[0201] In some embodiments, please refer to Figure 4 and in combination with Figure 1 、 Figure 1 (a), Figure 1 (b), Figure 1 (c) and Figure 1 (d) to understand that before depositing a semiconductor material layer, a dielectric material layer, and a second conductive material layer in sequence in the writing line pre-etching groove and the read transistor pre-etching groove in step S30, the manufacturing method of the memory further includes steps S251 to S254:

[0202] S251: Fill the sacrificial material in the first etching groove, the first etching hole, and the removal area of the first conductive material layer;

[0203] S252: Remove the sacrificial material in the first etching groove and between the read transistor pre-etching grooves adjacent in the first direction (e.g., the X direction);

[0204] S253: Fill a third conductive material layer L13 in the removal area of the sacrificial material;

[0205] S254: Etch the third conductive material layer L13 to form a second etching hole exposing the sacrificial material in the writing line pre-etching groove and a third etching hole exposing the sacrificial material in the read transistor pre-etching groove;

[0206] S255: Remove the remaining sacrificial material based on the second etching hole and the third etching hole, and deposit a semiconductor material layer, a dielectric material layer, and a second conductive material layer in sequence in the removal area of the remaining sacrificial material.

[0207] In some embodiments, please refer to Figure 5 and in combination with Figure 1 、 Figure 1 (a), Figure 1 (b), Figure 1 (c) and Figure 1 (d) to understand that in step S30, patterning the semiconductor material layer, the dielectric material layer, and the second conductive material layer includes steps S31 to S36:

[0208] S31: Etch the third etching hole, as well as the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the third etching hole, to form a fourth etching hole;

[0209] S32: Based on the fourth etching hole, etch the semiconductor material layer, dielectric material layer, and second conductive material layer near the connection part A in the read transistor preset groove along the first direction (e.g., the X direction), correspondingly forming an initial second semiconductor layer, an initial second dielectric layer, an initial extension part, and a first gap between the initial extension part B0 and the connection part A;

[0210] S33: Fill the fourth conductive material layer L14 in the fourth etching hole and the first gap; the fourth conductive material layer L14 in the first gap and the initial extension part B0 together constitute the extension part B;

[0211] S34: Form fifth etching holes on opposite sides of the write line preset groove along the first direction (e.g., the X direction), and make the second conductive material layer remaining in the write line preset groove form the first gate 11; the fifth etching holes are located in the area between adjacent connection parts A in the first direction (e.g., the X direction), and the fifth etching holes expose part of the side walls of the first gate 11;

[0212] S35: Based on the fifth etching hole, wet-etch the first insulating material layer L21, semiconductor material layer, and dielectric material layer, and make the semiconductor material layer and dielectric material layer remaining in the write line preset groove correspondingly form the first semiconductor layer 21 and the first dielectric layer 41, and at the same time make the initial second semiconductor layer and the initial second dielectric layer correspondingly form the second semiconductor layer 22 and the second dielectric layer 42;

[0213] S36: Fill the second insulating material layer L22 in the fifth etching hole and the etching areas of the first insulating material layer L21, semiconductor material layer, and dielectric material layer.

[0214] In the embodiments of the present application, the parasitic transistor is eliminated by using the narrow-side wet etching method, thereby improving the performance of the memory.

[0215] In other embodiments, other methods may be used to implement step S30. Please refer to Figure 6 and combine with Figure 1 、 Figure 1 (a), Figure 1 (b), Figure 1 (c) and Figure 1 (d) to understand that patterning the semiconductor material layer, dielectric material layer, and second conductive material layer includes steps S31’ to S39’:

[0216] S31’: Form seventh etching holes on opposite sides of the write line preset groove along the first direction (e.g., the X direction), and make the second conductive material layer remaining in the write line preset groove form the first gate 11; the seventh etching holes are located in the area between adjacent connection parts A in the first direction (e.g., the X direction), and the seventh etching holes expose part of the side walls of the first gate 11.

[0217] S32': Based on the seventh etching hole, wet-etch the semiconductor material layer and the dielectric material layer, and make the semiconductor material layer and the dielectric material layer retained in the write line preset groove correspondingly form the first semiconductor layer 21 and the first dielectric layer 41.

[0218] S33': Fill the fourth insulating material layer L24 in the seventh etching hole and the etching regions of the semiconductor material layer and the dielectric material layer.

[0219] S34': Etch the semiconductor material layer, the dielectric material layer, the second conductive material layer, and the fourth insulating material layer L24 in the third etching hole to form the eighth etching hole.

[0220] S35': Based on the eighth etching hole, etch the semiconductor material layer, the dielectric material layer, and the second conductive material layer near the connection portion A in the read transistor preset groove along the first direction (e.g., the X direction), and correspondingly form the initial second semiconductor layer, the initial second dielectric layer, the initial extension portion B0, and the second gap located between the initial extension portion B0 and the connection portion A.

[0221] S36': Fill the sixth conductive material layer in the eighth etching hole and the second gap; the sixth conductive material layer in the second gap and the initial extension portion together constitute the extension portion B.

[0222] S37': Remove the sixth conductive material layer in the eighth etching hole.

[0223] S38': Based on the eighth etching hole, wet-etch the first insulating material layer L21, the initial second semiconductor layer, and the initial second dielectric layer, so that the initial second semiconductor layer and the initial second dielectric layer correspondingly form the second semiconductor layer 22 and the second dielectric layer 42;

[0224] S39': Fill the fifth insulating material layer in the eighth etching hole and the etching regions of the first insulating material layer L21, the initial second semiconductor layer, and the initial second dielectric layer.

[0225] In the embodiments of the present application, the parasitic transistor is eliminated by using the narrow-side wet-etching method, thereby improving the performance of the memory.

[0226] In some embodiments, after filling the second insulating material layer L22 in step S36, step S40 may be executed to form the write bit line BL1.

[0227] In other embodiments, after filling the fifth insulating material layer in step S39', step S40 may be executed to form the write bit line BL1.

[0228] In some embodiments, please refer to Figure 7 and combine with Figure 1 、 Figure 1 (a)、 Figure 1(b), Figure 1 (c) and Figure 1 (d) It can be understood that in step S60, the stacked structure is etched to expose the circumferential surface of the third source / drain 221, and a read word line WL1 that covers the circumferential surface of the third source / drain 221 and extends in a direction perpendicular to the substrate is formed, including the following steps:

[0229] S61: Etch the third conductive material layer between adjacent read transistor preset slots along a first direction (e.g., the X direction) to form a sixth etch hole; the sixth etch hole exposes the sidewall of the third source / drain 221;

[0230] S62: Based on the sixth etch hole, etch each first insulating material layer L21 to expose the circumferential surface of the third source / drain 221;

[0231] S63: Fill the fifth conductive material layer L15 in the etch regions of the sixth etch hole and the first insulating material layer L21;

[0232] S64: Etch the fifth conductive material layer L15 to form a read word line isolation hole, and make the remaining fifth conductive material layer L15 form a read word line;

[0233] S65: Fill the third insulating material layer L23 in the read word line isolation hole.

[0234] It can be understood that some of the steps in the above method for manufacturing a memory are shown in Figures 2 to 7 in sequence according to the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps has no strict order limit, and they can be executed in other orders. Moreover, Figures 2 to 7 at least some of the steps in

[0235] may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed simultaneously or alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0236] For the sake of clarity, the first conductive material layer L11, the second conductive material layer L12, the third conductive material layer L13, the fourth conductive material layer L14, the fifth conductive material layer L15, and the sixth conductive material layer L16 in the figure all adopt the same filling pattern in the figure, and the first insulating material layer L21, the second insulating material layer L22, the third insulating material layer L23, and the fourth insulating material layer L24 all adopt the same filling pattern in the figure.

[0237] In step S10, please refer to Figure 1 FIGS. 8(a), 8(b), 8(c) and 8(d), and provide a substrate 1, and form a stacked structure D on the substrate 1; the stacked structure D includes a plurality of first conductive material layers L11 and a plurality of first insulating material layers L21 that are alternately stacked along a direction perpendicular to the substrate 1.

[0238] Exemplarily, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductor material, or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 1 can be a layered substrate including a stack such as Si and SiGe, a stack of Si and SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0239] Exemplarily, the first conductive material layer L11 includes a metal layer, such as a metal tungsten layer.

[0240] Exemplarily, the first insulating material layer L21 includes, but is not limited to, a silicon oxide layer.

[0241] Here, the stacking number of the first conductive material layers L11 can be set according to the stacking number of the storage layers in the memory. And, the first insulating material layer L21 can be located between adjacent first conductive material layers L11 or on one side of the first and last first conductive material layers L11, and the number of layers of the first insulating material layer L21 can be set to match the stacking number of the first conductive material layers L11. Each of the first conductive material layers L11 and each of the first insulating material layers L21 can be formed by a deposition process.

[0242] In addition, after forming the plurality of first conductive material layers L11 and the plurality of first insulating material layers L21 that are alternately stacked in step S10, a first mask layer Y1, such as a photoresist layer and / or a hard mask layer, can be formed on the upper surface of the top first insulating material layer L21. Thus, it is convenient to etch the stacked structure D based on the mask pattern in the first mask layer Y1 in the subsequent process.

[0243] In step S20, please refer to Figure 1 and Figures 9(a) to 10(d) , etch the stacked structure D to form a write line WL1 pre-groove C2 and a read transistor T in the first conductive material layer L11 RA preset groove C3 is provided, and the remaining first conductive material layer L11 forms connection portions A of the read bit line BL2 and the second gate 12 respectively. Among them, the write line WL1 preset groove C2 extends along a first direction (for example, the X direction), and the connection portion A is located between the write line WL1 preset groove C2 and the read transistor T R preset groove C3, and the read bit line BL2 is located at the read transistor T R On one side of the preset groove C3 along a second direction (for example, the Y direction) away from the connection portion A; the second direction (for example, the Y direction) and the first direction (for example, the X direction) are parallel to the substrate 1 and intersect.

[0244] Exemplarily, step S20 includes step S21 and step S22.

[0245] In step S21, please refer to Figure 1 and FIGS. 9(a), 9(b), 9(c) and 9(d), etch the stacked structure D along the direction perpendicular to the substrate 1 to form at least one first etch groove C1 and a plurality of first etch holes K1 penetrating the stacked structure D. The first etch groove C1 extends along a first direction (for example, the X direction); the plurality of first etch holes K1 are distributed on both sides of the corresponding first etch groove C1 and are arranged at intervals along the first direction (for example, the X direction).

[0246] Here, the stacked structure D can be etched based on the mask pattern in the first mask layer Y1.

[0247] Exemplarily, a dry etching process can be used to etch the stacked structure D.

[0248] In step S22, please refer to Figure 1 and FIGS. 10(a), 10(b), 10(c) and 10(d), based on the first etch groove C1 and the first etch holes K1, etch the corresponding sidewalls of each first conductive material layer L11 to form the write line WL1 preset groove C2 and the read transistor T R preset groove C3, and the remaining first conductive material layer L11 forms the read bit line BL2 and the connection portion A respectively.

[0249] Exemplarily, a wet etching process can be used to etch the corresponding sidewalls of each first conductive material layer L11.

[0250] In step S251, please refer to Figure 1 and FIGS. 11(a), 11(b), 11(c) and 11(d), fill the sacrificial material L3 in the removal areas of the first etch groove C1, the first etch holes K1 and the first conductive material layer L11. The sacrificial material L3 can prevent leakage and play an insulating role between transistors.

[0251] In some embodiments, the sacrificial material L3 includes a spin-on insulating medium or a hard mask material.

[0252] Exemplarily, the sacrificial material L3 may include, but is not limited to, silicon nitride or carbon material.

[0253] Exemplarily, the sacrificial material L3 can be filled by a spin coating process.

[0254] In step S252, refer to Figure 1 and FIGS. 12(a), 12(b), 12(c) and 12(d), and remove the sacrificial material L3 in the first etching groove C1 and between the read transistors T adjacent in the first direction (e.g., the X direction) R and the sacrificial material L3 between the preset grooves C3.

[0255] Exemplarily, a dry etching process can be used to remove the sacrificial material L3.

[0256] In step S253, refer to Figure 1 and FIGS. 13(a), 13(b), 13(c) and 13(d), and fill the third conductive material layer L13 in the removal area of the sacrificial material L3.

[0257] Here, the materials of the third conductive material layer L13 and the first conductive material layer L11 may be the same. Exemplarily, the third conductive material layer L13 includes a metal layer, such as a tungsten metal layer.

[0258] Exemplarily, a deposition process can be used to fill the third conductive material layer L13.

[0259] In step S254, refer to Figure 1 and FIGS. 14(a), 14(b), 14(c) and 14(d), etch the third conductive material layer L3 to form a second etching hole K2 exposing the sacrificial material L3 in the write line WL1 preset groove C2, and exposing the read transistor T R and a third etching hole K3 exposing the third conductive material layer L13 in the read transistor T preset groove C3.

[0260] Exemplarily, a dry etching process can be used to form the second etching hole K2 and the third etching hole K3.

[0261] Here, it should be added that in some embodiments, after forming the second etching hole K2 and the third etching hole K3, the first mask layer Y1 can be removed by a grinding process. The grinding process includes, but is not limited to, Chemical Mechanical Polishing (CMP).

[0262] In step S255, refer to Figure 1With reference to FIGS. 15(a), 15(b), 15(c) and 15(d), the residual sacrificial material L3 is removed based on the second etch hole K2 and the third etch hole K3, and a removal region Q1 of the residual sacrificial material L3 is obtained.

[0263] Exemplarily, a dry etching process can be used to remove the residual sacrificial material L3.

[0264] Further exemplarily, please refer to Figure 1 and FIGS. 16(a), 16(b), 16(c) and 16(d) to sequentially deposit a semiconductor material layer L20, a dielectric material layer L40 and a second conductive material layer L12 on the removal region Q1 of the residual sacrificial material L3.

[0265] Exemplarily, the semiconductor material layer L20 includes but is not limited to a metal oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) layer.

[0266] Exemplarily, the semiconductor material layer L20 can be formed by a deposition process, such as an ALD process.

[0267] Exemplarily, the dielectric material layer L40 includes but is not limited to an HK (high-K) dielectric layer. The HK dielectric layer refers to a dielectric layer having a high dielectric constant K, and the high dielectric constant K is, for example, greater than 3.9.

[0268] Exemplarily, the dielectric material layer L40 can be formed by a deposition process, such as an ALD process.

[0269] Exemplarily, the second conductive material layer L12 includes a metal layer, such as a metal tungsten layer.

[0270] Exemplarily, the second conductive material layer L12 can be formed by a deposition process, such as an ALD process.

[0271] In step S30, please refer to Figure 1 and Figures 17(a) to 36(d) , a semiconductor material layer L20, a dielectric material layer L40 and a second conductive material layer L12 are sequentially deposited in the write word line WL1 preset groove C2 and the read transistor T R preset groove C3, and the semiconductor material layer L20, the dielectric material layer L40 and the second conductive material layer L12 are patterned so that the second conductive material layer L12, the dielectric material layer L40 and the semiconductor material layer L20 remaining in the write word line WL1 preset groove C2 correspondingly form a first gate 11 and a first dielectric layer 41 and a first semiconductor layer 21 that sequentially surround the first gate 11 circumferentially, and the remaining in the read transistor T RThe second conductive material layer L12, the dielectric material layer L40, and the semiconductor material layer L20 within the preset groove C3 correspondingly form an extension portion B of the second gate 12, and a second dielectric layer 42 and a second semiconductor layer 22 that sequentially coat the extension portion B; the extension portion B is electrically connected to the connection portion A and extends along a second direction (e.g., the Y direction); the second semiconductor layer 22 includes a third source / drain 221 that surrounds the circumference of the extension portion B, and a fourth source / drain 222 that is electrically connected to the third source / drain 221 and the read bit line BL2.

[0272] In some embodiments, referring to Figure 1 and Figures 17(a) to 22(d) , the patterning of the semiconductor material layer L20, the dielectric material layer L40, and the second conductive material layer L12 in step S30 includes steps S31 to S36.

[0273] In step S31, referring to Figure 1 and FIGS. 17(a), 17(b), 17(c), and 17(d), etch the third etch hole K3, as well as the semiconductor material layer L20, the dielectric material layer L40, and the second conductive material layer L12 within the third etch hole K3, to form a fourth etch hole K4.

[0274] Exemplarily, a dry etching process can be employed to form the fourth etch hole K4.

[0275] In addition, before step S31, a second mask layer Y2, such as a photoresist layer and / or a hard mask layer, can be formed on the upper surface of the top first insulating material layer L21.

[0276] In step S32, referring to Figure 1 and FIGS. 18(a), 18(b), 18(c), and 18(d), based on the fourth etch hole K4, etch the read transistor T along a first direction (e.g., the X direction) R the semiconductor material layer L20, the dielectric material layer L40, and the second conductive material layer L12 within the preset groove C3 near the connection portion A correspondingly form an initial second semiconductor layer 220, an initial second dielectric layer 420, an initial extension portion B0, and a first spacer J1 located between the initial extension portion B0 and the connection portion A.

[0277] In step S33, referring to Figure 1 and FIGS. 19(a), 19(b), 19(c), and 19(d), fill a fourth conductive material layer L14 within the fourth etch hole K4 and the first spacer J1; the fourth conductive material layer L14 within the first spacer J1 and the initial extension portion B0 together constitute the extension portion B. Wherein, the second gate 12 includes the connection portion A and the extension portion B.

[0278] Here, the extension part B is electrically connected to the connection part A and extends along the second direction (for example, the Y direction).

[0279] Exemplarily, the fourth conductive material layer L14 includes a metal layer, such as a tungsten metal layer.

[0280] In step S34, please refer to Figure 1 and FIGS. 20(a), 20(b), 20(c), and 20(d). Fifth etching holes K5 are respectively formed on opposite sides of the write line WL1 pre-set groove C2 along the first direction (for example, the X direction), and the second conductive material layer L12 remaining in the write line WL1 pre-set groove C2 forms the first gate 11. The fifth etching holes K5 are located in the region between the connection parts A adjacent in the first direction (for example, the X direction), and the fifth etching holes K5 expose partial sidewalls of the first gate 11.

[0281] In step S35, please refer to Figure 1 and FIGS. 21(a), 21(b), 21(c), and 21(d). Based on the fifth etching holes K5, the first insulating material layer L21, the semiconductor material layer L20, and the dielectric material layer L40 are wet-etched, and the semiconductor material layer L20 and the dielectric material layer L40 remaining in the write line WL1 pre-set groove C2 correspondingly form the first semiconductor layer 21 and the first dielectric layer 41. At the same time, the initial second semiconductor layer 220 and the initial second dielectric layer 420 correspondingly form the second semiconductor layer 22 and the second dielectric layer 42. Among them, the second semiconductor layer 22 includes a third source / drain 221 surrounding the circumferential direction of the extension part B, and a fourth source / drain 222 electrically connected to the third source / drain 221 and the read bit line BL2.

[0282] Here, the write transistor T W includes the first semiconductor layer 21, the first dielectric layer 41, and the first gate 11.

[0283] In step S36, please refer to Figure 1 and FIGS. 22(a), 22(b), 22(c), and 22(d). The second insulating material layer L22 is filled in the fifth etching holes K5 and the etching regions of the first insulating material layer L21, the semiconductor material layer L20, and the dielectric material layer L40.

[0284] Exemplarily, the second insulating material layer L22 includes, but is not limited to, a silicon oxide layer.

[0285] In step S40, please refer to Figure 1 and FIGS. 22(a), 22(b), 22(c), and 22(d). A write line WL1 is formed that is electrically connected to the first gate 11 and extends along the first direction (for example, the X direction).

[0286] In step S50, refer to Figure 1 and FIGS. 22(a), 22(b), 22(c) and 22(d), and form a write bit line BL1 on a side of the first semiconductor layer 21 away from the connection portion A.

[0287] In step S60, refer to Figure 1 and Figures 23(a) to 23(d) , etch the stacked structure D to expose a circumferential surface of the third source / drain 221; form a read word line WL2 that covers the circumferential surface of the third source / drain 221 and extends in a direction perpendicular to the substrate 1.

[0288] In some embodiments, step S60 includes steps S61 to S65.

[0289] In step S61, refer to Figure 1 and FIGS. 23(a), 23(b), 23(c) and 23(d), and etch a third conductive material layer L13 between the pre-set trenches C3 adjacent to the read transistor T in a first direction (e.g., the X direction) to form a sixth etch hole K6. The sixth etch hole K6 exposes a sidewall of the third source / drain 221. R Exemplarily, a dry etching process may be used to form the sixth etch hole K6.

[0290] In step S62, refer to

[0291] and FIGS. 24(a), 24(b), 24(c) and 24(d), and based on the sixth etch hole K6, etch each first insulating material layer L21 to expose the circumferential surface of the third source / drain 221. Figure 1 Exemplarily, a wet etching process may be used to etch each first insulating material layer L21 to expose the circumferential surface of the third source / drain 221.

[0292] In step S63, refer to

[0293] and FIGS. 25(a), 25(b), 25(c) and 25(d), and fill a fifth conductive material layer L15 in the etched regions of the sixth etch hole K6 and the first insulating material layer L21. Figure 1 Exemplarily, the fifth conductive material layer L15 includes a metal layer, such as a tungsten metal layer.

[0294] In step S64, refer to

[0295] and FIGS. 26(a), 26(b), 26(c) and 26(d), and etch the fifth conductive material layer L15 to form a read word line isolation hole KR, and make the remaining fifth conductive material layer L15 form a read word line WL2. Figure 1

[0296] ​Exemplarily, a dry etching process can be used to form the read word line isolation hole KR.

[0297] In step S65, refer to Figure 1 and FIGS. 27(a), 27(b), 27(c) and 27(d), and fill the third insulating material layer L23 into the read word line isolation hole KR.

[0298] Exemplarily, the third insulating material L23 includes, but is not limited to, a silicon oxide layer.

[0299] In some other embodiments, refer to Figure 1 and Figures 28(a) to 36(d) , the patterning of the semiconductor material layer L20, the dielectric material layer L40 and the second conductive material layer L12 in step S30 includes steps S31’ to S39’.

[0300] In step S31’, refer to Figure 1 and FIGS. 28(a), 28(b), 28(c) and 28(d), and form seventh etching holes K7 on opposite sides of the write word line WL1 pre-set groove C2 along the first direction (e.g., the X direction), and form the first gate 11 with the second conductive material layer L12 remaining in the write word line WL1 pre-set groove C2. The seventh etching holes K7 are located in the region between adjacent connection parts A in the first direction (e.g., the X direction), and the seventh etching holes K7 expose part of the side walls of the first gate 11.

[0301] In the embodiments of the present application, by forming the first gate 11 with the second conductive material layer L12 remaining in the write word line WL1 pre-set groove C2, the width of the first gate 11 can be reduced, thereby reducing the loss of the semiconductor material layer L20 in subsequent wet etching.

[0302] Exemplarily, a dry etching process can be used to form the seventh etching holes K7.

[0303] In step S32’, refer to Figure 1 and FIGS. 29(a), 29(b), 29(c) and 29(d), based on the seventh etching holes K7, wet etch the semiconductor material layer L20 and the dielectric material layer L40, and form the first semiconductor layer 21 and the first dielectric layer 41 corresponding to the semiconductor material layer L20 and the dielectric material layer L40 remaining in the write word line WL1 pre-set groove C2.

[0304] Here, the write transistor T W includes the first semiconductor layer 21, the first dielectric layer 41 and the fourth source / drain 222.

[0305] In step S33’, refer to Figure 1Refer to FIGS. 30(a), 30(b), 30(c) and 30(d). Fill the fourth insulating material layer L24 in the etching regions of the seventh etching hole K7, the semiconductor material layer L20 and the dielectric material layer L40.

[0306] Exemplarily, the fourth insulating material L24 includes, but is not limited to, a silicon oxide layer.

[0307] In step S34’, refer to Figure 1 Refer to FIGS. 31(a), 31(b), 31(c) and 31(d). Etch the semiconductor material layer L20, the dielectric material layer L40, the second conductive material layer L12 and the fourth insulating material layer L24 in the third etching hole K3 to form the eighth etching hole K8.

[0308] In step S35’, refer to Figure 1 Refer to FIGS. 32(a), 32(b), 32(c) and 32(d). Based on the eighth etching hole K8, etch the semiconductor material layer L20, the dielectric material layer L40 and the second conductive material layer L12 in the preset groove C3 near the connection portion A along the first direction (e.g., the X direction), and correspondingly form the initial second semiconductor layer 220, the initial second dielectric layer 420, the initial extension portion B0 and the second gap J2 located between the initial extension portion B0 and the connection portion A. R Exemplarily, the second gap J2 can be formed by a wet etching process.

[0309] In step S36’, refer to

[0310] Refer to FIGS. 33(a), 33(b), 33(c) and 33(d). Fill the sixth conductive material layer L16 in the eighth etching hole K8 and the second gap J2. The sixth conductive material layer L16 in the second gap J2 and the initial extension portion B0 together constitute the extension portion B. Wherein, the second gate 12 includes the connection portion A and the extension portion B. Figure 1 Here, the extension portion B is electrically connected to the connection portion A and extends along the second direction (e.g., the Y direction).

[0311] Exemplarily, the sixth conductive material layer L16 includes a metal layer, such as a tungsten metal layer.

[0312] In step S37’, refer to

[0313] Refer to FIGS. 34(a), 34(b), 34(c) and 34(d). Remove the sixth conductive material layer L16 in the eighth etching hole K8. Figure 1 In step S38’, refer to

[0314] In step S38’, refer to Figure 1With reference to FIGS. 35(a), 35(b), 35(c) and 35(d), based on the eighth etching hole K8, the first insulating material layer L21, the initial second semiconductor layer 220 and the initial second dielectric layer 420 are wet-etched to form the second semiconductor layer 22 and the second dielectric layer 42 corresponding to the initial second semiconductor layer 220 and the initial second dielectric layer 420. Among them, the second semiconductor layer 22 includes a third source / drain 221 surrounding the circumferential direction of the extension portion B, and a fourth source / drain 222 electrically connecting the third source / drain 221 and the read bit line BL2.

[0315] Here, the write transistor T W includes the first semiconductor layer 21, the first dielectric layer 41 and the fourth source / drain 222.

[0316] In step S39’, please refer to Figure 1 and FIGS. 36(a), 36(b), 36(c) and 36(d), and fill the etching regions of the eighth etching hole K8, the first insulating material layer L21, the initial second semiconductor layer 220 and the initial second dielectric layer 420 with the fifth insulating material layer L25.

[0317] Exemplarily, the fifth insulating material layer L25 includes, but is not limited to, a silicon oxide layer.

[0318] In step S40, please refer to Figure 1 and FIGS. 36(a), 36(b), 36(c) and 36(d), and form a writing line WL1 electrically connected to the first gate 11 and extending along the first direction (e.g., the X direction).

[0319] In step S50, please refer to Figure 1 and FIGS. 36(a), 36(b), 36(c) and 36(d), and form a write bit line BL1 on the side of the first semiconductor layer 21 away from the connection portion A.

[0320] In step S60, please refer to Figure 1 and Figures 37(a) to 41(d) , etch the stacked structure D to expose the circumferential surface of the third source / drain 221; form a read word line WL2 covering the circumferential surface of the third source / drain 221 and extending along the direction perpendicular to the substrate 1.

[0321] In some embodiments, step S60 includes steps S61 to S65.

[0322] In step S61, please refer to Figure 1 and FIGS. 37(a), 37(b), 37(c) and 37(d), and etch the read transistors T adjacent along the first direction (e.g., the X direction) RA third conductive material layer L13 is formed between the preset grooves C3, forming a sixth etching hole K6. The sixth etching hole K6 exposes the sidewalls of the third source / drain 221.

[0323] Exemplarily, a dry etching process may be employed to form the sixth etching hole K6.

[0324] In step S62, please refer to Figure 1 and FIGS. 38(a), 38(b), 38(c), and 38(d). Based on the sixth etching hole K6, each first insulating material layer L21 is etched to expose the circumferential surface of the third source / drain 221.

[0325] Exemplarily, a wet etching process may be employed to etch each first insulating material layer L21 to expose the circumferential surface of the third source / drain 221.

[0326] In step S63, please refer to Figure 1 and FIGS. 39(a), 39(b), 39(c), and 39(d). A fifth conductive material layer L15 is filled in the etching regions of the sixth etching hole K6 and the first insulating material layer L21.

[0327] Exemplarily, the fifth conductive material layer L15 includes a metal layer, such as a tungsten metal layer.

[0328] In step S64, please refer to Figure 1 and FIGS. 40(a), 40(b), 40(c), and 40(d). The fifth conductive material layer L15 is etched to form a read word line isolation hole KR, and the remaining fifth conductive material layer L15 forms a read word line WL2.

[0329] Exemplarily, a dry etching process may be employed to form the read word line isolation hole KR.

[0330] In step S65, please refer to Figure 1 and FIGS. 41(a), 41(b), 41(c), and 41(d). A third insulating material layer L23 is filled in the read word line isolation hole KR.

[0331] Exemplarily, the third insulating material L23 includes, but is not limited to, a silicon oxide layer.

[0332] In some embodiments, please refer to Figure 7 and in combination with Figures 8(a) to 22(d) it is understood that step S11 forms a write transistor T W , and further includes steps S101 to S111.

[0333] S101: Provide a substrate, and form a stacked structure on the substrate; the stacked structure includes a plurality of first conductive material layers and a plurality of first insulating material layers alternately stacked in a direction perpendicular to the substrate.

[0334] S102: Etch the stacked structure along the direction perpendicular to the substrate to form at least one first etching groove penetrating the stacked structure; the first etching groove extends along a first direction.

[0335] S103: Based on the first etching groove, etch the corresponding sidewalls of each first conductive material layer to form writing line pre - setting grooves.

[0336] S104: Fill the sacrificial material in the first etching groove and the removal area of the first conductive material layer.

[0337] S105: Remove the sacrificial material in the first etching groove.

[0338] S106: Fill the third conductive material layer in the first etching groove.

[0339] S107: Etch the third conductive material layer to form a second etching hole exposing the sacrificial material in the writing line pre - setting groove.

[0340] S108: Based on the second etching hole, remove the remaining sacrificial material, and sequentially deposit a semiconductor material layer, a dielectric material layer, and a second conductive material layer in the removal area of the remaining sacrificial material.

[0341] S109: Form fifth etching holes on opposite sides of the writing line pre - setting groove along the first direction, and make the second conductive material layer remaining in the writing line pre - setting groove form a first gate; the fifth etching holes are located in the area between adjacent connection parts in the first direction, and the fifth etching holes expose part of the sidewalls of the first gate.

[0342] S110: Based on the fifth etching holes, wet - etch the first insulating material layer, the semiconductor material layer, and the dielectric material layer, and make the semiconductor material layer and the dielectric material layer remaining in the writing line pre - setting groove respectively form a first semiconductor layer and a first dielectric layer.

[0343] S111: Fill the second insulating material layer in the fifth etching holes and the etching areas of the first insulating material layer, the semiconductor material layer, and the dielectric material layer.

[0344] In some embodiments, please refer to Figure 7 and combine with Figures 8(a) to 22(d) to understand that step S12 forms the read transistor T R , and further includes steps S201 - S213.

[0345] S201: Provide a substrate, and form a stacked structure on the substrate; the stacked structure includes multiple layers of first conductive material layers and multiple layers of first insulating material layers stacked alternately along the direction perpendicular to the substrate.

[0346] S202: Etch the stacked structure along the direction perpendicular to the substrate to form a plurality of first etching holes penetrating the stacked structure; the plurality of first etching holes are arranged at intervals along the first direction.

[0347] S203: Based on the first etching holes, etch the corresponding sidewalls of each first conductive material layer to form read transistor preset grooves, and make the remaining first conductive material layer form the connection part of the second gate.

[0348] S204: Fill the sacrificial material in the removal areas of the first etching holes and the first conductive material layer.

[0349] S205: Remove the sacrificial material between the adjacent read transistor preset grooves in the first direction.

[0350] S206: Fill the third conductive material layer in the removal area of the sacrificial material.

[0351] S207: Etch the third conductive material layer to form a third etching hole exposing the sacrificial material in the read transistor preset groove.

[0352] S208: Remove the remaining sacrificial material based on the third etching hole, and sequentially deposit a semiconductor material layer, a dielectric material layer, and a second conductive material layer in the removal area of the remaining sacrificial material.

[0353] S209: Etch the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the third etching hole to form a fourth etching hole.

[0354] S210: Based on the fourth etching hole, etch the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the read transistor preset groove close to the connection part along the first direction, and correspondingly form an initial second semiconductor layer, an initial second dielectric layer, an initial extension part, and a first interval between the initial extension part and the connection part.

[0355] S211: Fill the fourth conductive material layer in the fourth etching hole and the first interval; the fourth conductive material layer in the first interval and the initial extension part together form an extension part.

[0356] S212: Form a fifth etching hole to correspondingly form a second semiconductor layer and a second dielectric layer for the initial second semiconductor layer and the initial second dielectric layer; the fifth etching hole is located in the area between the connection parts adjacent in the first direction.

[0357] S213: Fill the second insulating material layer in the fifth etching hole and the etching areas of the first insulating material layer, the semiconductor material layer, and the dielectric material layer.

[0358] In some embodiments, please refer to Figure 7 and combine with Figures 8(a) to 16(d) and Figures 23(a) to 36(d)Understand that forming a read transistor further includes S201’ to S216’.

[0359] S201’: Provide a substrate and form a stacked structure on the substrate; the stacked structure includes multiple layers of first conductive material layers and multiple layers of first insulating material layers alternately stacked in a direction perpendicular to the substrate.

[0360] S202’: Etch the stacked structure in a direction perpendicular to the substrate to form multiple first etching holes penetrating the stacked structure; the multiple first etching holes are arranged at intervals in a first direction.

[0361] S203’: Based on the first etching holes, etch the corresponding sidewalls of each first conductive material layer to form a pre-set groove for the read transistor, and make the remaining first conductive material layer form a connection part of the second gate.

[0362] S204’: Fill a sacrificial material in the first etching holes and the removal area of the first conductive material layer.

[0363] S205’: Remove the sacrificial material between adjacent pre-set grooves for the read transistor in the first direction.

[0364] S206’: Fill a third conductive material layer in the removal area of the sacrificial material.

[0365] S207’: Etch the third conductive material layer to form a third etching hole exposing the sacrificial material in the pre-set groove for the read transistor.

[0366] S208’: Based on the third etching hole, remove the remaining sacrificial material, and sequentially deposit a semiconductor material layer, a dielectric material layer, and a second conductive material layer in the removal area of the remaining sacrificial material.

[0367] S209’: Form a seventh etching hole in the area between the connection parts adjacent in the first direction.

[0368] S210’: Fill a fourth insulating material layer in the seventh etching hole.

[0369] S211’: Etch the semiconductor material layer, the dielectric material layer, the second conductive material layer, and the fourth insulating material layer in the third etching hole to form an eighth etching hole.

[0370] S212’: Based on the eighth etching hole, etch the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the pre-set groove for the read transistor close to the connection part in the first direction, and correspondingly form an initial second semiconductor layer, an initial second dielectric layer, an initial extension part, and a second interval between the initial extension part and the connection part.

[0371] S213’: Fill a sixth conductive material layer in the eighth etching hole and the second spacer; the sixth conductive material layer in the second spacer and the initial extension portion together form an extension portion.

[0372] S214’: Remove the sixth conductive material layer in the eighth etching hole.

[0373] S215’: Based on the eighth etching hole, wet-etch the first insulating material layer, the initial second semiconductor layer, and the initial second dielectric layer, so that the initial second semiconductor layer and the initial second dielectric layer correspondingly form a second semiconductor layer and a second dielectric layer.

[0374] S216’: Fill a fifth insulating material layer in the eighth etching hole and the etching regions of the first insulating material layer, the initial second semiconductor layer, and the initial second dielectric layer.

[0375] Some embodiments of the present disclosure also provide an electronic device, such as a data storage device, a photocopier, a network device, a household appliance, an instrument, a mobile phone, a computer, and other devices with data storage functions. The electronic device may include a housing, a circuit board disposed in the housing, and a memory integrated on the circuit board. The structure of the memory may refer to the relevant descriptions in the above-mentioned some embodiments. Other necessary elements or components may also be included in the electronic device, which are not limited in the embodiments of the present disclosure.

[0376] In some embodiments, an external control device such as a processor or an actuator coupled to the memory may also be integrated on the circuit board. For example, the electronic device further includes a processor integrated on the circuit board. The processor is coupled to the memory, and the processor can control the read and write operations of the memory.

[0377] In some embodiments, the memory is a 3D-DRAM.

[0378] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0379] The above-described embodiments only represent several implementation manners of the present disclosure. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: a substrate, and at least one memory cell disposed on the substrate; the memory cell includes: a write transistor and a read transistor arranged along a direction parallel to the substrate; the write transistor includes a first gate and a first semiconductor layer; the read transistor includes a second gate and a second semiconductor layer; wherein, the first gate extends along a first direction parallel to the substrate; the first semiconductor layer at least partially and insulatingly surrounds the circumference of the first gate, and the first semiconductor layer includes a first source / drain and a second source / drain oppositely disposed in a second direction; the second direction is parallel to the substrate and intersects the first direction; the second gate is located on a side of the first semiconductor layer away from the first gate, and includes a connection portion electrically connected to the first semiconductor layer, and an extension portion located on a side of the connection portion away from the first semiconductor layer and extending along the second direction; the second semiconductor layer includes a third source / drain at least partially and insulatingly surrounding the circumference of the extension portion, and a fourth source / drain insulatingly covering an end face of the extension portion.

2. The semiconductor structure according to claim 1, wherein It further includes a second channel, and the third source / drain, the fourth source / drain and the second channel are integrally connected.

3. The semiconductor structure according to claim 1, wherein The dimension of the connection portion in a direction perpendicular to the substrate is greater than the dimension of at least a part of the extension portion in a direction perpendicular to the substrate.

4. A memory, characterized in that, Comprising: the semiconductor structure according to any one of claims 1 to 3, and a write word line, a write bit line, a read word line and a read bit line; the write word line is electrically connected to the first gate; the write bit line is located on a side of the first semiconductor layer away from the connection portion and is electrically connected to the first semiconductor layer; the read word line at least partially surrounds the third source / drain and is electrically connected to the third source / drain; the read bit line is located on a side of the fourth source / drain away from the second gate and is electrically connected to the fourth source / drain and is insulated from the write bit line.

5. The memory according to claim 4, characterized in that, The write word line and the read bit line extend along the first direction, and the write bit line and the read word line extend along a direction perpendicular to the substrate respectively.

6. The memory according to claim 5, characterized in that, The read bit line and the connection portion of the second gate are patterns of the same conductive layer in different regions and are insulated from each other.

7. A manufacturing method of a memory, characterized in that, Comprising: providing a substrate, and forming one or more memory cells on the substrate; wherein, forming the memory cell includes: forming a write transistor; the write transistor includes a first gate and a first semiconductor layer; the first gate extends along a first direction parallel to the substrate; the first semiconductor layer at least partially and insulatingly surrounds the circumference of the first gate, and the first semiconductor layer includes a first source / drain and a second source / drain oppositely disposed in a second direction; the second direction is parallel to the substrate and intersects the first direction; Form a read transistor; the read transistor includes a second gate and a second semiconductor layer; the second gate is located on a side of the first semiconductor layer away from the first gate, and includes a connection portion electrically connected to the first semiconductor layer, and an extension portion located on a side of the connection portion away from the first semiconductor layer and extending in a second direction; the second semiconductor layer includes at least a part of a third source / drain insulatingly surrounding the circumference of the extension portion, and a fourth source / drain insulatingly covering an end face of the extension portion; The method for manufacturing the memory further includes: Form a write word line electrically connected to the first gate; Form a write bit line electrically connected to the first semiconductor layer; Form a read word line electrically connected to the third source / drain; Form a read bit line electrically connected to the fourth source / drain.

8. The manufacturing method of the memory according to claim 7, characterized in that, Forming the memory cell, the write word line, the write bit line, the read word line, and the read bit line further includes: Provide a substrate, and form a stacked structure on the substrate; the stacked structure includes multiple layers of first conductive material layers and multiple layers of first insulating material layers alternately stacked in a direction perpendicular to the substrate; Etch the stacked structure to form a write word line preformed groove and a read transistor preformed groove in the first conductive material layer, and make the remaining first conductive material layer form the connection portion of the read bit line and the second gate respectively; wherein, the write word line preformed groove extends in a first direction, the connection portion is located between the write word line preformed groove and the read transistor preformed groove, and the read bit line is located on a side of the read transistor preformed groove away from the connection portion in the second direction; the second direction and the first direction are parallel to the substrate and intersect; Deposit a semiconductor material layer, a dielectric material layer, and a second conductive material layer in sequence in the write word line preformed groove and the read transistor preformed groove, and pattern the semiconductor material layer, the dielectric material layer, and the second conductive material layer, so that the second conductive material layer, the dielectric material layer, and the semiconductor material layer remaining in the write word line preformed groove form the first gate and a first dielectric layer and a first semiconductor layer sequentially surrounding the circumference of the first gate, and the second conductive material layer, the dielectric material layer, and the semiconductor material layer remaining in the read transistor preformed groove form the extension portion of the second gate and a second dielectric layer and a second semiconductor layer sequentially covering the extension portion; the extension portion is electrically connected to the connection portion and extends in the second direction; the second semiconductor layer includes a third source / drain surrounding the circumference of the extension portion, and a fourth source / drain electrically connecting the third source / drain and the read bit line; Form a write word line electrically connected to the first gate and extending in the first direction; Form a write bit line on a side of the first semiconductor layer away from the connection portion; the write bit line extends in the direction perpendicular to the substrate; Etch the stacked structure to expose a circumferential surface of the third source / drain; Form a read word line covering the circumferential surface of the third source / drain and extending in a direction perpendicular to the substrate.

9. The manufacturing method of the memory according to claim 8, wherein, Etching the stacked structure to form a writing line pre - groove and a read transistor pre - groove in the first conductive material layer, and enabling the remaining first conductive material layer to form connection portions of the read bit line and the second gate respectively, includes: Etching the stacked structure in a direction perpendicular to the substrate to form at least one first etching groove and a plurality of first etching holes penetrating the stacked structure; the first etching groove extends along the first direction; the plurality of first etching holes are distributed on both sides of the corresponding first etching groove and are arranged at intervals along the first direction; Based on the first etching groove and the first etching holes, etching the corresponding side walls of each first conductive material layer to form the writing line pre - groove and the read transistor pre - groove, and enabling the remaining first conductive material layer to form the read bit line and the connection portions respectively.

10. The manufacturing method of the memory according to claim 8, characterized in that, Before sequentially depositing a semiconductor material layer, a dielectric material layer, and a second conductive material layer in the writing line pre - groove and the read transistor pre - groove, the manufacturing method further includes: Filling a sacrificial material in the first etching groove, the first etching holes, and the removal area of the first conductive material layer; Removing the sacrificial material in the first etching groove and between the read transistor pre - grooves adjacent in the first direction; Filling a third conductive material layer in the removal area of the sacrificial material; Etching the third conductive material layer to form a second etching hole exposing the sacrificial material in the writing line pre - groove and a third etching hole exposing the sacrificial material in the read transistor pre - groove; Based on the second etching hole and the third etching hole, removing the remaining sacrificial material to sequentially deposit the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the removal area of the remaining sacrificial material.

11. The manufacturing method of the memory according to claim 10, characterized in that, The sacrificial material includes a spin - on dielectric or a hard mask material.

12. The manufacturing method of the memory according to claim 10, characterized in that, Patterning the semiconductor material layer, the dielectric material layer, and the second conductive material layer includes: Etching the third etching hole, and the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the third etching hole to form a fourth etching hole; Based on the fourth etching hole, etching the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the read transistor pre - groove near the connection portion along the first direction to correspondingly form an initial second semiconductor layer, an initial second dielectric layer, an initial extension portion, and a first gap between the initial extension portion and the connection portion; Filling a fourth conductive material layer in the fourth etching hole and the first gap; the fourth conductive material layer in the first gap and the initial extension portion together constitute the extension portion; Forming fifth etching holes on opposite sides of the writing line pre - groove along the first direction, and enabling the second conductive material layer remaining in the writing line pre - groove to form the first gate; the fifth etching holes are located in the area between the connection portions adjacent in the first direction, and the fifth etching holes expose part of the side wall of the first gate; Based on the fifth etching hole, wet-etch the first insulating material layer, the semiconductor material layer, and the dielectric material layer, and enable the semiconductor material layer and the dielectric material layer retained in the write line pre-set groove to correspondingly form the first semiconductor layer and the first dielectric layer. At the same time, enable the initial second semiconductor layer and the initial second dielectric layer to correspondingly form the second semiconductor layer and the second dielectric layer; Fill the fifth etching hole and the etching regions of the first insulating material layer, the semiconductor material layer, and the dielectric material layer with a second insulating material layer.

13. The manufacturing method of the memory according to claim 10, characterized in that, The patterning of the semiconductor material layer, the dielectric material layer, and the second conductive material layer includes: Form seventh etching holes on opposite sides of the write line pre-set groove along the first direction, and enable the second conductive material layer retained in the write line pre-set groove to form the first gate; the seventh etching holes are located in the region between the adjacent connection parts in the first direction, and the seventh etching holes expose partial side walls of the first gate; Based on the seventh etching hole, wet-etch the semiconductor material layer and the dielectric material layer, and enable the semiconductor material layer and the dielectric material layer retained in the write line pre-set groove to correspondingly form the first semiconductor layer and the first dielectric layer; Fill the seventh etching hole and the etching regions of the semiconductor material layer and the dielectric material layer with a fourth insulating material layer; Etch the semiconductor material layer, the dielectric material layer, the second conductive material layer, and the fourth insulating material layer in the third etching hole to form an eighth etching hole; Based on the eighth etching hole, etch the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the read transistor pre-set groove near the connection part along the first direction, and correspondingly form an initial second semiconductor layer, an initial second dielectric layer, an initial extension part, and a second gap located between the initial extension part and the connection part; Fill the eighth etching hole and the second gap with a sixth conductive material layer; the sixth conductive material layer in the second gap and the initial extension part together constitute the extension part; Remove the sixth conductive material layer in the eighth etching hole; Based on the eighth etching hole, wet-etch the first insulating material layer, the initial second semiconductor layer, and the initial second dielectric layer, so that the initial second semiconductor layer and the initial second dielectric layer correspondingly form the second semiconductor layer and the second dielectric layer; Fill the eighth etching hole and the etching regions of the first insulating material layer, the initial second semiconductor layer, and the initial second dielectric layer with a fifth insulating material layer.

14. The manufacturing method of the memory according to claim 12 or 13, characterized in that, The etching of the stacked structure to expose the circumferential surface of the third source / drain and form a read word line that covers the circumferential surface of the third source / drain and extends in the direction perpendicular to the substrate includes: Etch the third conductive material layer between the read transistor pre-set grooves adjacent to each other along the first direction to form a sixth etching hole; the sixth etching hole exposes the side wall of the third source / drain; Based on the sixth etching hole, etch each of the first insulating material layers to expose the circumferential surface of the third source / drain; Fill the sixth etching hole and the etching area of the first insulating material layer with a fifth conductive material layer; Etch the fifth conductive material layer to form a read word line isolation hole, and make the remaining fifth conductive material layer form the read word line; Fill the read word line isolation hole with a third insulating material layer.

15. The manufacturing method of the memory according to claim 7, wherein, The forming of the write transistor further includes: Provide a substrate, and form a stacked structure on the substrate; the stacked structure includes multiple layers of first conductive material layers and multiple layers of first insulating material layers alternately stacked in a direction perpendicular to the substrate; Etch the stacked structure in a direction perpendicular to the substrate to form at least one first etching groove penetrating the stacked structure; the first etching groove extends along the first direction; Based on the first etching groove, etch the corresponding sidewalls of each of the first conductive material layers to form the write word line pre-set groove; Fill the first etching groove and the removal area of the first conductive material layer with a sacrificial material; Remove the sacrificial material in the first etching groove; Fill the first etching groove with a third conductive material layer; Etch the third conductive material layer to form a second etching hole exposing the sacrificial material in the write word line pre-set groove; Based on the second etching hole, remove the remaining sacrificial material, and sequentially deposit the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the removal area of the remaining sacrificial material; Form fifth etching holes on opposite sides of the write word line pre-set groove along the first direction, and make the second conductive material layer remaining in the write word line pre-set groove form the first gate; the fifth etching hole is located in the area between the adjacent connection parts in the first direction, and the fifth etching hole exposes part of the sidewall of the first gate; Based on the fifth etching hole, wet-etch the first insulating material layer, the semiconductor material layer, and the dielectric material layer, and make the semiconductor material layer and the dielectric material layer remaining in the write word line pre-set groove correspondingly form the first semiconductor layer and the first dielectric layer; Fill the fifth etching hole and the etching areas of the first insulating material layer, the semiconductor material layer, and the dielectric material layer with a second insulating material layer.

16. The manufacturing method of the memory according to claim 7, characterized in that, The forming of the read transistor further includes: Provide a substrate, and form a stacked structure on the substrate; the stacked structure includes multiple layers of first conductive material layers and multiple layers of first insulating material layers alternately stacked in a direction perpendicular to the substrate; Etch the stacked structure in a direction perpendicular to the substrate to form a plurality of first etching holes penetrating the stacked structure; the plurality of first etching holes are arranged at intervals along the first direction; Based on the first etching hole, etch the corresponding sidewalls of each of the first conductive material layers to form the read transistor pre-set groove, and make the remaining first conductive material layer form the connection part of the second gate; Fill the first etching hole and the removal area of the first conductive material layer with a sacrificial material; Remove the sacrificial material between the adjacent read transistor pre-set grooves in the first direction; Fill a third conductive material layer in the removal area of the sacrificial material; Etch the third conductive material layer to form a third etch hole exposing the sacrificial material in the read transistor preset groove; Remove the remaining sacrificial material based on the third etch hole, and sequentially deposit the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the removal area where the sacrificial material remains; Etch the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the third etch hole to form a fourth etch hole; Based on the fourth etch hole, etch the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the read transistor preset groove near the connection portion along the first direction, and correspondingly form an initial second semiconductor layer, an initial second dielectric layer, an initial extension portion, and a first gap between the initial extension portion and the connection portion; Fill a fourth conductive material layer in the fourth etch hole and the first gap; the fourth conductive material layer in the first gap and the initial extension portion together constitute the extension portion; Form a fifth etch hole to correspondingly form the second semiconductor layer and the second dielectric layer for the initial second semiconductor layer and the initial second dielectric layer; the fifth etch hole is located in the area between the connection portions adjacent in the first direction; Fill a second insulating material layer in the fifth etch hole and the etched areas of the first insulating material layer, the semiconductor material layer, and the dielectric material layer.

17. The manufacturing method of the memory according to claim 7, characterized in that, The forming of the read transistor further includes: Provide a substrate and form a stacked structure on the substrate; the stacked structure includes multiple layers of first conductive material layers and multiple layers of first insulating material layers alternately stacked in a direction perpendicular to the substrate; Etch the stacked structure in a direction perpendicular to the substrate to form a plurality of first etch holes penetrating the stacked structure; the plurality of first etch holes are arranged at intervals along the first direction; Based on the first etch hole, etch the corresponding sidewalls of each first conductive material layer to form the read transistor preset groove, and make the remaining first conductive material layer form the connection portion of the second gate; Fill a sacrificial material in the first etch hole and the removal area of the first conductive material layer; Remove the sacrificial material between the read transistor preset grooves adjacent in the first direction; Fill a third conductive material layer in the removal area of the sacrificial material; Etch the third conductive material layer to form a third etch hole exposing the sacrificial material in the read transistor preset groove; Remove the remaining sacrificial material based on the third etch hole, and sequentially deposit the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the removal area where the sacrificial material remains; Form a seventh etch hole, and the seventh etch hole is located in the area between the connection portions adjacent in the first direction; Fill a fourth insulating material layer in the seventh etch hole; Etch the semiconductor material layer, the dielectric material layer, the second conductive material layer, and the fourth insulating material layer in the third etch hole to form an eighth etch hole; Based on the eighth etching hole, etch the semiconductor material layer, the dielectric material layer, and the second conductive material layer in the read transistor preset groove near the connection portion along the first direction, and correspondingly form an initial second semiconductor layer, an initial second dielectric layer, an initial extension portion, and a second interval between the initial extension portion and the connection portion; Fill a sixth conductive material layer in the eighth etching hole and the second interval; the sixth conductive material layer in the second interval and the initial extension portion together constitute the extension portion; Remove the sixth conductive material layer in the eighth etching hole; Based on the eighth etching hole, wet-etch the first insulating material layer, the initial second semiconductor layer, and the initial second dielectric layer, so that the initial second semiconductor layer and the initial second dielectric layer correspondingly form the second semiconductor layer and the second dielectric layer; Fill a fifth insulating material layer in the eighth etching hole and the etching regions of the first insulating material layer, the initial second semiconductor layer, and the initial second dielectric layer.

18. An electronic device, characterized in that, Comprising: The memory according to any one of claims 4 to 6.

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