Semiconductor structure, memory and manufacturing method thereof, and electronic equipment

Abstract

The invention relates to a semiconductor structure, a memory and a manufacturing method thereof, and electronic equipment. The semiconductor structure comprises a substrate, and a first grid electrode, a first semiconductor layer, a first grid electrode insulating layer, a second grid electrode, a second semiconductor layer and a second grid electrode insulating layer which are positioned on the substrate, wherein the first grid electrode extends along a first direction parallel to the substrate, the first semiconductor layer is arranged on the circumferential side wall of the first grid electrode in a surrounding manner, and the first grid electrode insulating layer is located between the first grid electrode and the first semiconductor layer; the second gate extends along a third direction perpendicular to the substrate, the second semiconductor layer is arranged around the circumferential side wall of the second gate, and the second gate insulating layer is located between the second gate and the second semiconductor layer; in the first direction, the second gate is located on one side of the first gate, and one side of the first gate close to the second gate contacts one side of the second semiconductor layer close to the first gate. The device provided by the invention does not have a parasitic MOS problem and is simple in manufacturing process.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, semiconductor technology, and particularly to a semiconductor structure, a memory and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly, making any minor difference in the process production likely to affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements of current products. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of the present application.

[0005] In one aspect, an exemplary embodiment of the present application provides a semiconductor structure, including a substrate, and a first gate, a first semiconductor layer, a first gate insulating layer, a second gate, a second semiconductor layer, and a second gate insulating layer located on the substrate;

[0006] Wherein, the first gate extends along a first direction parallel to the substrate, the first semiconductor layer is disposed around a circumferential sidewall of the first gate, and the first gate insulating layer is located between the first gate and the first semiconductor layer;

[0007] The second gate extends along a third direction perpendicular to the substrate, the second semiconductor layer is disposed around a circumferential sidewall of the second gate, and the second gate insulating layer is located between the second gate and the second semiconductor layer;

[0008] Along the first direction, the second gate is located on one side of the first gate, and a side of the first gate close to the second gate is in contact with a side of the second semiconductor layer close to the first gate.

[0009] In an exemplary embodiment, it further includes a first bit line and a second bit line extending along a second direction parallel to the substrate and a first word line and a second word line extending along the third direction, and the second direction intersects with the first direction;

[0010] Wherein, along the first direction, the first bit line is located on a side of the first gate away from the second gate and contacts the first semiconductor layer; along the first direction, the second bit line is located on a side of the second gate away from the first gate and contacts the second semiconductor layer;

[0011] Along the second direction, the first word line is located on a side of the first gate and contacts the first semiconductor layer; along the third direction, the second gate is a part of the second word line.

[0012] In an exemplary embodiment, a read transistor and a write transistor are included;

[0013] The read transistor includes the first gate, the first semiconductor layer, a first source / drain, and a second source / drain; the first source / drain is connected to the first bit line and the first semiconductor layer, and the second source / drain is connected to the first word line and the first semiconductor layer;

[0014] The write transistor includes the second gate, the second semiconductor layer, a third source / drain, and a fourth source / drain; the third source / drain and the fourth source / drain are located on two sides of the second semiconductor layer in the first direction and are respectively connected to the second semiconductor layer, and the fourth source / drain is connected to the second bit line;

[0015] The first gate is connected to the third source / drain.

[0016] In an exemplary embodiment, a first gate barrier layer is further included, and the first gate barrier layer is disposed around a circumferential sidewall of an end of the first gate close to the second gate and is located between the first semiconductor layer and the second semiconductor layer.

[0017] In another aspect, an exemplary embodiment of the present application provides a memory, including a substrate, a stacked structure located on the substrate, a plurality of first bit lines and second bit lines extending along a second direction parallel to the substrate, and a plurality of first word lines and second word lines extending along a third direction perpendicular to the substrate and passing through the stacked structure;

[0018] The stacked structure includes a plurality of storage units stacked along the third direction, and the storage unit includes a first gate, a first gate insulating layer, a first semiconductor layer, a second gate, a second gate insulating layer, and a second semiconductor layer;

[0019] Wherein, the first gate extends along a first direction parallel to the substrate, the first semiconductor layer surrounds the first gate, and the first gate insulating layer surrounds the first gate and is located between the first gate and the first semiconductor layer;

[0020] The second gate extends along the third direction. The second semiconductor layer surrounds the second gate and is discontinuously arranged in the third direction. The second gate insulating layer is located between the second gate and the second semiconductor layer;

[0021] Along the first direction, the second gate is located on one side of the first gate. The side of the first gate away from the second gate contacts the side of the second semiconductor layer close to the first gate;

[0022] The first semiconductor layers in a plurality of the memory cells arranged at intervals along the second direction are in contact with the same first bit line;

[0023] The second semiconductor layers in a plurality of the memory cells arranged at intervals along the second direction are in contact with the same second bit line;

[0024] The first semiconductor layers in a plurality of the memory cells arranged at intervals along the third direction are in contact with the same first word line;

[0025] The second gates in a plurality of the memory cells arranged at intervals along the third direction are connected to form a second word line. The first direction intersects with the second direction and both are perpendicular to the third direction.

[0026] In an exemplary embodiment, a second gate protection layer is further included. The second gate protection layer is disposed around the circumferential sidewall of the second word line and is discontinuously arranged in the third direction.

[0027] In an exemplary embodiment, the first bit line and the second bit line are located on both sides of the memory cell along the first direction. A plurality of the first bit lines are stacked and arranged at intervals along the third direction, and a plurality of the second bit lines are stacked and arranged at intervals along the third direction.

[0028] In an exemplary embodiment, the plurality of first word lines are arranged at intervals along the second direction on one side of the memory cell, and the plurality of second word lines are located on the side of the first gate away from the first bit line.

[0029] In another aspect, an exemplary embodiment of the present application provides a method for manufacturing a memory, including the following steps:

[0030] Provide a substrate;

[0031] Deposit an insulating layer and a sacrificial layer alternately on the substrate along a third direction perpendicular to the substrate to form a stacked structure including a plurality of insulating layers and sacrificial layers;

[0032] Pattern the stacked structure to form a plurality of isolation regions in the stacked structure that are spaced apart in the second direction and spaced apart in the first direction, where the first direction intersects the second direction and both are perpendicular to the third direction;

[0033] Form a first bit line trench that penetrates the stacked structure and extends along the second direction between adjacent isolation regions in the first direction to form a first bit line that extends along the second direction;

[0034] Form a first word line via hole that penetrates the stacked structure in each of the isolation regions to form a first word line that extends along the third direction;

[0035] Form a second bit line trench that penetrates the stacked structure and extends along the second direction between adjacent isolation regions in the first direction on a side of the first word line away from the first bit line;

[0036] By means of the second bit line trench, form a first gate that extends along the first direction, a first semiconductor layer that surrounds a circumferential sidewall of the first gate, and a first gate insulating layer that is located between the first gate and the first semiconductor layer in a region between adjacent isolation regions in the second direction and close to the first bit line;

[0037] Form a second gate that extends along the third direction, a second semiconductor layer that surrounds a circumferential sidewall of the second gate, and a second gate insulating layer that is located between the second gate and the second semiconductor layer between adjacent isolation regions in the second direction on a side of the second bit line trench close to the first word line via hole;

[0038] Form a second bit line that extends along the second direction by means of the second bit line trench.

[0039] In an exemplary embodiment, the forming, by means of the second bit line trench, of a first gate that extends along the first direction, a first semiconductor layer that surrounds a circumferential sidewall of the first gate, and a first gate insulating layer that is located between the first gate and the first semiconductor layer in a region between adjacent isolation regions in the second direction and close to the first bit line includes:

[0040] By means of the second bit line trench, etch and remove the material of the sacrificial layer to form a first lateral groove;

[0041] Deposit a semiconductor material thin film, an insulating material thin film, and a conductive material thin film in sequence in the second bit line trench and the first lateral groove;

[0042] Remove the semiconductor material film, insulating material film, and conductive material film in the second bit line trench, and remove a part of the semiconductor material film, insulating material film, and conductive material film in the first lateral groove to form a second lateral groove. The remaining semiconductor material film, insulating material film, and conductive material film in the first lateral groove form the first gate, the first semiconductor layer, and the first gate insulating layer.

[0043] In an exemplary embodiment, after forming the first semiconductor layer and before forming the second semiconductor layer, it further includes:

[0044] Etch laterally to remove a part of the material of the first semiconductor layer, and fill with an insulating material to form a first gate barrier layer surrounding the circumferential sidewall of the end of the first gate close to the second gate.

[0045] In an exemplary embodiment, form a first bit line trench penetrating the stacked structure and extending along the second direction between isolation regions adjacent in the first direction to form a first bit line extending along the second direction, including:

[0046] By means of the first bit line trench, etch the sacrificial layer to form a first bit line expansion groove at the sacrificial layer;

[0047] Fill the first bit line trench and the first bit line expansion groove with a conductive material,

[0048] Remove the conductive material in the first bit line trench, and retain the conductive material in the first bit line expansion groove to form a first bit line extending along the second direction.

[0049] In an exemplary embodiment, form a second bit line extending along the second direction by means of the second bit line trench, including:

[0050] Remove all the semiconductor material and conductive material in the second bit line trench, and retain the semiconductor material and conductive material in the second lateral groove; refill the second bit line trench with an insulating material to form a second bit line extending along the second direction at the second lateral groove.

[0051] In an exemplary embodiment, form a second gate extending along the third direction, a second semiconductor layer surrounding the circumferential sidewall of the second gate, and a second gate insulating layer between the second gate and the second semiconductor layer between isolation regions adjacent in the second direction on one side of the second bit line trench close to the first word line through hole, including:

[0052] Deposit an isolation material thin film and an insulating material thin film in the second bit line trench and the second lateral groove in sequence to form an isolation layer and an insulating layer;

[0053] Form a second word line through hole penetrating the stacked structure between the isolation regions adjacent in the second direction on one side of the second bit line trench close to the first word line through hole;

[0054] Deposit an isolation material thin film, an insulating material thin film, and a conductive material thin film in the second word line through hole in sequence to form a second gate extending along the third direction, a second gate insulating layer surrounding the second gate, and a second gate isolation layer surrounding the second gate insulating layer;

[0055] Remove the insulating material thin film and the isolation material thin film in the second bit line trench and the second lateral groove, and remove the material of the second gate isolation layer in the second lateral groove to expose the second gate insulating layer;

[0056] Deposit a semiconductor material thin film around the exposed second gate insulating layer in the second lateral groove, thereby forming a second semiconductor layer which is discontinuously arranged along the third direction.

[0057] In an exemplary embodiment, forming a first gate extending along the first direction, a first semiconductor layer surrounding the circumferential side wall of the first gate, and a first gate insulating layer located between the first gate and the first semiconductor layer between the isolation regions adjacent in the second direction and close to the first bit line by means of the second bit line trench includes:

[0058] Form a second word line through hole between the isolation regions adjacent in the second direction on one side of the second bit line trench close to the first word line through hole;

[0059] Laterally etch and remove the material of the sacrificial layer by means of the second bit line trench and the second word line through hole to form a first lateral groove;

[0060] Deposit a semiconductor material thin film, an insulating material thin film, and a conductive material thin film in sequence along the second bit line trench, the first lateral groove, and the second word line through hole;

[0061] Remove all the materials in the second word line through hole;

[0062] In the first lateral groove, remove a part of the semiconductor material thin film, the insulating material thin film, and the conductive material thin film to form a second lateral groove, and the remaining semiconductor material thin film, insulating material thin film, and conductive material thin film in the first lateral groove form the first gate, the first semiconductor layer, and the first gate insulating layer.

[0063] In an exemplary embodiment, on a side of the second bit line trench close to the first word line via and between isolation regions adjacent in the second direction, a second gate extending along a third direction, a second semiconductor layer disposed around a circumferential sidewall of the second gate, and a second gate insulating layer located between the second gate and the second semiconductor layer are formed, including:

[0064] Deposit a semiconductor material thin film, an insulating material thin film, and a conductive material thin film successively along the second word line via and the second lateral groove;

[0065] Remove all materials in the second word line via and retain all materials in the second lateral groove, so as to form the second semiconductor layer and the second gate insulating layer that are discontinuously disposed along the third direction in each second lateral groove;

[0066] Deposit a conductive material thin film in the second word line via to form the second gate.

[0067] In another aspect, some embodiments of the present application provide an electronic device including the memory described in any one of the above.

[0068] In some embodiments, the above electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0069] In the semiconductor structure of the present application, the bit line is in the horizontal direction and the word line is in the vertical direction, which is more conducive to enhancing the performance of the device.

[0070] The channels of the read transistor and the write transistor in the present application both adopt a wide-bandgap semiconductor material such as IGZO, which can reduce the leakage of the write transistor and increase the retention time.

[0071] The manufacturing process of the present application can more easily remove the parasitic MOS of the write transistor and the manufacturing process is simple.

[0072] Other features and advantages of the present application will be described in the subsequent specification, and, in part, will become apparent from the specification, or will be understood by implementing the present application. Other advantages of the present application can be realized and obtained through the solutions described in the specification and the drawings. Description of the Drawings

[0073] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. They are used together with the embodiments of the present application to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0074] Figure 1AA three-dimensional structure schematic diagram of a semiconductor structure provided for an exemplary embodiment of the present application;

[0075] Figure 1B A horizontal cross-sectional schematic diagram of a semiconductor structure provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate;

[0076] Figure 1C For the Figure 1B Vertical cross-sectional schematic diagram taken along the section line AA' in the structure shown;

[0077] Figure 1D For the Figure 1B Vertical cross-sectional schematic diagram taken along the section line BB' in the structure shown;

[0078] Figure 2 An equivalent circuit schematic diagram of a semiconductor structure provided for an exemplary embodiment of the present application;

[0079] Figure 3A A horizontal cross-sectional schematic diagram of a stacked structure formed in an initial step of a manufacturing method of a memory provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate (through the sacrificial layer);

[0080] Figure 3B For the Figure 3A Vertical cross-sectional schematic diagram taken along the section line AA' in the structure shown;

[0081] Figure 3C For the Figure 3A Vertical cross-sectional schematic diagram taken along the section line BB' in the structure shown;

[0082] Figure 4A A horizontal cross-sectional schematic diagram of an intermediate product formed in an intermediate step of a manufacturing method of a memory provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate (through the sacrificial layer);

[0083] Figure 4B For the Figure 4A Vertical cross-sectional schematic diagram taken along the section line AA' in the structure shown;

[0084] Figure 5A A horizontal cross-sectional schematic diagram of an intermediate product formed in an intermediate step of a manufacturing method of a memory provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate (through the insulating layer);

[0085] Figure 5B For the Figure 5A Vertical cross-sectional schematic diagram taken along the section line AA' in the structure shown;

[0086] Figure 5C A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown; Figure 5A ;

[0087] Fig. 6A A schematic horizontal cross-sectional view taken along a plane parallel to the substrate (through the insulating layer) of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0088] Figure 6B A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown; Fig. 6A ;

[0089] Figure 6C A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown; Fig. 6A ;

[0090] Fig. 7A A schematic horizontal cross-sectional view taken along a plane parallel to the substrate (through the insulating layer) of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0091] Figure 7B A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' of the formed intermediate product in the structure shown; Fig. 7A ;

[0092] Figure 7C A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown; Fig. 7A ;

[0093] Fig. 8A A schematic horizontal cross-sectional view taken along a plane parallel to the substrate (through the insulating layer) of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0094] Figure 8B A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown; Fig. 8A ;

[0095] Fig.9A A schematic horizontal cross-sectional view taken along a plane parallel to the substrate (through the insulating layer) of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0096] Fig. 9B A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown; Fig.9A ;

[0097] Fig. 9C is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown; Fig.9A ;

[0098] Fig. 10A is a schematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application, taken along a plane parallel to the substrate (through the insulating layer);

[0099] Fig. 10B is along Fig. 10A a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown;

[0100] Fig. 10C is along Fig. 10A a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown;

[0101] Fig.11A is a schematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application, taken along a plane parallel to the substrate (through the insulating layer);

[0102] Fig. 11B is along Fig.11A a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown;

[0103] Fig. 11C is along Fig.11A a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown;

[0104] Fig. 12A is a schematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application, taken along a plane parallel to the substrate (through the insulating layer);

[0105] Fig. 12B is along Fig. 12A a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown;

[0106] Fig. 12C is along Fig. 12A a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown;

[0107] Fig.13A is a schematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application, taken along a plane parallel to the substrate (through the insulating layer);

[0108] Fig. 13B is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown; Fig.13A

[0109] Fig. 13C is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown; Fig.13A

[0110] Fig.14A is a schematic horizontal cross-sectional view taken along a plane parallel to the substrate (through the insulating layer) of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0111] Fig. 14B is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown; Fig.14A

[0112] Fig.15A is a schematic horizontal cross-sectional view taken along a plane parallel to the substrate (through the insulating layer 10) of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0113] Fig. 15B is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown; Fig.15A

[0114] Fig. 15C is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown; Fig.15A

[0115] Fig.16A is a schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0116] Fig. 16B is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown; Fig.16A

[0117] Fig. 16C is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown; Fig.16A

[0118] Fig.17A is a schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0119] Fig. 17B is a schematic cross-sectional view perpendicular to the substrate taken along​​​​​​​ Fig.17A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the shown structure;

[0120] Fig. 17C For along Fig.17A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line BB' in the shown structure;

[0121] Fig.18A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0122] Fig.18B For along Fig.18A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the shown structure;

[0123] Fig.18C For along Fig.18A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line BB' in the shown structure;

[0124] Fig.19A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0125] Fig.19B For along Fig.19A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the shown structure;

[0126] Fig.19C For along Fig.19A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line BB' in the shown structure;

[0127] Fig. 20A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0128] Fig. 20B For along Fig. 20A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the shown structure;

[0129] Fig. 20C For along Fig. 20A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line BB' in the shown structure;

[0130] Fig.21A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0131] Fig. 21B is a schematic cross-sectional view perpendicular to the substrate taken along the section line BB' in the structure shown; Fig.21A as shown in

[0132] Fig.22A is a schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0133] Fig. 22B is along Fig.22A is a schematic cross-sectional view perpendicular to the substrate taken along the section line BB' in the structure shown;

[0134] Fig.23A is a schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0135] Fig. 23B is along Fig.23A is a schematic cross-sectional view perpendicular to the substrate taken along the section line AA' in the structure shown;

[0136] Fig.23C is along Fig.23A is a schematic cross-sectional view perpendicular to the substrate taken along the section line BB' in the structure shown;

[0137] Fig.24A is a schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0138] Fig. 24B is along Fig.24A is a schematic cross-sectional view perpendicular to the substrate taken along the section line AA' in the structure shown;

[0139] Fig.24C is along Fig.24A is a schematic cross-sectional view perpendicular to the substrate taken along the section line BB' in the structure shown;

[0140] Fig.25A is a schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0141] Fig.25B is along Fig.25A is a schematic cross-sectional view perpendicular to the substrate taken along the section line AA' in the structure shown; and

[0142] Fig.25Cis a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown in Fig.25A . Detailed implementation manners

[0143] To make the objectives, technical solutions and advantages of the present application clearer and more understandable, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments and features in the embodiments of the present application can be combined arbitrarily with each other.

[0144] The implementation manners in this document can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the implementation manners and contents can be transformed into various forms without departing from the gist and scope of the present application. Therefore, the present application should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present application can be combined arbitrarily with each other.

[0145] The size and proportional relationship between each film layer or component in the drawings of the present application can be used as a reference in actual processes, which is an implementation manner with good technical effects, but not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in the present application are only schematic structural diagrams, and one manner of the present application is not limited to the shapes or values shown in the drawings.

[0146] In this specification, for convenience, terms such as "middle part", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., which indicate the orientation or positional relationship, are used to describe the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. The positional relationship of the constituent elements is appropriately changed according to the directions describing each constituent element. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the situation.

[0147] In this specification, unless otherwise clearly specified and limited, the terms "arrange" and "connect" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0148] In the description of the present application, ordinal numbers such as "first" and "second" are set to avoid confusion of components, rather than to limit the quantity.

[0149] In this specification, "film" and "layer" can be interchanged. For example, sometimes "metal layer" can be changed to "metal film".

[0150] In the description of the present application, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel region, and the source. In the present application, the channel region refers to the region where current mainly flows.

[0151] The present application provides a semiconductor structure, including a substrate, and a first gate, a first semiconductor layer, a first gate insulating layer, a second gate, a second semiconductor layer, and a second gate insulating layer located on the substrate; wherein, the first gate extends along a first direction parallel to the substrate, the first semiconductor layer is disposed around the circumferential sidewall of the first gate, and the first gate insulating layer is located between the first gate and the first semiconductor layer; the second gate extends along a third direction perpendicular to the substrate, the second semiconductor layer is disposed around the circumferential sidewall of the second gate, and the second gate insulating layer is located between the second gate and the second semiconductor layer; along the first direction, the second gate is located on one side of the first gate, and the side of the first gate close to the second gate is in contact with the side of the second semiconductor layer close to the first gate.

[0152] As used in the embodiments of the present disclosure, the term "first direction" X is defined as the direction in which the first gate extends; the term "second direction" Y is defined as intersecting with the "first direction" X and being the direction in which the bit line extends; the term "third direction" Z is defined as the direction perpendicular to the plane where the substrate is located, that is, the extension direction of the word line; the plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, the "second direction" Y, and the "third direction" Z can be as Figure 1A-Figure 1D shown, etc.

[0153] As used in the embodiments of the present disclosure, the term "section line AA'" is a line parallel to the first direction X and passing through a plurality of isolation regions arranged along the first direction; the term "section line BB'" is a line parallel to the first direction X and not passing through a plurality of isolation regions arranged along the first direction X but only passing through the sacrificial layer and the insulating layer. The specific positions of these section lines can be as Figure 1A-Figure 1D shown, etc.

[0154] As used in the embodiments of the present disclosure, the term "integral structure" may refer to a structure where there is no obvious boundary interface such as a distinct fault or gap between A and B at the microscopic level. Generally, a patterned and connected film layer formed on a film layer is an integral structure. For example, A and B are made of the same material to form a film layer and are simultaneously formed with a connected structure through the same patterning process.

[0155] Figure 1A A three-dimensional structure schematic diagram of a semiconductor structure provided for an exemplary embodiment of the present application; Figure 1B A horizontal cross-sectional schematic diagram of a semiconductor structure provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate;

[0156] Figure 1C For Figure 1B A cross-sectional schematic diagram perpendicular to the substrate, taken along the cross-section line AA' in the structure shown; Figure 1D For Figure 1B A cross-sectional schematic diagram perpendicular to the substrate, taken along the cross-section line BB' in the structure shown. An exemplary embodiment of the present application provides a semiconductor structure. As Figures 1A-1D shown, the semiconductor structure may include a substrate, and a first gate 150, a first semiconductor layer 130, a first gate insulating layer 140, a second gate 250, a second semiconductor layer 230, and a second gate insulating layer 240 located on the substrate. The first gate 150 may extend along a first direction X parallel to the substrate, the first semiconductor layer 130 may be disposed around the circumferential sidewalls of the first gate 150, and the first gate insulating layer 140 may be located between the first gate 150 and the first semiconductor layer 130. The second gate 250 may extend along a third direction Z perpendicular to the substrate, the second semiconductor layer 230 may be disposed around the circumferential sidewalls of the second gate 250, and the second gate insulating layer 240 may be located between the second gate 250 and the second semiconductor layer 230.

[0157] In the present application, "surrounding" may be understood as partially or entirely surrounding the first gate 150 or the second gate 250. In some embodiments, "surrounding" may be entirely surrounding on the whole. The cross-section of the surrounding channel layer may be a closed ring, and the shape of the ring may be adapted to the outer contour shape of the cross-section of the first gate 150 or the second gate 250. Exemplarily, the cross-section of the first gate 150 or the second gate 250 may be a square or other structures. The cross-section is taken along a direction perpendicular to the substrate. In an exemplary embodiment, "surrounding" may be partial surrounding, and the cross-section after surrounding is not closed, such as a ring with an opening.

[0158] Refer to Figure 1DIt can be seen that along the first direction X, the second gate 250 can be located on one side of the first gate 150, and the side of the first gate 150 close to the second gate 250 is in contact with the side of the second semiconductor layer 230 close to the first gate 150.

[0159] As Figures 1A-1D shown, the semiconductor structure may further include a first bit line 160 and a second bit line 260 extending along a second direction Y parallel to the substrate, and a first word line 170 and a second word line 270 extending along the third direction; along the first direction X, the first bit line 160 can be located on the side of the first gate 150 away from the second gate 250 and in contact with the first semiconductor layer 130; along the first direction X, the second bit line 260 can be located on the side of the second gate 250 away from the first gate 150 and in contact with the second semiconductor layer 230; along the second direction Y, the first word line 170 can be located on one side of the first gate 150 and in contact with the first semiconductor layer 130; along the third direction Z, the second gate 250 is a part of the second word line 270.

[0160] In an exemplary embodiment, the semiconductor structure may include a read transistor and a write transistor. The read transistor may include the first gate 150, the first semiconductor layer 130, a first source / drain 110, and a second source / drain 120; the first source / drain 110 is connected to the first bit line 160 and is connected to the first semiconductor layer 130, and the second source / drain 120 is connected to the first word line 170 and is connected to the first semiconductor layer 130. The write transistor may include the second gate 250, the second semiconductor layer 230, a third source / drain 210, and a fourth source / drain 220; the third source / drain 210 and the fourth source / drain 220 may be located on both sides of the second semiconductor layer 230 in the first direction X and are respectively connected to the second semiconductor layer 230, and the fourth source / drain 220 may be connected to the second bit line 260

[0161] It can be Figure 1D seen that the first gate 150 and the third source / drain 210 may be an integral structure, that is, they are connected. In this application, by interconnecting the first gate of the read transistor and the third source / drain of the write transistor, a capacitorless memory, such as a 2T0C DRAM memory, is obtained.

[0162] As Figure 1DAs shown, the semiconductor structure may further include a first gate barrier layer 151, which is disposed around the circumferential sidewall of one end of the first gate 150 close to the second gate 250, and is located between the first semiconductor layer 130 and the second semiconductor layer 230.

[0163] An exemplary embodiment of the present application further provides a memory, such as Figures 1A-1D As shown, the memory may include a substrate, a stacked structure located on the substrate, a plurality of first bit lines 160 and second bit lines 260 extending along a second direction Y parallel to the substrate, and a plurality of first word lines 170 and second word lines 270 extending along a third direction Z perpendicular to the substrate and passing through the stacked structure.

[0164] The stacked structure may include a plurality of memory cells stacked along the third direction Z. The memory cells may include a first gate 150, a first gate insulating layer 140, a first semiconductor layer 130, a second gate 250, a second gate insulating layer 240, and a second semiconductor layer 230. The first gate 150 may extend along a first direction X parallel to the substrate, the first semiconductor layer 130 may surround the first gate 150, and the first gate insulating layer 140 may surround the first gate 150 and be located between the first gate 150 and the first semiconductor layer 130. The second gate 250 may extend along the third direction Z, the second semiconductor layer 230 may surround the second gate 250 and is discontinuously arranged in the third direction Z, and the second gate insulating layer 240 may be located between the second gate 250 and the second semiconductor layer 230. Along the first direction X, the second gate 250 may be located on one side of the first gate 150, and one side of the first gate 150 close to the second gate 250 is in contact with one side of the second semiconductor layer 230 close to the first gate 150.

[0165] The first semiconductor layers 130 in a plurality of the memory cells arranged at intervals along the second direction Y may be in contact with the same first bit line 160. The second semiconductor layers 230 in a plurality of the memory cells arranged at intervals along the second direction Y may be in contact with the same second bit line 260. The first semiconductor layers 130 in a plurality of the memory cells arranged at intervals along the third direction Z may be in contact with the same first word line 170. The second gates 250 in a plurality of the memory cells arranged at intervals along the third direction Z are connected to form a second word line 270.

[0166] Refer to Figure 1B and 1D, the memory may also have a second gate protection layer 40, which is disposed around the circumferential sidewalls of the second word line 270 / second gate 250 and is discontinuously disposed in the third direction Z. By providing the second gate protection layer, the second gate insulating layer 240 and the second gate 250 can be protected from being etched away in subsequent etching processes.

[0167] Figure 1A It is also shown that the first bit line 160 and the second bit line 260 may be located on both sides of the memory cell along the first direction X, and multiple first bit lines 160 may be stacked and spaced along the third direction Z, and multiple second bit lines 260 may be stacked and spaced along the third direction Z; multiple first word lines 170 may be spaced along the second direction Y on one side of the memory cell, and multiple second word lines 270 may be located on the side of the first gate 150 away from the first bit line 160.

[0168] Furthermore, Figures 1A-1D It is also shown that the first source / drain 110 may contact the first semiconductor layer 130 only in the first direction X; the second source / drain 120 contacts the first semiconductor layer 130 only in the second direction Y. Thus, the first channel region of the read transistor may be located on a side surface of the first semiconductor layer 130 facing the second source / drain 120, and this side surface extends along the first direction X, and current flows from the second source / drain to the first source / drain along this side surface.

[0169] Figure 1A-Figure 1D It is also shown that the second semiconductor layer 230 of the write transistor may contact the third source / drain 210 and the fourth source / drain 220 in the first direction X. Thus, the channel region of the write transistor may be located on at least one side of the second semiconductor layer 230 in the second direction Y. In an exemplary embodiment, the channel region of the write transistor may be located on both sides of the second semiconductor layer 230 in the second direction Y.

[0170] Although the first source / drain, the second source / drain, the third source / drain, and the fourth source / drain references are used herein to denote two separate and different source / drains, it is not intended that the source / drains referred to as the "first" source / drain, or "second" source / drain, and "third" source / drain and "fourth" source / drain have a unique meaning.

[0171] In some embodiments, the first source / drain and the second source / drain are independent of each other. In some embodiments, one of the first source / drain and the second source / drain may be the source of the read transistor, and the other may be the drain of the read transistor. Similarly, the third source / drain and the fourth source / drain are independent of each other, and one of the third source / drain and the fourth source / drain may be the source of the write transistor, and the other may be the drain of the write transistor.

[0172] Figure 2 An equivalent circuit diagram of a semiconductor structure provided for an exemplary embodiment of the present application. SN represents a storage node, and WWL, WBL, RWL, and RBL are a write word line, a write bit line, a read word line, and a read bit line, respectively. The first source / drain 110 of the read transistor can be electrically connected to the first bit line (i.e., the read bit line RBL) 160, and the second source / drain 120 can be electrically connected to the first word line (i.e., the read word line RWL) 170; the second gate 250 of the write transistor can be electrically connected to the second word line (i.e., the write word line WWL) 270, and the fourth source / drain 220 of the write transistor can be electrically connected to the second bit line (i.e., the write bit line WBL) 260. The first gate 150 of the read transistor can be electrically connected to the third source / drain 210 of the write transistor, that is, the two form an integral structure, and the first gate of the read transistor can serve as a storage node. Data "1" or "0" is stored in the storage node to control the on or off of the read transistor, and the data stored in the storage node is determined to be "1" or "0" according to the on and off states of the read transistor.

[0173] In the present application, in the extending direction of the second word line (i.e., the write word line), the second semiconductor layer is discontinuously arranged, that is, the second semiconductor layers 230 of different write transistors sharing the same write word line 270 are separated from each other. Therefore, the write transistor does not have the parasitic MOS problem, enhancing the performance of the device.

[0174] In the present application, in the extending direction of the read word line, the first semiconductor layer is also discontinuously arranged. That is, the read transistor also does not have the parasitic MOS problem, thus enhancing the performance of the device.

[0175] As used in the present application, the term "discontinuously arranged" can be achieved by physical disconnection to form a gap, such as by means of an isolation region formed of an insulating material, or can be an electrical disconnection, for example, the semiconductor region between two channel regions has conductivity approximately insulating.

[0176] The technical solution of the present application will be further described below through the manufacturing process of the memory in the exemplary embodiments of the present application. The "lithography process" mentioned in this exemplary embodiment includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in the related art. The "photolithography process" mentioned in this exemplary embodiment includes coating a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition, coating can use known coating processes, and etching can use known methods, which will not be specifically limited here. In the description of this exemplary embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a lithography process or a photolithography process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" still requires a lithography process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process or the photolithography process contains at least one "pattern".

[0177] In an exemplary embodiment, the manufacturing method of the memory may include the following steps:

[0178] S101: Form a stacked structure.

[0179] The exemplary steps may include: providing a substrate (not shown), and alternately depositing an insulating layer thin film and a sacrificial layer thin film on the substrate along the third direction Z to form a stacked structure 1 including an insulating layer 10 and a sacrificial layer 20, as Figure 3A 、 3B and shown in 3C. Figure 3A Schematic diagram of a horizontal cross-section taken along a plane parallel to the substrate (through the sacrificial layer) of the stacked structure formed in the initial step of a manufacturing method of a memory provided in an exemplary embodiment of the present application; Figure 3B For along Figure 3A Schematic diagram of a cross-section perpendicular to the substrate taken along the section line AA' of the structure shown; Figure 3C For along Figure 3A Schematic diagram of a cross-section perpendicular to the substrate taken along the section line BB' of the structure shown.

[0180] In an exemplary embodiment, the insulating layer thin film and the conductive layer thin film can be deposited by chemical vapor deposition or plasma enhanced chemical vapor deposition (PECVD).

[0181] In an exemplary embodiment, the substrate can be a semiconductor substrate, such as a silicon substrate.

[0182] In an exemplary embodiment, the insulating layer 10 may be selected from any one or more of silicon oxide (such as SiO2), silicon oxynitride (SiON), silicon carbonitride (SiCN), and SiGe independently. In an exemplary embodiment, the insulating layer 10 may be silicon dioxide.

[0183] In an exemplary embodiment, the sacrificial layer 20 may be silicon nitride (SiN).

[0184] Figure 3B and 3C The stacked structure 1 shown in may include 4 insulating layers 10 and 4 sacrificial layers 20. In other exemplary embodiments, the stacked structure may further include more or fewer alternately arranged insulating layers 10 and sacrificial layers 20.

[0185] S102: Pattern the stacked structure.

[0186] Exemplary steps may include: etching (such as dry etching) the stacked structure 1 to form a preset pattern, which may include a plurality of isolation grooves (not shown) penetrating through the stacked structure 1; filling an insulating material into each isolation groove to form a plurality of isolation regions 11, such as Figure 4A and 4B shown. Figure 4A Schematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application, taken along a plane parallel to the substrate (through the sacrificial layer); Figure 4B is Figure 4A Schematic vertical cross-sectional view taken along the section line AA' in the structure shown.

[0187] Referring to Figure 4A it can be seen that the preset pattern may include 1 column of 3 isolation regions 11 arranged at intervals along the second direction Y, with a total of 3 columns of isolation regions 11 shown. The distance between two adjacent isolation regions 11 in the second direction Y is W; 1 row of 3 isolation regions 11 arranged at intervals along the first direction X, with a total of 3 rows of isolation regions shown. Figure 4AIt is also shown that the middle 1-column isolation region 11 can be set as the word line region 100 (i.e., each column includes 3 word line regions), which is used to form the read word line (RWL) of the read transistor and the write word line (WWL) of the write transistor subsequently; the region between the 1-column isolation region 11 on the opposite side of the middle 1-column isolation region 11 along the first direction X and the middle 1-column isolation region 11 can be set as the write bit line region 200, which is used to form the write bit line (WBL) of the write transistor subsequently; the region between the 1-column isolation region 11 on one side of the middle 1-column isolation region 11 along the first direction X and the middle 1-column isolation region 11 can be set as the read bit line region 300 (i.e., between adjacent isolation regions in the first direction X), which can be used to form the read bit line (RBL) of the read transistor subsequently. That is, the preset pattern can include the word line region 100, the write bit line region 200 located on the opposite side of the word line region 100 along the first direction X, and the read bit line region 300 located on one side of the word line region 100 along the first direction X.

[0188] In an exemplary embodiment, the insulating layer 10 and the isolation region 11 can be made of the same or different insulating materials. Figure 4B It is shown that the insulating layer 10 and the isolation region 11 are made of the same material, such as silicon dioxide.

[0189] S103: Form the first bit line trench and the first bit line expansion slot.

[0190] Exemplary steps can include: within the range of the read bit line region 300, lithographically etch the stacked structure 1 to form the first bit line trench T1 of the read transistor that penetrates the stacked structure 1 and extends along the second direction Y, exposing the sidewalls of the insulating layer 10 and the sacrificial layer 20 along the third direction; by means of the first bit line trench T1, laterally etch (such as wet etching) each sacrificial layer 20 along the first direction X until the etching stops at the position of the isolation regions 11 on both sides of the first bit line trench T1 along the first direction X, forming the first bit line expansion slot R1 that extends along the second direction Y and has a length L in the first direction X, exposing the sidewalls of each isolation region 11 along the third direction, exposing the upper and lower surfaces of each insulating layer 10, and exposing the new sidewalls of the sacrificial layer along the third direction, such as Figure 5A 、 5B as well as shown in 5C. Figure 5A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate (through the insulating layer) of an intermediate product formed in an intermediate step of a manufacturing method of a memory provided by an exemplary embodiment of the present application; Figure 5B For Figure 5A schematic vertical cross-sectional view taken along the section line AA' in the structure shown; Figure 5C For Figure 5A schematic vertical cross-sectional view taken along the section line BB' in the structure shown.

[0191] S104: Fill the first bit line trench and the first bit line extension trench.

[0192] Exemplary steps may include: filling the first bit line trench T1 and the first bit line extension trench R1 with a conductive material and planarizing, such that the first bit line trench T1 and the first bit line extension trench R1 are filled with the conductive material and the upper surface of the stacked structure is flush, as Fig. 6A , 6B and shown in 6C. Fig. 6A Schematic diagram of a horizontal cross-section taken along a plane parallel to the substrate (through the insulating layer) of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0193] Figure 6B For Fig. 6A schematic diagram of a cross-section perpendicular to the substrate taken along the section line AA' in the structure shown; Figure 6C For Fig. 6A schematic diagram of a cross-section perpendicular to the substrate taken along the section line BB' in the structure shown.

[0194] In an exemplary embodiment, an Atomic Layer Deposition (ALD) method may be used to fill the conductive material into the first bit line trench T1 and the first bit line extension trench R1, and the conductive material includes but is not limited to W, ITO, etc.

[0195] In an exemplary embodiment, the planarization process may be performed using a Chemical Mechanical Polishing (CMP) process.

[0196] S105: Form the first source / drain of the read transistor.

[0197] Exemplary steps may include: etching away the conductive material in the first bit line trench T1 to re-form the first bit line trench T1, and only retaining the conductive material in the first bit line extension trench R1, thereby forming the first source / drain 110 of the read transistor at each first bit line extension trench R1, such that the formed first source / drain 110 is disconnected in the third direction Z; depositing and planarizing an insulating material film in the first bit line trench T1, as Fig. 7A , 7B and shown in 7C. Fig. 7A Schematic diagram of a horizontal cross-section taken along a plane parallel to the substrate (through the insulating layer) of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application; Figure 7B For the formed intermediate product, it is a schematic diagram of a cross-section perpendicular to the substrate taken along the section line AA' in the Fig. 7A structure shown; Figure 7C For Fig. 7A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line BB' in the structure shown.

[0198] S106: Form the second source / drain of the read transistor.

[0199] Exemplary steps may include: In the word line region 100, by etching (such as dry etching) the stacked structure 1, a first word line through hole K1 extending along the third direction Z is formed; depositing and planarizing a conductive material into the first word line through hole K1 to make the upper surface of the stacked structure flush, and forming the second source / drain 120 of the read transistor, as Fig. 8A and 8B shown. Fig. 8A Schematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a manufacturing method of a memory provided by an exemplary embodiment of the present application, taken along a plane parallel to the substrate (through the insulating layer); Figure 8B For Fig. 8A schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the structure shown.

[0200] In an exemplary embodiment, an atomic layer deposition method may be used to fill the conductive material into the first word line through hole K1, and the conductive material includes but is not limited to W, ITO, etc.

[0201] S107: Form the second bit line trench.

[0202] Exemplary steps may include: Within the range of the write bit line region 200, etching the stacked structure 1 to form a second bit line trench T2 of the write transistor that penetrates the stacked structure 1 and extends along the second direction Y, exposing the sidewalls of the insulating layer 10 and the sacrificial layer 20 along the third direction, as Fig.9A , 9B and 9C shown. Fig.9A Schematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a manufacturing method of a memory provided by an exemplary embodiment of the present application, taken along a plane parallel to the substrate (through the insulating layer); Fig. 9B For Fig.9A schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the structure shown; Fig. 9C For Fig.9A schematic cross-sectional view perpendicular to the substrate taken along the cross-section line BB' in the structure shown.

[0203] S108: Form the second bit line expansion trench and the first lateral groove.

[0204] Exemplary steps may include: By means of the second bit line trench T2, laterally etching (such as wet etching) each sacrificial layer 20 until etching stops at the position of the isolation region 11 on both sides of the second bit line trench T2 along the first direction X, forming a second bit line expansion groove R2 of the second bit line trench T2, and exposing the side wall of the isolation region 11 along the third direction Z; By means of the second bit line trench T2, at a position where there is no isolation region in the first direction, such as between two adjacent isolation regions 11 along the second direction Y, that is, along the position of the cross-section line BB', continue to laterally etch to remove the material of the entire sacrificial layer and terminate at the first source / drain 110 of the read transistor, that is, the region where the read word line and the read bit line of the read transistor are connected, forming a first lateral groove S1, exposing the upper and lower surfaces of the insulating layer 10, and exposing the side wall of the first source / drain 110 close to the first lateral groove S1, such as Fig. 10A , 10B as well as shown in 10C. Fig. 10A Schematic horizontal cross-sectional view of an intermediate product formed by an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application, taken along a plane parallel to the substrate (through the insulating layer); Fig. 10B is a schematic vertical cross-sectional view taken along the cross-section line AA' of the structure shown in Fig. 10A ; Fig. 10C is a schematic vertical cross-sectional view taken along the cross-section line BB' of the structure shown in Fig. 10A .

[0205] S109: Fill the second bit line trench, the second bit line expansion groove, and the first lateral groove.

[0206] Exemplary steps may include: sequentially depositing a semiconductor material thin film, an insulating material thin film covering the semiconductor material thin film, and a conductive material thin film covering the insulating material thin film on the inner walls of the second bit line trench T2, the second bit line expansion groove R2, and the first lateral groove S1, and flattening after filling the second bit line trench T2, the second bit line expansion groove R2, and the first lateral groove S1 with the conductive material thin film, so that the upper surface of the stacked structure is flush, such as Fig.11A , 11B as well as shown in 11C. Fig.11A Schematic horizontal cross-sectional view of an intermediate product formed by an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application, taken along a plane parallel to the substrate (through the insulating layer); Fig. 11B is a schematic vertical cross-sectional view taken along the cross-section line AA' of the structure shown in Fig.11A ; Fig. 11C is a schematic vertical cross-sectional view taken along the cross-section line BB' of the structure shown in Fig.11A .

[0207] In an exemplary embodiment, the conductive material may be a metal material for the SN (storage node), including but not limited to W, TiN, or a composite material thereof.

[0208] S110: Form a first gate, a first gate insulating layer, and a first semiconductor layer of the read transistor.

[0209] Exemplary steps may include: etching away all the semiconductor material film, insulating material film, and conductive material film within the second bit line trench T2, and reforming the second bit line trench T2 of the write transistor; by means of the second bit line trench T2, etching (such as wet etching) the materials filled in the second bit line expansion trench R2 and the first lateral groove S1 in the previous step along the first direction X, removing all the semiconductor material film, insulating material film, and conductive material film filled in the second bit line expansion trench R2 to reform the second bit line expansion trench R2; etching away a part of the semiconductor material film, a part of the insulating material film, and a part of the conductive material film filled in the first lateral groove S1 to form a second lateral groove S2 within the first lateral groove S1, where the size of the second lateral groove S2 along the first direction X is smaller than the size of the first lateral groove S1 along the first direction X; the semiconductor material film, insulating material film, and conductive material film not removed within the first lateral groove S1 respectively form the first gate 150, the first gate insulating layer 140, and the first semiconductor layer 130 of the read transistor, and one end of the first gate 150, the first gate insulating layer 140, and the first semiconductor layer 130 is exposed by the second lateral groove S2; continue to laterally etch away a part of the material of the first semiconductor layer 130 along a direction parallel to the substrate, and fill an insulating material to form a first gate barrier layer 151 surrounding the circumferential sidewall of the end of the first gate 150 away from the first source / drain 110, as Fig. 12A and 12B shown. Fig. 12A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate (through the insulating layer) of an intermediate product formed in an intermediate step of a manufacturing method of a memory provided by an exemplary embodiment of the present application; Fig. 12B is Fig. 12A schematic vertical cross-sectional view taken along the section line AA' of the structure shown; Fig. 12C is Fig. 12A schematic vertical cross-sectional view taken along the section line BB' of the structure shown.

[0210] In an exemplary embodiment, the first semiconductor layer 130 may be made of a metal oxide semiconductor material. In an exemplary embodiment, the metal oxide semiconductor material may be an amorphous or polycrystalline metal oxide semiconductor material, and the corrosion rate of the metal oxide semiconductor material in a weakly acidic or weakly basic solution is relatively slow. In an exemplary embodiment, the metal oxide semiconductor material may be an oxide of In, an oxide of Ga, an oxide of Zn, an oxide of Sn, etc. These metal oxide materials such as Indium Gallium Zinc Oxide (IGZO) may be used as channel materials. The side length dimension of the semiconductor layer 70 may also be W3.

[0211] In an exemplary embodiment, when the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15 A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide may also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO and other materials, as long as the leakage current of the transistor can meet the requirements, and specific adjustments can be made according to the actual situation.

[0212] In an exemplary embodiment, the first gate insulating layer 140 may be a dielectric layer with a high dielectric constant, that is, a dielectric layer with K≥3.9. The dielectric layer with a high dielectric constant may be used as a gate oxide. The first gate insulating layer 140 may be made of any one or more of silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.

[0213] In an exemplary embodiment, the material of the first gate 150 (read word line) may be made of p-type amorphous silicon, tungsten W, tungsten nitride, titanium nitride, or a composite material of tungsten and titanium nitride, etc.

[0214] In an exemplary embodiment, the deposition of each thin film layer may adopt atomic layer deposition.

[0215] S111: Form an isolation layer.

[0216] Exemplary steps may include: depositing a thin film of isolation layer material along all inner walls of the second bit line trench T2, the second bit line expansion trench R2, and the second lateral groove S2 to form the isolation layer 30; filling the second bit line trench T2, the second bit line expansion trench R2, and the second lateral groove S2 with an insulating material to cover the isolation layer 30 and fill the second bit line trench T2, the second bit line expansion trench R2, and the second lateral groove S2, and planarizing by a CMP process to make the surface of the stacked structure flush, as Fig.13A , 13B and as shown in 13C. Fig.13A Schematic horizontal cross-sectional view of an intermediate product formed by an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application, taken along a plane parallel to the substrate (through the insulating layer); Fig. 13B is a schematic vertical cross-sectional view taken along the cross-section line AA' in the structure shown in Fig.13A perpendicular to the substrate; Fig. 13C is a schematic vertical cross-sectional view taken along the cross-section line BB' in the structure shown in Fig.13A perpendicular to the substrate.

[0217] In an exemplary embodiment, the isolation layer 30 may be made of a material different from that of the insulating layer 10. For example, the isolation layer 30 may be made of silicon nitride, while the insulating layer 10 may be made of silicon oxide.

[0218] S112: Form the second gate (write word line) and the second gate insulating layer of the write transistor.

[0219] Exemplary steps may include: etching (such as dry etching) the stacked structure 1 in the word line region 100 to form a second word line via hole K2 extending in the third direction Z through the stacked structure between the isolation regions adjacent in the second direction Y on the side of the second bit line trench T2 close to the first word line via hole K1; sequentially depositing a nitride material, an insulating layer material, and a conductive material on the inner wall surrounding the second word line via hole K2 to form the second gate 250 and the second gate insulating layer 240 of the write transistor and the second gate protection layer 40 surrounding the second gate, as Fig.14A and 14B shown. Fig.14A Schematic horizontal cross-sectional view of an intermediate product formed by an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application, taken along a plane parallel to the substrate (through the insulating layer); Fig. 14B is a schematic vertical cross-sectional view taken along the cross-section line BB' in the structure shown in Fig.14A perpendicular to the substrate.

[0220] As Fig.14AAs shown, the size of the second word line via hole K2 along the second direction Y is smaller than the distance W between two adjacent isolation regions 11 in the second direction Y, that is, the orthographic projection of the second word line via hole K2 on the substrate falls into the orthographic projection on the substrate of the region between two adjacent isolation regions 11 in the second direction Y.

[0221] In an exemplary embodiment, the second gate protection layer 40 can be used to protect the second gate insulating layer 240 and the second gate 250 from being etched away when etching away the isolation layer 30 in subsequent steps.

[0222] S113: Form the second bit line trench and the second lateral groove again.

[0223] Exemplary steps may include: etching away all the materials of the isolation layer 30 and the insulating layer filled in the second bit line trench T2 in the foregoing step to form the second bit line trench T2 of the write transistor again; by means of the second bit line trench T2, laterally etching to remove all the materials of the isolation layer and the insulating layer filled in the second bit line expansion slot R2 in the foregoing step and all the materials of the isolation layer and the insulating layer filled in the second lateral groove S2 in the foregoing step; continuing to etch to remove all the materials of the outermost second gate protection layer 40 surrounding the second word line via hole K2 in the second lateral groove S2, so that the second gate insulating layer 240 becomes the outermost layer surrounding the second word line via hole K2 in the second lateral groove S2, as Fig.15A 、 15B and shown in 15C. Fig.15A Schematic diagram of a horizontal cross-section taken along a plane parallel to the substrate (through the insulating layer 10) of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application; Fig. 15B For Fig.15A Schematic diagram of a cross-section perpendicular to the substrate taken along the section line AA' in the structure shown;

[0224] Fig. 15C For Fig.15A Schematic diagram of a cross-section perpendicular to the substrate taken along the section line BB' in the structure shown.

[0225] S114: Form the second semiconductor layer of the write transistor.

[0226] Exemplary steps may include: depositing a thin film of semiconductor material along the inner walls of the second bit line trench T2, the second bit line expansion trench R2, and the second lateral groove S2, and depositing a thin film of semiconductor material around the second gate insulating layer 240 exposed in the second lateral groove S2 such that the second gate insulating layer 240 is completely covered, thereby forming the second semiconductor layer 230; continuing to deposit a thin film of conductive material on the surfaces of the semiconductor materials in the second bit line trench T2, the second bit line expansion trench R2, and the second lateral groove S2 until the second bit line trench T2, the second bit line expansion trench R2, and the second lateral groove S2 are filled, as Fig.16A , 16B and as shown in 16C. Fig.16A Schematic diagram of a horizontal cross-section taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application; Fig. 16B is a schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the structure shown in Fig.16A ; Fig. 16C is a schematic cross-sectional view perpendicular to the substrate taken along the cross-section line BB' in the structure shown in Fig.16A .

[0227] In an exemplary embodiment, semiconductor material may also be continued to be filled in the region 400 between the second gate insulating layer 240 and the first gate 150 of the read transistor such that one end of the first gate 150, the first gate insulating layer 140, and the first gate barrier layer 151 exposed in the second lateral groove S2 is completely covered, thereby further forming the second semiconductor layer 230 of the write transistor.

[0228] S115: Form the fourth source / drain (write bit line) of the write transistor.

[0229] Exemplary steps may include: removing all semiconductor materials and conductive materials in the second bit line trench T2, while retaining all semiconductor materials and conductive materials in the second bit line expansion trench R2 and partial semiconductor materials and conductive materials in the second lateral groove S2; refilling the second bit line trench T2 with an insulating material, thereby forming the fourth source / drain 220 (write bit line) of the write transistor and the second semiconductor layer 230 semi-surrounding the fourth source / drain at each second lateral groove S2, and the fourth source / drains 220 at two sacrificial layers adjacent in the third direction Z are discontinuous or disconnected, as shown in 17A, 17B, and 17C. Fig.17A Schematic diagram of a horizontal cross-section taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application; Fig. 17B is a schematic cross-sectional view perpendicular to the substrate taken along the cross-section line in Fig.17ASchematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown; Fig. 17C along Fig.17A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown.

[0230] In another exemplary embodiment, the method for manufacturing a memory may include the following steps:

[0231] Steps S201 - S207 are the same as steps S101 - S107 in the foregoing method;

[0232] S208: Form a second word line via.

[0233] Exemplary steps may include: In the word line region 100, etching (such as dry etching) the stacked structure 1 to form a second word line via K2 between the isolation regions 11 adjacent to each other in the second direction Y on one side of the second bit line trench T2 close to the first word line via K1, as Fig.18A , 18B and as shown in 18C. Among them, Fig.18A is a schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application; Fig.18B along Fig.18A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown; Fig.18C along Fig.18A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown.

[0234] As Fig.18A shown, the dimension of the second word line via K2 in the second direction Y is smaller than the distance W between two adjacent isolation regions 11 in the second direction Y, that is, the orthographic projection of the second word line via K2 on the substrate falls into the orthographic projection of the region between two adjacent isolation regions 11 in the second direction Y on the substrate.

[0235] S209: Form a second bit line expansion groove and a first lateral groove.

[0236] Exemplary steps may include: By means of the second bit line trench T2, laterally etching (such as wet etching) each sacrificial layer 20 until the etching stops at the position of the isolation region 11 on both sides of the second bit line trench T2 along the first direction X, forming a second bit line expansion groove R2 of the second bit line trench T2, and exposing the side wall of the isolation region 11 along the third direction Z; By means of the second bit line trench T2, at a position where there is no isolation region in the first direction, such as between two adjacent isolation regions 11 along the second direction Y, that is, along the position of the cross-section line BB', continue to etch to remove the material of the entire sacrificial layer and terminate at the first source / drain 110 of the read transistor, that is, the region where the read word line and the read bit line of the read transistor are connected, forming a first lateral groove S1, exposing the upper and lower surfaces of the insulating layer 10, and exposing the side wall of the first source / drain 110 close to the first lateral groove S1, such as Fig.19A 、 19B as shown in 19C. Fig.19A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed by an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application; Fig.19B is a schematic vertical cross-sectional view taken along the cross-section line AA' of the structure shown in Fig.19A ; Fig.19C is a schematic vertical cross-sectional view taken along the cross-section line BB' of the structure shown in Fig.19A .

[0237] S210: Fill the second bit line trench, the second bit line expansion groove, and the first lateral groove.

[0238] Exemplary steps may include: sequentially depositing a semiconductor material thin film, an insulating material thin film covering the semiconductor material thin film, and a conductive material thin film covering the insulating material thin film along the inner walls of the second word line through hole K2, the second bit line trench T2, the second bit line expansion groove R2, and the first lateral groove S1, and flattening after filling the second word line through hole K2, the second bit line trench T2, the second bit line expansion groove R2, and the first lateral groove S1 with the conductive material thin film to make the upper surface of the stacked structure flush, such as Fig. 20A 、 20B as shown in 20C. Fig. 20A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed by an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application; Fig. 20B is a schematic vertical cross-sectional view taken along the cross-section line AA' of the structure shown in Fig. 20A ; Fig. 20C is a schematic vertical cross-sectional view taken along the cross-section line BB' of the structure shown in Fig. 20A .

[0239] S211: Form a second lateral groove.

[0240] Exemplary steps may include: removing all materials within the second word line via K2 to re - form the second word line via K2; by means of the second word line via K2, laterally etching to remove a part of the semiconductor material thin film, a part of the insulating material thin film, and a part of the conductive material thin film filled in the first lateral groove S1, so as to form a second lateral groove S2 within the first lateral groove S1, and the size of the second lateral groove S2 along the first direction X is smaller than the size of the first lateral groove S1 along the first direction X; the semiconductor material thin film, the insulating material thin film, and the conductive material thin film that are not removed within the first lateral groove S1 respectively form the first gate 150, the first gate insulating layer 140, and the first semiconductor layer 130 of the read transistor, and one end of the first gate 150, the first gate insulating layer 140, and the first semiconductor layer 130 is exposed by the second lateral groove S2; continuing to laterally etch and remove a part of the material of the first semiconductor layer 130 along a direction parallel to the substrate, and filling with an insulating material to form a first gate barrier layer 151 surrounding the circumferential side wall of the end of the first gate 150 away from the first source - drain 110, as Fig.21A and 21B shown. Fig.21A Schematic diagram of a horizontal cross - section taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a manufacturing method of a memory provided by an exemplary embodiment of the present application; Fig. 21B is Fig.21A a schematic diagram of a cross - section perpendicular to the substrate taken along the section line BB' in the structure shown.

[0241] S212: Filling the second word line via and the second lateral groove

[0242] Exemplary steps may include: sequentially depositing a semiconductor material thin film, an insulating material thin film covering the semiconductor material thin film, a conductive material thin film covering the insulating material thin film along the inner walls of the second word line via K2 and the second lateral groove S2, and after filling the second word line via K2 and the second lateral groove S2 with the conductive material thin film and planarizing, making the upper surface of the stacked structure flush, as Fig.22A and 22B shown. Fig.22A Schematic diagram of a horizontal cross - section taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a manufacturing method of a memory provided by an exemplary embodiment of the present application; Fig. 22B is Fig.22A a schematic diagram of a cross - section perpendicular to the substrate taken along the section line BB' in the structure shown.

[0243] S213: Re - forming the second word line via and the second bit line trench.

[0244] Exemplary steps may include: etching to remove all materials within the second word line via, and reforming the second word line via K2; etching to remove all materials within the second bit line trench T2, and reforming the second bit line trench T2, as Fig.23A , 23B and as shown in 23C. Fig.23A Schematic diagram of a horizontal cross-section taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application; Fig. 23B is a schematic diagram of a cross-section perpendicular to the substrate taken along the cross-section line AA' in the structure shown in Fig.23A ; Fig.23C is a schematic diagram of a cross-section perpendicular to the substrate taken along the cross-section line BB' in the structure shown in Fig.23A .

[0245] S214: Fill the second word line via and the second bit line trench.

[0246] Exemplary steps may include: filling the second word line via K2 and the second bit line trench T2 with a conductive material and planarizing to make the upper surface of the stacked structure flush, as Fig.24A , 24B and as shown in 24C. Fig.24A Schematic diagram of a horizontal cross-section taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application; Fig. 24B is a schematic diagram of a cross-section perpendicular to the substrate taken along the cross-section line AA' in the structure shown in Fig.24A ; Fig.24C is a schematic diagram of a cross-section perpendicular to the substrate taken along the cross-section line BB' in the structure shown in Fig.24A .

[0247] S215: Form the write bit line.

[0248] Exemplary steps may include: removing the conductive material within the second bit line trench T2 and filling it with an insulating material, and planarizing to make the upper surface of the stacked structure flush, as Fig.25A , 25B and as shown in 25C. Fig.25A Schematic diagram of a horizontal cross-section taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application; Fig.25B is a schematic diagram of a cross-section perpendicular to the substrate taken along the cross-section line AA' in the structure shown in Fig.25A ; Fig.25C is a schematic diagram of a cross-section perpendicular to the substrate taken along the cross-section line BB' in the structure shown in Fig.25A .

[0249] Exemplary embodiments of the present application also provide a method for manufacturing a memory, including the following steps:

[0250] Providing a substrate;

[0251] Alternately depositing an insulating layer and a sacrificial layer on the substrate in a third direction perpendicular to the substrate to form a stacked structure including a plurality of insulating layers and sacrificial layers;

[0252] Patterning the stacked structure to form a plurality of isolation regions arranged at intervals in a second direction and arranged at intervals in a first direction in the stacked structure, the first direction intersecting the second direction and both being perpendicular to the third direction;

[0253] Forming a first bit line trench penetrating the stacked structure and extending in the second direction between adjacent isolation regions in the first direction to form a first bit line extending in the second direction;

[0254] Forming a first word line through hole penetrating the stacked structure in each of the isolation regions to form a first word line extending in the third direction;

[0255] Forming a second bit line trench penetrating the stacked structure and extending in the second direction between adjacent isolation regions in the first direction on a side of the first word line away from the first bit line;

[0256] By means of the second bit line trench, a first gate extending in a first direction, a first semiconductor layer surrounding a circumferential sidewall of the first gate, and a first gate insulating layer located between the first gate and the first semiconductor layer are formed in a region between adjacent isolation regions in the second direction and close to the first bit line;

[0257] By means of the second bit line trench, a second gate extending in a third direction, a second semiconductor layer surrounding a circumferential sidewall of the second gate, and a second gate insulating layer located between the second gate and the second semiconductor layer are formed on a side of the second bit line trench close to the first word line through hole and between adjacent isolation regions in the second direction;

[0258] Forming a second bit line extending in the second direction by means of the second bit line trench.

[0259] Exemplary embodiments of the present application also provide an electronic device including the memory provided by the exemplary embodiments of the present application as above.

[0260] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0261] Although the embodiments disclosed in this application are as above, the content described is only the embodiments adopted for the convenience of understanding this application and is not used to limit this application. Any person skilled in the art within the scope of this application can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the protection scope of this application shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, and a first gate, a first semiconductor layer, a first gate insulating layer, a second gate, a second semiconductor layer, and a second gate insulating layer located on the substrate; Wherein, the first gate extends along a first direction parallel to the substrate, the first semiconductor layer is disposed around the circumferential sidewall of the first gate, and the first gate insulating layer is located between the first gate and the first semiconductor layer; The second gate extends along a third direction perpendicular to the substrate, the second semiconductor layer is disposed around the circumferential sidewall of the second gate, and the second gate insulating layer is located between the second gate and the second semiconductor layer; Along the first direction, the second gate is located on one side of the first gate, and one side of the first gate close to the second gate is in contact with one side of the second semiconductor layer close to the first gate.

2. The semiconductor structure according to claim 1, wherein Further comprising a first bit line and a second bit line extending along a second direction parallel to the substrate, and a first word line and a second word line extending along the third direction, wherein the second direction intersects the first direction; Wherein, along the first direction, the first bit line is located on the side of the first gate away from the second gate and is in contact with the first semiconductor layer; along the first direction, the second bit line is located on the side of the second gate away from the first gate and is in contact with the second semiconductor layer; Along the second direction, the first word line is located on one side of the first gate and is in contact with the first semiconductor layer; along the third direction, the second gate is a part of the second word line.

3. The semiconductor structure according to claim 2, wherein Comprising a read transistor and a write transistor; The read transistor includes the first gate, the first semiconductor layer, a first source / drain, and a second source / drain; the first source / drain is connected to the first bit line and is connected to the first semiconductor layer, and the second source / drain is connected to the first word line and is connected to the first semiconductor layer; The write transistor includes the second gate, the second semiconductor layer, a third source / drain, and a fourth source / drain; the third source / drain and the fourth source / drain are located on both sides of the second semiconductor layer in the first direction and are respectively connected to the second semiconductor layer, and the fourth source / drain is connected to the second bit line; The first gate is connected to the third source / drain.

4. The semiconductor structure according to claim 1, wherein Further comprising a first gate barrier layer, which is disposed around the circumferential sidewall of one end of the first gate close to the second gate and is located between the first semiconductor layer and the second semiconductor layer.

5. A memory, characterized in that, Comprising a substrate and a stacked structure located on the substrate, a plurality of first bit lines and second bit lines extending along a second direction parallel to the substrate, and a plurality of first word lines and second word lines extending along a third direction perpendicular to the substrate and passing through the stacked structure; The stacked structure includes a plurality of memory cells stacked along the third direction, and each memory cell includes a first gate, a first gate insulating layer, a first semiconductor layer, a second gate, a second gate insulating layer, and a second semiconductor layer. Wherein, the first gate extends along a first direction parallel to the substrate, the first semiconductor layer surrounds the first gate, and the first gate insulating layer surrounds the first gate and is located between the first gate and the first semiconductor layer; The second gate extends along the third direction, the second semiconductor layer surrounds the second gate and is discontinuously arranged in the third direction, and the second gate insulating layer is located between the second gate and the second semiconductor layer; Along the first direction, the second gate is located on one side of the first gate, and one side of the first gate close to the second gate contacts one side of the second semiconductor layer close to the first gate; The first semiconductor layers in a plurality of the memory cells arranged at intervals along the second direction are in contact with the same first bit line; The second semiconductor layers in a plurality of the memory cells arranged at intervals along the second direction are in contact with the same second bit line; The first semiconductor layers in a plurality of the memory cells arranged at intervals along the third direction are in contact with the same first word line; The second gates in a plurality of the memory cells arranged at intervals along the third direction are connected to form a second word line, and the first direction intersects with the second direction and both are perpendicular to the third direction.

6. The memory according to claim 5, wherein It further includes a second gate protection layer, and the second gate protection layer is disposed around the circumferential sidewall of the second word line and is discontinuously arranged in the third direction.

7. The memory according to claim 5, characterized in that, The first bit line and the second bit line are located on both sides of the memory cell along the first direction, and a plurality of the first bit lines are stacked and arranged at intervals along the third direction, and a plurality of the second bit lines are stacked and arranged at intervals along the third direction.

8. The memory according to claim 5, characterized in that, The plurality of first word lines are arranged at intervals along the second direction on one side of the memory cell, and the plurality of second word lines are located on the side of the first gate away from the first bit line.

9. A manufacturing method of a memory, characterized in that, It includes the following steps: Provide a substrate; Alternately deposit an insulating layer and a sacrificial layer on the substrate along a third direction perpendicular to the substrate to form a stacked structure including a plurality of insulating layers and sacrificial layers; Pattern the stacked structure to form a plurality of isolation regions arranged at intervals along the second direction and arranged at intervals along the first direction in the stacked structure, and the first direction intersects with the second direction and both are perpendicular to the third direction; Form a first bit line trench penetrating the stacked structure and extending along the second direction between the isolation regions adjacent to each other in the first direction to form a first bit line extending along the second direction; Form a first word line via hole penetrating the stacked structure in each of the isolation regions to form a first word line extending along the third direction; Form a second bit line trench penetrating the stacked structure and extending along the second direction on the side of the first word line away from the first bit line and between the isolation regions adjacent to each other in the first direction; By means of the second bit line trench, a first gate extending in a first direction, a first semiconductor layer surrounding a circumferential sidewall of the first gate, and a first gate insulating layer located between the first gate and the first semiconductor layer are formed in a region between isolation regions adjacent in the second direction and close to the first bit line; On a side of the second bit line trench close to the first word line via hole and between isolation regions adjacent in the second direction, a second gate extending in a third direction, a second semiconductor layer surrounding a circumferential sidewall of the second gate, and a second gate insulating layer located between the second gate and the second semiconductor layer are formed; By means of the second bit line trench, a second bit line extending in the second direction is formed.

10. The manufacturing method according to claim 9, characterized in that, The forming of the first gate extending in the first direction, the first semiconductor layer surrounding the circumferential sidewall of the first gate, and the first gate insulating layer located between the first gate and the first semiconductor layer in the region between isolation regions adjacent in the second direction and close to the first bit line by means of the second bit line trench includes: By means of the second bit line trench, the material of the sacrificial layer is etched away to form a first lateral groove; In the second bit line trench and the first lateral groove, a semiconductor material thin film, an insulating material thin film, and a conductive material thin film are sequentially deposited; The semiconductor material thin film, the insulating material thin film, and the conductive material thin film in the second bit line trench are removed, and a part of the semiconductor material thin film, the insulating material thin film, and the conductive material thin film in the first lateral groove are removed to form a second lateral groove, and the remaining semiconductor material thin film, insulating material thin film, and conductive material thin film in the first lateral groove form the first gate, the first semiconductor layer, and the first gate insulating layer.

11. The manufacturing method according to claim 9, characterized in that, After forming the first semiconductor layer and before forming the second semiconductor layer, it further includes: Part of the material of the first semiconductor layer is etched away laterally, and an insulating material is filled to form a first gate barrier layer surrounding a circumferential sidewall of an end of the first gate close to the second gate.

12. The manufacturing method according to claim 9, characterized in that, The forming of a first bit line trench penetrating the stacked structure and extending in the second direction between isolation regions adjacent in the first direction to form a first bit line extending in the second direction includes: By means of the first bit line trench, the sacrificial layer is etched to form a first bit line expansion groove at the sacrificial layer; The first bit line trench and the first bit line expansion groove are filled with a conductive material, The conductive material in the first bit line trench is removed, and the conductive material in the first bit line expansion groove is retained to form a first bit line extending in the second direction.

13. The manufacturing method according to claim 9, characterized in that, The forming of a second bit line extending in the second direction by means of the second bit line trench includes: All the semiconductor material and the conductive material in the second bit line trench are removed, and the semiconductor material and the conductive material in the second lateral groove are retained; the second bit line trench is refilled with an insulating material to form a second bit line extending in the second direction at the second lateral groove.

14. The manufacturing method according to claim 10, characterized in that, A second gate extending in a third direction, a second semiconductor layer surrounding a circumferential sidewall of the second gate, and a second gate insulating layer located between the second gate and the second semiconductor layer are formed on a side of the second bit line trench close to the first word line via hole and between isolation regions adjacent in the second direction, including: Deposit an isolation material thin film and an insulating material thin film in the second bit line trench and the second lateral groove in sequence to form an isolation layer and an insulating layer; A second word line via hole penetrating the stacked structure is formed between isolation regions adjacent in the second direction on a side of the second bit line trench close to the first word line via hole; Deposit an isolation material thin film, an insulating material thin film, and a conductive material thin film in the second word line via hole in sequence to form a second gate extending in a third direction, a second gate insulating layer surrounding the second gate, and a second gate isolation layer surrounding the second gate insulating layer; Remove the insulating material thin film and the isolation material thin film in the second bit line trench and the second lateral groove, and remove the material of the second gate isolation layer in the second lateral groove to expose the second gate insulating layer; Deposit a semiconductor material thin film around the exposed second gate insulating layer in the second lateral groove, thereby forming a second semiconductor layer that is discontinuously arranged in the third direction.

15. The manufacturing method according to claim 9, characterized in that, A first gate extending in a first direction, a first semiconductor layer surrounding a circumferential sidewall of the first gate, and a first gate insulating layer located between the first gate and the first semiconductor layer are formed between isolation regions adjacent in the second direction and in a region close to the first bit line by means of the second bit line trench, including: A second word line via hole is formed between isolation regions adjacent in the second direction on a side of the second bit line trench close to the first word line via hole; Laterally etch and remove the material of the sacrificial layer by means of the second bit line trench and the second word line via hole to form a first lateral groove; Deposit a semiconductor material thin film, an insulating material thin film, and a conductive material thin film in sequence along the second bit line trench, the first lateral groove, and the second word line via hole; Remove all the materials in the second word line via hole; In the first lateral groove, remove a part of the semiconductor material thin film, the insulating material thin film, and the conductive material thin film to form a second lateral groove, and the remaining semiconductor material thin film, insulating material thin film, and conductive material thin film in the first lateral groove form the first gate, the first semiconductor layer, and the first gate insulating layer.

16. The manufacturing method according to claim 15, characterized in that, A second gate extending in a third direction, a second semiconductor layer surrounding a circumferential sidewall of the second gate, and a second gate insulating layer located between the second gate and the second semiconductor layer are formed between isolation regions adjacent in the second direction on a side of the second bit line trench close to the first word line via hole, including: Deposit a semiconductor material thin film, an insulating material thin film, and a conductive material thin film in sequence along the second word line via hole and the second lateral groove; Remove all the materials in the second word line via hole while retaining all the materials in the second lateral groove, thereby forming the second semiconductor layer and the second gate insulating layer which are discontinuously arranged along the third direction in each of the second lateral grooves; Deposit a conductive material thin film in the second word line via hole to form the second gate.

17. An electronic device, characterized in that, Comprising a memory according to any one of claims 5-8.

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