Semiconductor structure, semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention relates to the technical field of semiconductors, and provides a semiconductor structure, a semiconductor device and a manufacturing method thereof, the semiconductor structure comprises: a plurality of transistors arranged at intervals, each transistor comprising: a gate structure having a first portion, a second portion and a third portion arranged in sequence along a first direction; the first semiconductor channel and the second semiconductor channel respectively cover two opposite side walls of the second part along a second direction, and the first direction and the second direction are intersected; a first electrical contact structure in contact connection with the first portion and in contact connection with the first semiconductor channel and the second semiconductor channel; and the second electric contact structure and the third electric contact structure respectively cover two opposite side walls of the third part along the second direction. The embodiment of the invention is at least beneficial to improving the electrical performance of the transistor, the integration density of the transistor in the semiconductor structure and the electrical performance of the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and particularly to a semiconductor structure, a semiconductor device, and a manufacturing method thereof. Background Art

[0002] A transistor is a semiconductor device commonly used in memories, amplifiers, or electronic control switches. A transistor is a basic building block for regulating the operation of computers, mobile phones, and all other modern electronic circuits. Due to its fast response speed and high accuracy, a transistor can be used for a variety of digital and analog functions, including amplification, switching, voltage regulation, signal modulation, and oscillators. A transistor can be packaged independently or located in a very small area that is part of an integrated circuit that can accommodate one hundred million or more transistors.

[0003] Dynamic Random Access Memory (DRAM) is a memory component used to store programs and various data information. DRAM typically includes a capacitor and a transistor connected to the capacitor. The capacitor is used to store the charge representing the stored program and various data information, and the transistor is a switch that controls the inflow and outflow of the charge of the capacitor. When writing data, the word line gives a high level, the transistor conducts, and the bit line charges the capacitor; when reading data, the word line also gives a high level, the transistor conducts, and the capacitor discharges, causing the bit line to obtain a read signal.

[0004] However, with the continuous development of the manufacturing process of DRAM devices, the process nodes of semiconductor devices are continuously reduced, which makes the sizes of the functional structures in semiconductor devices gradually reduced, and the spacing between the functional structures gradually reduced, which easily increases the coupling effect between the functional structures, resulting in a reduction in the electrical performance of semiconductor devices. The functional structures include, but are not limited to, transistors. Summary of the Invention

[0005] Embodiments of the present disclosure provide a semiconductor structure, a semiconductor device, and a manufacturing method thereof, which are at least beneficial to improving the electrical performance of transistors, the integration density of transistors in the semiconductor structure, and the electrical performance of semiconductor devices.

[0006] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a plurality of transistors arranged at intervals, each of the transistors including: a gate structure having a first portion, a second portion, and a third portion arranged in sequence along a first direction; a first semiconductor channel and a second semiconductor channel respectively covering two opposite sidewalls of the second portion along a second direction, the first direction intersecting the second direction; a first electrical contact structure in contact connection with the first portion and in contact connection with the first semiconductor channel and the second semiconductor channel; and a second electrical contact structure and a third electrical contact structure respectively covering two opposite sidewalls of the third portion along the second direction.

[0007] In some embodiments, the first electrical contact structure has a groove with an opening facing the first portion, and the first portion is located in the groove.

[0008] In some embodiments, the first semiconductor channel and the second semiconductor channel also respectively cover two opposite sidewalls of the first portion along the second direction; the first electrical contact structure is located on a side of the first portion away from the second portion along the first direction.

[0009] In some embodiments, the gate structure includes: a gate dielectric layer and a gate conductive layer, wherein the first direction and the second direction form a projection plane, the positive projection shape of the gate dielectric layer on the projection plane is U-shaped, the U-shaped gate dielectric layer has a receiving cavity, and the gate conductive layer is located in the receiving cavity.

[0010] In some embodiments, the semiconductor structure further includes: active regions corresponding to the transistors one by one; wherein the first semiconductor channel and the second semiconductor channel are both part of the active region, the active region has a first end and a second end opposite to each other along the first direction, the first electrical contact structure is embedded in the first end, the second electrical contact structure and the third electrical contact structure are respectively embedded in different regions of the second end, and one active region corresponds to only one transistor.

[0011] In some embodiments, taking a plane perpendicular to the first direction as a reference plane, the positive projection of the first semiconductor channel on the reference plane is semicircular, triangular or N-sided; and / or, the positive projection of the second semiconductor channel on the reference plane is semicircular, triangular or N-sided, where N is a positive integer greater than or equal to 4.

[0012] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a semiconductor device including the semiconductor structure described in any one of the above.

[0013] In some embodiments, the semiconductor device further includes a word line structure extending along a third direction. One of the word line structures corresponds to the first semiconductor channel and the second semiconductor channel in at least one of the transistors. The gate structure in one of the transistors is a partial region of the word line structure; a bit line structure extending along a fourth direction, and the bit line structure is in contact connection with at least one of the first electrical contact structures on a side away from the gate structure along the first direction; wherein, the third direction intersects with the fourth direction, and both the third direction and the fourth direction intersect with the first direction, and the second direction, the third direction and the fourth direction are in the same plane.

[0014] In some embodiments, the third direction is the direction in which a plurality of the transistors are arranged at intervals. A plurality of the transistors arranged at intervals along the third direction share one gate word line structure, and different ones of the transistors sharing one word line structure correspond to different bit line structures one by one.

[0015] In some embodiments, a plurality of the transistors are arranged at intervals along both the third direction and the fourth direction, and a plurality of the transistors arranged at intervals along the fourth direction share one bit line structure, and different ones of the transistors sharing one bit line structure correspond to different word line structures one by one.

[0016] In some embodiments, the included angle between the third direction and the fourth direction is 30° to 150°.

[0017] In some embodiments, the semiconductor device further includes: an electrical connection layer, one electrical connection layer corresponding to one transistor; wherein, the electrical connection layer is located on a side of the third portion away from the second portion along the first direction, and the electrical connection layer is electrically connected to both the second electrical contact structure and the third electrical contact structure; a capacitor structure, one capacitor structure being electrically connected to one electrical connection layer.

[0018] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor device, including: providing an initial substrate; forming a plurality of transistors arranged at intervals in the initial substrate; wherein the step of forming the transistors includes: forming a gate structure having a first portion, a second portion, and a third portion arranged in sequence along a first direction; forming a first semiconductor channel and a second semiconductor channel, the first semiconductor channel and the second semiconductor channel respectively covering two opposite sidewalls of the second portion along a second direction, and the first direction intersects the second direction; forming a first electrical contact structure in contact connection with the first portion and in contact connection with the first semiconductor channel and the second semiconductor channel; forming a second electrical contact structure and a third electrical contact structure, the second electrical contact structure and the third electrical contact structure respectively covering two opposite sidewalls of the third portion along the second direction.

[0019] In some embodiments, the initial substrate has a front surface and a back surface opposite to each other along the first direction; the steps of forming the first semiconductor channel, the second semiconductor channel, and the gate structure include: forming an initial semiconductor channel in the initial substrate; performing a first patterning process on the initial semiconductor channel from the front surface to divide at least a part of the thickness of the initial semiconductor channel in the first direction into the first semiconductor channel and the second semiconductor channel; forming a gate dielectric layer located between the first semiconductor channel and the second semiconductor channel, and a positive projection shape of the gate dielectric layer on a projection plane formed by the first direction and the second direction is U-shaped, and the U-shaped gate dielectric layer has a receiving cavity; forming a gate conductive layer in the receiving cavity, and the gate structure includes the gate dielectric layer and the gate conductive layer.

[0020] In some embodiments, the initial substrate has a front surface and a back surface opposite to each other along the first direction; the step of forming the first electrical contact structure includes: performing a second patterning process on the initial substrate from the back surface to form an opening in the initial substrate exposing the initial substrate opposite to the gate structure along the first direction; performing a first doping process on the initial substrate exposed by the opening to form the first electrical contact structure in contact connection with the gate structure.

[0021] In some embodiments, the manufacturing method further includes: forming a bit line structure in the opening, or forming a partial area of the bit line structure in the opening.

[0022] In some embodiments, the initial substrate has a front surface and a back surface opposite to each other in the first direction; the steps of forming the second electrical contact structure and the third electrical contact structure include: performing a second doping process on different regions of the initial substrate located around the gate structure from the front surface, so as to form the second electrical contact structure and the third electrical contact structure on two opposite sidewalls of the gate structure in the second direction respectively.

[0023] In some embodiments, the initial substrate has a front surface and a back surface opposite to each other in the first direction; the manufacturing method further includes: forming an electrical connection layer on the front surface, the electrical connection layer is electrically connected to both the second electrical contact structure and the third electrical contact structure, and one electrical connection layer corresponds to one transistor; forming a capacitor structure on a side of the electrical connection layer away from the front surface in the first direction, and one capacitor structure is electrically connected to one electrical connection layer.

[0024] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0025] Design a new transistor. When a transistor works, two channel regions will be generated. The two channel regions are respectively formed by a first semiconductor channel and a second semiconductor channel, and the two channel regions are controlled by the same gate structure. One end of the two channel regions corresponds to the same first electrical contact structure, and the other ends of the two channel regions correspond to the second electrical contact structure and the third electrical contact structure respectively.

[0026] Moreover, on the one hand, design the combined structure of the first electrical contact structure, the second electrical contact structure and the third electrical contact structure to be directly opposite in the first direction. When the two channel regions formed by the first semiconductor channel and the second semiconductor channel are conducting, the current mainly transmits along the first direction, which is beneficial to shortening the length of the current transmission path in a single channel region, so as to improve the sensitivity of the channel region to turn on / off, and thus it is easier to control the conduction or turn-off of the transistor, so as to improve the electrical performance of the transistor; on the other hand, one gate structure controls two channel regions, and the two channel regions can complement each other, which is beneficial to improving the sensitivity of the gate structure to control the conduction or turn-off of the transistor, so as to improve the electrical performance of the transistor. In addition, the transistor extends as a whole in the first direction, so multiple transistors can be arranged in a plane perpendicular to the first direction, which is beneficial to improving the integration density of transistors in the semiconductor structure.

[0027] Moreover, on yet another aspect, the semiconductor device includes the above semiconductor structure having transistors. Based on the improvement of the electrical performance of the transistors and the improvement of the integration density of the transistors in the semiconductor structure, it is beneficial to improve the electrical performance of the semiconductor device and the integration density of the semiconductor structure and transistors in the semiconductor device. Description of the Drawings

[0028] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, unless otherwise stated. The drawings in the figures do not constitute a scale limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0029] Figure 1 FIG. is a partial cross-sectional structure schematic diagram of two spaced-apart transistors in a semiconductor structure provided by an embodiment of the present disclosure;

[0030] Figure 2 FIG. is a partial cross-sectional structure schematic diagram of a transistor in a semiconductor structure provided by an embodiment of the present disclosure;

[0031] Figure 3 FIG. is another partial cross-sectional structure schematic diagram of a transistor in a semiconductor structure provided by an embodiment of the present disclosure;

[0032] Figure 4 FIG. is a cross-sectional structure schematic diagram of a gate dielectric layer in a semiconductor structure provided by an embodiment of the present disclosure;

[0033] Figure 5 FIG. is a partial top-down structure schematic diagram of a word line structure, a bit line structure, a first semiconductor channel, and a second semiconductor channel in a semiconductor device provided by another embodiment of the present disclosure;

[0034] Figure 6 FIG. is another partial top-down structure schematic diagram of a word line structure, a bit line structure, a first semiconductor channel, and a second semiconductor channel in a semiconductor device provided by another embodiment of the present disclosure;

[0035] Figure 7 FIG. is a partial cross-sectional structure schematic diagram of a semiconductor device provided by another embodiment of the present disclosure;

[0036] Figures 8 to 18 FIG. is a cross-sectional structure schematic diagram corresponding to each step in the manufacturing method of a semiconductor device provided by still another embodiment of the present disclosure.

[0037] Description of reference numerals: 100, transistor; 101, gate structure; 111, first part; 121, second part; 131, third part; 141, gate dielectric layer; 141a, receiving cavity; 141b, first sub-receiving cavity; 141c, second sub-receiving cavity; 151, gate conductive layer; 161, diffusion barrier layer; 171, isolation layer; 181, word line structure; 102, initial semiconductor channel; 112, first semiconductor channel; 122, second semiconductor channel; 132, initial active region; 103, first electrical contact structure; 1 13. groove; 114. second electrical contact structure; 124. third electrical contact structure; 105. active area; 115. first end; 125. second end; 106. bit line structure; 116. bit line contact block; 126. bit line conductive layer; 107. electrical connection layer; 117. capacitor structure; 108. initial substrate; 108a. front side; 108b. back side; 118. opening; 118a. fourth groove; 118b. through hole; 128. substrate; 138. third groove; 109. semiconductor structure; 119. semiconductor device. DETAILED DESCRIPTION

[0038] As can be seen from the background technology, the electrical performance of transistors and semiconductor devices needs to be improved.

[0039] Embodiments of the present disclosure provide a semiconductor structure, a semiconductor device, and a manufacturing method thereof. In the semiconductor structure, a new transistor is designed. When a transistor operates, two channel regions are generated. The two channel regions are respectively formed by a first semiconductor channel and a second semiconductor channel, and the two channel regions are controlled by the same gate structure. One end of each of the two channel regions corresponds to the same first electrical contact structure, and the other ends of the two channel regions correspond to a second electrical contact structure and a third electrical contact structure respectively. Moreover, on the one hand, it is designed that the combined structure of the first electrical contact structure, the second electrical contact structure, and the third electrical contact structure is directly opposite in the first direction. When the two channel regions formed by the first semiconductor channel and the second semiconductor channel are turned on, the current mainly transmits along the first direction, which is beneficial to shortening the length of the current transmission path in a single channel region, so as to improve the sensitivity of the channel region to turn on / off, and thus it is easier to control the conduction or cut-off of the transistor, so as to improve the electrical performance of the transistor. On the other hand, one gate structure controls two channel regions, and the two channel regions can complement each other, which is beneficial to improving the sensitivity of the gate structure to control the conduction or cut-off of the transistor, so as to improve the electrical performance of the transistor. In addition, the transistor extends as a whole in the first direction, so that multiple transistors can be arranged in a plane perpendicular to the first direction, which is beneficial to improving the integration density of the transistors in the semiconductor structure. Moreover, on the other hand, the semiconductor device includes the above-mentioned semiconductor structure with transistors. Based on the improvement of the electrical performance of the transistors and the improvement of the integration density of the transistors in the semiconductor structure, it is beneficial to improve the electrical performance of the semiconductor device and the integration density of the semiconductor structure and transistors in the semiconductor device.

[0040] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are proposed to help readers better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the embodiments of the present disclosure can still be implemented.

[0041] An embodiment of the present disclosure provides a semiconductor structure, and the semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0042] Reference Figures 1 to 3, the semiconductor structure 109 includes: a plurality of transistors 100 arranged at intervals, each transistor 100 includes: a gate structure 101 having a first portion 111, a second portion 121, and a third portion 131 arranged in sequence along a first direction X; a first semiconductor channel 112 and a second semiconductor channel 122 respectively covering two opposite sidewalls of the second portion 121 along a second direction Y, the first direction X and the second direction Y intersecting; a first electrical contact structure 103 in contact connection with the first portion 111 and in contact connection with the first semiconductor channel 112 and the second semiconductor channel 122; a second electrical contact structure 114 and a third electrical contact structure 124 respectively covering two opposite sidewalls of the third portion 131 along the second direction Y.

[0043] Wherein, Figure 1 is a schematic diagram of a partial cross-sectional structure of two transistors arranged at intervals in the semiconductor structure provided by an embodiment of the present disclosure; Figure 2 is a schematic diagram of a partial cross-sectional structure of a transistor in the semiconductor structure provided by an embodiment of the present disclosure; Figure 3 is another schematic diagram of a partial cross-sectional structure of a transistor in the semiconductor structure provided by an embodiment of the present disclosure.

[0044] It should be noted that, Figures 1 to 3 the first portion 111, the second portion 121, and the third portion 131 of the gate structure 101 are all schematically shown by relatively sparse dotted lines in Figure 2 and Figure 3 the first semiconductor channel 112 and the second semiconductor channel 122 are both schematically shown by relatively dense dotted lines in. In addition, Figure 1 only 2 transistors 100 in the semiconductor structure 109 are schematically shown in Figure 1 In actual applications, the number of transistors 100 arranged in the semiconductor structure 109 is not limited, and the arrangement manner of the plurality of transistors 100 will be described in detail later. Moreover,

[0045] On the one hand, the first electrical contact structure 103 is designed to be in contact connection with the first part 111, and the second electrical contact structure 114 and the third electrical contact structure 124 respectively cover two opposite sidewalls of the third part 131 along the second direction Y. In this way, the first electrical contact structure 103 can be one of the source or drain of the transistor 100, and the combined structure of the second electrical contact structure 114 and the third electrical contact structure 124 can be the other of the source or drain of the transistor. Moreover, the first semiconductor channel 112 and the second semiconductor channel 122 respectively cover two sidewalls of the second part 121, and the first part 111, the second part 121, and the third part 131 are arranged in sequence along the first direction X. Then, the first electrical contact structure 103 is directly opposite to the combined structure of the second electrical contact structure 114 and the third electrical contact structure 124 along the first direction X. When the transistor 100 is operating, a channel region can be generated between the first electrical contact structure 103 and the second electrical contact structure 114 by means of the first semiconductor channel 112 and the second semiconductor channel 122, and a channel region can be generated between the first electrical contact structure 103 and the third electrical contact structure 124.

[0046] In this way, a new transistor 100 is designed. When a transistor 100 is operating, two channel regions will be generated. The two channel regions are respectively formed by the first semiconductor channel 112 and the second semiconductor channel 122, and the two channel regions are controlled by the same gate structure 101. One end of each of the two channel regions corresponds to the same first electrical contact structure 103, and the other ends of the two channel regions respectively correspond to the second electrical contact structure 114 and the third electrical contact structure 124.

[0047] In some cases, referring to Figures 1 to 3 , the first semiconductor channel 112 is located between the first electrical contact structure 103 and the second electrical contact structure 114, and the second semiconductor channel 122 is located between the first electrical contact structure 103 and the third electrical contact structure 124. In practical applications, it can also be that the second semiconductor channel is located between the first electrical contact structure and the second electrical contact structure, and the first semiconductor channel is located between the first electrical contact structure and the third electrical contact structure.

[0048] It should be noted that for the convenience of description, hereinafter, it will be described by taking the first semiconductor channel 112 being located between the first electrical contact structure 103 and the second electrical contact structure 114, and the second semiconductor channel 122 being located between the first electrical contact structure 103 and the third electrical contact structure 124 as an example.

[0049] On the other hand, the combined structure of the first electrical contact structure 103, the second electrical contact structure 114, and the third electrical contact structure 124 is designed to face each other along the first direction X. When the two channel regions formed by the first semiconductor channel 112 and the second semiconductor channel 122 are conducting, the current mainly travels along the first direction X, which helps to shorten the length of the current transmission path in a single channel region, thereby improving the sensitivity of the channel region to turn on / off, and making it easier to control the on or off state of the transistor 100, so as to improve the electrical performance of the transistor 100.

[0050] On the other hand, one gate structure 101 controls two channel regions, and the two channel regions can be complementary to each other. In other words, one gate structure 101 controls the first semiconductor channel 112 and the second semiconductor channel 122 simultaneously, which helps to improve the sensitivity of the gate structure 101 to control the on or off state of the transistor 100, so as to improve the electrical performance of the transistor 100. In addition, the transistor 100 extends as a whole along the first direction X, so multiple transistors 100 can be arranged in the plane perpendicular to the first direction X, which helps to increase the integration density of the transistors 100 in the semiconductor structure 109.

[0051] On the other hand, as the source and drain of the transistor 100, the first electrical contact structure 103 and the second electrical contact structure 114 are respectively located on the opposite sides of the first semiconductor channel 112 along the first direction X, and the first electrical contact structure 103 and the third electrical contact structure 124 are respectively located on the opposite sides of the second semiconductor channel 122 along the first direction X. That is, taking the plane parallel to the first direction X as the reference plane, the source and drain of the transistor 100 do not face each other, that is, the positive projections of the source and drain of the transistor 100 on the reference plane do not overlap, so as to increase the distance between the source and drain of the transistor 100, which helps to reduce the coupling effect of the source and drain of the transistor 100 on each other. In other words, it reduces the coupling effect between the first electrical contact structure 103 and the second electrical contact structure 114, and reduces the coupling effect between the first electrical contact structure 103 and the third electrical contact structure 124.

[0052] In some cases, a first conductive structure is designed on one side of the source or drain of the transistor 100 away from the gate structure 101, and a second conductive structure is designed on the other side away from the gate structure 101. Since the plane parallel to the first direction X is used as the reference plane, the positive projections of the source and drain of the transistor 100 on the reference plane do not overlap, which helps to avoid the first conductive structure and the second conductive structure facing each other, thereby reducing the coupling effect of the first conductive structure and the second conductive structure on each other and improving the electrical performance of the structure composed of the transistor 100, the first conductive structure, and the second conductive structure as a whole. In some embodiments, the semiconductor structure 109 including the transistor 100 is applied to a semiconductor device. The first conductive structure can be a capacitor structure, and the second conductive structure can be a bit line structure. The bit line structure and the capacitor structure in the semiconductor device will be described in detail later.

[0053] In some embodiments, referring to Figure 1 , the semiconductor structure 109 further includes a substrate 128, and multiple transistors 100 are all electrical devices embedded in the substrate 128.

[0054] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0055] In some embodiments, referring to Figure 1 or Figure 2 , the first electrical contact structure 103 has a groove 113 with an opening facing the first portion 111, and the first portion 111 is located in the groove 113. In other words, at least a partial region of the first portion 111 in the gate structure 101 is embedded in the first electrical contact structure 103, which helps to increase the facing area between the gate structure 101 and the first electrical contact structure 103 and improve the electrical performance of the transistor 100.

[0056] It should be noted that due to different manufacturing processes, the cross-sectional morphology of the gate structure 101 includes at least Figure 2 and Figure 3 the two morphologies shown, and the two cross-sectional morphologies of the gate structure 101 will be described in detail later.

[0057] In other embodiments, referring to Figure 3, the first semiconductor channel 112 and the second semiconductor channel 122 also respectively cover two opposite sidewalls of the first part 111 along the second direction Y; the first electrical contact structure 103 is located on one side of the first part 111 away from the second part 121 along the first direction X. In other words, the first electrical contact structure 103 is only in contact connection with the bottom surface of the gate structure 101 along the first direction X. In the gate structure 101, not only the second part 121 is respectively opposite to the first semiconductor channel 112 and the second semiconductor channel 122, but also the first part 111 is opposite to the first semiconductor channel 112 and the second semiconductor channel 122, which is beneficial to increasing the facing area between the gate structure 101 and the first semiconductor channel 112, and increasing the facing area between the gate structure 101 and the second semiconductor channel 122, thereby being beneficial to improving the control ability of the gate structure 101 over the first semiconductor channel 112 and the second semiconductor channel 122.

[0058] In some embodiments, referring to Figure 2 or Figure 3 , the gate structure 101 may include: a gate dielectric layer 141 and a gate conductive layer 151. Wherein, the first direction X and the second direction Y form a projection plane, the orthographic projection shape of the gate dielectric layer 141 on the projection plane is U-shaped, the U-shaped gate dielectric layer 141 has a receiving cavity 141a, and the gate conductive layer 151 is located in the receiving cavity 141a.

[0059] It should be noted that in some cases, the contour of the U-shaped orthographic projection of the gate dielectric layer 141 on the projection plane may be smoothly connected at the corners as Figure 2 shown, in other words, the contour of the U-shaped orthographic projection is a curve; in other cases, the contour of the U-shaped orthographic projection of the gate dielectric layer 141 on the projection plane may be bent and connected at the corners as Figure 3 shown, in other words, the contour of the U-shaped orthographic projection is a straight line. In practical applications, the gate structure 101 with the cross-sectional morphology as Figure 2 shown or the gate structure 101 with the cross-sectional morphology as Figure 3 shown can be selected according to requirements.

[0060] In some embodiments, the material of the gate dielectric layer 141 may be a material with a relatively high relative dielectric constant such as silicon oxide, hafnium oxide or zirconium oxide.

[0061] In some embodiments, the material of the gate conductive layer 151 may be a metal material such as titanium, tungsten or copper, or the material of the gate conductive layer 151 may be a compound material such as titanium nitride.

[0062] In some embodiments, referring to Figure 2 or Figure 3, the gate structure 101 may further include: a diffusion barrier layer 161 located between the gate dielectric layer 141 and the gate conductive layer 151. In some cases, the diffusion barrier layer 161 conformally covers the inner wall of the accommodation cavity 141a, and the gate conductive layer 151 is located on the side of the diffusion barrier layer 161 away from the gate dielectric layer 141. In other words, the accommodation cavity 141a is a first trench with open ends, the diffusion barrier layer 161 conformally covers the inner wall of the first trench, and the diffusion barrier layer 161 encloses a second trench with open ends, and the gate conductive layer 151 is located in the second trench.

[0063] It should be noted that the diffusion barrier layer 161 is used to prevent the conductive ions in the gate conductive layer 151 from diffusing and migrating into the gate dielectric layer 141, avoiding the reduction of the conductivity of the gate conductive layer 151 due to the diffusion and migration of conductive ions, and avoiding the reduction of the insulation performance of the gate dielectric layer 141 due to the migration of conductive ions, that is, it is beneficial to the high conductivity of the gate conductive layer 151 itself and the high insulation performance of the gate dielectric layer 141 itself.

[0064] In some embodiments, with reference to Figure 2 and Figure 4 , the accommodation cavity 141a includes a first sub-accommodation cavity 141b and a second sub-accommodation cavity 141c arranged in sequence along the first direction X, and the gate conductive layer 151 is located in the first sub-accommodation cavity 141b; the semiconductor structure may further include: an isolation layer 171, and the isolation layer 171 fills the second sub-accommodation cavity 141c.

[0065] In some cases, the diffusion barrier layer 161 is located between the gate dielectric layer 141 and the gate conductive layer 151, and the diffusion barrier layer 161 covers the inner walls of the first sub-accommodation cavity 141b and the second sub-accommodation cavity 141c. Thus, a part of the diffusion barrier layer 161 and the gate conductive layer 151 together fill the first sub-accommodation cavity 141b, and the remaining part of the diffusion barrier layer 161 and the isolation layer 171 together fill the second sub-accommodation cavity 141c. In other words, both the first part 111 and the second part 121 include the gate dielectric layer 141 and the gate conductive layer 151, and the third part 131 includes the gate dielectric layer 141 and the isolation layer 171. In other cases, the gate conductive layer may fill the first sub-accommodation cavity, and the isolation layer may fill the second sub-accommodation cavity.

[0066] Among them, Figure 4 is a schematic cross-sectional structure diagram of a gate dielectric layer in a semiconductor structure provided by an embodiment of the present disclosure. In addition, Figure 4 delineates the first sub-accommodation cavity 141b and the second sub-accommodation cavity 141c in the accommodation cavity 141a with a dashed line.

[0067] In some embodiments, the material of the isolation layer 171 may be a dielectric material such as silicon nitride, silicon oxynitride, or silicon carbonitride.

[0068] In some embodiments, with reference to Figure 2 or Figure 3 , the semiconductor structure may further include: an active region 105, corresponding to the transistor 100 one by one; wherein, the first semiconductor channel 112 and the second semiconductor channel 122 are both part of the active region 105, the active region 105 has opposite first and second ends 115 and 125 in the first direction X, the first electrical contact structure 103 is embedded in the first end 115, and the second electrical contact structure 114 and the third electrical contact structure 124 are respectively embedded in different regions of the second end 125, and one active region 105 corresponds to only one transistor 100.

[0069] Thus, the first semiconductor channel 112, the second semiconductor channel 122, and the other active regions 105 have the same semiconductor elements. In other words, the first semiconductor channel 112, the second semiconductor channel 122, and the other active regions 105 are an integral structure. The active regions 105 controlled by the gate structure 101 will form channel regions and be regarded as the first semiconductor channel 112 and the second semiconductor channel 122 respectively, which is conducive to making the materials of the first semiconductor channel 112 and the second semiconductor channel 122 the same and having similar electrical properties, facilitating the unified control of the first semiconductor channel 112 and the second semiconductor channel 122 by the same gate structure 101 to improve the electrical performance of the transistor 100.

[0070] It should be noted that Figure 2 and Figure 3 both schematically show the approximate regions of the first semiconductor channel 112 and the second semiconductor channel 122 in the active region 105 with relatively dense dotted lines, and both schematically show the approximate regions of the first end 115 and the second end 125 in the active region 105 with dotted frames. In addition, Figure 2 and Figure 3 the dotted lines used to schematically show the first part 111, the second part 121, and the third part 131 in the gate structure 101, the dotted lines used to schematically show the first semiconductor channel 112 and the second semiconductor channel 122 in the active region 105, and the dotted lines used to schematically show the first end 115 and the second end 125 in the active region 105 have different degrees of density.

[0071] In some cases, the first electrical contact structure 103 can be regarded as being transformed from the first end portion after additional processing, and the second electrical contact structure 114 and the third electrical contact structure 124 can be regarded as being transformed from different regions in the second end portion after additional processing, so that the first electrical contact structure 103 is embedded in the unprocessed portion of the first end portion 115, and the second electrical contact structure 114 and the third electrical contact structure 124 are respectively embedded in the unprocessed portions of the second end portion 125. Thus, since the active region 105, the first electrical contact structure 103, the second electrical contact structure 114, and the third electrical contact structure 124 have the same semiconductor element, the active region 105, the first electrical contact structure 103, the second electrical contact structure 114, and the third electrical contact structure 124 can be formed using the same film layer structure composed of the semiconductor element, which is beneficial to improving the interface state defects between the semiconductor channel and the first electrical contact structure 103, the second electrical contact structure 114, and the third electrical contact structure 124, so as to improve the electrical performance of the semiconductor structure. It should be noted that the semiconductor channels described here refer to the first semiconductor channel 112 and the second semiconductor channel 122.

[0072] In some embodiments, the semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, or indium. In one example, the active region 105, the first electrical contact structure 103, the second electrical contact structure 114, and the third electrical contact structure 124 all include silicon elements.

[0073] In some embodiments, there is a shallow trench isolation structure (not shown) between adjacent active regions 105.

[0074] In some embodiments, taking the plane perpendicular to the first direction X as the reference plane, the positive projection of the first semiconductor channel 112 on the reference plane is semicircular, triangular, or an N-sided polygon, where N is a positive integer greater than or equal to 4. When N is 4, the N-sided polygon can be a rectangle. It should be noted that it is sufficient that at least one sidewall of the first semiconductor channel 112 extending along the first direction X is in contact connection with the sidewall of the gate structure 101 extending along the first direction X. Therefore, in the positive projection on the reference plane, it is sufficient that at least one side of the positive projection shape of the first semiconductor channel 112 coincides with one side of the positive projection shape of the gate structure 101. Therefore, in practical applications, based on different requirements, the positive projection shape of the first semiconductor channel 112 in an embodiment of the present disclosure can also be other figures with one side.

[0075] In some embodiments, with the plane perpendicular to the first direction X as the reference plane, the orthographic projection of the second semiconductor channel 122 on the reference plane is semi-circular, triangular, or N-sided. It should be noted that the corresponding or identical parts of the second semiconductor channel 122 and the first semiconductor channel 112 will not be elaborated here. In addition, the orthographic projections of the first semiconductor channel 112 and the second semiconductor channel 122 on the reference plane will be described in detail later when describing the semiconductor device.

[0076] In summary, a new transistor 100 is designed. When a transistor 100 operates, two channel regions are generated. The two channel regions are respectively formed by the first semiconductor channel 112 and the second semiconductor channel 122, and the two channel regions are controlled by the same gate structure 101. One end of the two channel regions corresponds to the same first electrical contact structure 103, and the other ends of the two channel regions correspond to the second electrical contact structure 114 and the third electrical contact structure 124 respectively. Moreover, on the one hand, the combined structure of the first electrical contact structure 103, the second electrical contact structure 114, and the third electrical contact structure 124 is arranged facing each other along the first direction X. When the two channel regions formed by the first semiconductor channel 112 and the second semiconductor channel 122 are conducting, the current mainly transmits along the first direction X, which is beneficial to shortening the length of the current transmission path in a single channel region, so as to improve the sensitivity of the channel region to turn on / off, and thus it is easier to control the conduction or turn-off of the transistor 100 to improve the electrical performance of the transistor 100. On the other hand, one gate structure 101 controls two channel regions, and the two channel regions can be complementary to each other, which is beneficial to improving the sensitivity of the gate structure 101 to control the conduction or turn-off of the transistor 100 to improve the electrical performance of the transistor 100. In addition, the transistor 100 extends integrally along the first direction X, so multiple transistors 100 can be arranged in the plane perpendicular to the first direction X, which is beneficial to improving the integration density of the transistors 100 in the semiconductor structure 109.

[0077] Another embodiment of the present disclosure further provides a semiconductor device, including the semiconductor structure provided in the foregoing embodiment. It should be noted that the same or corresponding parts as the foregoing embodiment will not be elaborated here.

[0078] With reference to Figure 1 and Figure 5 , the semiconductor device 119 includes the semiconductor structure 109 provided in the foregoing embodiment. The semiconductor device 119 provided in another embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings. In some embodiments, with reference to Figure 5 , the semiconductor device 119 may further include: a word line structure 181 extending along the third direction Z, and one word line structure 181 is associated with at least one transistor 100 (with reference to Figure 3) The first semiconductor channel 112 and the second semiconductor channel 122 in Figure 3 ) are corresponding, and the gate structure 101 in a transistor 100 (refer to

[0079] Among them, Figure 5 is a partial top view structural schematic diagram of a word line structure, a bit line structure, a first semiconductor channel, and a second semiconductor channel in a semiconductor device provided in another embodiment of the present disclosure.

[0080] It should be noted that, to reflect the corresponding relationship between the word line structure and the bit line structure with the first semiconductor channel and the second semiconductor channel respectively, Figure 5 other structures in the transistor are not shown. In addition, Figures 1 to 3 can all be regarded as Figure 4 a partial cross-sectional structural schematic diagram of the semiconductor device shown along the first cross-sectional direction AA1. With reference to Figure 3 and Figure 5 , the semiconductor device 119 may further include: a bit line structure 106 extending along the fourth direction P, and the bit line structure 106 is in contact connection with at least one first electrical contact structure 103 on a side away from the gate structure 101 along the first direction X; wherein, the third direction Z intersects with the fourth direction P, and both the third direction Z and the fourth direction P intersect with the first direction X, and the second direction Y, the third direction Z, and the fourth direction P are in the same plane.

[0081] It should be noted that the third direction Z intersects with the fourth direction P, that is, the extending directions of the word line structure 181 and the bit line structure 106 are different. Taking the plane formed by the third direction Z and the fourth direction P as the reference plane, other components of the transistor 100 can be arranged at the overlapping part of the orthographic projections of the word line structure 181 and the bit line structure 106 on the reference plane. For example, the first semiconductor channel 112, the second semiconductor channel 122, the first electrical contact structure 103, the second electrical contact structure 114, and the third electrical contact structure 124 are arranged such that two transistors 100 either share only one word line structure 181, or share only one bit line structure 106, or do not share either the word line structure 181 or the bit line structure 106, so as to ensure that each transistor 100 can be independently controlled and operated.

[0082] The corresponding relationship among the word line structure 181, the bit line structure 106, and the transistor 10 will be described in detail below.

[0083] In some embodiments, with reference to Figure 3 and Figure 5 , the third direction Z is the direction in which multiple transistors 100 are arranged at intervals. Multiple transistors 100 arranged at intervals along the third direction Z share one word line structure 181, and different transistors 100 among the multiple transistors 100 sharing one word line structure 181 correspond one-to-one with different bit line structures 106. In other words, the arrangement of multiple transistors 100 is related to the extending direction of the word line structure 181, that is, the third direction Z. Along the third direction Z, different regions of one word line structure 181 can be utilized by different transistors 100 to control the first semiconductor channel 112 and the second semiconductor channel 122 in different transistors 100. In this way, it is beneficial to improve the integration density of transistors 100 in the semiconductor device 119 and to simplify the control logic for each transistor 100.

[0084] In some embodiments, with reference to Figure 3 and Figure 5 , multiple transistors 100 are arranged at intervals along both the third direction Z and the fourth direction P, and multiple transistors 100 arranged at intervals along the fourth direction P share one bit line structure 106, and different transistors 100 among the multiple transistors 100 sharing one bit line structure 106 correspond one-to-one with different word line structures 181. In other words, the arrangement of multiple transistors 100 is also related to the extending direction of the bit line structure 106, that is, the fourth direction P. Along the fourth direction P, different regions of one bit line structure 106 can be utilized by different transistors 100 to make contact connections with the first electrical contact structure 103 in different transistors 100. In this way, it is beneficial to further improve the integration density of transistors 100 in the semiconductor device 119 and to further simplify the control logic for each transistor 100.

[0085] In some embodiments, the included angle between the third direction Z and the fourth direction P may be 30° to 150°.

[0086] In one example, referring to Figure 4 , the included angle between the third direction Z and the fourth direction P is 60°, such that a plurality of transistors 100 are arranged in a rhombus along the third direction Z and the fourth direction P; in another example, referring to Figure 5 , the third direction Z and the fourth direction P may be orthogonal, then the second direction Y is the same as the fourth direction P, such that a plurality of transistors 100 are arranged in a square along the third direction Z and the fourth direction P, which is beneficial to making the pitch between any adjacent transistors 100 equal.

[0087] If the included angle between the third direction Z and the fourth direction P is less than 30° or greater than 150°, the extending directions of the word line structure 181 and the bit line structure 106 will be relatively close to parallel. It should be noted that, taking the plane formed by the third direction Z and the fourth direction P as the reference plane, the orthographic projections of two adjacent word line structures 181 and two adjacent bit line structures 106 on the reference plane may have 4 overlapping points. Designing a transistor 100 at each of the 4 overlapping points, then the 4 transistors 100 can be connected into a quadrilateral. If the included angle between the third direction Z and the fourth direction P is less than 30° or greater than 150°, it is easy to make one diagonal of the quadrilateral formed by the 4 transistors 100 very long and the other diagonal very short, such that the total layout area occupied by the 4 transistors 100 is relatively large, which is not conducive to the high-integration arrangement of the transistors 100.

[0088] Therefore, designing the included angle between the third direction Z and the fourth direction P to be 30° to 150° is beneficial to avoiding the extending directions of the word line structure 181 and the bit line structure 106 from approaching parallel, thereby being beneficial to reducing the length difference between the two diagonals of the quadrilateral formed by the above 4 transistors 100, making the arrangement of the above 4 transistors 100 more regular, and thus being beneficial to reducing the total layout area occupied by the 4 transistors 100 to improve the integration density of the transistors 100 in the semiconductor device 119.

[0089] Among them, Figure 6 is another partial top-view structural schematic diagram of a word line structure, a bit line structure, a first semiconductor channel, and a second semiconductor channel in a semiconductor device provided by another embodiment of the present disclosure.

[0090] It should be noted that, to reflect the corresponding relationship between the word line structure and the bit line structure and the first semiconductor channel and the second semiconductor channel respectively, Figure 6 does not show other structures in the transistor. In addition, Figures 1 to 3 can also be regarded as Figure 6 a partial cross-sectional structural schematic diagram of the semiconductor device shown along the second cross-sectional direction BB1.

[0091] In addition, based on the change in the angle between the third direction Z and the fourth direction P, there are multiple arrangements of the multiple transistors 100, which will not be enumerated one by one here.

[0092] In some embodiments, referring to Figure 5 or Figure 6 , along the direction perpendicular to the third direction Z, the multiple word line structures 181 are arranged at intervals; along the direction perpendicular to the fourth direction P, the multiple bit line structures 106 are arranged at intervals. Since the third direction Z intersects with the fourth direction P, taking the plane formed by the third direction Z and the fourth direction P as the reference plane, the positive projections of different regions of a word line structure 181 in the third direction Z and different bit line structures 106 on the reference plane may overlap, and the positive projections of different regions of a bit line structure 106 in the fourth direction P and different word line structures 181 on the reference plane may overlap. A transistor 100 can be designed at the position where the positive projections of any word line structure 181 and any bit line structure 106 overlap on the reference plane, which is beneficial to improving the integration density of the transistors 100 in the semiconductor device 119.

[0093] In some embodiments, referring to Figure 5 or Figure 6 , taking the plane perpendicular to the first direction X as the reference plane, the positive projection of the first semiconductor channel 112 on the reference plane is semicircular. In other embodiments, taking the plane perpendicular to the first direction X as the reference plane, the positive projection of the first semiconductor channel on the reference plane may also be triangular or an N-sided polygon, where N is a positive integer greater than or equal to 4. Among them, when N is 4, the N-sided polygon can be a rectangle.

[0094] It should be noted that it is only necessary for at least one side wall of the first semiconductor channel 112 extending along the first direction X to be in contact connection with the side wall of the word line structure 181 extending along the first direction X. Therefore, in the positive projection on the reference plane, it is only necessary for at least one side of the positive projection shape of the first semiconductor channel 112 on the reference plane to coincide with one side of the positive projection shape of the word line structure 181 on the reference plane. Therefore, in practical applications, based on different requirements, the positive projection shape of the first semiconductor channel 112 on the reference plane in another embodiment of the present disclosure may also be other figures with one side.

[0095] In some embodiments, referring to Figure 5 or Figure 6, taking the plane perpendicular to the first direction X as the reference plane, the positive projection of the second semiconductor channel 122 on the reference plane is semicircular. In other embodiments, taking the plane perpendicular to the first direction X as the reference plane, the positive projection of the second semiconductor channel on the reference plane may also be triangular or N-sided. It should be noted that the corresponding or identical parts of the second semiconductor channel 122 and the first semiconductor channel 112 will not be elaborated here.

[0096] In some embodiments, referring to Figure 7 , the semiconductor device 119 may further include: an electrical connection layer 107, where an electrical connection layer 107 corresponds to a transistor 100 (refer to Figure 3 ); wherein, the electrical connection layer 107 is located on the side of the third part 131 away from the second part 121 along the first direction X, and the electrical connection layer 107 is electrically connected to both the second electrical contact structure 114 and the third electrical contact structure 124; a capacitive structure 117, where a capacitive structure 117 is electrically connected to an electrical connection layer 107.

[0097] It should be noted that the electrical connection layer 107 is equivalent to a capacitive contact structure for transmitting electrical signals between the transistor 100 and the capacitive structure 117. Moreover, an electrical connection layer 107 is electrically connected to both the second electrical contact structure 114 and the third electrical contact structure 124 in a transistor 100 at the same time, which is beneficial to increasing the contact area between the electrical connection layer 107 and the transistor 100, thereby being beneficial to reducing the resistance when the electrical signal is transmitted between the transistor 100 and the capacitive structure 117, so as to improve the electrical performance of the semiconductor device 119.

[0098] It should be noted that Figure 7 is a schematic diagram of a partial cross-sectional structure of a semiconductor device provided in another embodiment of the present disclosure. In addition, Figure 7 is only an example of the electrical connection layer 107 and the capacitive structure 117, and the specific structures of the electrical connection layer 107 and the capacitive structure 117 are not limited in another embodiment of the present disclosure. Moreover, Figure 7 shows that the electrical connection layer 107 is in contact connection with both the second electrical contact structure 114, the third electrical contact structure 124 and the gate structure 101, and the electrical connection layer 107 is in contact connection with the insulating part in the gate structure 101. In practical applications, the electrical connection layer may only be in contact connection with the second electrical contact structure and the third electrical contact structure. It should be noted that the insulating part of the electrical connection layer 107 and the gate structure 101 includes a gate dielectric layer 141 and an isolation layer 171.

[0099] In some embodiments, the first electrical contact structure 103, the second electrical contact structure 114 and the third electrical contact structure 124 are all doped with P-type doping ions or all doped with N-type doping ions.

[0100] In some embodiments, the N-type doping ions may include at least one of arsenic ions, phosphorus ions, or antimony ions; the P-type doping ions may include at least one of boron ions, indium ions, or gallium ions.

[0101] In some embodiments, the first electrical contact structure 103, the second electrical contact structure 114, and the third electrical contact structure 124 are all doped with first-type doping ions, and the first semiconductor channel 112 and the second semiconductor channel 122 are both doped with second-type doping ions. In some cases, both the first-type doping ions and the second-type doping ions are P-type doping ions or both are N-type doping ions, and the doping concentration of the first-type doping ions in any one of the first electrical contact structure 103, the second electrical contact structure 114, and the third electrical contact structure 124 is greater than the doping concentration of the second-type doping ions in any one of the first semiconductor channel 112 and the second semiconductor channel 122; in other cases, the first-type doping ions are one of P-type doping ions and N-type doping ions, and the second-type doping ions are the other of P-type doping ions and N-type doping ions.

[0102] In summary, the semiconductor device 119 includes a semiconductor structure 109 having a transistor 100. Due to the improvement in the electrical performance of the novel transistor 100 based on the design and the increase in the integration density of the transistor 100 in the semiconductor structure 109, it is beneficial to improve the electrical performance of the semiconductor device 119 and the integration density of the semiconductor structure 109 and the transistor 100 in the semiconductor device 119.

[0103] Another embodiment of the present disclosure further provides a manufacturing method of a semiconductor device for forming the semiconductor device provided in the foregoing embodiment. Figures 8 to 18 FIG. is a schematic cross-sectional structure diagram corresponding to each step in the manufacturing method of the semiconductor device provided in another embodiment of the present disclosure. It should be noted that, for the convenience of description and to clearly illustrate the steps of the semiconductor device manufacturing method, the Figures 8 to 18 are all schematic diagrams of local structures of the semiconductor device. In addition, the same or corresponding parts as those in the foregoing embodiments will not be described in detail herein.

[0104] Refer to Figures 8 to 18, A method for manufacturing a semiconductor device includes: providing an initial substrate 108; forming a plurality of transistors 100 arranged at intervals in the initial substrate 108; wherein, the step of forming the transistors 100 includes: forming a gate structure 101, the gate structure 101 having a first portion 111, a second portion 121, and a third portion 131 arranged in sequence along a first direction X; forming a first semiconductor channel 112 and a second semiconductor channel 122, the first semiconductor channel 112 and the second semiconductor channel 122 respectively covering two opposite sidewalls of the second portion 121 along a second direction Y, the first direction X and the second direction Y intersecting; forming a first electrical contact structure 103, the first electrical contact structure 103 being in contact connection with the first portion 111, and in contact connection with the first semiconductor channel 112 and the second semiconductor channel 122; forming a second electrical contact structure 114 and a third electrical contact structure 124, the second electrical contact structure 114 and the third electrical contact structure 124 respectively covering two opposite sidewalls of the third portion 131 along the second direction Y.

[0105] In some cases, the gate structure 101, the first semiconductor channel 112, and the second semiconductor channel 122 are formed in one step, the first electrical contact structure 103 is formed in another step, and the second electrical contact structure 114 and the third electrical contact structure 124 are formed in yet another step. The order of the above three steps can be adjusted according to actual situations. In addition, for the sake of understanding, the subsequent description will use the formation of Figure 6 the semiconductor device shown for an exemplary illustration of the manufacturing method. In practical applications, various semiconductor devices in the foregoing embodiments can all be manufactured by the manufacturing method provided by another embodiment of the present disclosure.

[0106] In some embodiments, the initial substrate 108 has a front surface 108a and a back surface 108b opposite to each other along the first direction X; forming the first semiconductor channel 112, the second semiconductor channel 122, and the gate structure 101 may include the following steps:

[0107] Referring to Figure 8 and Figure 9 , an initial semiconductor channel 102 is formed in the initial substrate 108, and the initial semiconductor channel 102 is used for subsequently forming the first semiconductor channel and the second semiconductor channel.

[0108] , Figure 9 For Figure 8 a schematic top view structure of the semiconductor device shown along the first cross-sectional direction AA1. It should be noted that, in order to schematically show the positional relationship between the initial semiconductor channel 102 and the gate structure and the bit line structure formed in other steps, Figure 7It not only shows a plurality of initial semiconductor channels 102 formed in the initial substrate 108, but also shows the approximate regions of the word line structure 181 and the bit line structure 106 formed in other steps, and the relationship between the step of forming the word line structure 181 and the step of forming the gate structure will be described in detail later.

[0109] In some cases, with reference to Figure 8 and Figure 9 , the step of forming the initial semiconductor channels 102 may include: performing a third doping process on the initial substrate 108 from the front surface 108a to form the initial active region 132. It should be noted that the initial semiconductor channels 102 are partial regions in the initial active region 132, and the subsequent steps of forming the gate structure, the first semiconductor channel, the second semiconductor channel, the first electrical contact structure, the second electrical contact structure, and the third electrical contact structure can all be based on the initial active region 132. After forming the gate structure, the first semiconductor channel, the second semiconductor channel, the first electrical contact structure, the second electrical contact structure, and the third electrical contact structure, the remaining initial active region 132 serves as the active region. In other words, the gate structure, the first semiconductor channel, the second semiconductor channel, the first electrical contact structure, the second electrical contact structure, and the third electrical contact structure are all structures embedded in the active region. Here, the active region can be the Figure 7 active region 105 shown.

[0110] It should be noted that Figure 9 delineates the approximate region of the initial semiconductor channels 102 in the initial active region 132 with a dashed line.

[0111] With reference to Figure 9 and Figure 10 , perform a first patterning process on the initial semiconductor channels 102 from the front surface 108a to divide the initial semiconductor channels 102 with at least partial thickness in the first direction X into a first semiconductor channel 112 and a second semiconductor channel 122.

[0112] In some embodiments, with reference to Figure 10 , the first patterning process divides the initial semiconductor channels 102 with only partial thickness in the first direction X into two parts, and the two parts with partial thickness in the first direction X serve as the first semiconductor channel 112 and the second semiconductor channel 122 respectively. Thus, other parts of the initial active region 132 are exposed between the first semiconductor channel 112 and the second semiconductor channel 122 to finally form a semiconductor structure as shown in Figure 7 , and a partial region of the first part 111 in the gate structure 101 is embedded in the first electrical contact structure 103.

[0113] In other embodiments, the first patterning process divides the initial semiconductor channel with the entire thickness in the first direction into two parts, and the two parts with partial thickness in the first direction X are respectively used as the first semiconductor channel and the second semiconductor channel. In this way, the initial substrate is exposed between the first semiconductor channel and the second semiconductor channel, rather than the initial active region. In this way, the transistors in the finally formed semiconductor device can be as Figure 3 shown, both of the two opposite sidewalls of the first part 111 and the second part 121 in the gate structure 101 in the second direction Y are covered by the first semiconductor channel 112 and the second semiconductor channel 122, and the first electrical contact structure 103 is located on one side of the first part 111 away from the second part 121 in the first direction X.

[0114] In the above two embodiments, taking Figure 10 as an example, both the initial substrate 108 and the remaining initial semiconductor channel 102 including the first semiconductor channel 112 and the second semiconductor channel 122 will enclose an unclosed third trench 138 at both ends. The third trench 138 extends in the third direction Z (refer to Figure 7 ), and a word line structure is formed in the third trench 138 subsequently.

[0115] Referring to Figure 11 , a gate dielectric layer 141 is formed. The gate dielectric layer 141 is located between the first semiconductor channel 112 and the second semiconductor channel 122, and the orthographic projection shape of the gate dielectric layer 141 on the projection plane formed by the first direction X and the second direction Y is U-shaped. The U-shaped gate dielectric layer 141 has a receiving cavity 141a; a gate conductive layer 151 is formed in the receiving cavity 141a, and the gate structure 101 includes the gate dielectric layer 141 and the gate conductive layer 151.

[0116] In some embodiments, in combination with referring to Figure 10 and Figure 11 , the first semiconductor channel 112 and the second semiconductor channel 122 used to form a transistor are taken as a pair. The same third trench 138 formed will expose multiple pairs of the first semiconductor channel 112 and the second semiconductor channel 122 arranged at intervals in the third direction Z. The step of forming the gate structure 101 based on the third trench 138 is the step of forming the word line structure 181 (refer to Figure 8 ) based on the third trench 138. In other words, in the step of forming the word line structure 181, a partial region in the word line structure 181 is the gate structure 101 constituting the transistor.

[0117] In combination with referring to Figure 10 and Figure 11 , the step of forming the gate dielectric layer 141 includes: forming a gate dielectric layer 141 that conformally covers the inner wall of the third trench 138. In some cases, referring to Figure 11, after forming the gate dielectric layer 141 and before forming the gate conductive layer 151, the manufacturing method may further include: forming a diffusion barrier layer 161 that conformally covers the inner wall of the accommodation cavity 141a, and the diffusion barrier layer 161 encloses a second trench that is not closed at both ends; the step of forming the gate conductive layer 151 includes: forming the gate conductive layer 151 located in the second trench.

[0118] In some embodiments, referring to Figure 11 , the accommodation cavity 141a includes a first sub-accommodation cavity 141b (refer to Figure 4 ) and a second sub-accommodation cavity 141c (refer to Figure 4 ) that are arranged in sequence along the first direction X. In some cases, referring to Figure 11 , on the basis of forming the diffusion barrier layer 161, the step of forming the gate conductive layer 151 includes: forming the gate conductive layer 151 that fills the remaining part of the first sub-accommodation cavity 141b; after forming the gate conductive layer 151, the manufacturing method may further include: forming an isolation layer 171 that fills the remaining part of the second sub-accommodation cavity 141c.

[0119] In other cases, the diffusion barrier layer may not be formed, and the step of forming the gate conductive layer includes: forming the gate conductive layer that fills the first sub-accommodation cavity; after forming the gate conductive layer, the manufacturing method may further include: forming the isolation layer that fills the second sub-accommodation cavity.

[0120] In some embodiments, referring to Figures 12 to 16 , the initial substrate 108 has a front surface 108a and a back surface 108b that are opposite to each other along the first direction X; forming the first electrical contact structure 103 may include the following steps:

[0121] Referring to Figure 12 , Figure 13 and Figure 16 , performing a second patterning process on the initial substrate 108 from the back surface 108b to form an opening 118 in the initial substrate 108 that exposes the initial substrate 108 that is aligned with the gate structure 101 along the first direction X; in combination with referring to Figure 12 and Figure 14 , performing a first doping process on the initial substrate 108 exposed by the opening 118 to form the first electrical contact structure 103 that is in contact connection with the gate structure 101. The steps of forming the opening 118 and the first electrical contact structure 103 will be described in detail below.

[0122] In other embodiments, in the step of performing a second patterning process on the initial substrate from the back surface, the formed opening may expose the gate dielectric layer in the gate structure; the step of forming the first electrical contact structure may be: forming a conductive layer in the opening that is in contact connection with the gate dielectric layer, and this conductive layer is the first electrical contact structure.

[0123] In some cases, before the step of performing second patterning on the initial substrate 108 from the back surface 108b, the manufacturing method further includes: thinning the initial substrate 108 from the back surface 108b, and the thinning process includes a CMP (Chemical Mechanical Polishing) process. In this way, it is convenient to expose the initial substrate 108 closer to the gate structure 101 in the first direction X through subsequent second patterning, so as to form the first electrical contact structure based on this subsequently, or it is convenient to expose the gate dielectric layer 141 in the gate structure 101 through subsequent second patterning.

[0124] In some embodiments, referring to Figure 12 , the gate structure 101 can be formed first and then second patterning is performed on the initial substrate 108. And before forming the gate structure 101, an initial active region 132 is formed in the initial substrate 108, and the initial substrate 108 exposed by the opening 118 is the initial active region 132. For the convenience of description, subsequent steps will be described in detail by taking the example of forming the gate structure 101 first and then performing second patterning on the initial substrate 108. In practical applications, second patterning on the initial substrate 108 and subsequent steps based on the opening 118 can also be performed according to requirements first, and then the gate structure 101 is formed.

[0125] Performing second patterning on the initial substrate 108 from the back surface 108b to form the opening 118 includes at least the following two embodiments.

[0126] In some embodiments, with reference to Figure 12 and Figure 13 , after performing second patterning on the initial substrate 108 from the back surface 108b, the opening 118 is a fourth trench 118a extending in the fourth direction P, and the fourth trench 118a is aligned with a plurality of gate structures 101 arranged at intervals in the fourth direction P. In some cases, with reference to Figure 12 and Figure 13 , a part of the bottom surface of the initial active region 132 exposed by the fourth trench 118a can be aligned with the first semiconductor channel 112 and / or the second semiconductor channel 122 in the first direction X.

[0127] It should be noted that Figure 13 is a partial rear view of the initial substrate with an opening formed in the manufacturing method provided by another embodiment of the present disclosure, Figure 12 which can be regarded as Figure 13 a schematic partial cross-sectional structure diagram of the semiconductor structure along the first cross-sectional direction AA1. In addition, to clearly show the relative positional relationship between the fourth trench 118a and the initial active region 132 in the rear view, Figure 13 the initial substrate 108 is drawn in a perspective manner in

[0128] In combination with reference Figure 13 and Figure 14 , the step of performing a first doping process on the initial substrate 108 exposed through the opening 118 may include: performing a first doping process on the initial active region 132 exposed through the fourth trench 118a to form a plurality of first electrical contact structures 103 arranged at P intervals in the fourth direction, and one first electrical contact structure 103 is in contact connection with one gate structure 101.

[0129] In combination with reference Figure 14 and Figure 15 , after forming the first electrical contact structures 103, the manufacturing method may further include: forming a bit line structure 106 in the opening 118. In other words, in combination with reference Figure 13 and Figure 15 , a bit line structure 106 extending in the fourth direction P is formed in the remaining region of the fourth trench 118a, that is, one fourth trench 118a corresponds to form one bit line structure 106, and one bit line structure 106 is in contact connection with a plurality of first electrical contact structures 103 arranged at P intervals in the fourth direction.

[0130] In other embodiments, in the step of performing a second patterning process on the initial substrate from the back side to form a fourth trench extending in the fourth direction, the fourth trench may expose the gate dielectric layer in the gate structure; the step of forming the first electrical contact structure may be: forming a conductive layer in the fourth trench in contact connection with the gate dielectric layer, and this conductive layer is the first electrical contact structure. Based on this, the first electrical contact structure can be regarded as a bit line structure. In some other embodiments, in combination with reference Figure 12 and Figure 16 , after performing a second patterning process on the initial substrate 108 from the back side 108b, a plurality of openings 118 are a plurality of through holes 118b arranged at intervals in the fourth direction P, and the through holes 118b are directly opposite to a plurality of gate structures 101 arranged at intervals in the fourth direction P one by one. In some cases, a part of the bottom surface of the initial active region 132 exposed by the through holes 118b may also be directly opposite to the first semiconductor channel 112 and / or the second semiconductor channel 122 in the first direction X.

[0131] It should be noted that Figure 16 is another partial rear view of the initial substrate with an opening formed in the manufacturing method provided by another embodiment of the present disclosure, Figure 12 which can be regarded as Figure 16 a partial cross-sectional structure schematic diagram of the semiconductor structure shown along the first cross-sectional direction AA1. In addition, to clearly show the relative positional relationship between the through holes 118b and the initial active region 132 in the rear view, Figure 16 the initial substrate 108 is drawn in a perspective manner in

[0132] With reference to Figure 16 and Figure 14 , the step of performing a first doping process on the initial substrate 108 exposed through the opening 118 may include: performing a first doping process on the initial active region 132 exposed through the via 118b to form a plurality of first electrical contact structures 103 arranged at intervals in the fourth direction P, and one first electrical contact structure 103 is in contact connection with one gate structure 101.

[0133] With reference to Figure 16 and Figure 17 , after forming the first electrical contact structure 103, the manufacturing method may further include: forming a partial region of the bit line structure 106 in the opening 118 (refer to Figure 13 ). In other words, a bit line contact block 116 is formed in the remaining region of the via 118b, that is, one via 118b corresponds to form one bit line contact block 116, the bit line contact blocks 116 and the first electrical contact structures 103 are in one-to-one correspondence, and the plurality of bit line contact blocks 116 are arranged at intervals in the fourth direction P and are in contact connection.

[0134] In other embodiments, in the step of performing a second patterning process on the initial substrate from the back side to form a plurality of vias arranged at intervals in the fourth direction, the vias may expose the gate dielectric layer in the gate structure, and the vias and the gate dielectric layer are in one-to-one correspondence; the step of forming the first electrical contact structure may be: forming a conductive layer in the via in contact connection with the gate dielectric layer, and this conductive layer is the first electrical contact structure. Based on this, the first electrical contact structure can be regarded as a bit line contact block.

[0135] With reference to Figure 17 , after forming the bit line contact blocks 116, the manufacturing method may further include: forming a bit line conductive layer 126 extending in the fourth direction P, and the same bit line conductive layer 126 is in contact connection with a plurality of bit line contact blocks 116 arranged at intervals in the fourth direction P. It should be noted that the bit line conductive layer 126 and the plurality of bit line contact blocks 116 in contact connection with the bit line conductive layer 126 and arranged at intervals in the fourth direction P together constitute the bit line structure 106.

[0136] In other embodiments, in the step of performing a second patterning process on the initial substrate from the back side to form a plurality of vias arranged at intervals in the fourth direction, the vias may expose the gate dielectric layer in the gate structure; after forming the first electrical contact structure, that is, the bit line contact block, a bit line conductive layer 126 extending in the fourth direction P may also be formed as shown in Figure 17 , and the same bit line conductive layer 126 is in contact connection with a plurality of first electrical contact structures arranged at intervals in the fourth direction P.

[0137] It should be noted that Figure 17A partial rear view of an initial substrate formed with a bit line structure in the manufacturing method provided by another embodiment of the present disclosure. In addition, to clearly show the bit line conductive layer 126 and its relative positional relationship in the rear view, Figure 17 a perspective drawing method is used for the bit line conductive layer 126. In some embodiments, referring to Figure 18 , the initial substrate 108 has a front surface 108a and a back surface 108b opposite to each other in the first direction X; forming the second electrical contact structure 114 and the third electrical contact structure 124 may include the following steps: performing a second doping process on different regions of the initial substrate 108 located outside the gate structure 101 from the front surface 108a, so as to form the second electrical contact structure 114 and the third electrical contact structure 124 on two opposite sidewalls of the gate structure 101 in the second direction Y respectively.

[0138] In some cases, with reference to Figure 15 and Figure 18 , the step of performing a second doping process on different regions of the initial substrate 108 located outside the gate structure 101 from the front surface 108a includes: performing a second doping process on the initial active regions 132 located on both sides of the gate structure 101 in the second direction Y from the front surface 108a, so that one side of the initial active region 132 is transformed into the second electrical contact structure 114 in contact connection with the first semiconductor channel 112, and the other side of the initial active region 132 is transformed into the third electrical contact structure 124 in contact connection with the second semiconductor channel 122. It should be noted that the initial active region 132 for the second doping process may be the initial semiconductor channel 102 that has not been divided into the first semiconductor channel 112 and the second semiconductor channel 122.

[0139] In some embodiments, with reference to Figure 18 and Figure 7 , the initial substrate 108 has a front surface 108a and a back surface 108b opposite to each other in the first direction X; the manufacturing method may further include: forming an electrical connection layer 107 on the front surface 108a, the electrical connection layer 107 is electrically connected to both the second electrical contact structure 114 and the third electrical contact structure 124, and one electrical connection layer 107 corresponds to one transistor 100; forming a capacitor structure 117 on the side of the electrical connection layer 107 away from the front surface 108a in the first direction X, and one capacitor structure 117 is electrically connected to one electrical connection layer 107.

[0140] It should be noted that another embodiment of the present disclosure does not limit the specific processes for forming the electrical connection layer 107 and the capacitor structure 117.

[0141] In some embodiments, the types of doping ions in the first electrical contact structure 103, the second electrical contact structure 114, and the third electrical contact structure 124 are the same. Then, the types of doping ions doped into different regions of the initial active region 132 in the first doping process and the second doping process are the same. On this basis, in some cases, the types of doping ions in the first electrical contact structure 103 and the initial semiconductor channel 102 are the same. Then, the types of doping ions doped into the initial active region 132 in the first doping process and the types of doping ions doped into the initial substrate 108 in the third doping process are the same, but the concentration of the doping ions doped into the initial active region 132 in the first doping process is higher than the concentration of the doping ions doped into the initial substrate 108 in the second doping process. In other cases, the types of doping ions in the first electrical contact structure 103 and the initial semiconductor channel 102 are different. Then, the types of doping ions doped into the initial active region 132 in the first doping process and the types of doping ions doped into the initial substrate 108 in the third doping process are different, and the type of the effective doping ions in the first electrical contact structure 103 is the type of the doping ions doped into the initial active region 132 in the first doping process.

[0142] In summary, in the formed semiconductor device, when a transistor 100 operates, two channel regions are generated. The two channel regions are respectively formed by the first semiconductor channel 112 and the second semiconductor channel 122, and the two channel regions are controlled by the same gate structure 101. One end of each of the two channel regions corresponds to the same first electrical contact structure 103, and the other ends of the two channel regions respectively correspond to the second electrical contact structure 114 and the third electrical contact structure 124. Moreover, on the one hand, the combined structure of the first electrical contact structure 103, the second electrical contact structure 114, and the third electrical contact structure 124 is designed to be directly opposite along the first direction X. When the two channel regions formed by the first semiconductor channel 112 and the second semiconductor channel 122 are conducting, the current mainly transmits along the first direction X, which is beneficial to shortening the length of the current transmission path in a single channel region, so as to improve the sensitivity of the channel region to conduct / turn off, and thus it is easier to control the conduction or turn off of the transistor 100, so as to improve the electrical performance of the transistor 100. On the other hand, one gate structure 101 controls two channel regions, and the two channel regions can be complementary to each other, which is beneficial to improving the sensitivity of the gate structure 101 to control the conduction or turn off of the transistor 100, so as to improve the electrical performance of the transistor 100. In addition, the transistor 100 extends as a whole along the first direction X, so multiple transistors 100 can be arranged in the plane perpendicular to the first direction X, which is beneficial to improving the integration density of the transistors 100 in the semiconductor device.

[0143] Those of ordinary skill in the art can understand that the above-described embodiments are specific examples for implementing the present disclosure. In actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A plurality of transistors arranged at intervals, each of the transistors comprising: A gate structure having a first portion, a second portion, and a third portion arranged in sequence in a first direction; A first semiconductor channel and a second semiconductor channel respectively covering two opposite sidewalls of the second portion in a second direction, the first direction intersecting the second direction; A first electrical contact structure in contact connection with the first portion and in contact connection with the first semiconductor channel and the second semiconductor channel; a second electrical contact structure and a third electrical contact structure respectively covering two opposite sidewalls of the third portion in the second direction.

2. The semiconductor structure according to claim 1, wherein The first electrical contact structure has a groove with an opening facing the first portion, and the first portion is located in the groove.

3. The semiconductor structure according to claim 1, wherein, The first semiconductor channel and the second semiconductor channel also respectively cover two opposite sidewalls of the first portion in the second direction; the first electrical contact structure is located on a side of the first portion away from the second portion in the first direction.

4. The semiconductor structure according to claim 1, wherein The gate structure includes: a gate dielectric layer and a gate conductive layer, wherein the first direction and the second direction form a projection plane, the positive projection shape of the gate dielectric layer on the projection plane is U-shaped, the U-shaped gate dielectric layer has a receiving cavity, and the gate conductive layer is located in the receiving cavity.

5. The semiconductor structure according to claim 1, characterized in that, Further comprising: Active regions corresponding to the transistors one by one; Wherein, both the first semiconductor channel and the second semiconductor channel are part of the active region, the active region has opposite first and second ends in the first direction, the first electrical contact structure is embedded in the first end, the second electrical contact structure and the third electrical contact structure are respectively embedded in different regions of the second end, and one active region corresponds to only one transistor.

6. The semiconductor structure according to claim 1, wherein Taking a plane perpendicular to the first direction as a reference plane, the positive projection of the first semiconductor channel on the reference plane is semicircular, triangular or N-sided; and / or, the positive projection of the second semiconductor channel on the reference plane is semicircular, triangular or N-sided, where N is a positive integer greater than or equal to 4.

7. A semiconductor device, characterized in that, Comprising: The semiconductor structure according to any one of claims 1 to 6.

8. The semiconductor device according to claim 7, wherein Further comprising: A word line structure extending in a third direction, one word line structure corresponding to the first semiconductor channel and the second semiconductor channel in at least one of the transistors, and the gate structure in one transistor is a partial region of the word line structure; A bit line structure extending in a fourth direction, the bit line structure being in contact connection with a side of at least one of the first electrical contact structures away from the gate structure in the first direction; Wherein, the third direction intersects the fourth direction, and both the third direction and the fourth direction intersect the first direction, and the second direction, the third direction and the fourth direction are in the same plane.

9. The semiconductor device according to claim 8, wherein, The third direction is the direction in which the multiple transistors are arranged at intervals. A plurality of the transistors arranged at intervals along the third direction share one word line structure, and different ones of the plurality of transistors sharing one word line structure correspond one-to-one to different bit line structures.

10. The semiconductor device according to claim 9, wherein, The multiple transistors are arranged at intervals along both the third direction and the fourth direction. A plurality of the transistors arranged at intervals along the fourth direction share one bit line structure, and different ones of the plurality of transistors sharing one bit line structure correspond one-to-one to different word line structures.

11. The semiconductor device according to claim 8, wherein, The included angle between the third direction and the fourth direction is 30° to 150°.

12. The semiconductor device according to claim 7, wherein, Further comprising: An electrical connection layer, one electrical connection layer corresponding to one transistor; wherein, the electrical connection layer is located on one side of the third portion away from the second portion along the first direction, and the electrical connection layer is electrically connected to both the second electrical contact structure and the third electrical contact structure; A capacitor structure, one capacitor structure being electrically connected to one electrical connection layer.

13. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing an initial substrate; Forming a plurality of transistors arranged at intervals in the initial substrate; Wherein, the step of forming the transistor comprises: Forming a gate structure, the gate structure having a first portion, a second portion, and a third portion arranged in sequence along a first direction; Forming a first semiconductor channel and a second semiconductor channel, the first semiconductor channel and the second semiconductor channel respectively covering two opposite sidewalls of the second portion along a second direction, the first direction and the second direction intersecting; forming a first electrical contact structure, the first electrical contact structure being in contact connection with the first portion, and in contact connection with the first semiconductor channel and the second semiconductor channel; Forming a second electrical contact structure and a third electrical contact structure, the second electrical contact structure and the third electrical contact structure respectively covering two opposite sidewalls of the third portion along the second direction.

14. The manufacturing method according to claim 13, characterized in that, The initial substrate has a front surface and a back surface opposite to each other along the first direction; The step of forming the first semiconductor channel, the second semiconductor channel, and the gate structure comprises: Forming an initial semiconductor channel in the initial substrate; performing a first patterning process on the initial semiconductor channel from the front surface to divide the initial semiconductor channel with at least a partial thickness in the first direction into the first semiconductor channel and the second semiconductor channel; Forming a gate dielectric layer, the gate dielectric layer being located between the first semiconductor channel and the second semiconductor channel, and a positive projection shape of the gate dielectric layer on a projection plane formed by the first direction and the second direction is U-shaped, and the U-shaped gate dielectric layer has a receiving cavity; Forming a gate conductive layer in the receiving cavity, the gate structure comprising the gate dielectric layer and the gate conductive layer.

15. The manufacturing method according to claim 13, wherein, The initial substrate has a front surface and a back surface opposite to each other along the first direction; The step of forming the first electrical contact structure comprises: Perform a second patterning process on the initial substrate from the back surface to form an opening in the initial substrate that exposes the initial substrate opposite to the gate structure along the first direction; Perform a first doping process on the initial substrate exposed by the opening to form the first electrical contact structure in contact connection with the gate structure.

16. The manufacturing method according to claim 15, characterized in that, Further comprising: Form a bit line structure in the opening, or form a partial region of the bit line structure in the opening.

17. The manufacturing method according to claim 13, characterized in that, The initial substrate has a front surface and a back surface opposite to each other along the first direction; The steps of forming the second electrical contact structure and the third electrical contact structure include: Perform a second doping process on different regions of the initial substrate located outside the gate structure from the front surface to form the second electrical contact structure and the third electrical contact structure on two sidewalls of the gate structure opposite to each other along the second direction, respectively.

18. The manufacturing method according to claim 13, characterized in that, The initial substrate has a front surface and a back surface opposite to each other along the first direction; The manufacturing method further comprises: Form an electrical connection layer on the front surface, the electrical connection layer is electrically connected to both the second electrical contact structure and the third electrical contact structure, and one electrical connection layer corresponds to one transistor; Form a capacitor structure on a side of the electrical connection layer away from the front surface along the first direction, and one capacitor structure is electrically connected to one electrical connection layer.

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