HEMT device with non-metallized gate

Abstract

The invention relates to an HEMT device with a non-metallized gate. An integrated circuit includes a first layer of III-N material (505) and a different second layer of III-N material (510) supported by the first layer of III-N material. A p-doped III-N material layer (520) over the second III-N material layer includes a wider portion having a first width in a first lateral direction parallel to the top surface, and a narrower portion (535) extending from the wider portion in a different second lateral direction parallel to the top surface, the narrower portion has a second width in the first lateral direction that is less than the first width.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor devices, and more particularly but not exclusively, to integrated circuits incorporating GaN-based transistor devices. Background Art

[0002] Gallium nitride (GaN) field effect transistors (FETs), sometimes referred to as high electron mobility transistors (HEMTs), offer advantages over silicon FETs in terms of weight, size, cost, switching speed, and energy consumption, and are used in applications such as 5G rectifiers, motor drivers, and AC-to-DC power converters, and can be used to power laptop computers and charge mobile device batteries. GaN devices come in enhancement-mode (e-GaN) and depletion-mode (d-GaN) types. Depletion-mode devices are normally on when their gate-source voltage is zero, while enhancement-mode FETs are normally off when their gate-source voltage is zero. Enhancement-mode FETs can be turned on by maintaining the gate voltage greater than the source voltage in an NMOS circuit and maintaining the gate voltage less than the source voltage in a PMOS circuit. Enhancement-mode FETs are commonly used as power switches. Summary of the Invention

[0003] The inventors disclose various methods and devices that can be advantageously applied to GaN-based FET devices and systems employing such devices. While such embodiments are expected to provide various benefits in a variety of usage applications, the present invention does not require specific results unless expressly recited in the specific claims.

[0004] One example is an integrated circuit that includes a first III-N material layer and a different second III-N material layer supported by the first III-N material layer. A p-doped III-N material layer above the second III-N material layer includes a wider portion having a first width in a first lateral direction parallel to the top surface, and a narrower portion extending from the wider portion in a different second lateral direction parallel to the top surface, the narrower portion having a second width less than the first width in the first lateral direction.

[0005] Another example is a transistor that includes a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer on the GaN layer. Source and drain contacts are spaced apart along the top surface of the AlGaN layer. A p-doped GaN (p-GaN) layer is located on the AlGaN layer and includes a metallized gate terminal portion and a non-metallized gate drive portion that extends from the gate terminal portion between the source and drain contacts.

[0006] Other examples include methods of manufacturing the devices described above. Brief Description of the Drawings

[0007] Figure 1A-1C A view illustrating an exemplary electronic device including a gate electrode having a terminal portion and a driving portion extending from the terminal portion;

[0008] Figure 2A-2D Illustrating various exemplary configurations of a gate electrode having a terminal portion and a driving portion;

[0009] Figure 3 A graph for showing the drive currents (I dsat ) of four populations of fabricated transistors, each population having one of four different gate lengths; and

[0010] Figure 4 is a graph showing Figure 3 the threshold voltages (V T ) of four populations of fabricated transistors shown in

[0011] Figure 5A -C to Figure 11A-11C Describing aspects of forming an exemplary electronic device in accordance with the principles of the present disclosure. Detailed Description

[0012] The present disclosure is described with reference to the accompanying drawings. The figures are not necessarily drawn to scale, and the figures are provided to illustrate the various described examples without implying limitation. Several aspects of the present disclosure are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the present disclosure. Unless otherwise stated, the present disclosure is not limited to the illustrated ordering of acts or events, as some acts may occur in a different order and / or concurrently with other acts or events. In addition, not all of the illustrated acts or events may be required to implement the method according to the present disclosure.

[0013] The present disclosure presents various methods and devices that can be advantageously applied to integrated circuits including GaN or other III-N field effect transistors (FETs) having a narrow gate length. Although it may be expected that such embodiments support scaling of transistor designs to dimensions that are not easily adaptable to current strategies for mitigating gate leakage, specific features or results are not required unless expressly recited in a particular claim.

[0014] Although the various embodiments of the present disclosure have been described above, it should be understood that they are presented by way of example and not limitation. Many changes may be made to the disclosed embodiments in light of the disclosure herein without departing from the spirit or scope of the present disclosure. Accordingly, the breadth and scope of the present invention should not be limited by any of the above-described embodiments. Indeed, the scope of the present disclosure should be defined in accordance with the appended claims and their equivalents.

[0015] HEMT transistors can operate according to the following principle: adjusting the conductivity in a portion of a two-dimensional electron gas (2DEG) formed by spontaneous polarization at the interface between different compound semiconductors (e.g., between aluminum gallium nitride (AlGaN) and gallium nitride (GaN)). In some baseline HEMTs, the gate structure includes a substantially metallized gate driving portion. For example, such a device may include a p-GaN gate above the AlGaN layer. Such baseline devices typically include a metal layer above the p-GaN gate. The metal layer can form a Schottky capacitance C between the metal layer and the p-GaN gate schottky , and the p-GaN gate can form a capacitance C between the p-GaN gate and the underlying AlGaN layer AlGaN . In a typical baseline device, the metal layer extends almost to the edge of the p-GaN gate to maximize C schottky . If the metal layer extends close to the edge of the p-GaN gate, excessive leakage from the metal layer to the AlGaN layer may occur, thereby degrading the performance of the transistor. Conversely, if the metal layer is too far from the edge of the p-GaN gate, C may be reduced schottky , thereby reducing the capacitive coupling to the AlGaN layer. This reduction can reduce the effectiveness of the p-GaN gate in controlling the current flow through the transistor

[0016] The inventors have found that, with appropriate device design, the metal layer can be omitted from the driving portion of the p-GaN gate structure. Although the driving portion has resistance, one or more metallized gate terminal portions directly connected to the driving portion may be sufficient to control the channel conductance of the transistor, thereby avoiding problems related to gate metallization leakage. Devices formed according to such principles and according to the examples described herein may have a gate length shorter than that of similar baseline devices, while eliminating performance variations that may otherwise exist between devices due to manufacturing variations

[0017] Figure 1A-1C A view of an example transistor 100 in accordance with various aspects of the present disclosure is presented Figure 1A is a plan view of transistor 100, and Figure 1B and 1C are cross-sectional views taken at two positions of transistor 100 marked along Figure 1A . It should be noted that Figure 1B and 1C The features in may not necessarily be drawn to the same scale as the same features in Figure 1A . First, refer to Figure 1A, the transistor includes a gate electrode 105 over an active region 110. The gate electrode 105 includes a wider gate terminal portion 115 and a narrower gate driving portion 120. As used herein, "driving portion" and like terms refer to the portion of the gate electrode 105 that is located over the channel region of the transistor 100, e.g., the portion of the transistor 100 through which current flows when the transistor 100 is configured in an appropriate manner. According to common transistor nomenclature, the gate driving portion 120 has a gate length L g and a gate width W g . The gate driving portion 120 extends from the gate terminal portion 115 between a pair of source / drain (S / D) contacts 125. The gate terminal portion 115 is metallized and has a metal layer 130 located thereabove ( Figure 1A and 1C ). In contrast, the gate driving portion 120 is not metallized and thus no metal layer is formed thereabove.

[0018] The transistor 100 is an enhancement-mode or "e-type" transistor. For such a device, a gap is formed under the gate driving portion 120 in the 2DEG (indicated by the dashed line in Figure 1B ) such that the transistor 100 is non-conductive or off in the absence of a bias voltage applied to the gate electrode 105. It should be noted that the 2DEG is also suppressed under the gate terminal portion 115.

[0019] Figure 2A-2D Illustrate various configurations of the HEMT gate according to the present disclosure. Figure 2A The "dogbone" configuration 210 is shown, where the gate driving portion extends between one or more (e.g., three) pairs of source / drain contacts from a first gate terminal portion to a second gate terminal portion. Figure 2B The second configuration 220 is shown, where the gate driving portion extends only from a single gate terminal portion, e.g., as illustrated in Figure 1A . Figure 2C The configuration 230 is illustrated, which includes a plurality (at least three) of gate terminal portions spaced apart in a linear manner, where the gate driving portion extends from each gate terminal portion to the nearest neighboring gate terminal portion. And Figure 2D the example configuration 240 is illustrated, where a plurality of gate driving portions extend in parallel from a single gate terminal portion. Each of the example configurations 210, 220, 230, and 240 may include any number of source / drain contacts determined to meet the performance specifications of the device. It is expected that in various instances, the gate driving portion may extend from the gate terminal portion by up to at least 10 μm (or 20 μm between two gate terminal portions) without significantly degrading the transistor performance parameters due to, e.g., the resistivity of the gate material.

[0020] Figure 3 Present the saturation current I DsatA series of box plots, such as for a device conforming to Configuration 210, which for example does not have metal over the gate in the active region of a transistor and has a gate width of approximately 13 μm. Four different device populations with gate lengths of 1.4 μm, 1.1 μm, 0.8 μm, and 0.5 μm are shown. This figure shows that, despite the lack of metallization on the gate, I dsat scales approximately linearly with decreasing gate width, indicating an effective coupling between the gate and the underlying AlGaN layer.

[0021] Figure 4 Present Figure 3 a series of box plots of the threshold voltage V of the example devices represented in T . This figure shows that V T is approximately constant over the example range of gate lengths, indicating a consistent operating voltage and feasibility for use in circuits that would otherwise use a metallized gate structure.

[0022] Turning now to Figure 5A-5C 11A - 11C, an example method of manufacturing an integrated circuit (IC) is described, the integrated circuit including a transistor 500 that is consistent with transistor 100 and example configurations 210 - 240. In some instances, and as illustrated, transistor 500 is an e-type transistor. Figure 5A-11A Illustrates a plan view of transistor 500, Figure 5B-11B shows a first cross-sectional view labeled in the corresponding plan view, and Figure 5C-11C shows a second cross-sectional view labeled in the corresponding plan view. Unless further differentiation between the figures is needed for clarity, each set of corresponding figures may be described together.

[0023] Figure 5A-5CDescribe the transistor 500 in the early stage of manufacturing. The substrate 501 supports the first compound semiconductor layer 505 and the second compound semiconductor layer 510. The 2DEG, represented by a dashed line, is formed in the layer 505 near the interface with the layer 510. In various examples, the layers 505 and 510 can be implemented as a GaN layer and an AlGaN layer respectively, or any two semiconductor materials that form a 2DEG at the interface. In this context, the layer 510 can be regarded as a barrier layer. Such semiconductor materials can generally be referred to as "III-N" materials, and contain one or more elements of Group III of the periodic table (such as Al, Ga, and In) and nitrogen. In addition to GaN and AlGaN, other III-N materials also include compounds with the general empirical formula In(x)Al(y)Ga(1 - x - y)N, non-limiting examples include InAlN, AlN, and InAlGaN. In the remaining discussion, the layer 505 can be referred to as the "first III-N layer 505", and the layer 510 can be referred to as the "second III-N layer 510". The 2DEG is located within the active region 515. Outside the active region, the 2DEG may be damaged or destroyed by an amorphous implant (such as argon (Ar) or other non-doped ion species). The active region 515, similar to the active region 110 ( Figure 1A ), defines the lateral perimeter of the transistor 500. Several stress compensation layers between the substrate 501 (which can be a silicon wafer or die) and the first III-N layer 505 are not explicitly shown. Such stress compensation layers are well known in the art and are therefore not described in more detail.

[0024] Figure 6A-6C Describe the transistor 500 after forming the doped semiconductor layer 520 above the second III-N layer 510. Consistent with forming an e-type device, the semiconductor layer 520 is doped p-type, for example, doped with magnesium (Mg). Such materials can generally be referred to as "p-doped III-N" materials. In the remaining discussion, the layer 520 can be referred to as the "p-doped III-N layer 520". The presence of the p-doped III-N layer 520 suppresses the 2DEG in the active region 515, which is reflected by the absence of the dashed line at the interface between the first III-N layer 505 and the second III-N layer 510. Not shown, a dielectric passivation layer such as a SiN thin layer can be formed above the p-doped III-N layer 520.

[0025] Next, refer to Figure 7A-7C, the gate structure 525 is formed by patterning and removing a portion of the p-doped III-N layer 520. The gate structure 525 has a shape commonly referred to as a "dog bone" shape, and has two wider gate terminal portions 530 having a first width in a first lateral direction parallel to the top surface of the second III-N layer 510, and a narrower gate drive portion 535 extending from one gate terminal portion 530 to the other gate terminal portion 530. The gate drive portion 535 has a second width less than the first width in the first lateral direction. As Figure 7B and 7C illustrated, the removal of the p-doped III-N layer 520 allows the 2DEG to reform at the interface between the second III-N layer 510 and the first III-N layer 505, but there is no 2DEG under the gate terminal portions 530 and the gate drive portion 535.

[0026] Figure 8A-8C FIG. shows the transistor 500 after forming a dielectric layer 540 that may be or include, for example, SiN over the gate structure 525. If the surface shape of the top surface is undesirable, the top surface of the dielectric layer 540 can be planarized, for example, by CMP. Source / drain contact openings 545 have been formed by photolithographic patterning and etching to produce, in one non-limiting example, three pairs of source / drain contact openings 545 that extend to the top surface of the first III-N layer 505.

[0027] In Figure 9A-9C , a contact liner 550 has been formed within the source / drain contact openings 545 ( Figure 9A and 9B ). The contact liner 550 directly contacts the first III-N layer 505 and forms an ohmic contact to the 2DEG. In one non-limiting example, the contact liner 550 can include a first sub-layer of Ti, followed by AlCu, TiN, and W. These conductive layers can be formed by physical vapor deposition (PVD) and / or chemical vapor deposition (CVD) techniques.

[0028] Figure 10A-10C FIG. illustrates the transistor 500 after forming gate contact openings 555 ( Figure 10A and 10C ) over the gate terminal portions 530. The gate contact openings can be formed by photolithographic patterning and etching to remove the dielectric layer 540 over the gate terminal portions 530. Although the size of the gate contact openings 555 is not limited to any particular value, it can have a lateral extent approximately equal to the lateral extent of the gate terminal portions 530, but with a small annular offset, which is consistent with reducing leakage between the subsequently formed metal gate terminal contacts and the second III-N layer 510.

[0029] Figure 11A-11C5. The transistor 500 is shown after a gate contact 560 is formed over the gate terminal portion 530. Figure 11A and 11C ). The gate contact 560 may be implemented by a layer of TiW to provide a conductive connection to the gate terminal portion 530 and subsequently formed metal interconnects. Additional processing may be performed as needed to connect the transistor 500 to other devices of the integrated circuit. It should be noted that process sequences that differ from the process sequence shown are within the scope of the present disclosure, such as forming the gate contact 560 before forming the contact liner 550. Additional background is described in U.S. Patent Application No. 2022 / 0399328A, which is incorporated herein by reference in its entirety.

[0030] In contrast to a similar baseline transistor, the metal layer forming gate contact 560 does not extend over gate drive portion 535. The omission of metallization over gate drive portion 535 avoids the potential for leakage from such metallization that might otherwise exist, thereby simplifying scaling of the device to sizes that are not easily accommodated by the design layer.

Claims

1. An integrated circuit IC, comprising: a first III-N material layer; a second, different III-N material layer supported by the first III-N material layer, the second III-N material layer having a top surface; as well as and a p-doped III-N material layer over the top surface of the second III-N material layer, the p-doped III-N material layer comprising a wider portion having a first width in a first lateral direction parallel to the top surface, and a narrower portion extending from the wider portion in a second, different lateral direction parallel to the top surface, the narrower portion having a second width in the first lateral direction that is less than the first width. 2 . The IC of claim 1 , further comprising a metal layer on the p-doped III-N material layer, the metal layer being confined to the wider portion. 3 . The IC of claim 1 , wherein the narrower portion is located between first and second ohmic contacts to the second III-N material layer. 4 . The IC of claim 1 , wherein the wider portion is a first wider portion and further comprises a second wider portion, the narrower portion extending from the first wider portion to the second wider portion.

5. The IC of claim 1, wherein the narrower portion is a first narrower portion, and the IC additionally comprises a second narrower portion extending from the wider portion in the second lateral direction. The IC of claim 1 , wherein the second III-N material layer comprises AlGaN. The IC of claim 6 , wherein the p-doped III-N material layer comprises GaN.

8. A transistor comprising: Gallium nitride (GaN) layer; an aluminum gallium nitride (AlGaN) layer on the GaN layer; source and drain contacts spaced apart along a top surface of the AlGaN layer; as well as A p-doped GaN (p-GaN) layer is on the AlGaN layer, the p-GaN layer including a metallized gate terminal portion and a non-metallized gate drive portion extending from the gate terminal portion between the source and drain contacts. 9 . The transistor of claim 8 , wherein the gate terminal portion has a first width in a lateral direction parallel to the top surface, and the gate driving portion has a smaller second width in the lateral direction.

10. The transistor of claim 8, wherein the gate drive portion extends between a plurality of pairs of source and drain contacts.

11. The transistor of claim 8, wherein the metallized gate terminal portion is a first metallized gate terminal portion, and the gate drive portion extends from the first metallized gate terminal portion to a second metallized gate terminal portion. 12 . The transistor of claim 8 , wherein the gate driving portion is a first gate driving portion, and the transistor further comprises a second gate driving portion extending from the gate terminal portion.

13. The transistor of claim 11, wherein the gate terminal portion is a first metallized gate terminal portion, and a second gate drive portion extends from the second metallized gate terminal portion to a third gate terminal portion.

14. The transistor of claim 8, wherein the gate driving portion has a length of at least about 10 μm.

15. A method of forming an integrated circuit, comprising: forming a gallium nitride (GaN) layer over a semiconductor substrate; forming an AlGaN layer on the GaN layer; as well as A p-doped GaN (p-GaN) layer is formed on the AlGaN layer, the p-GaN layer including a gate terminal portion having a first width in a lateral direction and a gate driving portion extending from the gate terminal portion and having a second width in the lateral direction, the first width being greater than the second width.

16. The method of claim 15, further comprising masking the gate driving portion and forming a metal layer on the gate terminal portion.

17. The method of claim 15, further comprising forming first and second ohmic contacts to the AlGaN layer, the gate drive portion extending between the first and second ohmic contacts.

18. The method of claim 15, wherein the gate terminal portion is a first gate terminal portion, and the method further comprises forming a second gate terminal portion spaced apart from the first gate terminal portion, the gate driving portion extending from the first gate terminal portion to the second gate terminal portion.

19. The method of claim 18, further comprising forming a third gate terminal portion spaced apart from the second gate terminal portion, and forming a second gate driving portion extending from the second gate terminal portion to the third gate terminal portion.

20. The method of claim 15, wherein the gate driving portion is a first gate driving portion, and the method further comprises forming a second gate driving portion extending from the gate terminal portion.

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