Laterally diffused metal oxide semiconductor field effect transistor and manufacturing method thereof

Abstract

The invention relates to a laterally diffused metal oxide semiconductor field effect transistor and a manufacturing method thereof, and the laterally diffused metal oxide semiconductor field effect transistor comprises the components of a substrate which has a second conductive type; a buffer region located in the substrate and having a first conductive type; the buried region is located on the buffer region, the buried region has a first conduction type, and the doping concentration of the buffer region is smaller than that of the buried region; the first conductive type and the second conductive type are opposite; the second conduction type region is located on the buried region and has a second conduction type; the LDMOS main body structure comprises a source electrode region, a drain electrode region and a grid electrode, the drain electrode region is located above the buried region, and the source electrode region is located in the second conduction type region. When the body diode freewheeling is carried out, the parasitic triode generates a Kirk effect in a buffer region, so that the amplification coefficient of the parasitic triode is rapidly reduced, and the leakage current of the substrate is also reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a laterally diffused metal oxide semiconductor field effect transistor, and also to a manufacturing method of a laterally diffused metal oxide semiconductor field effect transistor. Background Art

[0002] In an exemplary N-channel laterally diffused metal oxide semiconductor field effect transistor (NLDMOS) with a junction isolation structure, when the body diode of the NLDMOS is in a freewheeling state, due to the presence of a longitudinal parasitic PNP, a large substrate current (leakage current) will be generated, and this substrate current will cause a series of problems such as product failure. Summary of the Invention

[0003] Based on this, it is necessary to provide a laterally diffused metal oxide semiconductor field effect transistor with a very small substrate current when the body diode is in freewheeling.

[0004] A laterally diffused metal oxide semiconductor field effect transistor includes: a substrate having a second conductivity type; a buffer region located in the substrate and having a first conductivity type; a buried region located on the buffer region, the buried region having a first conductivity type, and the doping concentration of the buffer region being less than that of the buried region; the first conductivity type and the second conductivity type being opposite conductivity types; a second conductivity type region located on the buried region and having a second conductivity type; an LDMOS main structure including a source region, a drain region, and a gate, the drain region being located above the buried region, and the source region being located in the second conductivity type region.

[0005] In the above laterally diffused metal oxide semiconductor field effect transistor, when the body diode of the LDMOS is in freewheeling, the buffer region with a low doping concentration will be in a depleted state. As the current of the body diode gradually increases, the parasitic triode composed of the second conductivity type region - buried region - buffer region - substrate will have a base width expansion effect (Kirk effect) in the buffer region, thereby rapidly decreasing the amplification factor of the parasitic triode and also reducing the leakage current of the substrate.

[0006] In one embodiment, the source region and the drain region have a first conductivity type.

[0007] In one embodiment, the laterally diffused metal oxide semiconductor field effect transistor further includes a first well region, the first well region being located on the buried region, and the first well region forming a surrounding wall structure in the lateral direction, the surrounding wall structure and the buried region at the bottom forming an enclosing structure, the first well region having a first conductivity type; the second conductivity type region and the drain region are located within the enclosing structure.

[0008] In one embodiment, the second conductivity type region includes a body region, and the source region is located in the body region.

[0009] In one embodiment, the second conductivity type region includes a first doped region, the first doped region is located in the surrounding structure and has a second conductivity type; the LDMOS body structure further includes a drift region of a first conductivity type, the drift region is located within the surrounding structure, at least part of the structure of the drift region is located between the source region and the drain region, the bottom of the drift region is separated from the buried region by the first doped region, at least part of the structure of the gate is located above the drift region between the source region and the drain region, and the drain region is in direct contact with the drift region.

[0010] In one embodiment, the bottom of the buried region is in direct contact with the top of the buffer region.

[0011] In one embodiment, the laterally diffused metal oxide semiconductor field effect transistor further includes a second well region, the second well region has a second conductivity type, and the second well region is located outside the first well region and is in direct contact with the substrate.

[0012] In one embodiment, the laterally diffused metal oxide semiconductor field effect transistor is an N-channel laterally diffused metal oxide semiconductor field effect transistor, the first conductivity type is N-type, and the second conductivity type is P-type.

[0013] It is also necessary to provide a manufacturing method for a laterally diffused metal oxide semiconductor field effect transistor.

[0014] A manufacturing method for a laterally diffused metal oxide semiconductor field effect transistor includes: obtaining a substrate formed with a buffer region and a buried region; the substrate has a second conductivity type, the buffer region and the buried region have a first conductivity type, the buried region is located on the buffer region, and the doping concentration of the buffer region is less than that of the buried region; the first conductivity type and the second conductivity type are opposite conductivity types; forming a second conductivity type region on the buried region; forming an LDMOS body structure; the LDMOS body structure includes a source region, a drain region and a gate, the drain region is formed above the buried region, and the source region is formed in the second conductivity type region.

[0015] In the manufacturing method of the above-mentioned laterally diffused metal oxide semiconductor field effect transistor, when the formed LDMOS has body diode freewheeling, the buffer region with a low doping concentration will be in a depleted state. As the current of the body diode gradually increases, the parasitic triode composed of the second conductivity type region - buried region - buffer region - substrate will have a base width expansion effect (Kirk effect) in the buffer region, so that the amplification factor of the parasitic triode will rapidly decrease, and the leakage current of the substrate will also decrease.

[0016] In one embodiment, it further includes the step of forming a first well region on the buried region; the first well region forms a surrounding wall structure in the transverse direction, and the surrounding wall structure and the buried region at the bottom form an enclosed structure, and the second conductivity type region and the drain region are located within the enclosed structure, and the first well region has a first conductivity type.

[0017] In one embodiment, the step of forming a second conductivity type region on the buried region includes: forming an epitaxial layer of a second conductivity type on the substrate; forming a body region and a first doped region located within the enclosed structure in the epitaxial layer; the body region and the first doped region have a second conductivity type, the second conductivity type region includes the body region and the first doped region, and the source region is located in the body region; the step of forming a first well region on the buried region includes: forming a first well region in the epitaxial layer.

[0018] In one embodiment, the method further includes the step of forming a drift region; the drift region has a first conductivity type, the drift region is located within the enclosed structure, the bottom of the drift region is separated from the buried region by the first doped region, at least part of the structure of the drift region is located between the source region and the drain region, at least part of the structure of the gate is located above the drift region between the source region and the drain region, and the drain region is in direct contact with the drift region.

[0019] In one embodiment, the doping concentration of the first doped region is 2 to 3 orders of magnitude higher than that of the epitaxial layer.

[0020] In one embodiment, it further includes the step of forming a second well region; the second well region has a second conductivity type, the second well region is located outside the first well region and is in direct contact with the substrate. Description of the Drawings

[0021] To better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, and the currently understood best mode of these inventions.

[0022] Figure 1 is a schematic cross-sectional structure diagram of a laterally diffused metal oxide semiconductor field effect transistor in an embodiment of the present application;

[0023] Figure 2 is a flowchart of a manufacturing method of a laterally diffused metal oxide semiconductor field effect transistor in an embodiment of the present application;

[0024] Figure 3a and Figure 3b is the schematic cross-sectional structure diagram of the device in the process of manufacturing LDMOS by using the method shown in Figure 2 . Detailed implementation manners

[0025] For the convenience of understanding the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present invention is thorough and complete.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention belongs. The terms used in the description of the present invention herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0027] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or part discussed below may be denoted as a second element, component, region, layer or part without departing from the teachings of the present invention.

[0028] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under other elements" or "beneath them" or "below them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0029] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0030] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. As such, variations from the shapes as shown, for example due to manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present invention.

[0031] The semiconductor field vocabulary used herein is common technical vocabulary for those skilled in the art. For example, for P-type and N-type impurities, to distinguish the doping concentrations, simply P+ type represents P-type with a high doping concentration, P-type represents P-type with a medium doping concentration, P- type represents P-type with a low doping concentration, N+ type represents N-type with a high doping concentration, N-type represents N-type with a medium doping concentration, and N- type represents N-type with a low doping concentration.

[0032] When an exemplary NLDMOS conducts current through its body diode, in order to suppress the turn-on of the longitudinal parasitic PNP, an N+ buried layer with a relatively large thickness (longitudinal width) and a relatively high concentration is usually adopted to reduce substrate leakage current. However, due to process capabilities and the solubility of N-type impurities in silicon, the amplification factor of the longitudinal parasitic PNP cannot be further reduced.

[0033] Figure 1 It is a schematic cross-sectional structure diagram of a laterally diffused metal oxide semiconductor field effect transistor in an embodiment of the present application. Figure 1 The shown structure is symmetric left and right, so only the structure on one side is labeled. The laterally diffused metal oxide semiconductor field effect transistor includes a substrate 210, a buffer region 222, a buried region 232, a region of the second conductivity type, and an LDMOS main structure. The substrate 210 has the second conductivity type. The buffer region 222 is located in the substrate 210 and has the first conductivity type. The buried region 232 is located on the buffer region 222. The buried region 232 has the first conductivity type, and the doping concentration of the buffer region 222 is less than that of the buried region 232. In Figure 1 the shown embodiment, the bottom of the buried region 232 is in direct contact with the top of the buffer region 222. The region of the second conductivity type is located on the buried region 232. The LDMOS main structure includes a source region 244, a drain region 242, and a gate 252. The drain region 242 is located above the buried region 232, and the source region 244 is located in the region of the second conductivity type. The source region 244 and the drain region 242 have the first conductivity type. In one embodiment of the present application, the region of the second conductivity type includes a body region 234. The source region 244 is located in the body region 234. In Figure 1 the shown embodiment, the laterally diffused metal oxide semiconductor field effect transistor is an NLDMOS. Correspondingly, the first conductivity type is N-type, and the second conductivity type is P-type; in other embodiments, the laterally diffused metal oxide semiconductor field effect transistor can also be a PLDMOS, the first conductivity type is P-type, and the second conductivity type is N-type.

[0034] For the above-mentioned laterally diffused metal oxide semiconductor field effect transistor, when the body diode of the LDMOS conducts current, the buffer region 222 with a low doping concentration will be in a depleted state. As the current of the body diode gradually increases, the collector junction (including the buffer region 222) of the parasitic triode composed of the region of the second conductivity type - the buried region 232 - the buffer region 222 - the substrate 210 will undergo the base-width modulation effect (Kirk effect), thereby causing the amplification factor of the parasitic triode to rapidly decrease, and the leakage current of the substrate 210 will also decrease, which can improve the application current capacity of the LDMOS.

[0035] In an embodiment of the present application, the doping concentration of the buffer region 222 is 2 to 3 orders of magnitude lower than that of the buried region 232 to ensure that the base broadening effect can occur when the body diode of the LDMOS conducts a continuous current and the current is relatively large.

[0036] In an embodiment of the present application, the laterally diffused metal oxide semiconductor field effect transistor further includes a first well region 226. The first well region 226 has a first conductivity type. The first well region 226 is located on the buried region 232, and the first well region 226 forms a surrounding wall structure in the transverse direction, that is, a surrounding region of a first conductivity type with a certain height. The bottom of the first well region 226 is in direct contact with the buried region 232, and the surrounding wall structure and the buried region 232 at the bottom form a surrounding structure that surrounds the perimeter and the bottom. The second conductivity type region and the drain region 242 are located within this surrounding structure.

[0037] In an embodiment of the present application, the second conductivity type region includes a first doped region 224. The first doped region 224 is located within this surrounding structure and has a second conductivity type. The LDMOS main structure further includes a drift region 236 of a first conductivity type. The drift region 236 is located within the surrounding structure, at least a part of the structure of the drift region 236 is located between the source region 244 and the drain region 242, and the bottom of the drift region 236 is separated from the buried region 232 by the first doped region 224. The gate 252 is located above the region between the source region 244 and the drain region 242, and at least a part of the structure of the gate 252 is located above the drift region 236 between the source region 244 and the drain region 242. The drain region 242 is in direct contact with the drift region 236 and, further, can be located within the drift region 236.

[0038] In an embodiment of the present application, the laterally diffused metal oxide semiconductor field effect transistor further includes a second well region 228. The second well region 228 has a second conductivity type, and the second well region 228 is located outside the first well region 226 and is in direct contact with the substrate 210.

[0039] In an embodiment of the present application, the doping concentrations of the source region 242 and the drain region 244 are greater than the doping concentration of the drift region 236.

[0040] In an embodiment of the present application, the substrate 210 is a semiconductor substrate, and its material can be undoped single crystal silicon, doped single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), etc. In Figure 2 In the illustrated embodiment, the constituent material of the substrate 210 is selected as single crystal silicon of a second conductivity type.

[0041] In one embodiment of the present application, the material of the gate 252 is polysilicon material. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds can also be used as the gate material. In one embodiment of the present application, a gate dielectric layer is further provided under the gate 252 ( Figure 1 not shown in the figure). The gate dielectric layer can include traditional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant ranging from about 4 to about 20 (measured in a vacuum). Alternatively, the gate dielectric layer can include dielectric materials with a generally higher dielectric constant ranging from about 20 to at least about 100. Such higher dielectric constant dielectric materials can include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs). The gate 252 can extend above the source region 244 or to the edge of the source region 244, that is, form an overlap with a partial region at the edge of the source region 244, or be tangent to the edge of the source region 244.

[0042] In one embodiment of the present application, the laterally diffused metal oxide semiconductor field effect transistor further includes a first body lead-out region 223 located in the first doped region 224. The first body lead-out region 223 has a second conductivity type, and its doping concentration is greater than that of the first doped region 224. In one embodiment of the present application, the laterally diffused metal oxide semiconductor field effect transistor further includes a second body lead-out region 246 located in the body region 234. The second body lead-out region 246 has a second conductivity type, and its doping concentration is greater than that of the body region 234. In one embodiment of the present application, the laterally diffused metal oxide semiconductor field effect transistor further includes a substrate lead-out region 229 located in the second well region 228. The substrate lead-out region 229 has a second conductivity type, and its doping concentration is greater than that of the second well region 228. In one embodiment of the present application, the laterally diffused metal oxide semiconductor field effect transistor further includes a buried layer lead-out region 225 located in the first well region 226. The buried layer lead-out region 225 has a first conductivity type, and its doping concentration is greater than that of the first well region 226.

[0043] In one embodiment of the present application, a field oxide layer 254 is further formed on the drift region 236. The gate 252 extends from the edge of the source region 244 to the field oxide layer 254. The drain region 242 is located on the side of the field oxide layer 254 away from the gate 252.

[0044] In one embodiment of the present application, the laterally diffused metal oxide semiconductor field effect transistor further includes an insulating isolation structure 272. Further, the insulating isolation structure 272 can be a shallow trench isolation structure (STI). The insulating isolation structure 272 can be disposed between the substrate lead-out region 229 and the buried layer lead-out region 225, between the buried layer lead-out region 225 and the first body lead-out region 223, between the first body lead-out region 223 and the drain region 242, and other positions.

[0045] In an embodiment of the laterally diffused metal oxide semiconductor field effect transistor (NLDMOS), the substrate 210 is a P-type substrate, the buffer region 222 is an N- region, the buried region 232 is an N+ buried layer, the first well region 226 is an N well, the buried layer lead-out region 225 is an N+ region, the second well region 228 is a P well, the substrate lead-out region 229, the first body lead-out region 223 and the second body lead-out region 246 are P+ regions, the drift region 236 is an N-type drift region, and the source region 244 and the drain region 242 are N+ regions.

[0046] The present application correspondingly provides a manufacturing method for a laterally diffused metal oxide semiconductor field effect transistor, which can be used to manufacture the laterally diffused metal oxide semiconductor field effect transistor described in any of the foregoing embodiments. Figure 2 FIG. is a flowchart of a manufacturing method for a laterally diffused metal oxide semiconductor field effect transistor according to an embodiment of the present application, including the following steps:

[0047] S210, obtaining a substrate formed with a buffer region and a buried region.

[0048] The substrate 210 has a second conductivity type, and the buffer region 222 and the buried region 232 have a first conductivity type. The buried region 232 is located on the buffer region 222, and the doping concentration of the buffer region 222 is less than that of the buried region 232.

[0049] In an embodiment of the present application, first, patterning (such as lithography) and ion implantation (implanting ions of the first conductivity type) of the buffer region 222 are performed in the substrate 210, and then the well is pushed; then, patterning (such as lithography) and ion implantation (implanting ions of the first conductivity type) of the buried region 232 are performed, and then the well is pushed, so as to form the buffer region 222 and the buried region 232.

[0050] In an embodiment of the present application, the substrate 210 is a semiconductor substrate, and its material can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), and germanium on insulator (GeOI), etc. In an embodiment of the present application, the first conductivity type is N-type, and the second conductivity type is P-type; in other embodiments, the first conductivity type is P-type, and the second conductivity type is N-type.

[0051] S220, forming a region of the second conductivity type on the buried region.

[0052] In an embodiment of the present application, step S220 includes growing an epitaxial layer 212 of the second conductivity type on the buried region 232, referring to Figure 3a .

[0053] S230, form the LDMOS body structure.

[0054] The LDMOS body structure includes a source region 244, a drain region 242, and a gate 252. The drain region 242 is formed above the buried region 232, and the source region 244 is formed in the second conductivity type region.

[0055] In the manufacturing method of the above-mentioned laterally diffused metal oxide semiconductor field effect transistor, when the body diode of the LDMOS conducts a continuous current, the low-doping-concentration buffer region 222 will be in a depleted state. As the current of the body diode gradually increases, the parasitic triode composed of the second conductivity type region - the buried region 232 - the buffer region 222 - the substrate 210 will have a base-width-expansion effect (Kirk effect) in the buffer region 222, thereby causing the amplification factor of the parasitic triode to rapidly decrease, and the leakage current of the substrate 210 will also decrease.

[0056] In an embodiment of the present application, an insulating isolation structure 272 may be formed after the epitaxial layer 212 is formed. Further, the insulating isolation structure 272 may be a shallow trench isolation structure (STI).

[0057] In an embodiment of the present application, after the insulating isolation structure 272 is formed, a first well region 226, a first doped region 224, and a body region 234 may also be formed by patterning (such as lithography) and ion implantation, referring to Figure 3b ... The first well region 226 has a first conductivity type. The first well region 226 forms a surrounding wall structure in the lateral direction, and this surrounding wall structure and the buried region 232 at the bottom form an enclosing structure. The drain region 242 is located within the enclosing structure. The second conductivity type region is a semiconductor structure with a second conductivity type within the enclosing structure, specifically including the first doped region 224, the body region 234, and the epitaxial layer 212 within the enclosing structure. The first doped region 224 is used to prevent current from flowing longitudinally into the substrate 210. In an embodiment of the present application, the doping concentration of the first doped region 224 is 2 to 3 orders of magnitude higher than that of the epitaxial layer 212.

[0058] In an embodiment of the present application, a drift region 236 may also be formed by patterning (such as lithography) and ion implantation after the insulating isolation structure 272 is formed. The drift region 236 has a first conductivity type. The drift region 236 is located within the enclosing structure. The bottom of the drift region 236 is separated from the buried region 232 by the first doped region. At least part of the structure of the drift region 236 is located between the source region 244 and the drain region 242, and at least part of the structure of the gate 252 is located above the drift region 236 between the source region 244 and the drain region 242. The drain region 242 is in direct contact with the drift region 236, and further, it may be located within the drift region 236.

[0059] In one embodiment of the present application, after forming the insulating isolation structure 272, the second well region 228 can also be formed by patterning (such as lithography) and ion implantation. The second well region 228 has a second conductivity type, and the second well region 228 is located outside the first well region 226 and is in direct contact with the substrate 210.

[0060] In one embodiment of the present application, after step S220, forming a P+ region and an N+ region is included, including a source region 244, a drain region 242, a first body lead-out region 223 in the first doped region 224, a second body lead-out region 246 in the body region 234, a substrate lead-out region 229 in the second well region 228, and a buried layer lead-out region 225 in the first well region 226. The device structure after step S230 can be referred to Figure 1 .

[0061] In one embodiment of the present application, the material of the gate 252 is polysilicon material. In other embodiments, metals, metal nitrides, metal silicides or similar compounds can also be used as the gate material. In one embodiment of the present application, a gate dielectric layer is further provided under the gate 252. The gate dielectric layer can include traditional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant ranging from about 4 to about 20 (measured in vacuum), or the gate dielectric layer can include dielectric materials having a generally higher dielectric constant ranging from about 20 to at least about 100. Such higher dielectric constant dielectric materials can include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs) and lead zirconate titanate (PZTs).

[0062] The manufacturing method of the laterally diffused metal oxide semiconductor field effect transistor of the present application and the laterally diffused metal oxide semiconductor field effect transistor are based on the same inventive concept. For the content not specifically described in the manufacturing method of the laterally diffused metal oxide semiconductor field effect transistor, reference can be made to the introduction of the laterally diffused metal oxide semiconductor field effect transistor above.

[0063] It should be understood that although the steps in the flowchart of the present application are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application can include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps or stages in other steps.

[0064] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0065] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0066] The above-described embodiments only express several implementation manners of the present application. The descriptions are relatively specific and detailed, but should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A laterally diffused metal oxide semiconductor field effect transistor, characterized in that, Comprising: A substrate having a second conductivity type; A buffer region located in the substrate and having a first conductivity type; A buried region located on the buffer region, the buried region having a first conductivity type, and the doping concentration of the buffer region being less than that of the buried region; the first conductivity type and the second conductivity type are opposite conductivity types; A second conductivity type region located on the buried region and having a second conductivity type; An LDMOS body structure including a source region, a drain region, and a gate, the drain region being located above the buried region, and the source region being located in the second conductivity type region.

2. The lateral diffusion metal oxide semiconductor field effect transistor according to claim 1, wherein Further comprising a first well region, the first well region being located on the buried region, and the first well region forming a surrounding wall structure in the lateral direction, the surrounding wall structure and the buried region at the bottom constituting an enclosed structure, the first well region having a first conductivity type; The second conductivity type region and the drain region are located within the enclosed structure.

3. The lateral diffusion metal oxide semiconductor field effect transistor according to claim 2, wherein The second conductivity type region includes a body region, and the source region is located in the body region.

4. The lateral diffused metal oxide semiconductor field effect transistor according to claim 3, wherein, The second conductivity type region includes a first doped region, the first doped region being located within the enclosed structure and having a second conductivity type; The LDMOS body structure further includes a drift region of the first conductivity type, the drift region being located within the enclosed structure, at least part of the structure of the drift region being located between the source region and the drain region, the bottom of the drift region being separated from the buried region by the first doped region, at least part of the structure of the gate being located above the drift region between the source region and the drain region, and the drain region being in direct contact with the drift region.

5. The lateral diffused metal oxide semiconductor field effect transistor according to claim 1, wherein The bottom of the buried region is in direct contact with the top of the buffer region; and / or The laterally diffused metal oxide semiconductor field effect transistor further includes a second well region having a second conductivity type, the second well region being located outside the first well region and in direct contact with the substrate.

6. The laterally diffused metal oxide semiconductor field effect transistor according to any one of claims 1-5, characterized in that, The laterally diffused metal oxide semiconductor field effect transistor is an N-channel laterally diffused metal oxide semiconductor field effect transistor, the first conductivity type is N-type, and the second conductivity type is P-type.

7. A method for manufacturing a laterally diffused metal oxide semiconductor field effect transistor, comprising: Obtaining a substrate formed with a buffer region and a buried region; the substrate has a second conductivity type, the buffer region and the buried region have a first conductivity type, the buried region is located on the buffer region, and the doping concentration of the buffer region is less than that of the buried region; the first conductivity type and the second conductivity type are opposite conductivity types; Forming a second conductivity type region on the buried region; Forming an LDMOS body structure; The LDMOS body structure includes a source region, a drain region, and a gate, the drain region is formed above the buried region, and the source region is formed in the second conductivity type region.

8. The manufacturing method of the lateral diffusion metal oxide semiconductor field effect transistor according to claim 7, wherein, Further including the step of forming a first well region on the buried region; the first well region forms a surrounding wall structure in the lateral direction, the surrounding wall structure and the buried region at the bottom constitute an enclosed structure, the second conductivity type region and the drain region are located within the enclosed structure, and the first well region has a first conductivity type.

9. The manufacturing method of the lateral diffusion metal oxide semiconductor field effect transistor according to claim 8, wherein The step of forming a second conductivity type region on the buried region includes: Forming an epitaxial layer of a second conductivity type on the substrate; Forming a body region and a first doped region within the surrounding structure in the epitaxial layer; the body region and the first doped region have a second conductivity type, the second conductivity type region includes the body region and the first doped region, and the source region is located in the body region; The step of forming a first well region on the buried region includes: forming a first well region in the epitaxial layer; The method further includes a step of forming a drift region; the drift region has a first conductivity type, the drift region is located within the surrounding structure, the bottom of the drift region is separated from the buried region by the first doped region, at least a part of the structure of the drift region is located between the source region and the drain region, at least a part of the structure of the gate is located above the drift region between the source region and the drain region, and the drain region is in direct contact with the drift region.

10. The manufacturing method of the lateral diffusion metal oxide semiconductor field effect transistor according to claim 9, wherein The doping concentration of the first doped region is 2 to 3 orders of magnitude higher than the doping concentration of the epitaxial layer.

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