LDMOS and LIGBT hybrid power device with auxiliary electrode and super electron accumulation effect
By introducing auxiliary electrodes and dielectric layers into SOI LDMOS devices, a potential difference is formed to promote electron accumulation, which solves the problem of high on-resistance of traditional SOI LDMOS devices, achieving lower on-power consumption and better performance.
Patent Information
- Application Number
- CN202510368882.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-26
- Publication Date
- 2025-06-27
AI Technical Summary
While increasing the reverse withstand voltage, traditional SOI LDMOS devices are difficult to effectively reduce the on-resistance, resulting in high on-power consumption.
By introducing the auxiliary electrode and the dielectric layer, a potential difference between the high potential drift region and the low potential drift region is formed, which promotes electron accumulation on the low potential side and forms an ultra-low resistance channel, thereby reducing the on-resistance.
It realizes that the on-resistance of SOI LDMOS devices is significantly reduced without affecting device reliability, improves the quality factor of the device, and improves the compromise relationship between breakdown voltage and on-resistance.
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Figure CN120224739A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of power semiconductors. Specifically, it relates to a SOI LDMOS for reducing on-resistance and a manufacturing method thereof. Technical Background
[0002] With the continuous development of power electronics technology in recent years, the concept of intelligent power integrated circuits has been proposed and widely concerned. The application of this technology can, on the one hand, reduce manufacturing costs, and on the other hand, enhance device reliability. Its greatest advantage lies in the ability to integrate high-voltage discrete devices and low-voltage control circuits on a single chip. The lateral double-diffused power MOSFET (LDMOS) device based on silicon-on-insulator technology still occupies a dominant position in the field of power device applications due to its high input impedance and faster conversion rate. At the same time, since the electrodes of SOI LDMOS are all located on the surface of the device, it is easier to be compatible with the CMOS integrated circuit process.
[0003] In the design of power device structures, two important indicators used to characterize the performance of SOI LDMOS power devices are the breakdown voltage and the specific on-resistance, and there is a mutually restrictive contradictory relationship between them. Therefore, how to improve the reverse breakdown voltage and reduce the specific on-resistance of SOI LDMOS devices without affecting the reliability of the devices has become a research hotspot for industry scholars.
[0004] Taking the traditional N-type trench-gate structure LDMOS as an example, as Figure 1 shown. Its structure consists of:
[0005] Substrate region: A P-type semiconductor substrate 1, with a substrate electrode connected below it and a buried oxide layer 2 above it.
[0006] Drift region: Composed of an N-type lightly doped region 12.
[0007] P-type body region: Composed of a P-well region 3.
[0008] Source region: Composed of an N-type heavily doped region 7, and a heavy P-doped region 5 jointly leads out an electrode 16 as the source-body electrode.
[0009] Drain region: Composed of an N-type heavily doped region 9, with a drain electrode 18 connected above it.
[0010] Gate region: Composed of a silicon dioxide dielectric layer 15 and the metal filled inside it, and leads out an electrode 17 as the gate.
[0011] For the P-type trench-gate structure LDMOS, only need to take the opposite of all the above doping regions.
[0012] In the traditional N-type trench-gate structure LDMOS, since only the width of the conducting channel is widened and the drift region is not optimized, there is still a large drift resistance in the drift region, which in turn causes the trench-gate LDMOS to maintain a high on-state power consumption. Summary of the Invention
[0013] The object of the present invention is to propose an LDMOS with high performance. By introducing a high-potential drift region through an auxiliary electrode, a controllable high-density electron accumulation layer is formed in the low-potential drift region, thereby reducing the on-resistance of the drift region of the device, reducing the specific on-resistance of the device, improving the figure of merit of the device, and improving the trade-off relationship between the breakdown voltage and the on-resistance, so that the device can exhibit better performance in practical applications.
[0014] The present invention includes:
[0015] A substrate, on which a buried oxide layer, i.e., Silicon-On-Insulator (SOI), is formed.
[0016] A silicon film layer is formed on the buried oxide layer. The silicon film layer includes a source region, a well region, a drain region, a drift region, a vertical trench gate, a gate oxide layer, and a dielectric layer.
[0017] A device top layer is formed on the surface of the silicon film layer. The device top layer includes a source electrode, a drain electrode, and an auxiliary electrode.
[0018] Furthermore, a dielectric layer structure is provided in the middle of the silicon film layer, penetrating the entire device from the source region to the drain region. The dielectric layer structure is rectangular, with its bottom in contact with the buried oxide layer, its top in contact with the top of the silicon film layer, and its sides flush with both sides of the device.
[0019] Furthermore, in the high-potential region, a vertical trench gate perpendicular to the buried oxide layer is etched on one side of the dielectric layer. Through processes such as oxidation or filling with other dielectric materials and metal filling, a vertical trench gate structure is fabricated. The bottom of the trench gate is in contact with the surface of the buried oxide layer, and the top is in contact with the top of the silicon film layer. One side of the trench gate structure provides a conducting channel for the LDMOS end conduction, and the other side provides a conducting channel for the LIGBT end conduction.
[0020] Furthermore, the auxiliary electrode region is located on one side of the high-potential region and is composed of a heavily doped P region. It is jointly connected with the heavily doped N region and a diode is formed in series to form an auxiliary electrode. The diode is externally connected to a reverse-biased auxiliary voltage. By applying a voltage to the auxiliary electrode, the potential of the high-potential region can be increased without affecting the potential of the low-potential region, thereby controlling the electron accumulation effect on the low-potential side of the dielectric layer and further optimizing the on-state power consumption of the device.
[0021] Advantages of the present invention:
[0022] 1. By introducing the auxiliary electrode 19, the present invention creates a potential difference between the first drift region 12 and the second drift region 13 separated by the dielectric layer structure 14. As a result, electrons in the first drift region 12 are attracted to the silicon dioxide dielectric on the low-potential side 14, forming an ultra-low-resistance channel. Moreover, the thickness of the electron accumulation layer can be controlled by adjusting the auxiliary electrode 19, thereby regulating the on-resistance.
[0023] 2. In addition, the high-potential side separated by the dielectric layer structure 14 is equivalent to an LIGBT device, with the auxiliary electrode 19 corresponding to the cathode and the drain 18 corresponding to the anode. Therefore, a large current exists on the high-potential side. In summary, the present invention greatly reduces the on-state power consumption of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0025] Figure 1 It is a three-dimensional structure diagram of a traditional trench-gate LDMOS
[0026] Figure 2 It is a three-dimensional structure diagram of the LDMOS in the embodiment of the present application
[0027] Figure 3 It is a perspective view of the cross-sectional current distribution of the trench-gate structure in the present invention
[0028] Figure 4 It is a potential distribution diagram of applying different auxiliary electrode voltages on both sides of the dielectric layer in the present invention
[0029] Figure 5 It is a relationship curve of the drain current with the auxiliary voltage under different drain voltages
[0030] Figure 6 It is an output characteristic curve of different auxiliary electrodes in the present invention DETAILED DESCRIPTION OF THE EMBODIMENTS
[0031] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only some of the embodiments of this application, rather than all of them. The components of the embodiments of this application usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of this application that is required to be protected, but merely represents the selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative efforts belong to the scope of protection of this application.
[0032] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0033] The following first gives the definitions of some terms in the embodiments of this application:
[0034] LDMOS: Lateral Diffused Metal Oxide Semiconductor, a lateral diffused metal-oxide semiconductor, is a semiconductor device that uses a double diffusion technique to perform two successive diffusions of boron and phosphorus in the same window. The channel length can be precisely determined by the difference in the lateral junction depths of the two impurity diffusions.
[0035] SOI: Silicon On Insulator, which means silicon on insulator. This is a semiconductor technology in which a silicon layer is placed on top of an insulator layer, usually this insulator layer is silicon dioxide (SiO2). SOI technology can reduce the parasitic capacitance of the device, improve the switching speed, reduce power consumption, and improve the breakdown voltage of the device. LDMOS combined with SOI technology can provide effective isolation and lower leakage current.
[0036] LIGBT: That is, Lateral Insulated Gate Bipolar Transistor, a power semiconductor device that combines the high input impedance of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and the current-carrying capacity of BJT (Bipolar Junction Transistor).
[0037] Based on the above definitions, the embodiments of this application provide a trench-gate SOI LDMOS structure with auxiliary electrodes and a dielectric layer. As Figure 2 and Figure 3 shown, taking the N-type LDMOS structure as an example, its various parts are composed as follows:
[0038] Substrate region: P-type semiconductor substrate 1, with a substrate electrode connected below it and a buried oxide layer 2 above it.
[0039] Drift region: Composed of an N-type lightly doped region, including a first drift region 12 and a second drift region 13.
[0040] P-type body region: Composed of a first P-well region 3 and a second P-well region 4.
[0041] Source region: Composed of an N-type heavily doped region 7, and jointly connected to an electrode 16 with a heavily doped P region 5 as the source-body electrode.
[0042] Drain region: Composed of an N-type heavily doped region 9, an N-type buffer region 10, and a P-type heavily doped region 11. The N-type heavily doped region 9 and the P-type heavily doped region 11 are jointly connected to a drain electrode 18.
[0043] Gate region: Composed of a silicon dioxide dielectric layer 15 and the metal filled therein, and an electrode 17 is connected as the gate.
[0044] Auxiliary electrode region: Composed of a heavily doped P region 6, and jointly connected to an electrode 19 with a heavily doped N region 8, and a diode is connected in series as the auxiliary electrode.
[0045] Dielectric layer region: Through deep silicon etching technology, a dielectric layer structure 14 composed of a dielectric material is vertically etched out.
[0046] In the present invention, by introducing the auxiliary electrode 19, a potential difference is generated between the first drift region 12 and the second drift region 13 separated by the dielectric layer structure 14. As Figure 4 shown, the electrons in the first drift region 12 are attracted to the silicon dioxide dielectric on the low-potential side 14 to form an ultra-low resistance channel, and the thickness of the electron accumulation layer can be controlled by adjusting the auxiliary electrode 19, thereby adjusting the on-resistance. As Figure 5 and Figure 6 shown, the present invention can achieve a single-stage conduction mode and a bipolar conduction mode by adjusting the auxiliary voltage. The single-stage conduction mode is to achieve an ultra-low on-resistance LDMOS with an in-body electron accumulation effect. The bipolar conduction mode is to achieve the parallel use of LIGBT and LDMOS devices, and at the same time has a large current and an electron-hole accumulation effect. In the manufacturing process of the dielectric layer structure 14, the present invention is realized by using a sub-micron deep reactive ion etching technology and a thermal oxidation process. This etching technology can achieve a depth-to-width ratio of 120:1 at an etching width of 35 nanometers. Therefore, the electron accumulation effect in the drift region can be further increased by reducing the width of the dielectric layer, thereby reducing the on-power consumption of the device.
[0047] It should be noted that like reference numerals and letters denote like items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and should not be construed as indicating or implying relative importance.
[0048] Finally, it should be noted that the above-described embodiments are only specific embodiments of the present invention, used to illustrate the technical solutions of the present invention, rather than limiting it. The protection scope of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that any person skilled in the art within the technical scope disclosed by the present invention can still modify the technical solutions recorded in the foregoing embodiments or can easily think of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims
1. A trench gate SOI-LDMOS structure with an auxiliary electrode and a dielectric layer, comprising a substrate region, a drift region, a source region, a drain region, a gate region, a dielectric layer region and an auxiliary electrode region, characterized in that : The dielectric layer region has a dielectric layer structure perpendicular to the buried oxide layer, and the dielectric layer region material can be silicon oxide or other dielectric materials. This structure is used to block the high potential region and the low potential region, thereby forming an electron accumulation layer on one side of the dielectric layer through the electron accumulation effect.
2. The novel trench gate structure LDMOS according to claim 1, characterized in that: A vertical groove is etched in the P-base region of the device, and a vertical groove gate structure is made through oxidation or other dielectric material filling and metal filling processes. The bottom of the groove gate is in contact with the surface of the buried oxide layer; one side of the groove gate structure provides a conduction channel for the LDMOS end, and the other side provides a conduction channel for the LIGBT end.
3. The LDMOS with auxiliary electrode structure according to claim 1, characterized in that: The auxiliary electrode area is located on one side of the high potential area, and is composed of a heavily doped P area. It is connected to the heavily doped N area and connected in series with a diode to form an auxiliary electrode. The diode is externally connected to a reverse-biased auxiliary voltage. By applying a voltage to the auxiliary electrode, the potential of the high potential area can be increased without affecting the potential of the low potential area, thereby controlling the electron accumulation effect on the low potential side of the dielectric layer, thereby optimizing the device on-state power consumption. The characteristics of having a high current and high potential area are: The drain end of the high potential region is composed of a heavily doped P region and connected to a drain electrode, and the heavily doped P region is located above the heavily doped N region. In addition, when the auxiliary electrode is grounded, the high potential region is equivalent to a traditional trench gate LIGBT device, and the low potential is a traditional trench gate LDMOS device.