Vertical diode and preparation method thereof, chip and electronic equipment

Abstract

The invention provides a vertical diode and a preparation method thereof, a chip and electronic equipment, relates to the technical field of semiconductors, and aims to improve the performance of a device. The preparation method of the vertical diode comprises the steps that a buffer layer with a plurality of pits in the surface is formed on a first substrate, a recovery layer is formed on the surface, with the pits, of the buffer layer, so that a plurality of randomly-distributed holes are formed in the recovery layer, and the recovery layer is low in structural strength and easy to strip and break. And then, forming a device layer group on one side, far away from the first substrate, of the recovery layer, and forming a first electrode on one side, far away from the first substrate, of the device layer group. And breaking the recovery layer to form a first sub-recovery layer and a second sub-recovery layer, and obtaining a device structure comprising the first electrode, the device layer group and the first sub-recovery layer. And finally, a second electrode is formed on the device structure, the second electrode is located on the side, away from the first electrode, of the first sub-recovery layer, and preparation of the vertical diode is achieved. The vertical diode can be applied to a chip and used as a power device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular, to a vertical diode, a preparation method thereof, a chip, and an electronic device. Background Art

[0002] By using a wide-bandgap semiconductor material, a vertical power device is prepared on a silicon substrate, and the working current vertically flows through the device. According to the characteristics of the wide-bandgap semiconductor material, the vertical power device has advantages such as good scalability, high current density, large breakdown voltage, low defect sensitivity, and simple heat dissipation management system, and can avoid reliability problems such as dynamic on-resistance degradation.

[0003] Currently, in the process of preparing a fully vertical diode, an ion implantation process is usually used to strip the substrate. However, the damage depth and damage degree of the ion implantation process are not easy to control, the process cost is also relatively high, and when growing a device layer on a substrate with an ion damage layer, the film quality of the device layer is also poor, which is not conducive to improving the device performance. Summary of the Invention

[0004] Embodiments of this application provide a vertical diode, a preparation method thereof, a chip, and an electronic device, aiming to improve the performance of the device.

[0005] To achieve the above object, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a preparation method of a vertical diode is provided. The preparation method includes: forming a buffer layer with a plurality of pits on a first substrate, forming a recovery layer on the surface of the buffer layer having a plurality of pits. The surface of the buffer layer is uneven. In this way, during the process of forming the recovery layer on the surface of the buffer layer, nano-scale gaps randomly distributed are easily generated in the recovery layer, and these gaps can form a plurality of tiny holes, so that a plurality of randomly distributed holes are formed in the recovery layer. The structural strength of the recovery layer is relatively low and is easy to be peeled off and disconnected. Then, a device layer group is formed on the side of the recovery layer away from the first substrate, and a first electrode is formed on the side of the device layer group away from the first substrate. The recovery layer is disconnected to form a first sub-recovery layer and a second sub-recovery layer, and a device structure including the first electrode, the device layer group, and the first sub-recovery layer is obtained. Finally, a second electrode is formed on the device structure, and the second electrode is located on the side of the first sub-recovery layer away from the first electrode, realizing the preparation of the vertical diode.

[0007] Compared with the method of stripping the substrate by ion implantation process, the present application forms a buffer layer and a recovery layer by epitaxial process, and forms a device layer group on the recovery layer, avoiding forming the device layer group on the ion damage layer, which is beneficial to improving the film quality of the device layer group. Moreover, by disconnecting the recovery layer, the stripping of the first substrate and the buffer layer is realized, and this process is simple and has low cost. In addition, the film quality of the first sub-recovery layer remaining on the device layer group is good, and there is no need to etch away the first sub-recovery layer, avoiding the risk of damage to the device layer group caused by etching. There is only one epitaxial layer, the first sub-recovery layer, between the second electrode and the device layer group in the vertical diode, simplifying the epitaxial layer structure.

[0008] In some embodiments, group IIIA elements and group VA elements are used to form a buffer layer. Among them, the mass ratio range of group VA elements to group IIIA elements is 5000-10000. When the mass ratio of the two satisfies this range, a plurality of randomly distributed pits will be formed on the surface of the prepared buffer layer, that is, the surface of the buffer layer has an aperiodic porous morphology.

[0009] In some embodiments, group IIIA elements and group VA elements are used to form a recovery layer. Among them, the mass ratio range of group VA elements to group IIIA elements is 100-2000. When the mass ratio of the two satisfies this range, it is beneficial to generate randomly distributed nano-scale gaps in the recovery layer, thereby forming a plurality of holes in the recovery layer.

[0010] In some embodiments, trimethylgallium, trimethylaluminum and ammonia are used to form a buffer layer and a recovery layer.

[0011] In some embodiments, metal organic chemical vapor deposition process, molecular beam epitaxy process or physical vapor deposition process is used to form a buffer layer and a recovery layer.

[0012] In some embodiments, a mechanical stripping process is used to apply mechanical forces in opposite directions to the recovery layer. Since there are a plurality of tiny holes in the recovery layer, the structural strength of the recovery layer is low. Therefore, the recovery layer will break. Or, a laser stripping process is used. Since there are a plurality of tiny holes in the recovery layer, the laser is easily focused in the recovery layer, thereby ablating and separating the recovery layer. Or, a wet stripping process is used. Since there are a plurality of tiny holes in the recovery layer, the wet stripping liquid is easily penetrated into the recovery layer and reacts fully with the recovery layer, thereby corroding and separating the recovery layer.

[0013] In some embodiments, the device layer group is bonded to the second substrate. The surface of the device layer group away from the first substrate is connected to the second substrate through a bonding metal layer, and the bonding metal layer can be used as the first electrode.

[0014] In a second aspect, a vertical diode is provided. The vertical diode includes a first electrode, a device layer group, a first sub-recovery layer, and a second electrode. The device layer group is disposed on the first electrode. The first sub-recovery layer is disposed on a side of the device layer group away from the first electrode. A surface of the first sub-recovery layer away from the first electrode has a plurality of holes. The second electrode is disposed on a side of the first sub-recovery layer away from the first electrode, and at least a part of the second electrode is embedded in the plurality of holes of the first sub-recovery layer.

[0015] In the vertical diode provided by the above embodiments of the present application, the surface of the first sub-recovery layer away from the first electrode has a plurality of holes because during the preparation of the recovery layer, a plurality of randomly distributed holes are formed in the recovery layer, and the structural strength of the recovery layer is relatively low and is prone to peeling and disconnection. After the recovery layer is disconnected to form the first sub-recovery layer and the second sub-recovery layer, the first sub-recovery layer with a plurality of holes on its surface is obtained.

[0016] At least a part of the second electrode is embedded in the plurality of holes of the first sub-recovery layer, which can increase the contact area between the first sub-recovery layer and the second electrode, thereby improving the conduction performance of the vertical diode and being beneficial to enhancing the performance of the device.

[0017] In some embodiments, the material of the first sub-recovery layer includes elements of Group IIIA and Group VA, and the mass ratio range of the Group VA element to the Group IIIA element is 100 to 2000.

[0018] In some embodiments, the material of the first sub-recovery layer includes aluminum gallium nitride.

[0019] In some embodiments, in the X-ray diffraction reciprocal space map of the device layer group, when the materials of multiple film layers in the device layer group all include gallium nitride, the deformation amount of the device layer group compared with its bulk material is less than or equal to 0.1%, and compared with the deformation amount of the device layer of the current vertical diode, the deformation amount of the device layer group is smaller, indicating that the residual stress of the material of the device layer group is smaller. By releasing the stress in the device layer group and reducing the stress in the material of the device layer group, it is beneficial to the regulation of strain.

[0020] In some embodiments, when the materials of multiple film layers in the device layer group all include gallium nitride, the full width at half maximum of the X-ray diffraction rocking curve of the (002) crystal plane of the device layer group is less than or equal to 1000 arcsec. Compared with the device layer of the current vertical diode, the full width at half maximum of the X-ray diffraction rocking curve of the (002) crystal plane of the device layer group is smaller, indicating that both the screw dislocation density and the edge dislocation density of the material of the device layer group decrease, and the film layer quality of the device layer group is improved.

[0021] In some embodiments, the device layer group includes a p-type semiconductor layer, a first n-type semiconductor layer, and a second n-type semiconductor layer which are stacked. The materials of the p-type semiconductor layer, the first n-type semiconductor layer, and the second n-type semiconductor layer all include Group IIIA elements and Group VA elements. Based on this structure of the device layer group, the vertical diode is a "PIN diode".

[0022] In some embodiments, the device layer group includes a first n-type semiconductor layer and a second n-type semiconductor layer which are stacked. The materials of the first n-type semiconductor layer and the second n-type semiconductor layer all include Group IIIA elements and Group VA elements. Based on this structure of the device layer group, the vertical diode is a "Schottky diode".

[0023] In a third aspect, a chip is provided. The chip includes a substrate and the vertical diode in any of the above embodiments, and the vertical diode is connected to the substrate.

[0024] In a fourth aspect, an electronic device is provided. The electronic device includes a circuit board and the chip in the above embodiments, and the chip is electrically connected to the circuit board.

[0025] It can be understood that for the chip and the electronic device provided in the above embodiments of the present application, the beneficial effects that can be achieved can refer to the beneficial effects of the vertical diode in the above text, which will not be elaborated here. Description of the Drawings

[0026] To more clearly illustrate the technical solutions in the present application, the drawings required to be used in some embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual sizes of the products, the actual processes of the methods, etc. involved in the embodiments of the present application.

[0027] Figure 1 It is a flowchart for preparing a vertical diode provided by an embodiment of the present application;

[0028] Figures 2A to 2G It is a diagram of each step for preparing a vertical diode provided by an embodiment of the present application;

[0029] Figure 3 It is a structural diagram of a chip provided by an embodiment of the present application;

[0030] Figure 4 It is a structural diagram of a charger provided by an embodiment of the present application.

[0031] Reference Signs:

[0032] 1 - First substrate; 2 - Buffer layer; 20 - Pit; 3 - Recovery layer; 30 - Hole; 31 - First sub - recovery layer; 32 - Second sub - recovery layer; 33 - Hole; 4 - Device layer group; 41 - Heavily doped n - type semiconductor layer; 42 - Lightly doped n - type semiconductor layer; 43 - Heavily doped p - type semiconductor layer; 5 - First electrode; 6 - Second substrate; 7 - Device structure; 8 - Second electrode; 9 - Vertical diode; 10 - Substrate; 11 - Solder ball; 100 - Chip; 200 - Charger; 201 - Transformer; 202 - Resistor; 203 - Inductor; 204 - Capacitor; 205 - Circuit board. Detailed implementation manners

[0033] Next, in combination with the accompanying drawings, the technical solutions in some embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0034] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to has a specific orientation, is constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application.

[0035] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0036] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0037] In describing some embodiments, the expressions "connected" and its derivatives may be used. For example, in describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0038] "At least one of A, B, or C" includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0039] In the context of this application, the meanings of "on", "above", and "over" should be interpreted in the broadest possible way such that "on..." not only means "directly on something", but also includes "on something" with intermediate features or layers therebetween, and "above" or "over" not only means "above" or "over" something, but also includes "above" or "over" something with no intermediate features or layers therebetween (i.e., directly on something).

[0040] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Thus, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused by, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0041] Currently, substrate peeling technology is generally used to fabricate fully vertical diodes. For example, an ion implantation process is used to implant ions into the substrate to form an ion damage layer within the substrate. Then, multiple device layers are formed on the substrate. Finally, the ion damage layer is disconnected, and the remaining substrate and residual ion damage layer are on the multiple device layers. The residual ion damage layer on the multiple device layers is removed by an ion thinning process or an inductively coupled plasma (ICP) etching process.

[0042] However, the above preparation method requires processing of the substrate, and in the case of a large substrate size, the process is difficult and costly. Moreover, the damage depth and degree of the ion implantation process are not easily controlled, and the process cost is also high. When growing multiple device layers on a substrate with an ion damage layer, the film quality of the device layers is also poor, which is not conducive to improving the device performance. In addition, the thickness of the residual ion damage layer on the multiple device layers is relatively large (usually greater than 3 μm), and the removal process is difficult.

[0043] To solve the above problems, embodiments of the present application provide a vertical diode and a method for manufacturing the same. Figure 1 is a flowchart for manufacturing the vertical diode provided by an embodiment of the present application; Figures 2A to 2G are diagrams of respective steps for manufacturing the vertical diode provided by an embodiment of the present application.

[0044] Referring to Figure 1 , the method for manufacturing the vertical diode includes the following S1 to S6:

[0045] Referring to Figure 2A , provide a first substrate 1.

[0046] Exemplarily, the size of the first substrate 1 can be 4 to 18 inches. The first substrate 1 can be an n-type, p-type, or intrinsic semiconductor substrate. The material of the first substrate 1 can include silicon, silicon carbide, sapphire, gallium nitride, or silicon on insulator (SOI), etc. When the material of the first substrate 1 is silicon, the silicon substrate can be of <111> or <100> crystal orientation.

[0047] For example, Figure 2A in [reference], the first substrate 1 is a 6-inch, heavily doped p-type, low-resistance, <111>-oriented silicon substrate, and the resistivity of the first substrate 1 is less than 10 Ω·mm.

[0048] S1: Referring to Figure 2B , form a buffer layer 2 on the first substrate 1. The surface of the buffer layer 2 away from the first substrate 1 has a plurality of pits 20.

[0049] Exemplarily, group IIIA elements and group VA elements can be used to prepare and form the buffer layer 2. Among them, the mass ratio range of the group VA element to the group IIIA element is 5000 to 10000. For example, the mass ratio of the group VA element to the group IIIA element is 5000, 6250, 7500, 8750, or 10000. When the mass ratio of the group VA element to the group IIIA element satisfies the range of 5000 to 10000, a plurality of randomly distributed pits 20 will be formed on the surface of the prepared buffer layer 2, that is, the surface of the buffer layer 2 has a non-periodic porous morphology.

[0050] Exemplarily, the thickness range of the buffer layer 2 is 10 nm to 1000 nm, and the depth range of the pits 20 is 10 nm to 500 nm. When the shape of the pits 20 in the X-Y plane is circular, the diameter range of the pits 20 is 10 nm to 500 nm.

[0051] Exemplarily, a Metal Organic Chemical Vapor Deposition (MOCVD) process, a Molecular Beam Epitaxy (MBE) process, or a Physical Vapor Deposition (PVD) process may be employed to form the buffer layer 2.

[0052] For example, Figure 2B in [reference], the MOCVD process is used to grow a thin film in a MOCVD epitaxial device. Trimethylgallium, trimethylaluminum, and ammonia are used as the gallium source, aluminum source, and nitrogen source respectively. The ratio of the mass of the nitrogen source to the sum of the masses of the gallium source and aluminum source is 7500, and hydrogen is used as the carrier gas. The temperature for thin film growth is 1100 °C, and the buffer layer 2 is grown on the first substrate 1 with a thickness of 80 nm.

[0053] S2: Refer to Figure 2C , a recovery layer 3 is formed on the surface of the buffer layer 2 having a plurality of pits 20, and the recovery layer 3 has a plurality of holes 30.

[0054] It can be understood that since the surface of the buffer layer 2 has a plurality of pits 20 and the surface of the buffer layer 2 is uneven, in the process of forming the recovery layer 3 on the surface of the buffer layer 2, randomly distributed nano-scale gaps are likely to be generated in the recovery layer 3, and these gaps can form a plurality of tiny holes 30, making the structural strength of the recovery layer 3 relatively low, so as to facilitate the subsequent disconnection of the recovery layer 3.

[0055] Exemplarily, group IIIA elements and group VA elements may be used to prepare and form the recovery layer 3, wherein the mass ratio range of the group VA element to the group IIIA element is 100 - 2000. For example, the mass ratio of the group VA element to the group IIIA element is 100, 500, 1050, 1500, or 2000. When the mass ratio of the group VA element to the group IIIA element satisfies the range of 100 - 2000, it is also beneficial to generate randomly distributed nano-scale gaps in the recovery layer 3, thereby forming a plurality of holes 30 in the recovery layer 3.

[0056] Exemplarily, the thickness range of the recovery layer 3 is 10 nm - 500 nm, and the depth range of the holes 30 is 10 nm - 200 nm.

[0057] Exemplarily, an MOCVD process, an MBE process, or a PVD process may be employed to form the recovery layer 3.

[0058] For example, Figure 2CIn this case, the MOCVD process is adopted to grow a thin film in a MOCVD epitaxial device. Trimethylgallium, trimethylaluminum, and ammonia are used as the gallium source, aluminum source, and nitrogen source respectively. The ratio of the mass of the nitrogen source to the sum of the masses of the gallium source and the aluminum source is 500, and hydrogen is used as the carrier gas. The temperature for thin film growth is 1100 °C. A recovery layer 3 is grown on the buffer layer 2, and the material of the recovery layer 3 includes aluminum gallium nitride, and the thickness of the recovery layer 3 is 200 nm.

[0059] S3: Refer to Figure 2D , and a device layer group 4 is formed on the side of the recovery layer 3 away from the first substrate 1.

[0060] Exemplarily, a heavily doped n-type semiconductor layer 41 is formed on the recovery layer 3, and the thickness of the heavily doped n-type semiconductor layer 41 is 1 μm.

[0061] The material of the heavily doped n-type semiconductor layer 41 includes group IIIA elements and group VA elements. For example, the material of the heavily doped n-type semiconductor layer 41 may include gallium nitride, aluminum nitride, indium nitride, or any one or more of ternary and quaternary compounds composed of group IIIA elements and group VA elements. Among them, the range of the mass ratio of the group VA element to the group IIIA element is 3000, the temperature for thin film growth is 1100 °C, and the carrier concentration in the heavily doped n-type semiconductor layer 41 is 5×10 18 cm -3 .

[0062] Exemplarily, a lightly doped n-type semiconductor layer 42 is formed on the heavily doped n-type semiconductor layer 41, and the thickness of the lightly doped n-type semiconductor layer 42 is 5 μm.

[0063] The material of the lightly doped n-type semiconductor layer 42 includes group IIIA elements and group VA elements. For example, the material of the lightly doped n-type semiconductor layer 42 may include gallium nitride, aluminum nitride, indium nitride, or any one or more of ternary and quaternary compounds composed of group IIIA elements and group VA elements. Among them, the range of the mass ratio of the group VA element to the group IIIA element is 5000, and the temperature for thin film growth is 1100 °C.

[0064] Exemplarily, a heavily doped p-type semiconductor layer 43 is formed on the lightly doped n-type semiconductor layer 42, and the thickness of the heavily doped p-type semiconductor layer 43 is 200 nm.

[0065] The material of the heavily doped p-type semiconductor layer 43 includes group IIIA elements and group VA elements. For example, the material of the heavily doped p-type semiconductor layer 43 may include gallium nitride, aluminum nitride, indium nitride, or any one or more of ternary and quaternary compounds composed of group IIIA elements and group VA elements. Among them, the range of the mass ratio of the group VA element to the group IIIA element is 3000, and the temperature for thin film growth is 1100 °C.

[0066] The above-mentioned heavily doped n-type semiconductor layer 41, lightly doped n-type semiconductor layer 42, and heavily doped p-type semiconductor layer 43 form the device layer group 4. Based on this structure of the device layer group 4, the finally formed vertical diode is a "PIN diode".

[0067] In some other examples, a heavily doped n-type semiconductor layer 41 and a lightly doped n-type semiconductor layer 42 are sequentially formed on the recovery layer 3, and the heavily doped p-type semiconductor layer 43 is not formed. The heavily doped n-type semiconductor layer 41 and the lightly doped n-type semiconductor layer 42 form the device layer group 4. Based on this structure of the device layer group 4, the finally formed vertical diode is a "Schottky diode".

[0068] S4: Refer to Figure 2E , and a first electrode 5 is formed on the side of the device layer group 4 away from the first substrate 1.

[0069] Exemplarily, invert the Figure 2D device structure in, bond the device layer group 4 to the second substrate 6. The surface of the device layer group 4 away from the first substrate 1 is connected to the second substrate 6 through a bonding metal layer, and this bonding metal layer serves as the first electrode 5 of the vertical transistor. Moreover, the first electrode 5 is located on the side of the heavily doped p-type semiconductor layer 43 away from the heavily doped n-type semiconductor layer 41, and the first electrode 5 is closer to the heavily doped p-type semiconductor layer 43. Therefore, the first electrode 5 can also be called a p-type electrode.

[0070] The size of the above-mentioned second substrate 6 can be 4 - 18 inches. The second substrate 6 can be an n-type or p-type semiconductor substrate. The material of the second substrate 6 can include silicon, silicon carbide, sapphire, gallium nitride, or silicon on insulator, etc. When the material of the second substrate 6 is silicon, the silicon substrate can be of <111> or <100> crystal orientation.

[0071] For example, Figure 2E the second substrate 6 in is a 6-inch, conductive, <100> crystal orientation silicon substrate.

[0072] The material of the above-mentioned first electrode 5 includes at least one of nickel, titanium, titanium nitride, aluminum, copper, or gold, and the thickness of the first electrode 5 is 50 nm.

[0073] S5: Refer to Figure 2F , disconnect the recovery layer 3 to form a first sub-recovery layer 31 and a second sub-recovery layer 32, and obtain a device structure 7 including the first electrode 5, the device layer group 4, and the first sub-recovery layer 31.

[0074] Exemplarily, the recovery layer 3 can be disconnected by using a mechanical peeling process, a laser peeling process, or a wet peeling process.

[0075] For example, Figure 2FIn this case, a mechanical peeling process is adopted, and mechanical forces in opposite directions along the Z direction are applied to the first substrate 1 and the second substrate 6. Since there are multiple tiny holes 30 in the recovery layer 3 and the structural strength of the recovery layer 3 is low, the overall structure will break at the recovery layer 3.

[0076] Alternatively, a laser peeling process is adopted. Since there are multiple tiny holes 30 in the recovery layer 3, the laser is easily focused within the recovery layer 3, thereby ablating and separating the recovery layer 3.

[0077] Or, a wet peeling process is adopted. Since there are multiple tiny holes 30 in the recovery layer 3, the wet peeling liquid easily penetrates into the recovery layer 3 and fully contacts and reacts with the recovery layer 3, thereby corroding and separating the recovery layer 3.

[0078] Please continue to refer to Figure 2F , since there are multiple holes 30 in the recovery layer 3, after the recovery layer 3 breaks to form the first sub-recovery layer 31 and the second sub-recovery layer 32, the surface of the first sub-recovery layer 31 away from the first electrode 5 has multiple holes 33.

[0079] S6: Refer to Figure 2G , a second electrode 8 is formed on the device structure 7, and the second electrode 8 is located on the side of the first sub-recovery layer 31 away from the first electrode 5, realizing the preparation of the vertical diode 9.

[0080] Exemplarily, an evaporation process can be adopted to form the second electrode 8 on the surface of the first sub-recovery layer 31 having multiple holes 33, such that at least a part of the second electrode 8 is embedded in the multiple holes 33 of the first sub-recovery layer 31, which can increase the contact area between the first sub-recovery layer 31 and the second electrode 8, thereby improving the conduction performance of the vertical diode 9 and being beneficial to enhancing the performance of the device.

[0081] Exemplarily, the second electrode 8 is located on the side of the heavily doped n-type semiconductor layer 41 away from the heavily doped p-type semiconductor layer 43, and the second electrode 8 is closer to the heavily doped n-type semiconductor layer 41. Therefore, the second electrode 8 can also be called an n-type electrode.

[0082] Exemplarily, the material of the second electrode 8 includes at least one of nickel, titanium, titanium nitride, aluminum, copper, or gold, and the thickness of the second electrode 8 is 150 nm.

[0083] The method for preparing the vertical diode 9 provided by the embodiments of the present application forms a buffer layer 2 with multiple pits 20 on the first substrate 1, and forms a recovery layer 3 on the surface of the buffer layer 2 having multiple pits 20, such that multiple randomly distributed holes 30 are formed in the recovery layer 3, and the structural strength of the recovery layer 3 is low, being easy to peel and break.

[0084] Then, a device layer group 4 is formed on the side of the recovery layer 3 away from the first substrate 1, and a first electrode 5 is formed on the side of the device layer group 4 away from the first substrate 1. The recovery layer 3 is disconnected to form a first sub-recovery layer 31 and a second sub-recovery layer 32, obtaining a device structure 7 including the first electrode 5, the device layer group 4, and the first sub-recovery layer 31. Finally, a second electrode 8 is formed on the device structure 7, and the second electrode 8 is located on the side of the first sub-recovery layer 31 away from the first electrode 5, realizing the preparation of the vertical diode 9.

[0085] Compared with the method of stripping the substrate by ion implantation process, in this application, the buffer layer 2 and the recovery layer 3 are formed by epitaxial process, and the device layer group 4 is formed on the recovery layer 3, avoiding the formation of the device layer group 4 on the ion damage layer, which is beneficial to improving the film quality of the device layer group 4. Moreover, by disconnecting the recovery layer 3 to realize the stripping of the first substrate 1 and the buffer layer 2, this process is simple and has a low cost. In addition, the film quality of the first sub-recovery layer 31 remaining on the device layer group 4 is good, and there is no need to etch away the first sub-recovery layer 31, avoiding the risk of damage to the device layer group 4 caused by etching. There is only one epitaxial layer, the first sub-recovery layer 31, between the second electrode 8 and the device layer group 4 in the vertical diode 9, simplifying the epitaxial layer structure.

[0086] For the vertical diode 9 provided by the embodiment of this application, X-ray diffraction (XRD) reciprocal space mapping (RSM) measurement is performed on the device layer group 4. When the materials of multiple film layers in the device layer group 4 all include gallium nitride, the deformation amount of the device layer group 4 compared with its bulk material is less than or equal to 0.1%. Compared with the deformation amount of the device layer of the current vertical diode, the deformation amount of the device layer group 4 is smaller, indicating that the residual stress of the material of the device layer group 4 is smaller. The embodiment of this application can release the stress in the device layer group 4, reduce the stress in the material of the device layer group 4, and is beneficial to the regulation of strain.

[0087] Moreover, X-ray diffraction rocking curve measurement is performed on the device layer group 4. When the materials of multiple film layers in the device layer group 4 all include gallium nitride, the full width at half maximum of the X-ray diffraction rocking curve of the (002) crystal plane of the device layer group 4 is less than or equal to 1000 arcsec. Compared with the device layer of the current vertical diode, the full width at half maximum of the X-ray diffraction rocking curve of the (002) crystal plane of the device layer group 4 is smaller, indicating that both the screw dislocation density and the edge dislocation density of the material of the device layer group 4 decrease, and the film quality of the device layer group 4 in the embodiment of this application is improved.

[0088] The embodiment of this application also provides a chip. Figure 3 It is the structure diagram of the chip provided by the embodiment of this application.

[0089] SeeFigure 3 The chip 100 is a packaged chip. The chip 100 includes a substrate 10 and the vertical diode 9 in the above embodiment. The vertical diode 9 is connected to the substrate 10.

[0090] Exemplarily, the vertical diode 9 can be electrically connected to the substrate 10 through solder balls 11.

[0091] The above chip 100 can be a power chip, and the vertical diode 9 is used as a power device.

[0092] Embodiments of the present application also provide an electronic device. The electronic device can be, for example, different types of user devices or terminal devices such as a charger, a household small appliance (such as a soymilk maker, a floor sweeping robot) for charging, an on-board charger (OBC), etc. The embodiments of the present application do not impose special restrictions on the specific form of the electronic device.

[0093] Taking the electronic device as a charger as an example, Figure 4 is a structural diagram of the charger provided by the embodiments of the present application.

[0094] See Figure 4 , the charger 200 can include a transformer 201, a resistor 202, an inductor 203, a capacitor 204, and a circuit board 205. The transformer 201 can be the chip 100 including the vertical diode 9. The transformer 201, the resistor 202, the inductor 203, and the capacitor 204 are respectively coupled to the circuit board 205 to achieve the interconnection of the devices.

[0095] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A method for preparing a vertical diode, characterized in that, Comprising: Forming a buffer layer on a first substrate, a side surface of the buffer layer away from the first substrate having a plurality of pits; Forming a recovery layer on the surface of the buffer layer having a plurality of pits, the recovery layer having a plurality of holes; Forming a device layer group on a side of the recovery layer away from the first substrate; Forming a first electrode on a side of the device layer group away from the first substrate; Disconnecting the recovery layer to form a first sub-recovery layer and a second sub-recovery layer, obtaining a device structure including the first electrode, the device layer group, and the first sub-recovery layer; Forming a second electrode on the device structure, the second electrode being located on a side of the first sub-recovery layer away from the first electrode.

2. The preparation method according to claim 1, wherein Using group IIIA elements and group VA elements to form the buffer layer; The mass ratio range of the group VA element to the group IIIA element is 5000 - 10000.

3. The preparation method according to claim 1 or 2, characterized in that, Using group IIIA elements and group VA elements to form the recovery layer; The mass ratio range of the group VA element to the group IIIA element is 100 - 2000.

4. The preparation method according to claim 2 or 3, characterized in that, Using trimethylgallium, trimethylaluminum, and ammonia gas to form the buffer layer and the recovery layer.

5. The preparation method according to any one of claims 1 to 4, characterized in that, Using metalorganic chemical vapor deposition process, molecular beam epitaxy process, or physical vapor deposition process to form the buffer layer and the recovery layer.

6. The preparation method according to any one of claims 1 to 5, characterized in that, Using mechanical peeling process, laser peeling process, or wet peeling process to disconnect the recovery layer.

7. The preparation method according to any one of claims 1 to 6, characterized in that, Forming the first electrode includes: Bonding the device layer group to a second substrate, a side surface of the device layer group away from the first substrate being connected to the second substrate through a bonding metal layer; the bonding metal layer serves as the first electrode.

8. A vertical diode, characterized in that, Comprising: A first electrode; A device layer group, disposed on the first electrode; A first sub-recovery layer, disposed on a side of the device layer group away from the first electrode, a side surface of the first sub-recovery layer away from the first electrode having a plurality of holes; A second electrode, disposed on a side of the first sub-recovery layer away from the first electrode, at least a part of the second electrode being embedded in the plurality of holes of the first sub-recovery layer.

9. The vertical diode according to claim 8, characterized in that The material of the first sub-recovery layer includes group IIIA elements and group VA elements; The mass ratio range of the group VA element to the group IIIA element is 100 - 2000.

10. The vertical diode according to claim 8 or 9, characterized in that, The material of the first sub-recovery layer includes aluminum gallium nitride.

11. The vertical diode according to any one of claims 8 to 10, characterized in that, In the X-ray diffraction reciprocal space map of the device layer group, the deformation amount of the device layer group compared to its bulk material is less than or equal to 0.1%.

12. The vertical diode according to any one of claims 8 to 11, characterized in that, The full width at half maximum of the X-ray diffraction rocking curve of the (002) crystal plane of the device layer group is less than or equal to 1000 arcsec.

13. The vertical diode according to any one of claims 8 to 12, characterized in that The device layer group includes a p-type semiconductor layer, a first n-type semiconductor layer, and a second n-type semiconductor layer stacked; The materials of the p-type semiconductor layer, the first n-type semiconductor layer, and the second n-type semiconductor layer all include group IIIA elements and group VA elements.

14. The vertical diode according to any one of claims 8 to 12, characterized in that, The device layer group includes a first n-type semiconductor layer and a second n-type semiconductor layer stacked; The materials of the first n-type semiconductor layer and the second n-type semiconductor layer all include group IIIA elements and group VA elements.

15. A chip, characterized in that, Comprising: A vertical diode as described in any one of claims 8 - 14; A substrate, wherein the vertical diode is connected to the substrate.

16. An electronic device, characterized in that, Comprising: The chip according to claim 15; A circuit board, wherein the chip is connected to the circuit board.

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