Silicon wafer, preparation method of silicon wafer, solar cell and preparation method of solar cell

Abstract

The invention provides a silicon wafer and a preparation method thereof, and a solar cell and a preparation method thereof. The silicon wafer is provided with a first surface and a second surface which are opposite, the first surface is provided with a suede structure, and at least one part of the second surface is provided with an irregular hill-shaped structure. The preparation method of the silicon wafer comprises the following steps that acid etching is carried out on the first surface of the silicon wafer to be textured, then alkali texturing is carried out, so that a textured structure is formed on the first surface, and the textured structure can comprise a plurality of pyramid units; and immersing the silicon wafer subjected to alkali texturing into an alkali solution containing an organic polymer additive (such as polyoxyethylene), and finely adjusting the textured structure of the silicon wafer through etching of the alkali solution containing the organic polymer additive so as to form at least one concave part with a light trapping effect on at least one tower surface of the pyramid unit. The silicon wafer and the solar cell not only have excellent light trapping performance, but also do not affect the subsequent passivation effect, thereby effectively improving the current and efficiency of the solar cell.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and specifically, to silicon wafers and their preparation methods, solar cells and their preparation methods. Background Art

[0002] The light management of crystalline silicon solar cells is crucial for the effective utilization of sunlight. During the preparation of crystalline silicon solar cells, a pyramid structure is usually introduced on the light-facing surface of the solar cell by etching to increase light incidence. The backlight surface of the solar cell is more diverse and needs to match the light-facing surface to achieve the optimal light trapping effect. In addition, the introduction of various structures on the backlight surface of the solar cell should consider the impact on the subsequent passivation effect to avoid voltage loss of the battery.

[0003] Generally, a pyramid texture is used on the front of crystalline silicon solar cells. This structure can increase the number of reflections of light on the cell surface to increase incidence. However, the smooth pyramid surface and the fixed surface angle will cause specular reflection of light, resulting in fewer reflections of light on the silicon wafer surface and causing a large loss of incident light. Attaching nanoparticles to the light-facing surface of the solar cell can increase the number of light reflections on the light-facing surface and thus increase light incidence. However, this complex surface structure not only increases the preparation difficulty but also is not conducive to the deposition of the subsequent passivation layer, resulting in voltage loss of the battery. In addition, the backlight surface of crystalline silicon solar cells usually uses a pyramid texture similar to the light-facing surface without differential design, which leads to a large loss of long-wavelength light transmission and ultimately affects the battery current and efficiency. To enhance the internal reflection of long-wavelength light on the silicon wafer or the backlight surface of the battery, the backlight surface of the battery can be designed as a polished surface to effectively reduce light transmission. However, this solution also increases the escape loss of long-wavelength light on the light-facing surface to a certain extent, so the effect on improving the battery current and efficiency is not significant.

[0004] For example, CN113257931B discloses a method for preparing a full-angle light-trapping texture for crystalline silicon solar cells. Among them, a pyramid structure is used on the front of the crystalline silicon cell and the pyramid surface is covered with nano-TiO2 particles to achieve full-angle light trapping. However, the roughness of the front surface of this structure is too large, which is not conducive to the deposition of the subsequent passivation layer and causes voltage loss. In addition, CN101707222A discloses a surface structure of a silicon crystal cell and its manufacturing method. Among them, the morphology of the light-facing surface of the cell includes a plurality of conical bodies, and the surface morphology of the microstructure of the backlight surface includes a plurality of arc-shaped bodies or a plurality of polygonal bodies. The backlight surface of the crystalline silicon cell is flatter than the light-facing surface, so as to balance the transmission and reflection losses of long-wavelength light of the cell. However, this structure causes specular reflection of light on the light-facing surface, and the number of reflections is relatively small, resulting in a large loss of light reflection.

[0005] Therefore, it is necessary to design a more reasonable surface structure of the silicon wafer to reduce the light reflection and long-wavelength light escape on the light-facing surface of the solar cell and the long-wavelength light transmission loss on the backlight surface. Summary of the Invention

[0006] To solve the above technical problems, in the first aspect of the present application, a silicon wafer is provided. The silicon wafer has opposite first and second surfaces. The first surface is provided with a textured surface structure, and at least a part of the second surface is provided with an irregular mound-like structure.

[0007] Optionally, the irregular mound-like structure is a convex spherical crown structure.

[0008] Optionally, the irregular mound-like structure includes a plurality of irregular mound body units. The average value of the mound body height of the irregular mound body units is greater than or equal to 10 nm and less than or equal to 200 nm, and the average value of the mound body diameter of the irregular mound body units is greater than or equal to 20 nm and less than or equal to 400 nm.

[0009] Optionally, the average value of the ratio of the mound body height to the mound body diameter of the irregular mound body units is greater than 0 and less than or equal to 0.5.

[0010] Optionally, the ratio of the area of the section of the second surface provided with the irregular mound-like structure to the total area of the second surface is greater than 0 and less than or equal to 100%.

[0011] Optionally, the textured surface structure includes a plurality of pyramid units, and at least one concave portion is provided on at least one slope of each pyramid unit.

[0012] Optionally, the average value of the depth of the concave portion is greater than or equal to 3 nm and less than or equal to 200 nm, and the average value of the concave portion diameter of the concave portion is greater than or equal to 5 nm and less than or equal to 2000 nm.

[0013] Optionally, the entire second surface is provided with the irregular mound-like structure, or the section of the second surface provided with the irregular mound-like structure is located at the middle position or the end position of the second surface.

[0014] Optionally, the second surface forms a staggered distribution of high-level areas and low-level areas. The height difference between the high-level area and the low-level area is greater than 0 μm and less than or equal to 10 μm, and only the low-level area is provided with the irregular mound-like structure; or only the high-level area is provided with the irregular mound-like structure.

[0015] In the second aspect of the present application, a solar cell is provided. The solar cell includes the aforementioned silicon wafer.

[0016] Optionally, the solar cell is a double-sided contact solar cell, wherein a first doped semiconductor layer is provided on the first surface of the silicon wafer, and a second doped semiconductor layer is provided on the second surface of the silicon wafer.

[0017] Optionally, the solar cell is a TOPCON cell.

[0018] Optionally, the solar cell is an HJT cell.

[0019] Optionally, the first doped semiconductor layer is an N-type doped polysilicon layer, and the second doped semiconductor layer is a P-type doped amorphous silicon layer, a nanocrystalline silicon layer, a microcrystalline silicon layer, a nano-oxide silicon layer, or a micro-oxide silicon layer.

[0020] Optionally, the first doped semiconductor layer is a P-type doped amorphous silicon layer, a nanocrystalline silicon layer, a microcrystalline silicon layer, a nano-oxide silicon layer, or a micro-oxide silicon layer; and the second doped semiconductor layer is an N-type doped polysilicon layer.

[0021] Optionally, the solar cell is a back-contact solar cell, wherein a first doped semiconductor layer and a second doped semiconductor layer are provided on the second surface, the second doped semiconductor layer is provided in the region of the second surface including the irregular hill-like structure, and the second doped semiconductor layer is a P-type doped amorphous silicon layer or a P-type doped polysilicon layer.

[0022] Optionally, the solar cell is a back-contact solar cell, wherein a first doped semiconductor layer and a second doped semiconductor layer are provided on the second surface, the second doped semiconductor layer is provided in the region of the second surface including the irregular hill-like structure, and the second doped semiconductor layer is an N-type doped amorphous silicon layer or an N-type doped polysilicon layer.

[0023] Optionally, the second surface forms a high-level region and a low-level region distributed in a staggered manner. The low-level region is entirely provided with the irregular hill-like structure. The low-level region includes a first segment, a second segment, and a third segment. The second segment separates the first segment and the third segment. The high-level region and the first segment adjacent to the high-level region are provided with the second doped semiconductor layer, and the third segment is provided with the first doped semiconductor layer.

[0024] Optionally, the solar cell is a back-contact solar cell, wherein the second surface forms a high-level region and a low-level region distributed in a staggered manner. The low-level region is entirely provided with the irregular hill-like structure. The high-level region includes a first high-level segment and a second high-level segment. The low-level region separates the first high-level segment and the second high-level segment. The first high-level segment is provided with the second doped semiconductor layer, and the second high-level segment is provided with the first doped semiconductor layer.

[0025] Optionally, the solar cell is a back-contact solar cell, wherein the second surface forms a high-level region and a low-level region distributed in a staggered manner. The high-level region is entirely provided with the irregular mound-like structure. The high-level region includes a first segment, a second segment, and a third segment. The second segment separates the first segment and the third segment. The low-level region and the first segment and the third segment adjacent to the low-level region are provided with a second doped semiconductor layer.

[0026] In a third aspect of the present application, a method for preparing the foregoing silicon wafer is provided. The method includes the following steps:

[0027] S1: Acid-etch the first surface of the silicon wafer to be textured, and then perform alkaline texturing so that the first surface forms the textured surface structure, and the textured surface structure may include a plurality of pyramid units; and

[0028] S2: Immerse the silicon wafer after step S1 in an alkaline solution containing an organic polymer additive (such as polyethylene oxide), and fine-tune the textured surface structure of the silicon wafer by etching with the alkaline solution containing the organic polymer additive, so as to form at least one concave portion with a light-trapping effect on at least one side surface of the pyramid unit.

[0029] Optionally, the method further includes the following steps:

[0030] S3: Etch the second surface of the silicon wafer with a chemical etching solution, and by controlling the etching conditions and time, make at least a part of the second surface of the silicon wafer form the irregular mound-like structure.

[0031] Optionally, the method further includes the following steps:

[0032] S3’: Etch the second surface of the silicon wafer with a chemical etching solution, and by controlling the etching conditions and time, make a part of the second surface of the silicon wafer form the irregular mound-like structure, wherein the section of the second surface provided with the irregular mound-like structure is located at the middle position or the end position of the second surface.

[0033] In a fourth aspect of the present application, a method for preparing the foregoing solar cell is provided. The method includes the foregoing method for preparing a silicon wafer.

[0034] To solve the problem of insufficient light trapping ability of the surface structures of conventional silicon wafers and solar cells, and to avoid the influence of the light trapping structure on the battery voltage, the present application designs the matte surface structure on the light-facing surface of the silicon wafer and the polished backlight surface differently. The surface structure of the silicon wafer is designed as follows: dense recesses are distributed on the pyramid tower surfaces on the light-facing surface, and the backlight surface includes randomly distributed irregular mound-like structures. This design enables light to undergo diffuse reflection on both the light-facing and backlight surfaces of the silicon wafer. At the same time, the equivalent gradient graded refractive index is utilized on the backlight surface to increase the internal reflection of light, significantly increasing the optical path of light on the surface and inside the silicon wafer, reducing the reflection and escape of light on the light-facing surface of the silicon wafer and solar cell as well as the transmission loss on the backlight surface. The silicon wafer and solar cell of the present invention not only have excellent light trapping performance but also do not affect the subsequent passivation effect, thereby effectively improving the current and efficiency of the solar cell.

[0035] Those skilled in the art will better understand the above and other objects, advantages, and features of the present application from the following detailed description of specific embodiments of the present application in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The features, advantages, and exemplary embodiments of the present application will be described below with reference to the accompanying drawings, in which like reference numerals indicate like elements, and:

[0037] Figure 1 Shows a schematic structural diagram of a silicon wafer according to an embodiment of the present application;

[0038] Figure 2 is Figure 1 an enlarged view of part A of the silicon wafer shown in;

[0039] Figure 3 is Figure 1 an enlarged view of part B of the silicon wafer shown in;

[0040] Figure 4 Shows a schematic structural diagram of a silicon wafer according to another embodiment of the present application;

[0041] Figure 5 is Figure 4 an enlarged view of part C of the silicon wafer shown in;

[0042] Figure 6 is Figure 4 an enlarged view of part D of the silicon wafer shown in;

[0043] Figure 7 Shows a schematic structural diagram of a silicon wafer according to the first embodiment of the present application;

[0044] Figure 8 is Figure 7 an enlarged view of part E of the silicon wafer shown in;

[0045] Figure 9 is Figure 7 an enlarged view of part F of the silicon wafer shown in

[0046] Figure 10 shows a schematic structural diagram of a silicon wafer according to a second embodiment of the present application;

[0047] Figure 11 is Figure 10 an enlarged view of part G of the silicon wafer shown in

[0048] Figure 12 is Figure 10 an enlarged view of part H of the silicon wafer shown in

[0049] Figure 13 shows a schematic structural diagram of a deformed silicon wafer according to a second embodiment of the present application;

[0050] Figure 14 shows a schematic structural diagram of a silicon wafer according to a third embodiment of the present application;

[0051] Figure 15 is Figure 14 an enlarged view of part M of the silicon wafer shown in

[0052] Figure 16 is Figure 14 an enlarged view of part N of the silicon wafer shown in

[0053] Figure 17 is an enlarged schematic view of the surface texture structure of the silicon wafer in the embodiment of the present application;

[0054] Figure 18 is another enlarged schematic view of the surface texture structure of the silicon wafer in the embodiment of the present application;

[0055] Figure 19 is an enlarged schematic view of the irregular mound structure of the silicon wafer in the embodiment of the present application; and

[0056] Figure 20 is a schematic comparison diagram of the light absorption rates of the silicon wafer in the embodiment of the present application and a conventional silicon wafer. Detailed implementation manners

[0057] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0058] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. And those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0059] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element can be "under" the other layer / element. In order to make the technical problems to be solved, technical solutions, and beneficial effects of the present application clearer and more understandable, the following further details the present application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0060] Furthermore, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0061] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0062] The surfaces of conventional silicon wafers and solar cells are usually provided with pyramid structures. It is well known in the art that the light trapping ability of the pyramid structure is insufficient, resulting in relatively large reflection losses on the light-facing surface of the solar cell. The pyramid structure on the backlight surface, which is similar to the light-facing surface structure, will cause relatively serious long-wavelength light transmission losses, ultimately affecting the current collection and efficiency of the solar cell. In order to enhance the light trapping ability of the front side of the silicon wafer or solar cell, nanoparticles can be attached to the pyramids on the light-facing surface. However, the surface structure formed by such nanoparticles will increase the deposition difficulty of the subsequent passivation layer, causing battery voltage loss, and thus the effect on improving the efficiency of the battery is not significant. In order to enhance the internal reflection of long-wavelength light on the backlight surface of the silicon wafer or solar cell, the backlight surface of the silicon wafer or solar cell can be prepared into a polished surface. However, the surface structure of such a polished surface will increase the escape loss of long-wavelength light on the light-receiving surface of the battery, and therefore is not conducive to improving the current and efficiency of the solar cell.

[0063] To solve the above technical problems, on the first hand, a silicon wafer is provided in the embodiments of the present application.

[0064] Figure 1 FIG. shows a schematic structural diagram of a silicon wafer 100 according to an embodiment of the present application. Figure 2 For Figure 1 An enlarged view of part A of the silicon wafer 100 shown in, where only one pyramid unit 11 is shown. Figure 3 For Figure 1 An enlarged view of part B of the silicon wafer 100 shown in, where two irregular mound-like units 21 are shown. Figure 4 FIG. shows a schematic structural diagram of a silicon wafer 100' according to another embodiment of the present application. Figure 5 For Figure 4 An enlarged view of part C of the silicon wafer shown in, where only one pyramid unit 11 is shown. Figure 6 For Figure 4 An enlarged view of part D of the silicon wafer shown in, where two irregular mound-like units 21 are shown. Figure 7 FIG. shows a schematic structural diagram of a silicon wafer 200 according to the first embodiment of the present application. Figure 8 For Figure 7 An enlarged view of part E of the silicon wafer 200 shown in, where only one pyramid unit 41 is shown. Figure 9 For Figure 7 An enlarged view of part F of the silicon wafer 200 shown in, where two irregular mound-like units 31 are shown. Figure 10 FIG. shows a schematic structural diagram of a silicon wafer 200' according to the second embodiment of the present application. Figure 11 For Figure 10 An enlarged view of part G of the silicon wafer 200' shown in, where only one pyramid unit 11' is shown. Figure 12 For Figure 10An enlarged view of part H of the silicon wafer 200’, in which two irregular mound-shaped units 21’ are shown. Figure 13 A schematic structural view of a deformed silicon wafer according to a second embodiment of the present application is shown. Figure 14 A schematic structural view of the silicon wafer 200” according to a third embodiment of the present application is shown. Figure 15 is Figure 14 An enlarged view of part M of the silicon wafer 200” shown in , in which only one pyramid unit 11” is shown. Figure 16 is Figure 14 An enlarged view of part N of the silicon wafer 200” shown in , in which two irregular mound-shaped units 21” are shown. Figure 17 An enlarged side view of the textured surface structure of the silicon wafer in the embodiment of the present application. Figure 18 An enlarged top view of the textured surface structure of the silicon wafer in the embodiment of the present application. Figure 19 An enlarged side view of the irregular mound-shaped structure of the silicon wafer in the embodiment of the present application. Figure 20 A schematic comparison diagram of the light absorption rates of the silicon wafer in the embodiment of the present application and a conventional silicon wafer.

[0065] As Figures 1 to 6 shown, the silicon wafer 100 has opposite first surface 110 and second surface 120. The first surface 110 is provided with a textured surface structure 10, and at least a part of the second surface 120 is provided with an irregular mound-shaped structure 20. The first surface 110 can be the light-facing surface of the silicon wafer. From a microscopic perspective, the textured surface is a surface with an uneven micro-textured surface structure. The textured surface structure located on the first surface 110 can play a role in light trapping to reduce the reflection of light by the first surface 110 of the solar cell, so that more light can be refracted into the solar cell, improving the utilization rate of light energy by the solar cell. The second surface 120 can be the backlight surface of the silicon wafer. Among them, the irregular mound-shaped structure 20 can increase the internal light reflection in the silicon wafer through multiple reflections and optical resonance. Compared with the planar structure, this complex surface morphology greatly increases the path length of light propagation inside the material through an equivalent gradient refractive index, reducing the escape of light inside the silicon wafer from the second surface. At the same time, since the reflected light rays of the light inside the silicon wafer reflected by the irregular mound-shaped structure have different directions inside the silicon wafer, the escape of the internally reflected light rays from the surface of the textured surface structure on the first surface 110 is further reduced.

[0066] Specifically, Figures 1 to 3 A silicon wafer 100 according to an embodiment of the present application is shown. Among them, the first surface 110 of the silicon wafer 100 is provided with a textured surface structure 10, and the entire second surface 120 of the silicon wafer 100 is provided with an irregular mound-shaped structure 20, and the irregular mound-shaped structure 20 includes a plurality of irregular mound-shaped units 21. As Figure 3As shown in more detail, the irregular mound-shaped unit 21 as a whole is in a shape similar to a hill, with a relatively rounded top and no obvious sharp edges. The contour line on its side is relatively smooth, without obvious straight line segments, but presenting a natural undulating curve shape. It should be noted that although in the view shown in this application, the irregular mound-shaped units 21 are orderly shown in regular geometric shapes, in other embodiments not shown in this application, the irregular mound-shaped units may not have a consistent geometric shape, but have a certain degree of randomness and irregularity.

[0067] In addition, as Figure 3 shown, each irregular mound-shaped unit 21 has a mound diameter 122 along the first direction D1 and a mound height 121 along the second direction D2. In this embodiment, the mound height 121 is less than the mound diameter 122. It should be noted that in other embodiments not shown in this application, the mound height 121 may also be greater than the mound diameter 122.

[0068] Figures 4 to 6 Another silicon wafer 100' according to an embodiment of the present application is shown. A matte surface structure 10 identical to the matte surface structure of the silicon wafer 100 shown in Figures 1 to 3 is provided on the first surface 110' of the silicon wafer 100'. Different from the silicon wafer 100 shown in Figures 1 to 3 , only a part of the second surface 120' of the silicon wafer 100' is provided with an irregular mound structure 20. The irregular mound structure 20 includes a plurality of irregular mound-shaped units 21. Among them, the shape and size of the irregular mound-shaped units 21 are similar to those of the irregular mound-shaped units shown in Figures 1 to 3 . For the sake of brevity, they will not be described again here.

[0069] According to the technical solution of the present application, by providing an irregular mound structure on the second surface of the silicon wafer, on the one hand, the incident light received through the first surface of the silicon wafer can be diffusely reflected inside the silicon wafer and on the inner side of the second surface of the silicon wafer, thereby increasing the internal reflection of the light incident into the silicon wafer and reducing the escape of the light inside the silicon wafer from the second surface; on the other hand, since the reflected light rays reflected by the irregular mound structure of the incident light into the silicon wafer have different light propagation directions inside the silicon wafer, the escape of the reflected light rays reflected by the irregular mound structure from the surface of the matte surface structure on the first surface is further reduced, improving the ability to generate photo-generated carriers inside the silicon wafer, and thus improving the photoelectric conversion efficiency.

[0070] Optionally, the average value of the mound height 121 of the irregular mound-shaped unit 21 is greater than or equal to 10 nm and less than or equal to 200 nm, and the average value of the mound diameter 122 of the irregular mound-shaped unit 21 is greater than or equal to 20 nm and less than or equal to 400 nm.

[0071] For example, the average value of the mound height 121 of the irregular mound unit 21 may be 10 nm, or 20 nm, or 30 nm, or 40 nm, or 50 nm, or 60 nm, or 70 nm, or 80 nm, or 90 nm, or 100 nm, or 110 nm, or 120 nm, or 130 nm, or 140 nm, or 150 nm, or 160 nm, or 170 nm, or 180 nm, or 190 nm, or 200 nm, or any value between any two of the above.

[0072] For example, the average value of the mound diameter 122 of the irregular mound unit 21 may be 20 nm, or 30 nm, or 40 nm, or 50 nm, or 60 nm, or 70 nm, or 80 nm, or 90 nm, or 100 nm, or 110 nm, or 120 nm, or 130 nm, or 140 nm, or 150 nm, or 160 nm, or 170 nm, or 180 nm, or 190 nm, or 200 nm, or 210 nm, or 220 nm, or 230 nm, or 240 nm, or 250 nm, or 260 nm, or 270 nm, or 280 nm, or 290 nm, or 300 nm, or 310 nm, or 320 nm, or 330 nm, or 340 nm, or 350 nm, or 360 nm, or 370 nm, or 380 nm, or 390 nm, or 400 nm, or any value between any two of the above.

[0073] Preferably, the average value of the mound height 121 of the irregular mound unit 21 is greater than or equal to 20 nm and less than or equal to 100 nm, and the average value of the mound diameter 122 of the irregular mound unit 21 is greater than or equal to 30 nm and less than or equal to 300 nm.

[0074] In the embodiments of the present application, the average value of the ratio of the mound height 121 to the mound diameter 122 of the irregular mound unit 21 is greater than 0 and less than or equal to 0.5. Preferably, the average value of the ratio of the mound height 121 to the mound diameter 122 of the irregular mound unit 21 is greater than 0.03 and less than or equal to 0.3.

[0075] For example, the ratio of the mound height 121 of the irregular mound unit 21 to the mound diameter 122 of the irregular mound unit 21 can be 0.03, or 0.06, or 0.1, or 0.13, or 0.16, or 0.2, or 0.23, or 0.26, or 0.3, or 0.33, or 0.36, or 0.4, or 0.43, or 0.46, or 0.5, or any value between any two of the above.

[0076] Preferably, the average value of the ratio of the mound height 121 of the irregular mound unit 21 to the mound diameter 122 of the irregular mound unit 21 is greater than 0.05 and less than or equal to 0.2.

[0077] It should be noted that the specific values of the mound height 121 and the mound diameter 122 of the irregular mound unit 21 are also related to the shape and size of the pyramid unit 11 of the matte surface structure 10, which will be described in detail later.

[0078] Optionally, the ratio of the area of the section of the second surface provided with the irregular mound structure 20 to the total area of the second surface is greater than 0 and less than or equal to 100%.

[0079] For example, the ratio of the area of the section of the second surface provided with the irregular mound structure 20 to the total area of the second surface can be 5%, or 10%, or 15%, or 20%, or 25%, or 30%, or 35%, or 40%, or 45%, or 50%, or 55%, or 60%, or 65%, or 70%, or 75%, or 80%, or 85%, or 90%, or 95%, or 100%, or any value between any two of the above.

[0080] Preferably, the ratio of the area of the section of the second surface provided with the irregular mound structure 20 to the total area of the second surface is greater than 10% and less than or equal to 100%.

[0081] Optionally, the sections of the second surface provided with the irregular mound structure 20 are randomly or regularly distributed on the second surface of the silicon wafer as needed.

[0082] Such as Figures 1 to 6As shown, the suede structure 10 includes a plurality of pyramid units 11, and at least one concave portion 102 is provided on at least one side surface 101 of each pyramid unit 11. Specifically, the pyramid unit 11 is a regular pyramid. Among them, the average value of the pyramid height 111 of the pyramid unit 11 is greater than or equal to 0.2 μm and less than or equal to 10 μm. Preferably, the average value of the pyramid height 111 of the pyramid unit 11 is greater than or equal to 0.8 μm and less than or equal to 3 μm; the average value of the distance 112 between the apexes of adjacent pyramid units 11 is greater than or equal to 0.14 μm and less than or equal to 20 μm. Preferably, the average value of the distance 112 between the apexes of adjacent pyramid units 11 is greater than or equal to 0.58 μm and less than or equal to 6 μm; the average value of the pyramid base angle α of the pyramid unit 11 is greater than or equal to 45° and less than or equal to 70°. Preferably, the average value of the pyramid base angle α of the pyramid unit 11 is greater than or equal to 48° and less than or equal to 60°.

[0083] For example, the average value of the pyramid height 111 of the pyramid unit 11 can be 0.2 μm, or 0.4 μm, or 0.6 μm, or 0.8 μm, or 1 μm, or 1.2 μm, or 1.4 μm, or 1.6 μm, or 1.8 μm, or 2 μm, or 2.2 μm, or 2.4 μm, or 2.6 μm, or 2.8 μm, or 3 μm, or 3.2 μm, or 3.4 μm, or 3.6 μm, or 3.8 μm, or 4 μm, or 4.2 μm, or 4.4 μm, or 4.6 μm, or 4.8 μm, or 5 μm, or 5.2 μm, or 5.4 μm, or 5.6 μm, or 5.8 μm, or 6 μm, or 6.2 μm, or 6.4 μm, or 6.6 μm, or 6.8 μm, or 7 μm, or 7.2 μm, or 7.4 μm, or 7.6 μm, or 7.8 μm, or 8 μm, or 8.2 μm, or 8.4 μm, or 8.6 μm, or 8.8 μm, or 9 μm, or 9.2 μm, or 9.4 μm, or 9.6 μm, or 9.8 μm, or 10 μm, or any value between any two of the above.

[0084] For example, the average value of the distance 112 between the tops of adjacent pyramid cells 11 can be 0.14 μm, or 0.58 μm, or 1 μm, or 1.14 μm, or 1.58 μm, or 2 μm, or 2.14 μm, or 2.58 μm, or 3 μm, or 3.14 μm, or 3.58 μm, or 4 μm, or 4.14 μm, or 4.58 μm, or 5 μm, or 5.14 μm, or 5.58 μm, or 6 μm, or 6.14 μm, or 6.58 μm, or 7 μm, or 7.14 μm, or 7.58 μm, or 8 μm, or 8.14 μm, or 8.58 μm, or 9 μm, or 9.14 μm, or 9.58 μm, or 10 μm, or 10.14 μm, or 10.58 μm, or 11 μm, or 11.14 μm, or 11.58 μm, or 12 μm, or 12.14 μm, or 12.58 μm, or 13 μm, or 13.14 μm, or 13.58 μm, or 14 μm, or 14.14 μm, or 14.58 μm, or 15 μm, or 15.14 μm, or 15.58 μm, or 16 μm, or 16.14 μm, or 16.58 μm, or 17 μm, or 17.14 μm, or 17.58 μm, or 18 μm, or 18.14 μm, or 18.58 μm, or 19 μm, or 19.14 μm, or 19.58 μm, or 20 μm, or any value between any two of the above.

[0085] For example, the average value of the pyramid base angle α of the pyramid cell 11 can be 45°, or 48°, or 50°, or 52°, or 55°, or 58°, or 60°, or 62°, or 65°, or 68°, or 70°.

[0086] In addition, a number of concave portions 102 that are recessed toward the inside of the pyramid cell 11 are distributed on the pyramid cell 11. The concave portions 102 are substantially circular on the side surface of the pyramid cell 11. Specifically, in the embodiment of the present application, three concave portions 102 are provided on each side surface 101 of the pyramid cell 11. These three concave portions 102 are arranged at approximately equal intervals in the middle position of the side surface 101. Neither the top nor the bottom of the pyramid has a smooth arc or circular structure. By setting it in this way, incident light can undergo diffuse reflection at the concave portions on the side surface, increasing the number of reflections of the incident light on the light-facing surface of the silicon wafer. In particular, it can increase the light trapping effect of short-wavelength light on the first surface of the silicon wafer and reduce the reflectivity of the incident short-wavelength light on the first surface of the silicon wafer. It should be understood that in other embodiments not shown in the present application, other numbers of concave portions 102 may also be provided on each side surface 101 of the pyramid cell 11.

[0087] According to the technical solution of the present application, a matte surface structure is provided on the light-facing surface of the silicon wafer, and at the same time, an irregular mound-like structure is provided on the backlight surface of the silicon wafer. The matte surface structure and the irregular mound-like structure can cooperate to exert significant advantages. Specifically, the irregular mound-like structure on the backlight surface can significantly increase the internal reflection and light scattering phenomena on the backlight surface, making the propagation path of light inside the silicon wafer more complex and rich; while the irregular concave portions on the light-facing surface can further enhance the scattering effect of the light reflected from the backlight surface to the light-facing surface, thereby effectively reducing the escape of light from the surface of the matte surface structure on the light-facing surface. By combining the matte surface structure and the irregular mound-like structure, the synergistic improvement effect generated is more significant than using any one of the structures alone, which can significantly improve the light utilization efficiency of the silicon wafer, and further effectively improve the current and efficiency of the solar cell.

[0088] It should be noted that although in the views shown in the present application, the pyramid units are orderly shown in regular geometric shapes, in other embodiments not shown in the present application, the pyramid units may not have consistent geometric shapes, but are randomly and irregularly distributed on the first surface of the silicon wafer.

[0089] In addition, the average value of the depth 113 of the concave portion 102 is greater than or equal to 3 nm and less than or equal to 200 nm, and the average value of the concave diameter 114 of the concave portion 102 is greater than or equal to 5 nm and less than or equal to 2000 nm. Preferably, the average value of the depth 113 of the concave portion 102 is greater than or equal to 5 nm and less than or equal to 50 nm, and the average value of the concave diameter 114 of the concave portion 102 is greater than or equal to 10 and less than or equal to 150 nm.

[0090] For example, the average value of the depth 113 of the concave portion 102 can be 3 nm, or 10 nm, or 20 nm, or 30 nm, or 40 nm, or 50 nm, or 60 nm, or 70 nm, or 80 nm, or 90 nm, or 100 nm, or 110 nm, or 120 nm, or 130 nm, or 140 nm, or 150 nm, or 160 nm, or 170 nm, or 180 nm, or 190 nm, or 200 nm, or any value between any two of the above.

[0091] For example, the average value of the recess diameter 114 of the recess 102 can be 5 nm, or 10 nm, or 20 nm, or 30 nm, or 40 nm, or 50 nm, or 60 nm, or 70 nm, or 80 nm, or 90 nm, or 100 nm, or 110 nm, or 120 nm, or 130 nm, or 140 nm, or 150 nm, or 160 nm, or 170 nm, or 180 nm, or 190 nm, or 200 nm, or 210 nm, or 220 nm, or 230 nm, or 240 nm, or 250 nm, or 260 nm, or 270 nm, or 280 nm, or 290 nm, or 300 nm, or 310 nm, or 320 nm, or 330 nm, or 340 nm, or 350 nm, or 360 nm, or 370 nm, or 380 nm, or 390 nm, or 400 nm, or 450 nm, or 500 nm, or 550 nm, or 600 nm, or 650 nm, or 700 nm, or 750 nm, or 800 nm, or 850 nm, or 900 nm, or 950 nm, or 1000 nm, or 1050 nm, or 1100 nm, or 1150 nm, or 1200 nm, or 1250 nm, or 1300 nm, or 1350 nm, or 1400 nm, or 1450 nm, or 1500 nm, or 1550 nm, or 1600 nm, or 1650 nm, or 1700 nm, or 1750 nm, or 1800 nm, or 1850 nm, or 1900 nm, or 1950 nm, or 2000 nm, or any value between any two of the above.

[0092] Optionally, the entire second surface is provided with an irregular mound structure, or the section of the second surface provided with the irregular mound structure is located at the middle position or the end position of the second surface. Specifically, as Figures 1 to 3 shown, the entire second surface can be provided with an irregular mound structure. In addition, as Figures 4 to 15 shown, the second surface can be partially provided with an irregular mound structure, wherein the section of the second surface provided with the irregular mound structure can be located at the middle position of the second surface, or at the end position of the second surface, and the section of the second surface not provided with the irregular mound structure can be a flat surface. By setting it in this way, it is possible to improve the spatial distribution of the long-wavelength light incident into the silicon wafer, increase the internal reflection of the long-wavelength light on the second surface, and reduce the escape of the internally reflected light on the surface of the textured structure of the first surface.

[0093] As Figures 4 to 15As shown, the second surface can form a high-level area and a low-level area with a staggered distribution. The height difference between the high-level area and the low-level area is greater than 0 μm and less than or equal to 10 μm, and only the low-level area is provided with irregular mound-like structures. Specifically, as Figure 4 shown, the second surface 120’ can form a high-level area 201 and a low-level area 202 with a staggered distribution. The entire surface of the low-level area 202 is provided with irregular mound-like structures. By providing a high-level area and a low-level area on the second surface, on the one hand, the light incident into the silicon wafer can be continuously reflected between the high-level area and the low-level area, increasing the optical path of the light inside the silicon wafer, thereby increasing the absorption probability of the light. On the other hand, the staggered high-level area and low-level area can better adapt to the light with different angles and intensities incident into the silicon wafer, enabling the silicon wafer to effectively capture the light and improving the utilization rate of the silicon wafer for different ambient light. On the other hand, the high-level area and the low-level area can provide more space and flexibility for the layout of the back electrode. The electrodes can be better distributed in these high and low areas, reducing the path length and resistance of the current during transmission.

[0094] For example, the height difference between the high-level area and the low-level area can be 5 nm, or 10 nm, or 20 nm, or 30 nm, or 40 nm, or 50 nm, or 60 nm, or 70 nm, or 80 nm, or 90 nm, or 100 nm, or 110 nm, or 120 nm, or 130 nm, or 140 nm, or 150 nm, or 160 nm, or 170 nm, or 180 nm, or 190 nm, or 200 nm, or 210 nm, or 220 nm, or 230 nm, or 240 nm, or 250 nm, or 260 nm, or 270 nm, or 280 nm, or 290 nm, or 10 μm, or any value between any two of the above.

[0095] Figure 19 shows a comparison schematic diagram of the light absorption rates of the silicon wafer in the embodiment of the present application and a traditional silicon wafer. Among them, the first surface of the silicon wafer in the embodiment of the present application is provided with a pyramid velvet surface structure with recesses, at least a part of the second surface of the silicon wafer is provided with irregular mound-like structures, and among them, the first surface and the second surface of the traditional silicon wafer are both provided with pyramid velvet surface structures. As Figure 19As shown, for light of different wavelengths, the absorbance of the silicon wafer of the present application is higher than that of the conventional silicon wafer. Among them, the significant increase in the absorbance of light in the short-wavelength region on the silicon wafer of the present application compared to the conventional silicon wafer is mainly due to the reduced reflection loss of short-wavelength light on the pyramid texture structure with concave portions. And the significant increase in the absorbance of light in the long-wavelength region on the silicon wafer of the present application compared to the conventional silicon wafer is mainly due to the increased internal reflection of long-wavelength light on the second side, reducing the escape of internally reflected light on the surface of the texture structure on the first side.

[0096] In the second aspect of the present application, a solar cell is provided, and the solar cell includes the aforementioned silicon wafer.

[0097] In terms of the formation positions of the positive electrode and the negative electrode of the battery, the solar cell provided in the embodiment of the present application can be a double-sided contact solar cell with the positive electrode and the negative electrode on different sides, enabling the solar cell to receive light from both sides, effectively utilizing the reflected light in the environment, and improving the photoelectric conversion efficiency of the solar cell; in addition, the solar cell provided in the embodiment of the present application can also be a back-contact battery with both the positive electrode and the negative electrode on the backlight side.

[0098] Figures 7 to 9 FIG. shows a schematic structural diagram of a silicon wafer 200 according to the first embodiment of the present application. The silicon wafer 200 can be applied to a double-sided contact solar cell. Among them, a first doped semiconductor layer 4 is provided on the first side 210 of the silicon wafer 200, and a second doped semiconductor layer 3 is provided on the second side 220 of the silicon wafer 200. Specifically, in this embodiment, a texture structure is provided on the surface of the first doped semiconductor layer 4, and the texture structure includes a plurality of positive pyramid units 41. Among them, the pyramid height 211 of the pyramid unit 41, the distance 212 between the tops of adjacent pyramid units 41, the pyramid base angle α of the pyramid unit 41, and the depth 213 and the diameter 214 of the concave portion provided on the side surface of the pyramid unit 41 and other features are similar to those of the pyramid unit 11 and the shape, size, and distribution manner of the concave portion shown in the previous description Figures 1 to 6 are similar, and for the sake of brevity, they will not be described in detail here. By providing a texture structure on the surface of the first doped semiconductor layer 4, on the one hand, the light trapping effect on the surface of the first doped semiconductor layer is increased, improving the photoelectric conversion efficiency of the solar cell; on the other hand, the distribution of current on the surface of the first doped semiconductor layer is made more uniform, avoiding local overheating caused by current concentration in certain areas, and improving the stability and reliability of the solar cell.

[0099] In addition, an irregular mound-like structure is provided on the surface of the second doped semiconductor layer 3. The irregular mound-like structure includes a plurality of irregular mound units 31. Among them, the mound diameter 222, mound height 221 of the irregular mound unit 31, and the area ratio of the irregular mound-like structure 31 in the second surface and other features are the same as those described in the previous text Figures 1 to 6 The shape, size, area ratio in the second surface, and distribution mode of the irregular mound unit 21 shown in Figure 7 are similar. For the sake of brevity, they will not be elaborated here. As

[0100] shown, the irregular mound-like structure 31 is provided at one end of the second surface 220 in the first direction. By providing the irregular mound-like structure on the surface of the second doped semiconductor layer 3, on the one hand, the internal reflection of the incident light into the silicon wafer is increased through the diffuse reflection inside the irregular mound-like structure, thereby reducing the escape of the internally reflected light on the surface of the textured structure of the first doped semiconductor layer 4 and improving the light absorption efficiency; on the other hand, more photons can interact with the second doped semiconductor layer 3 to generate more photo-generated carriers, improving the photoelectric conversion efficiency of the solar cell.

[0101] Optionally, the double-sided contact solar cell can be a TOPCON (Tunnel Oxide Passivated Contact solar cell) cell. Among them, the first doped semiconductor layer 4 is a P-type doped polysilicon layer, and the second doped semiconductor layer 3 is an N-type doped polysilicon layer.

[0102] Optionally, the double-sided contact solar cell can be an HJT (Heterojunction Technology) cell. Among them, the first doped semiconductor layer 4 can be a P-type doped amorphous silicon layer, nanocrystalline silicon layer, microcrystalline silicon layer, nano-oxide layer or micro-oxide layer, and the second doped semiconductor layer 3 can be an N-type doped amorphous silicon layer, nanocrystalline silicon layer, microcrystalline silicon layer, nano-oxide layer or micro-oxide layer.

[0103] Optionally, the first doped semiconductor layer 4 may be an N-type doped polysilicon layer, and the second doped semiconductor layer 3 may be a P-type doped amorphous silicon layer, a nanocrystalline silicon layer, a microcrystalline silicon layer, a nano-silicon oxide layer or a micro-silicon oxide layer. The reason for such a design is that in the N-type doped region of a crystalline silicon cell, compared with materials such as N-type doped amorphous silicon, nanocrystalline silicon, and microcrystalline silicon, N-type doped polysilicon has more excellent passivation contact performance. Therefore, N-type doped polysilicon is selected in the N-type doped region; while in the P-type doped region, the passivation contact effect of materials such as P-type doped amorphous silicon, nanocrystalline silicon, and microcrystalline silicon is better than that of P-type doped polysilicon. Therefore, it is more appropriate to select materials such as P-type doped amorphous silicon, nanocrystalline silicon, and microcrystalline silicon in the P-type doped region.

[0104] As described above, the solar cell may also be a back-contact solar cell, wherein a first doped semiconductor layer and a second doped semiconductor layer are provided on the second surface, the second doped semiconductor layer is provided in a region of the second surface including an irregular mound-like structure, and the second doped semiconductor layer is a P-type doped amorphous silicon layer or a P-type doped polysilicon layer. Specifically, in the embodiments of the present application, the second surface of the solar cell may be entirely provided with an irregular mound-like structure; or the second surface may be partially provided with an irregular mound-like structure, wherein the section of the second surface provided with the irregular mound-like structure may be located in the middle position of the second surface, or at the end position of the second surface, and the section of the second surface not provided with the irregular mound-like structure may be a plane. In addition, the second doped semiconductor layer may be a P-type semiconductor layer, specifically, it may be a P-type doped polysilicon layer or a P-type doped amorphous silicon layer.

[0105] Figures 10 to 12 FIG. shows a schematic structural diagram of a silicon wafer 200' according to the second embodiment of the present application. The silicon wafer 200' can be applied to a back-contact solar cell. Among them, a high-level region 201' and a low-level region 202' are formed on the second surface 220' in a staggered distribution. The low-level region 202' is entirely provided with an irregular mound-like structure 20'. The low-level region 202' includes a first section 2021, a second section 2022, and a third section 2023. The second section 2022 separates the first section 2021 and the third section 2023. The high-level region 201' and the first section 2021 adjacent to the high-level region 201' are provided with a second doped semiconductor layer 3', and the third section 2023 is provided with a first doped semiconductor layer 4'. Specifically, in this embodiment, the first surface 210' is the light-facing surface, the second surface 220' is the backlight-facing surface, and the first surface 210' is provided with a textured structure 10'. The textured structure includes a plurality of regular pyramid units 11'. Among them, the pyramid height 211' of the pyramid unit 11', the distance 212' between the apexes of adjacent pyramid units 11', the pyramid base angle α of the pyramid unit 11', and the depth 213' and the diameter 214' of the concave portion provided on the side surface of the pyramid unit 11' and other features are the same as those described aboveFigures 1 to 6 The shapes, dimensions, and distribution patterns of the pyramid units 11 and the concave portions shown therein are similar. For the sake of brevity, they will not be elaborated here. By providing a matte structure 10' on the first surface 210', the light trapping effect of the first surface 210' is enhanced, improving the photoelectric conversion efficiency of the solar cell.

[0106] In addition, the entire surface of the high-rise area 201' is planar. The high-rise area 201' is arranged adjacent to the first segment 2021 of the low-rise area 202'. A second doped semiconductor layer 3' is provided between the high-rise area 201' and the first segment 2021 of the low-rise area 202'. The third segment 2023 of the low-rise area 202' is provided with a first doped semiconductor layer 4'. The second segment 2022 of the low-rise area 202' separates the second doped semiconductor layer 3' from the first doped semiconductor layer 4'. That is to say, the segments of the second surface 220' where the irregular hill-like structure 20' is provided are arranged with the first doped semiconductor layer 4' and a part of the second doped semiconductor layer 3'. It should be noted that the irregular hill-like structure 20' includes a plurality of irregular hill-like body units 21'. Among them, the characteristics such as the hill-like body diameter 222', the hill-like body height 221', and the area ratio of the irregular hill-like structure 21' in the second surface 220' are similar to those of the Figures 1 to 6 irregular hill-like body units 21 shown therein in terms of shape, dimensions, the ratio in the second surface, and distribution pattern. For the sake of brevity, they will not be elaborated here. Similarly, the irregular hill-like structure 21' is provided at one end of the second surface 220' in the first direction. By providing the irregular hill-like structure 21' on the surfaces of the first doped semiconductor layer 4' and a part of the second doped semiconductor layer 3', on the one hand, the internal reflection of the light incident into the silicon wafer is increased through the diffuse reflection inside the irregular hill-like structure, thereby reducing the escape of the internally reflected light on the surface of the matte structure of the first surface 210' and improving the light absorption efficiency. On the other hand, more photons can interact with the first doped semiconductor layer 4' and a part of the second doped semiconductor layer 3', generating more photo-generated carriers and improving the photoelectric conversion efficiency of the solar cell.

[0107] Figure 13FIG. 0 shows a schematic structural diagram of a silicon wafer 200' according to a modified embodiment of the second embodiment of the present application. The silicon wafer 200' can be applied to a back-contact solar cell. Among them, the second surface 220' forms a high-level region 201' and a low-level region 202' that are staggeredly distributed. The entire surface of the high-level region 201' is provided with an irregular mound-like structure 20'. The high-level region 201' includes a first segment 2011, a second segment 2012, and a third segment 2013. The second segment 2012 separates the first segment 2011 and the third segment 2013. The high-level region 201' and the first segment 2011 adjacent to the low-level region 202' are provided with a second doped semiconductor layer 3', and the third segment 2013 is provided with a first doped semiconductor layer 4'. Specifically, in this embodiment, the first surface 210' is the light-facing surface, and the second surface 220' is the backlight surface. The first surface 210' is provided with a textured surface structure 10', and the textured surface structure includes a plurality of regular pyramid units 11'. Among them, the pyramid height 211' of the pyramid unit 11', the distance 212' between the apexes of adjacent pyramid units 11', the pyramid base angle α of the pyramid unit 11', and the depth 213' and diameter 214' of the recess on the side surface of the pyramid unit 11' and other features are the same as those described in the Figures 1 to 6 shown in the pyramid unit 11 and the shape, size, and distribution of the recesses are similar. For the sake of brevity, they will not be described here again. By providing the textured surface structure 10' on the first surface 210', the light trapping effect of the first surface 210' is increased, and the photoelectric conversion efficiency of the solar cell is improved.

[0108] In addition, the entire surface of the low-level region 202' is a plane. The low-level region 202' is arranged adjacent to the first segment 2011 of the high-level region 201'. The low-level region 202' and the first segment 2011 of the high-level region 201' are provided with a second doped semiconductor layer 3'. The third segment 2013 of the high-level region 201' is provided with a first doped semiconductor layer 4'. The second segment 2012 of the high-level region 201' separates the second doped semiconductor layer 3' from the first doped semiconductor layer 4'. That is to say, the section of the second surface 220' provided with the irregular mound-like structure 20' is arranged with a first doped semiconductor layer 4' and a part of the second doped semiconductor layer 3'. Or the entire high-level region is provided with a first doped semiconductor layer 4', the second doped semiconductor layer 3' covers the first segment 2011, and the first semiconductor layer 4' and the second doped semiconductor layer 3' are isolated by an insulating film (not shown in the figure).

[0109] It should be noted that the irregular mound-like structure 20' includes a plurality of irregular mound body units 21'. Among them, the mound body diameter 222', the mound body height 221' of the irregular mound body unit 21', and the area ratio of the irregular mound-like structure 21' in the second surface 220' and other features are the same as those described in the Figures 1 to 6The shapes, sizes, proportions in the second surface, and distribution patterns of the irregular mound-shaped units 21 shown are similar, and for the sake of brevity, they will not be elaborated here. Similarly, an irregular mound-shaped structure 21' is disposed at one end of the second surface 220' in the first direction. By providing the irregular mound-shaped structure 21' on the surfaces of the first doped semiconductor layer 4' and a part of the second doped semiconductor layer 3', on the one hand, the internal reflection of the incident light into the silicon wafer is increased through the diffuse reflection inside the irregular mound-shaped structure, thereby reducing the escape of the internally reflected light on the surface of the textured structure of the first surface 210', and improving the light absorption efficiency; on the other hand, more photons can interact with the first doped semiconductor layer 4' and a part of the second doped semiconductor layer 3', generating more photo-generated carriers and improving the photoelectric conversion efficiency of the solar cell.

[0110] Figures 14 to 16 FIG. shows a schematic structural diagram of a silicon wafer 200'' according to a third embodiment of the present application. The silicon wafer 200'' can be applied to a back-contact solar cell. Among them, the second surface 220'' forms a high-level region 201'' and a low-level region 202'' with a staggered distribution. The low-level region 202'' is entirely provided with an irregular mound-shaped structure 20''. The high-level region 201'' includes a first high-level section 2011 and a second high-level section 2012. The low-level region 202'' separates the first high-level section 2011 and the second high-level section 2012. The first high-level section 2011 is provided with a second doped semiconductor layer 3'', and the second high-level section 2012 is provided with a first doped semiconductor layer 4''. Specifically, in this embodiment, the first surface 210'' is the light-facing surface, and the second surface 220'' is the backlight surface. The first surface 210'' is provided with a textured structure 10'', and the textured structure includes a plurality of regular pyramid units 11''. Among them, the pyramid height 211'' of the pyramid unit 11'', the distance 212'' between the tops of adjacent pyramid units 11'', the pyramid base angle α of the pyramid unit 11'', and the depth 213'' and the recess diameter 214'' of the recess provided on the side surface of the pyramid unit 11'' and other features are similar to those of the Figures 1 to 6 pyramid unit 11 and the shape, size, and distribution pattern of the recess shown above, and for the sake of brevity, they will not be elaborated here. By providing the textured structure 10'' on the first surface 210'', the light trapping effect of the first surface 210'' is increased, and the photoelectric conversion efficiency of the solar cell is improved.

[0111] In addition, an irregular hill-like structure 20” is provided across the entire low-layer region 202”. The irregular hill-like structure 20” is disposed between the first high-layer section 2011 and the second high-layer section 2012 of the high-layer region 201”, thereby spacing apart the second doped semiconductor layer 3” from the first doped semiconductor layer 4”, resulting in a lower probability of short circuit and enabling a higher yield and reliability to be maintained. It should be noted that, in this embodiment, the irregular hill-like structure 20” includes a plurality of irregular hill-like body units 21”. Among them, features such as the hill-like body diameter 222”, the hill-like body height 221” of the irregular hill-like body unit 21” and the area ratio of the irregular hill-like structure 21” in the second surface 220” are similar to those of the irregular hill-like body unit 21 shown in Figures 1 to 6 described above. For the sake of brevity, they will not be elaborated here. By providing the irregular hill-like structure 21”, the internal reflection of the light incident into the silicon wafer can be increased through the diffuse reflection and optical resonance inside the irregular hill-like structure, thereby reducing the escape of the internally reflected light on the surface of the velvet-like structure of the first surface 210” and improving the light absorption efficiency.

[0112] In a third aspect of the present application, a method for preparing the aforementioned silicon wafer is provided. The method includes the following steps:

[0113] S1: Acid-etch the first surface of the silicon wafer to be velvetized, and then perform alkali velvetization so that a velvet-like structure is formed on the first surface. The velvet-like structure may include a plurality of pyramid units; and

[0114] S2: Immerse the silicon wafer after step S1 in an alkaline solution containing an organic polymer additive (such as polyethylene oxide), and fine-tune the velvet-like structure of the silicon wafer through the etching of the alkaline solution containing the organic polymer additive to form at least one concave portion having a light-trapping effect on at least one surface of the pyramid unit.

[0115] Figure 17 and Figure 18 shows a partially enlarged schematic view of the velvet-like structure of the silicon wafer, where the pyramid units are randomly and irregularly distributed on the first surface of the silicon wafer.

[0116] In addition, the method for preparing the silicon wafer further includes the following steps:

[0117] S3: Etch the second surface of the silicon wafer using a chemical etching solution. By controlling the etching conditions and time, at least a part of the second surface of the silicon wafer is formed with an irregular hill-like structure.

[0118] In step S3, a mask such as silicon nitride, photoresist, etc. can be used to form an irregular hill-like structure in part on the second surface. Alternatively, in step S3, an irregular hill-like structure can be formed first, and then an irregular hill-like structure can be formed in part on the second surface through laser etching or wet etching.

[0119] Figure 19 Shows an enlarged side view of the irregular mound-like structure of the silicon wafer in the embodiment of the present application. Among them, the irregular mound-like structures are randomly and irregularly distributed on the second surface of the silicon wafer.

[0120] Optionally, the method for preparing the silicon wafer further includes the following steps:

[0121] S3': Etch the second surface of the silicon wafer with a chemical etching solution. By controlling the etching conditions and time, a part of the second surface of the silicon wafer forms an irregular mound-like structure. Among them, the section with the irregular mound-like structure on the second surface is located at the middle position or the end position of the second surface.

[0122] According to an alternative solution of the embodiment of the present application, first, the second surface of the silicon wafer is etched with an alkaline solution containing an organic molecular additive with a specific functional group (for example, dodecyltrimethylammonium chloride). During this process, the organic molecule containing the specific functional group can protect the second surface from forming an undesired textured structure and promote the formation of a polished surface on the second surface. At this time, a polished surface is formed on the entire second surface. Subsequently, the second surface of the silicon wafer with the polished surface formed is further modified and etched with an alkaline solution containing an organic polymer additive (for example, polyethylene oxide) to form an irregular mound-like structure. Among them, this modified etching needs to be carried out under specific conditions: the modified etching temperature is set at 70 °C, the modified etching time is controlled at 110 s, and the concentration of NaOH in the alkaline solution is ensured to be 3%. In the fourth aspect of the present application, a method for preparing the aforementioned solar cell is provided, and this method includes the aforementioned method for preparing the silicon wafer. For the sake of brevity, it will not be elaborated here.

[0123] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "one example", "some examples", or "preferred embodiment" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0124] The embodiments of the present application have been described in detail above. However, the aspects of the present application are not limited to the above embodiments. Without departing from the scope of the present application, various modifications and substitutions can be applied to the above embodiments.

Claims

1. A silicon wafer, characterized in that: The silicon wafer has a first surface and a second surface opposite to each other, the first surface is provided with a velvet structure, and at least a portion of the second surface is provided with an irregular hill-like structure.

2. The silicon wafer according to claim 1, characterized in that: The irregular hillock structure includes a plurality of irregular hillock units, the average hillock height of the irregular hillock units is greater than or equal to 10 nm and less than or equal to 200 nm, and the average hillock diameter of the irregular hillock units is greater than or equal to 20 nm and less than or equal to 400 nm.

3. The silicon wafer according to claim 2, characterized in that: An average value of the ratio of the mound height of the irregular mound unit to the mound diameter of the irregular mound unit is greater than 0 and less than or equal to 0.

5.

4. The silicon wafer according to claim 1, characterized in that: The ratio of the area of ​​the section of the second surface provided with the irregular hill-like structure to the total area of ​​the second surface is greater than 0 and less than or equal to 100%.

5. The silicon wafer according to any one of claims 1 to 4, characterized in that: The velvet structure includes a plurality of pyramid units, and at least one pyramid slope surface of each pyramid unit is provided with at least one recess.

6. The silicon wafer according to claim 5, characterized in that: The average value of the depth of the concave portion is greater than or equal to 3 nm and less than or equal to 200 nm, and the average value of the concave portion diameter of the concave portion is greater than or equal to 5 nm and less than or equal to 2000 nm.

7. The silicon wafer according to claim 4, characterized in that: The entire second surface is provided with the irregular hill-like structure, or the section of the second surface provided with the irregular hill-like structure is located in the middle or end of the second surface.

8. The silicon wafer according to claim 7, characterized in that: The second surface forms staggered high-rise areas and low-rise areas. The height difference between the high-rise area and the low-rise area is greater than 0 μm and less than or equal to 10 μm. Only the lower layer area is provided with the irregular hill-like structure; Alternatively, only the high-rise area is provided with the irregular hill-like structure.

9. A solar cell, characterized in that: The solar cell comprises the silicon wafer according to any one of claims 1 to 8.

10. The solar cell according to claim 9, characterized in that: The solar cell is a double-sided contact solar cell, wherein the first side of the silicon wafer is provided with a first doped semiconductor layer, and the second side of the silicon wafer is provided with a second doped semiconductor layer.

11. The solar cell according to claim 10, characterized in that The solar cell is a TOPCON cell.

12. The solar cell according to claim 10, characterized in that: The solar cell is a HJT cell.

13. The solar cell according to claim 10, characterized in that: The first doped semiconductor layer is an N-type doped polysilicon layer, and the second doped semiconductor layer is a P-type doped amorphous silicon layer, a nanocrystalline silicon layer, a microcrystalline silicon layer, a nano silicon oxide layer or a micron silicon oxide layer; or, The first doped semiconductor layer is a P-type doped amorphous silicon layer, a nanocrystalline silicon layer, a microcrystalline silicon layer, a nano silicon oxide layer or a micron silicon oxide layer, and the second doped semiconductor layer is an N-type doped polysilicon layer.

14. The solar cell according to claim 9, characterized in that The solar cell is a back-contact solar cell, wherein the second surface is provided with a first doped semiconductor layer and a second doped semiconductor layer, the second doped semiconductor layer is arranged in a region of the second surface containing the irregular hill-like structure, and the second doped semiconductor layer is a P-type doped amorphous silicon layer or a P-type doped polycrystalline silicon layer.

15. The solar cell according to claim 14, characterized in that: The second surface forms staggered high-level areas and low-level areas, the entire surface of the low-level area is provided with the irregular hill-like structure, the low-level area includes a first section, a second section and a third section, the second section separates the first section and the third section, the high-level area and the first section adjacent to the high-level area are provided with a second doped semiconductor layer, and the third section is provided with a first doped semiconductor layer.

16. The solar cell according to claim 14, characterized in that: The second surface forms staggered high-level areas and low-level areas, the irregular hill-like structure is arranged on the entire surface of the high-level area, the high-level area includes a first section, a second section and a third section, the second section separates the first section and the third section, and the low-level area and the first section and the third section adjacent to the low-level area are provided with a second doped semiconductor layer.

17. The solar cell according to claim 9, characterized in that: The solar cell is a back-contact solar cell, wherein the second surface forms staggered high-layer areas and low-layer areas, the entire surface of the low-layer area is provided with the irregular hill-like structure, the high-layer area includes a first high-layer segment and a second high-layer segment, the low-layer area separates the first high-layer segment and the second high-layer segment, the first high-layer segment is provided with a second doped semiconductor layer, and the second high-layer segment is provided with a first doped semiconductor layer.

18. A method for preparing a silicon wafer according to any one of claims 1 to 8, characterized in that: The method comprises the following steps: S1: performing acid etching on the first surface of the silicon wafer to be textured, and then performing alkali texture processing, so that the first surface forms the texture structure, and the texture structure may include a plurality of pyramid units; as well as S2: Immerse the silicon wafer after step S1 in an alkaline solution containing an organic polymer additive, and fine-tune the velvet structure of the silicon wafer by etching with the alkaline solution containing an organic polymer additive to form at least one recess with a light-trapping function on at least one tower surface of the pyramid unit.

19. The method according to claim 18, characterized in that The method further comprises the steps of: S3: etching the second surface of the silicon wafer using a chemical etching solution, and controlling etching conditions and time so that at least a portion of the second surface of the silicon wafer forms the irregular hill-like structure.

20. The method according to claim 18, characterized in that The method further comprises the steps of: S3': using a chemical etching solution to etch the second surface of the silicon wafer, and controlling the etching conditions and time so that a portion of the second surface of the silicon wafer forms the irregular hill-like structure, wherein the section of the second surface provided with the irregular hill-like structure is located in the middle or end position of the second surface.

21. A method for preparing the solar cell according to any one of claims 9 to 17, characterized in that: The method comprises the method for preparing a silicon wafer according to any one of claims 18 to 20.

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