Display panel and method of manufacturing the same

Abstract

A display panel and a method of manufacturing the same are disclosed. The display panel includes: a base layer; a barrier wall over the base layer and including a first barrier wall and a second barrier wall; a pixel defining layer over the base layer and defining a light emitting opening that overlaps the first barrier wall and is surrounded by the second barrier wall in a plan view; and a light emitting element including an anode over the barrier wall, a light emitting pattern over the anode and the pixel defining layer, and a cathode over the light emitting pattern and in contact with the second barrier wall.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10-2023-0191549, filed with the Korean Intellectual Property Office on December 26, 2023, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to a display panel having improved display quality and a method of manufacturing a display panel. BACKGROUND ART

[0004] Display devices (such as televisions, monitors, smartphones, and tablet computers) that provide images to users include a display panel that displays an image. Various types of display panels (such as liquid crystal display panels, organic light emitting display panels, electro-wetting display panels, and electrophoretic display panels) are being developed.

[0005] An organic light emitting display panel includes an anode, a cathode, and a light emitting pattern. The light emitting pattern is divided into portions to be positioned in light emitting regions, and the cathode provides a common voltage to each light emitting region. SUMMARY OF THE INVENTION

[0006] The present disclosure provides a display panel having improved display quality and including a light emitting element formed without using a metal mask.

[0007] The present disclosure provides a method of manufacturing a display panel.

[0008] Embodiments of the present disclosure provide a display panel including: a substrate layer; barrier ribs, above the substrate layer and including first barrier ribs and second barrier ribs; a pixel defining layer, above the substrate layer and defining a light emitting opening overlapping the first barrier ribs in a plan view and surrounded by the second barrier ribs; and a light emitting element including an anode above the barrier ribs, a light emitting pattern above the anode and the pixel defining layer, and a cathode above the light emitting pattern and in contact with the second barrier ribs.

[0009] The second barrier ribs may surround the first barrier ribs and may be spaced apart from the first barrier ribs in a plan view.

[0010] The first barrier ribs and the second barrier ribs may include a conductive material.

[0011] The first barrier ribs and the second barrier ribs may include: a first barrier rib layer, above the substrate layer; and a second barrier rib layer, above the first barrier rib layer.

[0012] The first barrier rib layer of the second barrier ribs may have an undercut shape with respect to the second barrier rib layer of the second barrier ribs.

[0013] The second barrier layer of the second barrier wall may protrude more toward the light-emitting opening than the first barrier layer of the second barrier wall.

[0014] The cathode may contact the inner surface of the first barrier layer of the second barrier wall.

[0015] The second barrier wall may define a barrier wall opening overlapping the light-emitting opening, and the first barrier wall is located in the barrier wall opening.

[0016] A part of the pixel defining layer that defines the light-emitting opening may be in the barrier wall opening.

[0017] The display panel may further include a lower encapsulation inorganic pattern above the cathode, covering the light-emitting element, and filling the barrier wall opening.

[0018] The display panel may further include a sacrificial pattern between the pixel defining layer and the anode.

[0019] Embodiments of the present disclosure provide a method of manufacturing a display panel, the method including: providing a preliminary display panel including a substrate layer, a preliminary barrier wall above the substrate layer, an anode layer above the preliminary barrier wall, and a sacrificial layer; etching the sacrificial layer to form a preliminary sacrificial pattern; etching the anode layer to form an anode; first etching the preliminary barrier wall to form a first barrier wall and a second preliminary barrier wall; depositing a preliminary pixel defining layer above the substrate layer; etching the preliminary pixel defining layer to form a pixel defining layer that defines a light-emitting opening overlapping the first barrier wall and an opening exposing the inner surface of the second preliminary barrier wall; second etching the preliminary barrier wall to form a second barrier wall defining a barrier wall opening; and forming a light-emitting pattern and a cathode overlapping the barrier wall opening.

[0020] The method may further include etching the preliminary sacrificial pattern to form a sacrificial pattern defining a sacrificial opening overlapping the light-emitting opening.

[0021] The first barrier wall and the second barrier wall may include: a first barrier layer above the substrate layer; and a second barrier layer above the first barrier layer.

[0022] The second barrier layer of the second barrier wall may protrude more toward the light-emitting opening than the first barrier layer of the second barrier wall.

[0023] Forming the light-emitting pattern and the cathode may include: depositing a light-emitting layer on the anode and the pixel defining layer by thermal evaporation; and sputtering a cathode layer on the light-emitting pattern.

[0024] Sputtering the cathode layer may include depositing the cathode layer to contact the inner surface of the first barrier layer of the second barrier wall.

[0025] The second etch stop layer may include etching the second etch stop layer to allow the first etch stop layer to be in the etch stop layer opening.

[0026] The second etch stop layer may surround the first etch stop layer and may be spaced apart from the first etch stop layer in a plan view.

[0027] The method may further include forming a lower encapsulation inorganic pattern on the cathode.

[0028] According to the above, the process of etching the etch stop layer (the process of forming the tip portion), the process of forming the outgassing opening, the process of forming the light-emitting opening, and the process of forming the sacrificial opening using a photoresist layer are integrated. That is, the process of etching the etch stop layer (the process of forming the tip portion), the process of forming the outgassing opening, the process of forming the light-emitting opening, and the process of forming the sacrificial opening are performed using one mask, and thus the number of masks suitable for manufacturing a display panel is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] When considered in conjunction with the accompanying drawings, the above and other aspects of the present disclosure will become more apparent by reference to the following detailed description, in which:

[0030] Figure 1A is a perspective view of a display device according to one or more embodiments of the present disclosure;

[0031] Figure 1B is an exploded perspective view of a display device according to one or more embodiments of the present disclosure;

[0032] Figure 2 is a cross-sectional view of a display module according to one or more embodiments of the present disclosure;

[0033] Figure 3 is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0034] Figure 4 is an enlarged plan view of a part of a display area of a display panel according to one or more embodiments of the present disclosure;

[0035] Figure 5 is along Figure 3 a cross-sectional view taken along line I-I'; and

[0036] Figures 6A through 6N is a cross-sectional view showing the process of a method of manufacturing a display panel according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0037] Aspects of some embodiments of the present disclosure and methods of implementing these embodiments can be more readily understood by reference to the detailed description of the exemplary embodiments and the accompanying drawings. The described embodiments are provided by way of example so that the present disclosure will be thorough and complete, and will fully convey aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are redundant, not relevant to the description of the embodiments, or not necessary for a complete understanding of aspects of the present disclosure by those of ordinary skill in the art may be omitted. Unless otherwise indicated, throughout the drawings and the written description, the same reference numerals, characters, or combinations thereof represent the same elements, and thus, repeated descriptions thereof may be omitted.

[0038] The described embodiments may have various modifications and may be implemented in different forms and should not be construed as limited to the embodiments shown herein. The use of "may", "can", or "may not" in the description of the embodiments corresponds to one or more embodiments of the present disclosure.

[0039] In view of the entirety of the present disclosure, those of ordinary skill in the art will understand that, unless otherwise stated or implied, the present disclosure covers all modifications, equivalents, and substitutions within the spirit and scope of the present disclosure. Each of the multiple features of the embodiments of the present disclosure may be combined, in part or in whole, with each other, and various interlocks and operations are possible technically, and each embodiment may be implemented independently of each other or may be implemented jointly together.

[0040] In the drawings, for clarity and / or for purposes of description, the relative dimensions of elements, layers, and regions may be exaggerated. In other words, since the dimensions and thicknesses of the elements in the drawings are arbitrarily shown for ease of description, the present disclosure is not limited thereto. Additionally, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonality between the elements shown, and / or any other feature, attribute, property, etc.

[0041] Various embodiments are described herein with reference to cross-sectional views, which are schematic views of the embodiments and / or intermediate structures. As such, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Additionally, for the purpose of describing embodiments in accordance with the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Accordingly, the embodiments disclosed herein should not be construed as limited to the shapes of the elements, layers, or regions shown, but should include deviations in shape caused, for example, by manufacturing.

[0042] For example, an implantation region illustrated as rectangular will typically have rounded or curved features at the edges of the implantation region and / or a gradient of implantation concentration, rather than a binary change from the implantation region to a non-implantation region at the edge of the implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface where the implantation occurs.

[0043] For ease of explanation, spatial relative terms, such as "under", "below", "beneath", "lower side", "underneath", "above", "on", "over", "upper", "upper side", and "side" (e.g., as in "sidewall"), may be used herein to describe the relationship of one element or feature (a plurality of other elements or features) shown in the drawings to another element or feature. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are also intended to encompass different orientations of the device during use or operation. For example, if the device is flipped in the drawings, an element described as "under", "beneath", or "underneath" another element or feature will then be positioned "over" the other element or feature. Thus, the example terms "under" and "underneath" can encompass both an upper and a lower orientation. The device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first component is described as being disposed "on" a second component, this indicates that the first component is disposed at the upper side or the lower side of the second component, and is not limited to being disposed at the upper side of the second component based on the direction of gravity.

[0044] In addition, the phrase "in a plan view" refers to viewing a portion of an object from above, while the phrase "when viewed in a cross-section" refers to viewing a schematic cross-section taken by vertically cutting a portion of the object from the side. The term "overlap" or "overlaps with" means that a first object may be above or below or on one side of a second object, and vice versa. In addition, the term "overlap" may include stacking, facing or confronting, extending throughout, covering or partially covering, or any other suitable term as would be recognized and understood by a person of ordinary skill in the art. The expression "does not overlap with" may include meanings such as "separate from", "detached from", or "deviated from", and any other suitable equivalents as would be recognized and understood by a person of ordinary skill in the art. The terms "face" and "face towards" may mean that a first object may be directly or indirectly opposite a second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite each other, although still facing each other.

[0045] It will be understood that when an element, layer, region or component is referred to as being "formed on", "on", "connected to" or "(operatively or communicatively) coupled to" another element, layer, region or component, the element, layer, region or component can be directly formed on, directly on, directly connected to or directly coupled to the other element, layer, region or component, or can be indirectly formed on, indirectly on, indirectly connected to or indirectly coupled to the other element, layer, region or component, such that there can be one or more intervening elements, layers, regions or components. Further, this can be collectively referred to as direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, the layer, region or component can be directly electrically connected or coupled to the other layer, region or component, or there can be one or more intervening layers, regions or components. One or more intervening components can include switches, resistors and / or capacitors, etc. When describing embodiments, unless explicitly described as a direct connection, the expression of connection indicates an electrical connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected or directly coupled to another component or directly on another component without an intervening component.

[0046] In addition, in this specification, when a part of a layer, film, region or plate, etc. is formed on another part, the forming direction is not limited to the upward direction, but includes forming the part on a side surface or in a downward direction. Conversely, when a part of a layer, film, region or plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components (such as "between", "immediately between" or "adjacent to" and "directly adjacent to") can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0047] For the purposes of the present disclosure, recitations such as "at least one of...", "any one of...", or "one or more of..." after a list of elements modify the entire list of elements and not individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z (such as, by way of example, XYZ, XY, YZ, and XZ or any variations thereof). Similarly, the recitation "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the recitation "A and / or B" can include A, B, or A and B. Similarly, recitations such as "at least one of...", "a plurality of", "one of...", and other prepositional phrases after a list of elements modify the entire list of elements and not individual elements in the list. Unless otherwise specified, when stating "C to D", it means C or more and D or less.

[0048] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms do not correspond to a particular order, position, or preference, and these terms are only used to distinguish one element, member, component, region, area, layer, portion, or part from another element, member, component, region, area, layer, portion, or part. Thus, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer, or first portion described below can be named the second element, second component, second region, second layer, or second portion. Designating an element as the "first" element does not require or imply the existence of a second element or other elements. The terms "first", "second", etc. can also be used herein to distinguish different classes or groups of elements. For the sake of brevity, the terms "first", "second", etc. can respectively denote "first class (or first group)", "second class (or second group)", etc.

[0049] In an example, the first direction DR1, the second direction DR2, and / or the third direction DR3 are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. This also applies to the first direction, the second direction, and / or the third direction.

[0050] The terms used herein are for the purpose of describing embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are also intended to include the plural forms, and the plural forms are also intended to include the singular form. It will also be understood that when the terms "comprises", "comprising", "have", "having", "includes" and "including" are used in this specification, it indicates the presence of the stated features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0051] When one or more embodiments can be implemented differently, a specific process order can be performed in an order different from that described. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order.

[0052] As used herein, the terms "substantially", "about", "approximate" and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for the inherent deviations of measured or calculated values that would be recognized by a person of ordinary skill in the art. For example, "substantially" can include a range of +5% / -5% of the corresponding value. When considering the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximate" as used herein includes the stated value and refers to within an acceptable deviation range of a particular value as determined by a person of ordinary skill in the art. For example, "about" can refer to within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in a general dictionary, should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense.

[0054] Figure 1A is a perspective view of a display device DD according to one or more embodiments of the present disclosure, and Figure 1B is an exploded perspective view of a display device DD according to one or more embodiments of the present disclosure.

[0055] The display device DD can be applied to large electronic products, such as televisions, monitors, or outdoor billboards. In addition, the display device DD can be applied to small and medium-sized electronic products, such as personal computers, notebook computers, personal digital assistants, automotive navigation units, gaming units, smart phones, tablet computers, and cameras. However, these are merely examples, and the display device DD can be used in other display devices as long as they do not deviate from the concept of the present disclosure. Figure 1A and Figure 1B shows a smart phone as a representative example of the display device DD.

[0056] Reference Figure 1A and Figure 1B , the display device DD can display an image IM through a display surface FS facing a third direction DR3, and the display surface FS is substantially parallel to each of a first direction DR1 and a second direction DR2. The image IM can include video as well as still images. Figure 1A shows a clock widget and an application icon as examples of the image IM. The display surface FS through which the image IM is displayed can correspond to the front surface of the display device DD.

[0057] The front (or upper) surface and the rear (or lower) surface of each component of the display device DD can be defined with respect to the direction of the displayed image IM. The front surface and the rear surface can face away from each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface can be substantially parallel to the third direction DR3. At the same time, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be relative to each other, and thus, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be changed to other directions. In the following description, the expression "when viewed in a plane" (i.e., in a plan view) refers to the state of viewing in the third direction DR3.

[0058] The display device DD can include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU can be coupled to each other to provide the exterior of the display device DD.

[0059] The window WP can include an optically transparent insulating material. For example, the window WP can include a glass or plastic material. The front surface of the window WP can define the display surface FS of the display device DD. The display surface FS can include a transmissive region TA and a border region BZA. The transmissive region TA can be an optically transparent region. As an example, the transmissive region TA can be a region having a visible light transmittance of about 90% or more.

[0060] The border area BZA may be an area having a transmittance relatively lower than that of the transmissive area TA. The border area BZA may define the shape of the transmissive area TA. The border area BZA may be positioned adjacent to the transmissive area TA and may surround the transmissive area TA. However, this is merely an example, and the border area BZA may be omitted from the window WP. The window WP may include at least one functional layer such as an anti-fingerprint layer, a hard coat, and an anti-reflection layer, and shall not be particularly limited.

[0061] The display module DM may be positioned below the window WP. The display module DM may have a configuration that substantially generates an image IM. The image IM generated by the display module DM may be displayed through the display surface IS of the display module DM and may be viewed by a user through the transmissive area TA.

[0062] The display module DM may include a display area DA and a non-display area NDA, that is, the display surface IS of the display module DM may include the display area DA and the non-display area NDA. The display area DA may be activated in response to an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may (e.g., in a plan view) surround the display area DA. The non-display area NDA may be covered by the border area BZA and may not be viewed from the outside.

[0063] The housing HAU may be coupled to the window WP. The housing HAU and the window WP coupled to each other may provide an internal space (e.g., a predetermined internal space). The display module DM may be accommodated in the internal space.

[0064] The housing HAU may include a material having relatively high rigidity. As an example, the housing HAU may include a plurality of frames and / or plates including a glass, plastic, or metal material or a combination thereof. The housing HAU may stably protect the components of the display device DD accommodated in the internal space from external impacts.

[0065] Figure 2 is a cross-sectional view of a display module DM according to one or more embodiments of the present disclosure.

[0066] Reference Figure 2 , the display module DM may include a display panel DP and an input sensor INS. In one or more embodiments, the display device DD (reference Figure 1A ) may further include a protection member positioned on / under the lower surface of the display panel DP or an anti-reflection member and / or a window member positioned on / above the upper surface of the input sensor INS.

[0067] The display panel DP can be a light-emitting display panel. However, the display panel DP should not be particularly limited. For example, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel can include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel can include quantum dots, quantum rods, or micro LEDs. The organic light-emitting display panel will be described as the display panel DP.

[0068] The display panel DP can include a substrate layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The circuit element layer DP-CL, the display element layer DP-OLED, and the thin film encapsulation layer TFE can be positioned on the substrate layer BL. The input sensor INS can be directly positioned on the thin film encapsulation layer TFE. In the present disclosure, the expression "component A is directly positioned on component B" means that there is no adhesive layer between component B and component A.

[0069] The substrate layer BL can include at least one plastic film. The substrate layer BL can be a flexible substrate and can include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate. Refer to Figure 1B The described display area DA and non-display area NDA can also be defined in the substrate layer BL.

[0070] The circuit element layer DP-CL can include circuit elements and at least one insulating layer. The insulating layer can include at least one inorganic layer and at least one organic layer. The circuit elements can include signal lines and pixel driving circuits.

[0071] The display element layer DP-OLED can include barrier walls and light-emitting elements. The light-emitting elements can include anodes, intermediate layers, and cathodes.

[0072] The thin film encapsulation layer TFE can include multiple thin layers. Some thin layers can be positioned to improve optical efficiency, and some thin layers can be positioned to protect the organic light-emitting diodes.

[0073] The input sensor INS can obtain coordinate information of an external input. The input sensor INS can have a multilayer structure. The input sensor INS can include a conductive layer having a single-layer or multilayer structure. The input sensor INS can include an insulating layer having a single-layer or multilayer structure. The input sensor INS can sense an external input by a capacitive method. However, the present disclosure should not be limited to this or be restricted thereby. As an example, the input sensor INS can sense an external input by an electromagnetic induction method or a pressure sensing method. Meanwhile, according to one or more embodiments, the input sensor INS can be omitted.

[0074] Figure 3 is a plan view of a display panel DP according to one or more embodiments of the present disclosure.

[0075] Reference Figure 3 ,The display panel DP may include a display area DA and a non-display area NDA around the display area DA. The display panel DP may include pixels PX and signal lines SGL electrically connected to the pixels PX. The display panel DP may further include a driving circuit GDC and a pad portion PLD. The display area DA and the non-display area NDA may be distinguished from each other by the presence or absence of the pixels PX. The pixels PX may be located in the display area DA. The driving circuit GDC and the pad portion PLD may be located in the non-display area NDA.

[0076] The pixels PX may be arranged in a first direction DR1 and a second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2, and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0077] The signal lines SGL may include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the gate lines GL may be connected to a corresponding one of the pixels PX, and each of the data lines DL may be connected to a corresponding one of the pixels PX. The power lines PL may be electrically connected to the pixels PX. The control signal lines CSL may be connected to the driving circuit GDC and may provide control signals to the driving circuit GDC.

[0078] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a plurality of gate signals and may sequentially output the gate signals to the gate lines GL. The gate driving circuit may also output other control signals to the pixel driving circuit.

[0079] The pad portion PLD may be connected to a flexible circuit board. The pad portion PLD may include pixel pads D-PD, and the pixel pads D-PD may be pads for connecting the flexible circuit board to the display panel DP. Each of the pixel pads D-PD may be connected to a corresponding one of the signal lines SGL. The pixel pads D-PD may be connected to the corresponding pixels PX via the signal lines SGL. In addition, the driving circuit GDC may be connected to one of the pixel pads D-PD.

[0080] In addition, the pad portion PLD may further include input pads. The input pads may be pads for connecting the flexible circuit board to the input sensor INS (Reference Figure 2 ). However, the present disclosure should not be limited to this or be restricted thereby. According to one or more embodiments, the input pads may be located on the input sensor INS (Reference Figure 2) and can be connected to a circuit board different from the circuit board to which the pixel pad D-PD is connected. According to one or more embodiments, the input sensor INS (reference Figure 2 ) can be omitted, and the pad portion PLD may not further include an input pad.

[0081] Figure 4 is an enlarged plan view of a part of the display area DA (reference Figure 2 ) of the display panel DP (reference Figure 2 ) according to one or more embodiments of the present disclosure. Figure 4 shows a plan view of the display module DM (reference Figure 1B ) when viewed from the upper side of the display surface IS (reference Figure 1B ) of the display module DM, and shows the arrangement of the light-emitting regions PXA-R, PXA-G, and PXA-B and the barrier walls PW.

[0082] Refer to Figure 4 , the display area DA may include a first light-emitting region PXA-R, a second light-emitting region PXA-G, and a third light-emitting region PXA-B, and a peripheral region NPXA surrounding the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B. The first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may respectively correspond to regions from which light provided by the light-emitting elements is emitted. The first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be distinguished from each other by the color of the light emitted outward from the display module DM (reference Figure 2 ).

[0083] The first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may respectively provide first-color light, second-color light, and third-color light having different colors from each other. As an example, the first-color light may be red light, the second-color light may be green light, and the third-color light may be blue light. However, the first-color light, the second-color light, and the third-color light should not be limited to this or be restricted thereby.

[0084] Each of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be defined as a region where the upper surface of the anode is exposed through a light-emitting opening described later. The peripheral region NPXA may define the boundaries between the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B, and may reduce or prevent the mixing of the colors of light between the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B.

[0085] Each of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be provided in plural and may be repeatedly arranged in a display region DA in an arrangement (e.g., a predetermined arrangement). As an example, the first light-emitting region PXA-R and the third light-emitting region PXA-B may be alternately arranged with each other in a first direction DR1 to form a first group. The second light-emitting region PXA-G may be arranged in the first direction DR1 to form a second group. Each of the first group and the second group may be provided in plural, and the first group may be alternately arranged with the second group in a second direction DR2.

[0086] One second light-emitting region PXA-G may be positioned to be spaced apart from one first light-emitting region PXA-R or one third light-emitting region PXA-B in a fourth direction DR4. The fourth direction DR4 may correspond to a direction between the first direction DR1 and the second direction DR2.

[0087] Meanwhile, Figure 4 An example of the arrangement of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B is shown. However, the arrangement of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be changed in various ways and should not be particularly limited. The first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be arranged in a pattern as shown in Figure 4 (e.g., type pattern, is a registered trademark of Samsung Display Co., Ltd. of the Republic of Korea). According to one or more embodiments, the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be arranged in a stripe pattern or a diamond pattern (e.g., Diamond type pattern, Diamond is a registered trademark of Samsung Display Co., Ltd. of the Republic of Korea).

[0088] When viewed in a plane, each of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have various shapes. As an example, each of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have a polygonal shape, a circular shape, or an oval shape. In Figure 4 , examples of the first light-emitting region PXA-R and the third light-emitting region PXA-B both having a quadrilateral shape or a rhombus shape and the second light-emitting region PXA-G having an octagonal shape are shown.

[0089] When viewed in a plane, the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have substantially the same shape as each other, or at least one of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have a shape different from the shapes of the other light-emitting regions among the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B. Figure 4 A structure is shown as an example in which the first light-emitting region PXA-R and the third light-emitting region PXA-B have the same shape as each other when viewed in a plane and in which the second light-emitting region PXA-G has a shape different from the shapes of the first light-emitting region PXA-R and the third light-emitting region PXA-B.

[0090] When viewed in a plane, at least one of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have a size different from the sizes of the other light-emitting regions among the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B. The size of the first light-emitting region PXA-R that emits red light may be larger than the size of the second light-emitting region PXA-G that emits green light and may be smaller than the size of the third light-emitting region PXA-B that emits blue light. However, the size relationship among the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B according to the color of the emitted light should not be limited to this or be restricted thereby, but may be changed in various ways according to the design of the display module DM (refer to Figure 2 ). In addition, according to one or more embodiments, when viewed in a plane, the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have substantially the same size as each other.

[0091] Meanwhile, the shapes, sizes, and arrangements of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B of the display module DM (refer to Figure 2 ) may be designed in various ways according to the color of the emitted light, the size of the display module DM (refer to Figure 2 ), and the structure of the display module DM (refer to Figure 2 ), and they should not be limited to one or more embodiments corresponding to Figure 4 .

[0092] The barrier wall PW may include a first barrier wall PW-S and a second barrier wall PW-E. The first barrier wall PW-S may overlap with a first light-emitting region PXA-R, a second light-emitting region PXA-G, and a third light-emitting region PXA-B, and the second barrier wall PW-E may surround the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B. An inner surface of the second barrier wall PW-E may define a barrier wall opening OP-P. The first barrier wall PW-S may be positioned in the barrier wall opening OP-P. That is, the second barrier wall PW-E may surround the first barrier wall PW-S, and the first barrier wall PW-S may be spaced apart from the second barrier wall PW-E when viewed in a plane.

[0093] Figure 5 is a cross-sectional view taken along Figure 3 line I-I' of Figure 5 . In Figure 2 , like reference numerals denote the same elements as Figure 5 the elements in Figure 4 , and thus, detailed descriptions of the same elements will be omitted. Figure 5 is an enlarged view showing a light-emitting region PXA of a display area DA (refer to Figure 4 ), and the light-emitting region PXA of

[0094] may correspond to one of a first light-emitting region PXA-R, a second light-emitting region PXA-G, and a third light-emitting region PXA-B of Figure 5 . Referring to

[0095] , the display panel DP may include a substrate layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE.

[0096] The circuit element layer DP-CL may be positioned on the substrate layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, and a fifth insulating layer 50, an electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0097] The buffer layer BFL can be positioned on the substrate layer BL. The buffer layer BFL can increase the adhesion between the substrate layer BL and the semiconductor pattern. The buffer layer BFL can include a silicon oxide layer and a silicon nitride layer, and the silicon oxide layer and the silicon nitride layer can be alternately stacked with each other.

[0098] The semiconductor pattern can be positioned on the buffer layer BFL. The semiconductor pattern can include polysilicon, but it should not be limited thereto or restricted thereby. The semiconductor pattern can include amorphous silicon or metal oxide. Figure 5 A part of the semiconductor pattern is shown, and the semiconductor pattern can be further positioned in the light-emitting regions PXA-R, PXA-G, and PXA-B (refer to Figure 4 ). The semiconductor pattern can be arranged in a specific rule throughout the light-emitting regions PXA-R, PXA-G, and PXA-B. The semiconductor pattern can have different electrical properties depending on whether it is doped or not. The semiconductor pattern can include a first region with a relatively high doping concentration and a second region with a relatively low doping concentration. The first region can be doped with an N-type dopant or a P-type dopant. The P-type transistor can include a first region doped with a P-type dopant.

[0099] The first region can have a conductivity greater than that of the second region and can basically serve as an electrode or a signal line. The second region can basically correspond to the active region (or channel region) of the transistor. In other words, a part of the semiconductor pattern can be the active region of the transistor, another part of the semiconductor pattern can be the source or drain of the transistor, and yet another part or the remaining part of the semiconductor pattern can be a conductive region.

[0100] The source S, active region A, and drain D of the transistor TR1 can be formed by the semiconductor pattern. Figure 5 A part of the signal transmission region SCL formed by the semiconductor pattern is shown. In one or more embodiments, the signal transmission region SCL can be connected to the drain D of the transistor TR1 in the plane.

[0101] The first insulating layer 10, second insulating layer 20, third insulating layer 30, fourth insulating layer 40, and fifth insulating layer 50 can be positioned on the buffer layer BFL. Each of the first insulating layer 10, second insulating layer 20, third insulating layer 30, fourth insulating layer 40, and fifth insulating layer 50 can be an inorganic layer or an organic layer.

[0102] The first insulating layer 10 may be positioned on the buffer layer BFL. The first insulating layer 10 may cover the source S, the active region A, and the drain D of the transistor TR1, as well as the signal transmission region SCL. The gate G of the transistor TR1 may be positioned on the first insulating layer 10. The second insulating layer 20 may be positioned on the first insulating layer 10 and may cover the gate G. The electrode EE may be positioned on the second insulating layer 20. The third insulating layer 30 may be positioned on the second insulating layer 20 and may cover the electrode EE.

[0103] The first connection electrode CNE1 may be positioned on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL via a contact hole CNT-1 defined through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. The fourth insulating layer 40 may be positioned on the third insulating layer 30 and may cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0104] The second connection electrode CNE2 may be positioned on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 via a contact hole CNT-2 defined through the fourth insulating layer 40. The fifth insulating layer 50 may be positioned on the fourth insulating layer 40 and may cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0105] The display element layer DP-OLED may be positioned on the circuit element layer DP-CL. The display element layer DP-OLED may include a barrier wall PW, a sacrificial pattern SP, a pixel defining layer PDL, and a light-emitting element ED.

[0106] The barrier wall PW may be positioned on the circuit element layer DP-CL. The barrier wall PW may include a first barrier wall PW-S and a second barrier wall PW-E. The first barrier wall PW-S may overlap with the light-emitting opening OP-E when viewed in a plane, and the second barrier wall PW-E may surround the light-emitting opening OP-E when viewed in a plane. That is, the second barrier wall PW-E may surround the first barrier wall PW-S, and the first barrier wall PW-S may be spaced apart from the second barrier wall PW-E when viewed in a plane. The barrier wall PW may be provided with a barrier wall opening OP-P defined therethrough. Specifically, the barrier wall opening OP-P may be defined by the inner surface of the second barrier wall PW-E. The barrier wall opening OP-P may correspond to the light-emitting opening OP-E or may overlap with the light-emitting opening OP-E.

[0107] The barrier wall PW may include a plurality of sequentially stacked layers. The first barrier wall PW-S may include a first barrier wall layer L1-S and a second barrier wall layer L2-S, and the second barrier wall PW-E may include a first barrier wall layer L1-E and a second barrier wall layer L2-E. The first barrier wall layers L1-S and L1-E may be positioned above the substrate layer BL. Specifically, the first barrier wall layers L1-S and L1-E may be positioned on the fifth insulating layer 50 of the circuit element layer DP-CL. The second barrier wall layers L2-S and L2-E may be respectively positioned on the first barrier wall layers L1-S and L1-E. As Figure 5 shown, the first barrier wall layers L1-S and L1-E may have a thickness greater than that of the second barrier wall layers L2-S and L2-E. However, the present disclosure should not be limited to this or restricted thereby.

[0108] Each of the first barrier wall PW-S and the second barrier wall PW-E may include a conductive material. That is, each of the first barrier wall layers L1-S and L1-E and the second barrier wall layers L2-S and L2-E may include a conductive material. As an example, the conductive material may include a metal, a transparent conductive oxide (TCO), or a combination thereof. As an example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0109] When viewed in cross-section, the inner surfaces S1-1 and S2-1 of the first barrier wall PW-S may be aligned with each other. The inner surface S1-1 of the first barrier wall layer L1-S of the first barrier wall PW-S may be aligned with the inner surface S2-1 of the second barrier wall layer L2-S of the first barrier wall PW-S.

[0110] When viewed in cross-section, the second barrier wall PW-E may have an undercut shape. At least one layer of the plurality of layers of the second barrier wall PW-E may be recessed much more than the other layers of the plurality of layers of the second barrier wall PW-E, and thus, the second barrier wall PW-E may have a tip portion. As an example, the first barrier wall layer L1-E of the second barrier wall PW-E may have an undercut shape with respect to the second barrier wall layer L2-E of the second barrier wall PW-E. The second barrier wall layer L2-E of the second barrier wall PW-E that protrudes much more toward the light-emitting opening OP-E than the first barrier wall layer L1-E of the second barrier wall PW-E may form a tip portion. The portion of the second barrier wall layer L2-E that protrudes toward the light-emitting region PXA may be defined as the tip portion in the barrier wall PW. That is, the inner surface S2-2 of the second barrier wall layer L2-E of the second barrier wall PW-E may be closer to the center of the anode AE than the inner surface S1-2 of the first barrier wall layer L1-E of the second barrier wall PW-E.

[0111] The light-emitting element ED may include an anode AE (or a first electrode), a light-emitting pattern EP, and a cathode CE (or a second electrode). The light-emitting element ED may be positioned in the barrier wall opening OP-P.

[0112] The anode AE may be positioned on the first barrier wall PW-S. The anode AE may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE may have a single-layer or multi-layer structure. The anode AE may include a layer containing indium tin oxide (ITO) and a layer containing silver (Ag). As an example, the anode AE may include a layer containing indium tin oxide (ITO) (hereinafter, referred to as the lower ITO layer), a layer positioned on the lower ITO layer and containing silver (Ag) (hereinafter, referred to as the Ag layer), and a layer positioned on the Ag layer and containing indium tin oxide (ITO) (hereinafter, referred to as the upper ITO layer).

[0113] The first barrier wall PW-S may be connected to the second connection electrode CNE2 via a barrier wall contact hole CNT-P defined by the fifth insulating layer 50. Accordingly, the anode AE formed on the first barrier wall PW-S may be electrically connected to the signal transmission region SCL through the first connection electrode CNE1, the second connection electrode CNE2, and the first barrier wall PW-S, and may be electrically connected to a corresponding circuit element.

[0114] The sacrificial pattern SP may be positioned on the anode AE. When viewed in cross-section, the sacrificial pattern SP may be positioned between the anode AE and the pixel defining layer PDL. A sacrificial opening OP-S may be defined by the sacrificial pattern SP, and a part of the upper surface of the anode AE may be exposed through the sacrificial opening OP-S. The sacrificial opening OP-S may overlap with the light-emitting opening OP-E described later.

[0115] The sacrificial pattern SP may include a transparent conductive oxide. As an example, the sacrificial pattern SP may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), aluminum zinc oxide, or zinc indium tin oxide (ZITO). The sacrificial pattern SP may include indium gallium zinc oxide (IGZO).

[0116] The pixel defining layer PDL may be positioned above the substrate layer BL. As an example, the pixel defining layer PDL may be positioned on the barrier wall PW and the circuit element layer DP-CL. A part of the pixel defining layer PDL may be positioned on the first barrier wall PW-S and the circuit element layer DP-CL, and another part of the pixel defining layer PDL may be positioned on the second barrier wall PW-E.

[0117] The pixel defining layer PDL may be provided with a light emitting opening OP-E. As an example, the part of the pixel defining layer PDL positioned on the first barrier wall PW-S may define the light emitting opening OP-E. The part of the pixel defining layer PDL that defines the light emitting opening OP-E may be positioned in the barrier wall opening OP-P. The light emitting opening OP-E may correspond to the anode AE, and at least a part of the anode AE may be exposed through the light emitting opening OP-E of the pixel defining layer PDL.

[0118] In addition, the light emitting opening OP-E may correspond to the sacrificial opening OP-S of the sacrificial pattern SP. When viewed in cross-section, the upper surface of the anode AE may be spaced apart from the pixel defining layer PDL and the sacrificial pattern SP may be interposed between the upper surface of the anode AE and the pixel defining layer PDL, and thus, during the process of forming the light emitting opening OP-E, damage to the anode AE may be reduced or prevented.

[0119] When viewed in plan, the inner surface of the sacrificial pattern SP provided with the sacrificial opening OP-S may be substantially aligned with the inner surface of the pixel defining layer PDL provided with the light emitting opening OP-E. In this case, the light emitting region PXA may be the region of the anode AE exposed through the corresponding sacrificial opening OP-S, but it should not be limited thereto or thereby. The size of the light emitting opening OP-E may be smaller than the size of the sacrificial opening OP-S. That is, the inner surface of the pixel defining layer PDL provided with the light emitting opening OP-E may be closer to the center of the anode AE than the inner surface of the sacrificial pattern SP provided with the sacrificial opening OP-S.

[0120] The pixel defining layer PDL may include an inorganic insulating material. As an example, the pixel defining layer PDL may include silicon nitride (SiN x)。The pixel defining layer PDL can be positioned between the anode AE and the second barrier wall PW-E, and can reduce or prevent the possibility of the anode AE being electrically connected to the second barrier wall PW-E. In addition, the pixel defining layer PDL can protect the anode AE and the sacrificial pattern SP during the process of forming the light emitting opening OP-E and the sacrificial opening OP-S. This will be described in detail later.

[0121] The light emitting pattern EP can be positioned on the anode AE. Specifically, the light emitting pattern EP can be positioned on the anode AE and the pixel defining layer PDL. The light emitting pattern EP can include a light emitting layer containing a light emitting material. The light emitting pattern EP can also include a hole injection layer and a hole transport layer positioned between the anode AE and the light emitting layer, and an electron transport layer and an electron injection layer positioned on the light emitting layer. The light emitting pattern EP can be referred to as an organic layer or an intermediate layer.

[0122] The light emitting pattern EP can be patterned through the tip portion defined by the second barrier wall PW-E. The light emitting pattern EP can be positioned in the sacrificial opening OP-S, the light emitting opening OP-E, and the barrier wall opening OP-P. The light emitting pattern EP can cover a part of the pixel defining layer PDL, a part of the upper surface of the fifth insulating layer 50 exposed through the barrier wall opening OP-P, and the anode AE.

[0123] The cathode CE can be positioned on the light emitting pattern EP and can cover the light emitting pattern EP. The cathode CE can be patterned through the tip portion defined by the second barrier wall PW-E. At least a part of the cathode CE can be positioned in the barrier wall opening OP-P and can contact the second barrier wall PW-E in the barrier wall opening OP-P. As an example, the cathode CE can contact the inner surface S1-2 of the first barrier wall layer L1-E of the second barrier wall PW-E.

[0124] The cathode CE can have conductivity. The cathode CE can be formed of various materials having conductivity (such as metals, transparent conductive oxides (TCOs), or conductive polymer materials). As an example, the cathode CE can include silver (Ag), magnesium (Mg), lead (Pb), copper (Cu), or their compounds. The second barrier wall PW-E can receive a driving voltage, and thus the cathode CE can be electrically connected to the second barrier wall PW-E and can receive the driving voltage.

[0125] According to the present disclosure, the light emitting pattern EP can be patterned in pixel units through the tip portion defined in the barrier wall PW and can be deposited. That is, the light emitting pattern EP can be formed using an opening mask together, but can be suitably separated in pixel units through the barrier wall PW.

[0126] On the other hand, in the case where a fine metal mask (FMM) is used to pattern the light-emitting pattern EP, the support spacers protruding from the barrier wall PW are suitable for supporting the fine metal mask. In addition, since the fine metal mask is spaced apart from the substrate surface on which the patterning process is performed by the height of the barrier wall or the spacer, there may be limitations in achieving high resolution. Further, since the fine metal mask contacts the spacer, foreign substances may remain on the spacer or the spacer may be damaged by the fine metal mask after the patterning process of the light-emitting pattern EP. As a result, a defective display panel may be formed.

[0127] Since the display panel DP includes the barrier wall PW, the light-emitting elements ED can be suitably physically separated from each other. Accordingly, leakage current or driving error between the adjacent light-emitting regions PXA-R, PXA-G, and PXA-B (refer to Figure 4 ) can be reduced or prevented, and the light-emitting elements ED can be driven independently of each other.

[0128] For example, since the light-emitting pattern EP is patterned without contacting a mask of components provided inside the display area DA (refer to Figure 1B ), the defect rate of the display panel DP can be reduced, and thus a display device DD having improved process reliability can be provided. Even if the support spacers protruding from the barrier wall PW are not provided, the light-emitting pattern EP can be patterned. Accordingly, the light-emitting regions PXA-R, PXA-G, and PXA-B can be finely formed in terms of their size, and thus, a display panel DP suitable for high-resolution implementation can be provided.

[0129] In addition, since a large-sized mask is not required when manufacturing a large-sized display panel, the process cost can be reduced, and since the display panel is not affected by defects caused by the large-sized mask, the process reliability of the display panel can be improved.

[0130] The thin film encapsulation layer TFE may be positioned on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower encapsulation inorganic pattern LIL, an encapsulation organic layer OL, and an upper encapsulation inorganic layer UIL.

[0131] The lower encapsulation inorganic pattern LIL may be positioned to correspond to the light-emitting opening OP-E. A part of the lower encapsulation inorganic pattern LIL may be positioned in the barrier wall opening OP-P, and another part of the lower encapsulation inorganic pattern LIL may be positioned above the barrier wall PW. The part of the lower encapsulation inorganic pattern LIL positioned in the barrier wall opening OP-P may be positioned on the cathode CE to cover the light-emitting element ED and may be filled in the barrier wall opening OP-P.

[0132] The encapsulation organic layer OL can cover the lower encapsulation inorganic pattern LIL and can provide a substantially flat upper surface thereon. The upper encapsulation inorganic layer UIL can be positioned on the encapsulation organic layer OL.

[0133] The lower encapsulation inorganic pattern LIL and the upper encapsulation inorganic layer UIL can protect the display element layer DP-OLED from moisture and oxygen, and the encapsulation organic layer OL can protect the display element layer DP-OLED from foreign substances such as dust particles.

[0134] Figures 6A through 6N is a cross-sectional view of a process showing a method of manufacturing a display panel according to one or more embodiments of the present disclosure. In Figures 6A through 6N the same / similar reference numerals denote the same / similar elements as those described in reference figures 1 to Figure 5 and thus, detailed descriptions of the same / similar elements will be omitted.

[0135] The method of manufacturing a display panel may include: providing a preliminary display panel including a substrate layer, a preliminary barrier wall positioned on the substrate layer, an anode layer and a sacrificial layer positioned on the preliminary barrier wall; etching the sacrificial layer to form a preliminary sacrificial pattern; etching the anode layer to form an anode; first etching the preliminary barrier wall to form a first barrier wall and a second preliminary barrier wall; depositing a preliminary pixel defining layer on the substrate layer; etching the preliminary pixel defining layer to form a pixel defining layer that defines a light-emitting opening overlapping the first barrier wall and an opening exposing an inner surface of the second preliminary barrier wall; second etching the preliminary barrier wall to form a second barrier wall defining a barrier wall opening; and forming a light-emitting pattern and a cathode to overlap the barrier wall opening when viewed in a plane.

[0136] Hereinafter, a method of forming one light-emitting element ED and the lower encapsulation inorganic pattern LIL, the encapsulation organic layer OL, and the upper encapsulation inorganic layer UIL covering the one light-emitting element ED will be described with reference to Figures 6A through 6N The display panel manufactured by the process shown in Figures 6A through 6N may correspond to the display panel DP of Figure 5 .

[0137] Referring to Figure 6A , the method of manufacturing a display panel may include providing a preliminary display panel DP-I. The preliminary display panel DP-I may include a substrate layer BL, a circuit element layer DP-CL, a preliminary barrier wall PW-I, an anode layer AE-I, and a sacrificial layer SPL.

[0138] The circuit element layer DP-CL can be formed by a conventional manufacturing process of circuit elements, and the conventional manufacturing process includes the following steps: forming an insulating layer, a semiconductor layer, and a conductive layer by a coating or deposition process; and using a photolithography process and an etching process to selectively pattern the insulating layer, the semiconductor layer, and the conductive layer to form a semiconductor pattern, a conductive pattern, and a signal line.

[0139] The preliminary barrier wall PW-I can include a first preliminary barrier wall layer L1-I and a second preliminary barrier wall layer L2-I. The first preliminary barrier wall layer L1-I can be deposited on the circuit element layer DP-CL, and the second preliminary barrier wall layer L2-I can be formed on the first preliminary barrier wall layer L1-I. The first preliminary barrier wall layer L1-I and the second preliminary barrier wall layer L2-I can be formed of a conductive material by a deposition process. As an example, the first preliminary barrier wall layer L1-I and the second preliminary barrier wall layer L2-I can include a metal, a transparent conductive oxide (TCO), or a combination thereof.

[0140] An anode layer AE-I can be formed on the second preliminary barrier wall layer L2-I. The anode layer AE-I can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode layer AE-I can include a layer containing indium tin oxide (ITO) (hereinafter, referred to as the lower ITO layer), a layer containing silver (Ag) positioned on the lower ITO layer (hereinafter, referred to as the Ag layer), and a layer containing indium tin oxide (ITO) positioned on the Ag layer (hereinafter, referred to as the upper ITO layer).

[0141] A sacrificial layer SPL can be formed on the anode layer AE-I. The sacrificial layer SPL can include a transparent conductive oxide. As an example, the sacrificial layer SPL can include indium gallium zinc oxide (IGZO).

[0142] The preliminary barrier wall PW-I, the anode layer AE-I, and the sacrificial layer SPL formed on the circuit element layer DP-CL can be formed by a continuous deposition process.

[0143] Then, the manufacturing method of the display panel can include forming a first photoresist layer PR1 on the sacrificial layer SPL. The first photoresist layer PR1 can be formed by forming a preliminary photoresist layer on the sacrificial layer SPL and patterning the preliminary photoresist layer using a photomask. First, a first light opening OP-PR1, a second light opening OP-PR2, and a third light opening OP-PR3 passing through the first photoresist layer PR1 can be formed by a patterning process. The first light opening OP-PR1 and the second light opening OP-PR2 can overlap with the barrier wall opening OP-P (refer to Figure 6H ) and the third light opening OP-PR3 can not overlap with the barrier wall opening OP-P.

[0144] Refer toFigure 6B , the method of manufacturing a display panel may include etching a sacrificial layer SPL (refer to Figure 6A ) to form a preliminary sacrificial pattern SP-I.

[0145] Forming the preliminary sacrificial pattern SP-I may be performed by a wet etching process using a first photoresist layer PR1 as a mask. The portion of the sacrificial layer SPL that does not overlap with the first photoresist layer PR1 may be etched and removed, and the remaining unetched portion of the sacrificial layer SPL may be used as the preliminary sacrificial pattern SP-I.

[0146] Refer to Figure 6C , the method of manufacturing a display panel may include etching an anode layer AE-I (refer to Figure 6B ) to form an anode AE.

[0147] Forming the anode AE may be performed by a wet etching process using a first photoresist layer PR1 as a mask. The portion of the anode layer AE-I that does not overlap with the first photoresist layer PR1 may be etched and removed, and the remaining unetched portion of the anode layer AE-I may be used as the anode AE.

[0148] Refer to Figure 6D , the method of manufacturing a display panel may include first etching a preliminary barrier wall PW-I (refer to Figure 6C ) to form a first barrier wall PW-S and a second preliminary barrier wall PW-EI.

[0149] Forming the first barrier wall PW-S and the second preliminary barrier wall PW-EI may be performed by a dry etching process using a first photoresist layer PR1 as a mask. The portion of the preliminary barrier wall PW-I that does not overlap with the first photoresist layer PR1 may be etched and removed, and the remaining unetched portion of the preliminary barrier wall PW-I may be used as the first barrier wall PW-S or the second preliminary barrier wall PW-EI.

[0150] As an example, a preliminary barrier opening OP-PI can be formed in a region where a portion of the preliminary barrier wall PW-I overlapping with the first light opening OP-PR1 and the second light opening OP-PR2 is removed, and a degassing opening OP-G can be formed in a region where a portion of the preliminary barrier wall PW-I overlapping with the third light opening OP-PR3 is removed. Inner surfaces of the first preliminary barrier layer L1-I and the second preliminary barrier layer L2-I of the second preliminary barrier wall PW-EI that define the preliminary barrier opening OP-PI can be aligned with each other. The degassing opening OP-G can be an opening through which gas generated from an insulating layer of the circuit element layer DP-CL is discharged. Further, among portions of the preliminary barrier wall PW-I that are not etched and remain, a portion that defines the preliminary barrier opening OP-PI can be used as the second preliminary barrier wall PW-EI, and a first barrier wall PW-S can be formed in the preliminary barrier opening OP-PI.

[0151] Reference Figure 6E , a method of manufacturing a display panel can include removing a first photoresist layer PR1 (Reference Figure 6D ) and depositing a preliminary pixel defining layer PDL-I on a substrate layer BL.

[0152] The preliminary pixel defining layer PDL-I can be deposited on the circuit element layer DP-CL and the preliminary sacrificial pattern SP-I. The preliminary pixel defining layer PDL-I can be deposited in the preliminary barrier opening OP-PI and the degassing opening OP-G. The preliminary pixel defining layer PDL-I can include an inorganic insulating material. As an example, the preliminary pixel defining layer PDL-I can include silicon nitride (SiN x ).

[0153] Reference Figure 6F , a method of manufacturing a display panel can include forming a second photoresist layer PR2 on the preliminary pixel defining layer PDL-I. The second photoresist layer PR2 can be formed by forming a preliminary photoresist layer on the preliminary pixel defining layer PDL-I and patterning the preliminary photoresist layer using a photomask. Fourth, fifth, and sixth light openings OP-PR4, OP-PR5, and OP-PR6 passing through the second photoresist layer PR2 can be formed by a patterning process.

[0154] Reference Figure 6G , a method of manufacturing a display panel can include etching the preliminary pixel defining layer PDL-I to form a pixel defining layer PDL that defines a light emitting opening OP-E overlapping with the first barrier wall PW-S and an opening OP that exposes an inner surface of the second preliminary barrier wall PW-EI (Reference Figure 6H ).

[0155] The formation of the pixel defining layer PDL can be performed by dry etching using the second photoresist layer PR2 as a mask. Portions of the preliminary pixel defining layer PDL-I that do not overlap with the second photoresist layer PR2 can be etched and removed, and the remaining unetched portions of the preliminary pixel defining layer PDL-I can be used as the pixel defining layer PDL.

[0156] As an example, a light emitting opening OP-E passing through the removed portion of the preliminary pixel defining layer PDL-I can be formed in a region overlapping with the fourth light opening OP-PR4. The light emitting opening OP-E can be formed above the first barrier wall PW-S and can overlap with the first barrier wall PW-S. An opening OP passing through the removed portion of the preliminary pixel defining layer PDL-I can be formed in a region overlapping with the fifth light opening OP-PR5 and the sixth light opening OP-PR6. The inner surface of the second preliminary barrier wall PW-EI can be exposed through the opening OP.

[0157] Reference Figure 6H , the method of manufacturing a display panel can include removing the second photoresist layer PR2 (reference Figure 6G ) and secondarily etching the first preliminary barrier wall PW-I (reference Figure 6G ) to form a second barrier wall PW-E defining a barrier wall opening OP-P.

[0158] The formation of the second barrier wall PW-E can be performed by wet etching the first preliminary barrier wall layer L1-I (reference Figure 6G ) and the second preliminary barrier wall layer L2-I (reference Figure 6G ). The formation of the second barrier wall PW-E can include etching the second preliminary barrier wall PW-EI (reference Figure 6G ) to allow the first barrier wall PW-S to be positioned in the barrier wall opening OP-P. During the above process, the side surface of the first barrier wall PW-S covered by the pixel defining layer PDL may not be etched, and the side surface of the second preliminary barrier wall PW-EI exposed through the opening OP of the pixel defining layer PDL may be etched.

[0159] The second barrier wall PW-E can surround the first barrier wall PW-S, and the first barrier wall PW-S can be spaced apart from the second barrier wall PW-E when viewed in a plane. The first barrier wall PW-S can include a first barrier wall layer L1-S and a second barrier wall layer L2-S, and the second barrier wall PW-E formed by an etching process can include a first barrier wall layer L1-E and a second barrier wall layer L2-E.

[0160] The wet etching process can be performed in an environment with a high etching selectivity between the first preliminary barrier wall layer L1-I and the second preliminary barrier wall layer L2-I. Therefore, the second barrier wall layer L2-E of the second barrier wall PW-E can have a shape that protrudes much more toward the light-emitting opening OP-E than the first barrier wall layer L1-E of the second barrier wall PW-E. Specifically, since the etching rate of the first preliminary barrier wall layer L1-I is greater than that of the second preliminary barrier wall layer L2-I, the first preliminary barrier wall layer L1-I can be mainly etched or can be etched to a greater extent. Therefore, the side surface of the first barrier wall layer L1-E of the second barrier wall PW-E can be recessed much more inward than the side surface of the second barrier wall layer L2-E of the second barrier wall PW-E. A tip portion can be formed in the barrier wall PW by a portion of the second barrier wall layer L2-E of the second barrier wall PW-E that protrudes much more than the first barrier wall layer L1-E of the second barrier wall PW-E.

[0161] Reference Figure 6I , the method of manufacturing a display panel can include etching a preliminary sacrificial pattern SP-I (reference Figure 6H ) to form a sacrificial pattern SP having a sacrificial opening OP-S overlapping with the light-emitting opening OP-E.

[0162] The sacrificial pattern SP can be formed by wet-etching the preliminary sacrificial pattern SP-I using the pixel defining layer PDL as a mask. The portion of the preliminary sacrificial pattern SP-I that does not overlap with the pixel defining layer PDL can be etched and removed, and the remaining unetched portion of the preliminary sacrificial pattern SP-I can be used as the sacrificial pattern SP.

[0163] According to the present disclosure, reference Figures 6C through 6I , the process of etching the barrier wall PW (the process of forming the tip portion), the process of forming the outgassing opening OP-G, the process of forming the light-emitting opening OP-E, and the process of forming the sacrificial opening OP-S using the first photoresist layer PR1 and the second photoresist layer PR2 can be integrated. That is, the process of etching the barrier wall PW (the process of forming the tip portion), the process of forming the outgassing opening OP-G, the process of forming the light-emitting opening OP-E, and the process of forming the sacrificial opening OP-S can be performed using one mask, and the number of masks suitable for manufacturing the display panel DP can be reduced.

[0164] Reference Figure 6J and Figure 6K , the method of manufacturing a display panel can include forming a light-emitting pattern EP and a cathode CE that overlap with the barrier wall opening OP-P when viewed in a plane. Figure 6J shows the formation of the light-emitting pattern EP, and Figure 6K shows the formation of the cathode CE.

[0165] Reference Figure 6J The process of forming the light-emitting pattern EP may include a deposition process of the light-emitting layer. As an example, forming the light-emitting pattern EP may include depositing the light-emitting layer on the anode AE and the pixel defining layer PDL by thermal evaporation. However, this is only an example, and the deposition process of the light-emitting layer should not be limited to this or restricted thereby. The light-emitting layer may be divided into multiple parts by the tip portions formed in the second barrier wall PW-E, and the light-emitting pattern EP and the first dummy layer D1 may be formed. The light-emitting pattern EP may be formed on the first barrier wall PW-S and the circuit element layer DP-CL, and the first dummy layer D1 may be formed on the second barrier wall PW-E. As an example, the light-emitting pattern EP may be formed on the anode AE and may overlap with the barrier wall opening OP-P, and the light-emitting pattern EP may be formed to cover the anode AE and the pixel defining layer PDL.

[0166] That is, the first dummy layer D1 spaced apart from the light-emitting pattern EP may be formed during the formation of the light-emitting pattern EP. The first dummy layer D1 may include an organic material. As an example, the first dummy layer D1 may include the same material as the light-emitting pattern EP. The first dummy layer D1 may be formed with the light-emitting pattern EP by a single process, and may be separated from the light-emitting pattern EP due to the undercut shape of the second barrier wall PW-E.

[0167] Reference Figure 6K The process of forming the cathode CE may include a deposition process of the cathode layer. As an example, forming the cathode CE may include a process of sputtering the cathode layer on the light-emitting pattern EP. However, this is only an example, and the deposition process of the cathode layer should not be limited to this or restricted thereby. The cathode layer may be divided into multiple parts by the tip portions formed in the second barrier wall PW-E, and the cathode CE and the second dummy layer D2 may be formed. The cathode CE may be positioned on the light-emitting pattern EP and may cover the light-emitting pattern EP, and the second dummy layer D2 may be formed on the first dummy layer D1. The cathode layer may be sputtered to contact the inner surface S1-2 of the first barrier wall layer L1-E of the second barrier wall PW-E. The second barrier wall PW-E may receive a driving voltage, and the cathode CE may be electrically connected to the second barrier wall PW-E and may receive the driving voltage.

[0168] That is, the second dummy layer D2 spaced apart from the cathode CE may be formed during the process of forming the cathode CE. The second dummy layer D2 may include a conductive material. As an example, the second dummy layer D2 may include the same material as the cathode CE. The second dummy layer D2 and the cathode CE may be formed by a single process, and the second dummy layer D2 may be separated from the cathode CE by the undercut shape of the second barrier wall PW-E.

[0169] The anode AE, the light-emitting pattern EP, and the cathode CE can be sequentially stacked in a third direction DR3. The anode AE, the light-emitting pattern EP, and the cathode CE can form a light-emitting element ED.

[0170] Reference Figure 6L and Figure 6M , a method of manufacturing a display panel may include forming a lower encapsulation inorganic pattern LIL on the cathode CE.

[0171] Reference Figure 6L , forming the lower encapsulation inorganic pattern LIL may include depositing a lower encapsulation inorganic layer LIL-I. The lower encapsulation inorganic layer LIL-I can be formed by a deposition process. The lower encapsulation inorganic layer LIL-I can be formed by a chemical vapor deposition process. The lower encapsulation inorganic layer LIL-I can be formed to cover the cathode CE and the barrier rib PW (reference Figure 5 ). A part of the lower encapsulation inorganic layer LIL-I can be filled in the barrier rib opening OP-P.

[0172] Then, forming the lower encapsulation inorganic pattern LIL may include forming a third photoresist layer PR3. The third photoresist layer PR3 can be formed by forming a preliminary photoresist layer and patterning the preliminary photoresist layer using a photomask. Through a patterning process, the third photoresist layer PR3 can be formed in a pattern corresponding to the light-emitting element ED.

[0173] Reference Figure 6M , forming the lower encapsulation inorganic pattern LIL may include removing a portion of the lower encapsulation inorganic layer LIL-I (reference Figure 6L ) that does not overlap with the light-emitting element ED.

[0174] The removal of the portion of the lower encapsulation inorganic layer LIL-I that does not overlap with the light-emitting element ED can be performed by a dry etching process of dry-etching the lower encapsulation inorganic layer LIL-I using the third photoresist layer PR3 as a mask. The portion of the lower encapsulation inorganic layer LIL-I that does not overlap with the third photoresist layer PR3 can be removed, and the remaining unetched portion of the lower encapsulation inorganic layer LIL-I can be used as the lower encapsulation inorganic pattern LIL.

[0175] A method of manufacturing a display panel may include removing a first dummy layer D1 and a second dummy layer D2. The second dummy layer D2 in the dummy layers D1 and D2 can be removed by a wet etching process, and the first dummy layer D1 in the dummy layers D1 and D2 can be removed by a lift-off process.

[0176] Reference Figure 6N , a method of manufacturing a display panel may include removing the third photoresist layer PR3 (reference Figure 6M) and form an encapsulation organic layer OL and an upper encapsulation inorganic layer UIL (e.g., to complete a display panel DP). The encapsulation organic layer OL can be formed by coating an organic material using an inkjet method. However, it should not be limited to this or restricted thereby. The encapsulation organic layer OL can provide a flat upper surface thereon. Then, the upper encapsulation inorganic layer UIL can be formed by depositing an inorganic material. Thus, a display panel DP including a substrate layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE can be manufactured.

[0177] Figures 6A through 6N The process in shows the process of forming a display panel corresponding to a first light-emitting region PXA-R. A process of forming light-emitting openings OP-E corresponding to a second light-emitting region PXA-G and a third light-emitting region PXA-B (refer to Figure 4 ) in a barrier wall PW and a pixel defining layer PDL, a process of forming light-emitting elements ED corresponding to the second light-emitting region PXA-G and the third light-emitting region PXA-B, and a process of forming a lower encapsulation inorganic pattern LIL covering the light-emitting elements ED corresponding to the second light-emitting region PXA-G and the third light-emitting region PXA-B can be further performed between forming the lower encapsulation inorganic pattern LIL and completing the display panel DP.

[0178] According to the present disclosure, one mask for forming barrier wall openings OP-P, light-emitting openings OP-E, and sacrificial openings OP-S corresponding to a first light-emitting region PXA-R, a second light-emitting region PXA-G, and a third light-emitting region PXA-B, and three masks for forming lower encapsulation inorganic patterns LIL corresponding to the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B respectively can be suitable. That is, four masks can be suitable for manufacturing a display panel, although the number of masks should not be limited to four.

[0179] As an example, according to one or more embodiments, one mask for forming a preliminary barrier wall opening OP-PI, a light-emitting opening OP-E, and a sacrificial opening OP-S corresponding to a first light-emitting region PXA-R, a second light-emitting region PXA-G, and a third light-emitting region PXA-B, one mask for forming a barrier wall opening OP-P corresponding to the first light-emitting region PXA-R, one mask for forming a lower encapsulation inorganic pattern LIL corresponding to the first light-emitting region PXA-R, one mask for forming a barrier wall opening OP-P corresponding to the second light-emitting region PXA-G, one mask for forming a lower encapsulation inorganic pattern LIL corresponding to the second light-emitting region PXA-G, one mask for forming a barrier wall opening OP-P corresponding to the third light-emitting region PXA-B, and one mask for forming a lower encapsulation inorganic pattern LIL corresponding to the third light-emitting region PXA-B may be suitable. That is, seven masks may be suitable for manufacturing a display panel.

[0180] According to the present disclosure, a process of etching a barrier wall PW (a process of forming a tip portion) using a first photoresist layer PR1 and a second photoresist layer PR2, a process of forming a degassing opening OP-G, a process of forming a light-emitting opening OP-E, and a process of forming a sacrificial opening OP-S may be integrated. That is, one mask may be used to perform the process of etching the barrier wall PW (the process of forming a tip portion), the process of forming the degassing opening OP-G, the process of forming the light-emitting opening OP-E, and the process of forming the sacrificial opening OP-S, and thus the number of masks suitable for manufacturing a display panel DP may be reduced.

[0181] Although embodiments of the present disclosure have been described, it is understood that the present disclosure should not be limited to these embodiments, but various changes and modifications can be made by those of ordinary skill in the art within the spirit and scope of the present disclosure as claimed. Therefore, the subject matter disclosed should not be limited to any single embodiment described herein, and the scope of the present disclosure should be determined according to the appended claims, and equivalents thereof will be included therein.

Claims

1. A display panel, wherein: The display panel comprises: Base layer; a barrier wall, which is above the base layer and includes a first barrier wall and a second barrier wall; a pixel defining layer over the base layer and defining a light emitting opening overlapping the first barrier wall and surrounded by the second barrier wall in a plan view; and The light emitting element includes an anode above the barrier wall, a light emitting pattern above the anode and the pixel defining layer, and a cathode above the light emitting pattern and in contact with the second barrier wall.

2. The display panel according to claim 1, wherein: The second barrier wall surrounds the first barrier wall and is spaced apart from the first barrier wall in a plan view.

3. The display panel according to claim 1, wherein: The first barrier wall and the second barrier wall include a conductive material.

4. The display panel according to claim 1, wherein: The first barrier wall and the second barrier wall include: a first barrier layer over the base layer; and A second barrier wall layer is above the first barrier wall layer.

5. The display panel according to claim 4, wherein: The first barrier wall layer of the second barrier wall has an undercut shape with respect to the second barrier wall layer of the second barrier wall.

6. The display panel according to claim 5, wherein: The second barrier wall layer of the second barrier wall protrudes toward the light emitting opening to a greater extent than the first barrier wall layer of the second barrier wall.

7. The display panel according to claim 5, wherein: The cathode contacts an inner side surface of the first barrier wall layer of the second barrier wall.

8. The display panel according to claim 1, wherein: The second barrier wall defines a barrier wall opening overlapping the light emitting opening and the first barrier wall is located in the barrier wall opening.

9. The display panel according to claim 8, wherein: A portion of the pixel defining layer defining the light emitting opening is in the barrier wall opening.

10. The display panel according to claim 8, wherein: The display panel further includes a lower encapsulation inorganic pattern over the cathode, covering the light emitting element and filling in the barrier wall opening.

11. The display panel according to claim 1, wherein: The display panel further includes a sacrificial pattern between the pixel defining layer and the anode.

12. A method for manufacturing a display panel, wherein: The method comprises: providing a preliminary display panel including a base layer, a preliminary barrier wall over the base layer, an anode layer over the preliminary barrier wall, and a sacrificial layer; etching the sacrificial layer to form a preliminary sacrificial pattern; etching the anode layer to form an anode; etching the preliminary barrier wall for a first time to form a first barrier wall and a second preliminary barrier wall; depositing a preliminary pixel defining layer over the base layer; etching the preliminary pixel defining layer to form a pixel defining layer, the pixel defining layer defining a light emitting opening overlapping the first barrier wall and an opening exposing an inner side surface of the second preliminary barrier wall; etching the preliminary barrier wall for a second time to form a second barrier wall defining a barrier wall opening; and A light emitting pattern and a cathode are formed to overlap the barrier wall opening.

13. The method according to claim 12, wherein: The method also includes etching the preliminary sacrificial pattern to form a sacrificial pattern defining a sacrificial opening overlapping the light emitting opening.

14. The method according to claim 12, wherein: The first barrier wall and the second barrier wall include: a first barrier layer over the base layer; and A second barrier wall layer is above the first barrier wall layer.

15. The method according to claim 14, wherein: The second barrier wall layer of the second barrier wall protrudes toward the light emitting opening to a greater extent than the first barrier wall layer of the second barrier wall.

16. The method according to claim 14, wherein: The forming of the light emitting pattern and the cathode comprises: depositing a light emitting layer on the anode and the pixel defining layer by thermal evaporation; and A cathode layer is sputtered on the light emitting pattern.

17. The method according to claim 16, wherein: The sputtering the cathode layer includes depositing the cathode layer to contact an inner side surface of the first barrier wall layer of the second barrier wall.

18. The method according to claim 12, wherein: The second etching of the preliminary barrier wall includes etching the second preliminary barrier wall to allow the first barrier wall to be in the barrier wall opening.

19. The method according to claim 12, wherein: The second barrier wall surrounds the first barrier wall and is spaced apart from the first barrier wall in a plan view.

20. The method according to claim 12, wherein: The method further includes forming a lower encapsulation inorganic pattern on the cathode.

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