SOC (State of Charge) state estimation system and estimation method used in BMS (Battery Management System)

Abstract

The invention discloses an SOC state estimation system and method used in a BMS. The SOC state estimation system comprises a current signal conditioning circuit, a voltage detection circuit and an SOC estimation module. The input end of the current signal conditioning circuit is connected with the positive electrode of the battery pack; the input end of the voltage detection circuit is connected with the positive and negative electrodes of the battery pack respectively; the voltage detection circuit is used for obtaining an open-circuit voltage VOC of the battery pack and is connected to a data sampling port of the SOC estimation module; the current signal conditioning circuit is used for detecting the current of the battery pack and is connected to a data sampling port of the SOC estimation module; on one hand, the SOC estimation module calculates an initial value SOC0 when the battery pack works according to a pre-stored battery model and an open-circuit voltage VOC, and on the other hand, the SOC estimation module calculates an SOC value of the battery at any moment according to current and an ampere-hour integral method. The SOC detection of the battery is realized by combining the open-circuit voltage method and the ampere-hour integral method, and the method has the advantages of being simple, practical and accurate in result.

Description

Technical Field

[0001] The present invention relates to the field of power batteries, and specifically to BMS current detection and state estimation. Background Art

[0002] In the field of power batteries, the battery management system (BMS) plays a crucial role in ensuring the safe and efficient operation of batteries. Among them, accurately estimating the state of charge (SOC) of the battery is one of the core functions of the BMS. However, there are many deficiencies in the existing SOC estimation methods. On the one hand, when measuring the initial state of the battery, it is difficult to achieve high-precision measurement for some methods, resulting in inaccurate initial SOC values, which in turn affect the accuracy of SOC estimation during the subsequent entire battery operation process. On the other hand, when detecting the charge and discharge current of the battery, traditional current detection circuits are often complex in structure, high in cost, and unable to automatically adjust detection parameters according to the magnitude of the battery current, making the detected current signal inaccurate and ultimately affecting the accuracy of SOC estimation. In addition, due to the inability to achieve integrated detection of charging mode current and discharging mode, the estimation efficiency and accuracy of SOC under different working conditions are low, and it is difficult to meet the requirements of modern power batteries for high safety, long life, and efficient operation. Summary of the Invention

[0003] The purpose of the present invention is to provide a BMS current conditioning circuit and an SOC state estimation method. The present invention accurately detects SOC by combining the open-circuit voltage method and the ampere-hour integration method, optimizes the current conditioning circuit to achieve integrated charge and discharge detection to reduce costs and improve reliability, and based on this, can quickly and accurately estimate SOC under various working conditions, improving battery life and safety.

[0004] The technical solution provided by the present invention is as follows: An SOC state estimation system for BMS includes a current signal conditioning circuit, a voltage detection circuit, and an SOC estimation module; the input end of the current signal conditioning circuit is connected to the positive electrode of the battery pack; the input ends of the voltage detection circuit are respectively connected to the positive and negative electrodes of the battery pack; the voltage detection circuit is used to obtain the open-circuit voltage VOC of the battery pack and is connected to the data sampling port of the SOC estimation module; the current signal conditioning circuit is used to detect the current i B of the battery pack and is connected to the data sampling port of the SOC estimation module; on the one hand, the SOC estimation module calculates the initial value SOC0 when the battery pack is working based on the pre-stored battery model and the open-circuit voltage VOC, and on the other hand, calculates the SOC value of the battery at any time based on the current i B and the ampere-hour integration method;

[0005] The current signal conditioning circuit includes a current-to-voltage module, a DC bias circuit, and a CT matching resistor control module; the current-to-voltage module consists of a current transformer CT, a parallel-connected controllable matching resistor network, and a TVS protection circuit, and is used to convert the battery loop current into a proportional voltage signal; the DC bias circuit is composed of an operational amplifier OP and an equivalent resistor network, receives the voltage signal output by the current-to-voltage module, and outputs a positive unipolar voltage after applying a reference bias; the CT matching resistor control module includes a voltage comparator array, a logic gate circuit, and a bidirectional shift register group, which real-time monitors the voltage amplitude output by the DC bias circuit, and makes the output voltage stable in the measurement range of the ADC range by dynamically switching the parallel branches of the controllable matching resistor network.

[0006] The above SOC state estimation system for BMS, the current-to-voltage module includes a current transformer CT, a matching resistor R1, a matching resistor R2, a matching resistor R3, a matching resistor R4, a dual N-channel MOS transistor M1, a dual N-channel MOS transistor M2, a dual N-channel MOS transistor M3, a dual N-channel MOS transistor M4, and a bidirectional TVS diode D1; the input side of the current transformer CT receives the current i of the battery pack B , one end of the output side of the current transformer CT is respectively connected to one end of the matching resistor R1, one end of the matching resistor R2, one end of the matching resistor R3, one end of the matching resistor R4, and one end of the bidirectional TVS diode D1; the other end of the matching resistor R1 is connected to one end pin of the dual N-channel MOS transistor M1, and the other end pin of the dual N-channel MOS transistor M1 is grounded; the other end of the matching resistor R2 is connected to one end pin of the dual N-channel MOS transistor M2, and the other end pin of the dual N-channel MOS transistor M2 is grounded; the other end of the matching resistor R3 is connected to one end pin of the dual N-channel MOS transistor M3, and the other end pin of the dual N-channel MOS transistor M3 is grounded; the other end of the matching resistor R4 is connected to one end pin of the dual N-channel MOS transistor M4, and the other end pin of the dual N-channel MOS transistor M4 is grounded; the other end of the bidirectional TVS diode D1 is grounded; the dual N-channel MOS transistors M1, M2, M3, and M4 are also connected to the CT matching resistor control module.

[0007] The aforementioned SOC state estimation system for the BMS, the DC bias circuit includes an operational amplifier OP, four resistors R5 with the same resistance value, a resistor R6, a resistor R7, and a resistor R8; the non-inverting input terminal of the operational amplifier OP is respectively connected to one end of the resistor R5 and one end of the resistor R6, the other end of the resistor R5 is connected to the output terminal of the current-to-voltage module, and the other end of the resistor R6 is connected to a 2.5V reference voltage; the inverting input terminal of the operational amplifier OP is connected to one end of the resistor R7 and one end of the resistor R8, the other end of the resistor R7 is grounded, and the other end of the resistor R8 is connected to the output terminal of the operational amplifier OP.

[0008] The aforementioned SOC state estimation system for BMS, wherein the CT matching resistor control module includes voltage comparators CP1, CP2, CP3, CP4, OR gates OR1, OR2, OR3, OR4, OR5, OR6, bidirectional shift register U1 and bidirectional shift register U2; the non-inverting input terminals of voltage comparator CP1, the inverting input terminal of voltage comparator CP2, the inverting input terminal of voltage comparator CP3, and the non-inverting input terminal of voltage comparator CP4 are respectively connected to the output terminal of operational amplifier OP; the inverting input terminal of voltage comparator CP1 is connected to a 3V reference voltage, and the output terminal of voltage comparator CP1 is respectively connected to one input terminal of OR gate OR1 and the pin S0 of bidirectional shift register U1; the non-inverting input terminal of voltage comparator CP2 is connected to a 2.6V reference voltage, and the output terminal of voltage comparator CP2 is respectively connected to the other input terminal of OR gate OR1 and the pin S1 of bidirectional shift register U1; the output terminal of OR gate OR1 is connected to the CP pin of bidirectional shift register U1; the non-inverting input terminal of voltage comparator CP3 is connected to a 2V reference voltage, and the output terminal of voltage comparator CP3 is respectively connected to one input terminal of OR gate OR2 and the pin S0 of bidirectional shift register U2; the inverting input terminal of voltage comparator CP4 is connected to a 2.4V reference voltage, and the output terminal of voltage comparator CP4 is respectively connected to the other input terminal of OR gate OR2 and the pin S1 of bidirectional shift register U2; the output terminal of OR gate OR2 is connected to the CP pin of bidirectional shift register U2; the two input terminals of OR gate OR3 are respectively connected to the Q0 pin of bidirectional shift register U1 and the Q4 pin of bidirectional shift register U2, and the output terminal of OR gate OR3 is connected to the signal receiving terminal of dual N-channel MOS transistor M4; the two input terminals of OR gate OR4 are respectively connected to the Q1 pin of bidirectional shift register U1 and the Q5 pin of bidirectional shift register U2, and the output terminal of OR gate OR4 is connected to the signal receiving terminal of dual N-channel MOS transistor M3; the two input terminals of OR gate OR5 are respectively connected to the Q2 pin of bidirectional shift register U1 and the Q6 pin of bidirectional shift register U2, and the output terminal of OR gate OR5 is connected to the signal receiving terminal of dual N-channel MOS transistor M2; the two input terminals of OR gate OR6 are respectively connected to the Q3 pin of bidirectional shift register U1 and the Q7 pin of bidirectional shift register U2, and the output terminal of OR gate OR6 is connected to the signal receiving terminal of dual N-channel MOS transistor M1.

[0009] The estimation method of the aforementioned SOC state estimation system for BMS includes the following steps:

[0010] Step 1: When the battery starts to work, the SOC estimation module obtains the open-circuit voltage VOC of the battery pack, calculates the battery SOC value based on the pre-stored battery model and VOC data, and takes it as the initial value SOC0;

[0011] Step 2: After the battery starts to work, the current signal conditioning circuit realizes the detection of wide-range current i B through adaptive resistance switching. Subsequently, the SOC estimation module calculates the SOC value of the battery at any time according to the current i B and the ampere-hour integration method.

[0012] The estimation method for the SOC state estimation system in the BMS described above. The specific calculation process of the SOC value of the battery at any time is as follows:

[0013] Step 2.1: Obtain the drive signal state values of the dual N-channel MOS transistors M1, M2, M3, and M4 in the current conditioning circuit, and then determine the equivalent matching resistance value R CT ;

[0014] Step 2.2: Obtain the value of the signal v1 at the output end of the operational amplifier OP in the current conditioning circuit, and obtain the value of the signal v B at the output end of the current-to-voltage module according to v B = v1 - 2.5;

[0015] Step 2.3: Calculate the battery current i CT according to the current decay coefficient K CT of the current transformer CT and the CT equivalent matching resistance R B = v B / K CT R CT ;

[0016] Step 2.4: Apply the ampere-hour integration method to calculate the increment of SOC at time k, that is, calculate ΔSOC k = i B (k)T; where: k is the calculation time of the increment, T is the interval time of the increment calculation, and the corresponding time t k at time k = kT;

[0017] Step 2.5: The BMS calculates the SOC value at time k according to SOC k = SOC k-1 + i B (k)T, where: k ≥ 1.

[0018] Compared with the prior art, the present invention has the following advantages:

[0019] 1. Before the battery pack operates, the initial state of the battery each time it works is calculated by measuring the open-circuit voltage of the battery pack. After the operation starts, by measuring the charge and discharge current of the battery pack with high precision and integrating over time, the change amount of the battery state is obtained, so as to calculate the state value of the battery at any time during operation. Therefore, the present invention realizes the SOC detection of the battery by combining the open-circuit voltage method and the ampere-hour integration method, and has the advantages of simplicity, practicality and accurate results.

[0020] 2. The current conditioning circuit of the present invention can automatically adjust the matching resistance of CT according to the magnitude of the battery current i B value to ensure that the voltage signal v B converted after i B is within a suitable voltage range. The current conditioning circuit of the present invention realizes the integrated detection of the charging mode current and the discharging mode, and has the advantages of simple and reliable structure, low cost, etc. In addition, based on the integrated detection of the charge and discharge current, the BMS realizes the rapid and accurate estimation of the SOC under the charging mode, discharging mode and charge-discharge working conditions, and improves the battery life and safe operation. Description of the Drawings

[0021] Figure 1 is a connection schematic diagram of the system of the present invention;

[0022] Figure 2 is the current conditioning circuit diagram of the present invention; Detailed Embodiment

[0023] The present invention will be further described below in conjunction with the embodiments and the drawings, but it is not used as the basis for limiting the present invention.

[0024] Embodiment: A SOC state estimation system for a BMS, as Figure 1 shown, includes a current signal conditioning circuit, a voltage detection circuit and a SOC estimation module; the input end of the current signal conditioning circuit is connected to the positive electrode of the battery pack; the input ends of the voltage detection circuit are respectively connected to the positive and negative electrodes of the battery pack; the voltage detection circuit is used to obtain the open-circuit voltage VOC of the battery pack and is connected to the data sampling port of the SOC estimation module; the current signal conditioning circuit is used to detect the current i B of the battery pack and is connected to the data sampling port of the SOC estimation module; on the one hand, the SOC estimation module calculates the initial value SOC0 when the battery pack works according to the pre-stored battery model and the open-circuit voltage VOC, and on the other hand, according to the current i BThe Ampere-hour integration method is used to calculate the SOC value of the battery at any moment. In this embodiment, the voltage detection circuit is a conventional circuit. Its principle is to attenuate the high-voltage battery pack voltage to a safe range in proportion through a voltage division network. After signal conditioning (differential amplification, filtering) and isolation processing, it is converted into a digital signal by a high-precision ADC for use by the SOC estimation module. This belongs to the conventional technical means well-known and mastered by those skilled in the art, so it will not be described in detail here. In this embodiment, the SOC estimation module is integrated on the BMS main control circuit board, including an STM32F4 series microcontroller, a current / voltage signal input interface, and a memory. The microcontroller collects the conditioned current signal through the built-in ADC and executes the Ampere-hour integration algorithm stored in the Flash to update the SOC value in real time.

[0025] The current signal conditioning circuit includes a current-to-voltage conversion module, a DC bias circuit, and a CT matching resistor control module; the current-to-voltage conversion module consists of a current transformer CT, a parallel controllable matching resistor network, and a TVS protection circuit, and is used to convert the battery loop current into a proportional voltage signal; the DC bias circuit is composed of an operational amplifier OP and an equivalent resistor network, receives the voltage signal output by the current-to-voltage conversion module, and outputs a positive unipolar voltage after applying a 2.5V reference bias; the CT matching resistor control module includes a voltage comparator array, a logic gate circuit, and a bidirectional shift register group, and monitors the voltage amplitude output by the DC bias circuit in real time. By dynamically switching the parallel branches of the controllable matching resistor network, the output voltage is stabilized within the measurement range of the ADC range.

[0026] In this embodiment, the current-to-voltage conversion module includes a current transformer CT, a matching resistor R1, a matching resistor R2, a matching resistor R3, a matching resistor R4, a dual N-channel MOS transistor M1, a dual N-channel MOS transistor M2, a dual N-channel MOS transistor M3, a dual N-channel MOS transistor M4, and a bidirectional TVS diode D1; the models of the dual N-channel MOS transistors M1, M2, M3, and M4 are all 8205A; the input side of the current transformer CT receives the current i of the battery pack B, one end of the output side of the current transformer CT is respectively connected to one end of the matching resistor R1, one end of the matching resistor R2, one end of the matching resistor R3, one end of the matching resistor R4, and one end of the bidirectional TVS tube D1; the other end of the matching resistor R1 is connected to one end pin of the double N-channel MOS tube M1, and the other end pin of the double N-channel MOS tube M1 is grounded; the other end of the matching resistor R2 is connected to one end pin of the double N-channel MOS tube M2, and the other end pin of the double N-channel MOS tube M2 is grounded; the other end of the matching resistor R3 is connected to one end pin of the double N-channel MOS tube M3, and the other end pin of the double N-channel MOS tube M3 is grounded; the other end of the matching resistor R4 is connected to one end pin of the double N-channel MOS tube M4, and the other end pin of the double N-channel MOS tube M4 is grounded; the other end of the bidirectional TVS tube D1 is grounded; the double N-channel MOS tubes M1, M2, M3, and M4 are also connected to the CT matching resistor control module. Among them, CT is a through-type current transformer, and its current attenuation coefficient K CT satisfies K CT = N / 1, that is, the current of the CT output coil is 1 / N of the input current i B ; M1 is the control switch of R1, M2 is the control switch of R2, M3 is the control switch of R3, and M4 is the control switch of R4. M1, M2, M3, and M4 are controlled by the output signals X1, X2, X3, and X4 of the CT matching resistor control module, and are used to match different resistors when the battery current is different, and convert the battery charge and discharge current i B into a suitable voltage signal v B , ensuring that v B is of a reasonable magnitude. D1 realizes the limiting of the voltage signal v B to protect the CT and the signal conditioning circuit. v B and i B satisfy the following formula:

[0027] v B = K CT R CT i B ;

[0028] where: R CT is the equivalent matching resistor of the secondary output coil of the CT, and satisfies:

[0029]

[0030] The DC bias circuit includes an operational amplifier OP, four resistors R5 with the same resistance value, a resistor R6, a resistor R7, and a resistor R8; the non-inverting input terminal of the operational amplifier OP is respectively connected to one end of the resistor R5 and one end of the resistor R6, the other end of the resistor R5 is connected to the output terminal of the current-to-voltage module, and the other end of the resistor R6 is connected to a 2.5V reference voltage; the inverting input terminal of the operational amplifier OP is connected to one end of the resistor R7 and one end of the resistor R8, the other end of the resistor R7 is grounded, and the other end of the resistor R8 is connected to the output terminal of the operational amplifier OP. According to the knowledge of electrical engineering, v1 and v B Satisfy:

[0031] v1 = 2.5 + v B .

[0032] The CT matching resistor control module includes voltage comparators CP1, CP2, CP3, CP4, OR gates OR1, OR2, OR3, OR4, OR5, OR6, bidirectional shift register U1 and bidirectional shift register U2. The non-inverting input terminal of voltage comparator CP1, the inverting input terminal of voltage comparator CP2, the inverting input terminal of voltage comparator CP3 and the non-inverting input terminal of voltage comparator CP4 are respectively connected to the output terminal of operational amplifier OP. The inverting input terminal of voltage comparator CP1 is connected to a 3V reference voltage, and the output terminal of voltage comparator CP1 is respectively connected to one input terminal of OR gate OR1 and the pin S0 of bidirectional shift register U1. The non-inverting input terminal of voltage comparator CP2 is connected to a 2.6V reference voltage, and the output terminal of voltage comparator CP2 is respectively connected to the other input terminal of OR gate OR1 and the pin S1 of bidirectional shift register U1. The output terminal of OR gate OR1 is connected to the CP pin of bidirectional shift register U1. The non-inverting input terminal of voltage comparator CP3 is connected to a 2V reference voltage, and the output terminal of voltage comparator CP3 is respectively connected to one input terminal of OR gate OR2 and the pin S0 of bidirectional shift register U2. The inverting input terminal of voltage comparator CP4 is connected to a 2.4V reference voltage, and the output terminal of voltage comparator CP4 is respectively connected to the other input terminal of OR gate OR2 and the pin S1 of bidirectional shift register U2. The output terminal of OR gate OR2 is connected to the CP pin of bidirectional shift register U2. The two input terminals of OR gate OR3 are respectively connected to the Q0 pin of bidirectional shift register U1 and the Q4 pin of bidirectional shift register U2, and the output terminal of OR gate OR3 is connected to the signal receiving terminal of dual N-channel MOS transistor M4. The two input terminals of OR gate OR4 are respectively connected to the Q1 pin of bidirectional shift register U1 and the Q5 pin of bidirectional shift register U2, and the output terminal of OR gate OR4 is connected to the signal receiving terminal of dual N-channel MOS transistor M3. The two input terminals of OR gate OR5 are respectively connected to the Q2 pin of bidirectional shift register U1 and the Q6 pin of bidirectional shift register U2, and the output terminal of OR gate OR5 is connected to the signal receiving terminal of dual N-channel MOS transistor M2. The two input terminals of OR gate OR6 are respectively connected to the Q3 pin of bidirectional shift register U1 and the Q7 pin of bidirectional shift register U2, and the output terminal of OR gate OR6 is connected to the signal receiving terminal of dual N-channel MOS transistor M1. Among them, CP1 compares v1 with 3V to obtain the output signal v2, CP2 compares v1 with 2.6V to obtain the output signal v3, CP3 compares v1 with 2.4V to obtain the output signal v4, and CP4 compares v1 with 2V to obtain the output signal v5; G1 performs an OR operation on v2 and v3 to obtain the output signal v P+ ; G2 performs an OR operation on v4 and v5 to obtain the output signal v P-; The shift mode control terminals S1 and S0 of U1 are respectively connected to v2 and v3, and are used to set whether U1 shifts left or right. The shift clock pulse terminal CP of U1 is connected to v P+ ; The data input terminals D3, D2, D1, D0 of U1 and the left shift data DSL are all connected to GND. The reset terminal and the right shift data DSR of U1 are connected to VCC. The output signals of the output terminals Q0, Q1, Q2, Q3 of U1 are respectively connected to the input terminals of OR3, OR4, OR5, OR6; The shift mode control terminals S1 and S0 of U2 are respectively connected to v4 and v5, and are used to set whether U2 shifts left or right. The shift clock pulse terminal CP of U2 is connected to v P- ; The data input terminals D3, D2, D1, D0 of U2 and the left shift data DSL are all connected to GND. The reset terminal and the right shift data DSR of U2 are connected to VCC. The output signals of the output terminals Q4, Q5, Q6, Q7 of U2 are respectively connected to the other input terminals of OR3, OR4, OR5, OR6; OR3 performs an OR operation on Q0 and Q4 to obtain the drive signal X4 of M4; OR4 performs an OR operation on Q1 and Q5 to obtain the drive signal X3 of M3; OR5 performs an OR operation on Q2 and Q6 to obtain the drive signal X2 of M2; OR6 performs an OR operation on Q3 and Q7 to obtain the drive signal X1 of M1. CP1, CP2, OR1 and U1 in the CT matching resistor control module form a charging mode CT matching resistor control function, CP3, CP4, OR2 and U2 form a discharging mode CT matching resistor control function, and OR3, OR4, OR5 and OR6 implement the drive of the CT matching resistor control switches M1, M2, M3 and M4. The working principle is as follows:

[0033] In the charging mode: The voltage v B at the output terminal of CT is greater than zero, and the value of the voltage signal v1 at the output terminal of OP is greater than 2.5V. When the charging current i B increases to make v1 greater than 3V, the signal v2 at the output terminal of the voltage comparator CP1 changes from low level to high level, and the signal v3 at the output terminal of the voltage comparator CP2 remains low level. The level state of the mode control terminals S1S0 of the bidirectional shift register U1 changes from 00 to 01, and U1 works in the right shift mode. Since the shift clock pulse signal v p+ obtained by performing an OR operation on v2 and v3 by the OR gate OR1 is connected to the CP terminal of U1, so v p+ jumps with a slight delay compared to v2. When i B increases to make v1 greater than 3V, S1S0 first changes from 00 to 01, setting U1 to the right shift mode; then, the signal v p+A rising edge is generated, the high level is shifted to the output terminal Q0 of the bidirectional shift register U1, and Q1, Q2, and Q3 are shifted one bit to the right in sequence. Furthermore, a new 8205A is turned on, and the corresponding matching resistor is connected in parallel to the circuit to reduce the conversion resistor when the current increases, ensuring that i B is converted into a voltage signal v of appropriate magnitude B . As the conversion resistor decreases, v1 quickly drops and becomes less than 3V, and the signal v2 at the output terminal of CP1 changes from high level to low level. At the same time, by reasonably selecting the values of R1, R2, R3, and R4, it can be ensured that the value at which v1 quickly drops is greater than 2.6V. Therefore, the level state of the mode control terminals S1S0 of the bidirectional shift register U1 changes from 01 to 00, and it is in the hold mode. After that, if the current i B continues to increase such that v1 is greater than 3V again, the high level is shifted to the output terminal Q0 of the bidirectional shift register U1, and Q1, Q2, and Q3 are shifted one bit to the right in sequence. Furthermore, a new 8205A is turned on, and the corresponding matching resistor is connected in parallel to the circuit to reduce the conversion resistor when the current increases, ensuring that i B is converted into a voltage signal v of appropriate magnitude B . Following this principle and by analogy, when the current i B increases to make v1 greater than 3V, the high level is shifted one bit to the right among Q3, Q2, Q1, and Q0, one more 8205A transistor is turned on, the CT matching resistor value decreases, and thus v B and the magnification of i B decrease, ensuring that v B is within an appropriate voltage range. Repeat the above process until the states of Q3, Q2, Q1, and Q0 become 1111, the magnification of v B and i B is the smallest, and the corresponding i B operates in the maximum value range. Similarly, when the current i B decreases to make v1 less than 2.6V, the signal v3 at the output terminal of the voltage comparator CP2 changes from low level to high level, the signal v2 at the output terminal of the voltage comparator CP1 remains low level, and the level state of the mode control terminals S1S0 of the bidirectional shift register U1 changes from 00 to 10, and U1 operates in the left shift mode. Since the shift clock pulse signal v p+ obtained by performing an OR operation on v2 and v3 by the OR gate OR1 is connected to the CP terminal of U1, so v p+ jumps with a slight delay compared to v3. When i B decreases to make v1 less than 2.6V, S1S0 first changes from 00 to 10, setting U1 to the left shift mode; then, the signal v p+Generate a rising edge, shift the low level to the output terminal Q3 of the bidirectional shift register U1, and shift Q2, Q1, and Q0 one bit to the left in turn, thereby turning off one path of 8205A conduction, disconnecting the corresponding matching resistor, and realizing an increase in the conversion resistor when the current decreases to ensure that i B is converted into a voltage signal v of appropriate magnitude B . As the conversion resistor increases, v1 increases rapidly and is greater than 2.6V, and the output terminal signal v3 of CP2 changes from high level to low level. At the same time, by reasonably selecting the values of R1, R2, R3, and R4, it can be ensured that the rapidly increasing value of v1 is less than 3V. Therefore, the level state of the mode control terminals S1S0 of the bidirectional shift register U1 changes from 10 to 00 and is in the hold mode. After that, if the current i B continues to decrease such that v1 is less than 2.6V again, the low level is shifted to the output terminal Q3 of the bidirectional shift register U1, and Q2, Q1, and Q0 are shifted one bit to the left in turn, and then another path of 8205A conduction is turned off, disconnecting the corresponding matching resistor, and realizing an increase in the conversion resistor when the current decreases to ensure that i B is converted into a voltage signal v of appropriate magnitude B . Following this principle and so on, when the current i B decreases to make v1 less than 2.6V, the low level is shifted one bit to the left among Q3, Q2, Q1, and Q0, one corresponding 8205A tube is turned off, the CT matching resistor value increases, and then v B and i B amplification factor increases, ensuring that v B is within an appropriate voltage range. Repeat the above process until the states of Q3, Q2, Q1, and Q0 become 0001, and the amplification factor of v B and i B is the largest, corresponding to the minimum value range of i B .

[0034] In the discharge mode: The battery current i B is reversed, and the output terminal voltage v of the corresponding CT B is less than zero, and the value of the voltage signal v1 at the output terminal of OP1 is less than 2.5V. When the current i B increases to make v1 less than 2V, the output terminal signal v4 of the voltage comparator CP3 changes from low level to high level, the output terminal signal v5 of the voltage comparator CP4 remains low level, and the level state of the mode control terminals S1S0 of the bidirectional shift register U2 changes from 00 to 01, and U2 operates in the right shift mode. Since the shift clock pulse signal v p- obtained by the OR operation of v4 and v5 by the OR gate OR2 is connected to the CP terminal of U2, so v p- jumps a little later than v4. At i BWhen it increases to make v1 less than 2V, S1S0 of U2 first changes from 00 to 01, and U2 is set to the right shift mode; then, the output signal v of OR2 p- generates a rising edge, and the high level shifts to the output terminal Q4 of the bidirectional shift register U2, and Q5, Q6, and Q7 are shifted one bit to the right in sequence. Furthermore, a new 8205A is turned on, and the corresponding matching resistor is connected in parallel to the circuit, realizing the reduction of the conversion resistor when the current increases, ensuring that i B is converted into a voltage signal v with a suitable magnitude B . As the conversion resistor decreases, v1 rapidly increases and is greater than 2V, and the output signal v4 of CP3 changes from high level to low level. At the same time, by reasonably selecting the values of R1, R2, R3, and R4, it can be ensured that v1 is less than 2.4V. Therefore, the level state of the mode control terminal S1S0 of the bidirectional shift register U2 changes from 01 to 00 and is in the hold mode. After that, if the current i B continues to increase to make v1 less than 2V again, the high level shifts to the output terminal Q4 of the bidirectional shift register U2, and Q5, Q6, and Q7 are shifted one bit to the right in sequence. Furthermore, a new 8205A is turned on, and the corresponding matching resistor is connected in parallel to the circuit, realizing the reduction of the conversion resistor when the current increases, ensuring that i B is converted into a voltage signal v with a suitable magnitude B . Following this principle and so on, when the current i B increases to make v1 less than 2V, the high level is shifted one bit to the right among Q7, Q6, Q5, and Q4, one more 8205A tube is turned on, the CT matching resistor value decreases, and then v B and i B amplification factor decreases, ensuring that v B is within a suitable voltage range. Repeat the above process until the states of Q7, Q6, Q5, and Q4 become 1111, and the amplification factor of v B and i B is the smallest, and the corresponding i B works in the maximum value range. Similarly, when the current i B decreases to make v1 greater than 2.4V, the output signal v5 of the voltage comparator CP4 changes from low level to high level, the output signal v4 of the voltage comparator CP3 remains low level, and the level state of the mode control terminal S1S0 of the bidirectional shift register U2 changes from 00 to 10, and U2 works in the left shift mode. Since the shift clock pulse signal v p- obtained by performing an OR operation on v4 and v5 by the OR gate OR2 is connected to the CP terminal of U2, so v p- jumps with a slight delay compared to v5. When i BWhen it is reduced to make v1 greater than 2.4V, S1S0 first changes from 00 to 10, setting U2 to the left shift mode; then, the output signal v of OR2 p- generates a rising edge, and the low level is shifted to the output Q7 of the bidirectional shift register U2, and Q6, Q5, and Q4 are shifted left by one bit in turn, thereby turning off one path of 8205A conduction, disconnecting the corresponding matching resistor, and realizing an increase in the conversion resistance when the current decreases to ensure that i B is converted into an appropriate voltage signal v B . As the conversion resistance increases, v1 rapidly decreases and becomes less than 2.4V. At the same time, the output signal v5 of CP4 changes from high level to low level. At the same time, by reasonably selecting the values of R1, R2, R3, and R4, it can be ensured that v1 is greater than 2V. Therefore, the level state of the mode control terminal S1S0 of the bidirectional shift register U2 changes from 10 to 00, and it is in the hold mode. After that, if the current i B continues to decrease to make v1 greater than 2.4V again, the low level is shifted to the output Q7 of the bidirectional shift register U2, and Q6, Q5, and Q4 are shifted left by one bit in turn, and then another path of 8205A conduction is turned off, and the corresponding matching resistor is disconnected, realizing an increase in the conversion resistance when the current decreases to ensure that i B is converted into an appropriate voltage signal v B . Following this principle and so on, when the current i B is reduced to make v1 greater than 2.4V, the low level is shifted left by one bit among Q7, Q6, Q5, and Q4, one corresponding 8205A tube is turned off, the CT matching resistance value increases, and then v B and i B amplification factor increases, ensuring that v B is within a reasonable voltage range. Repeat the above process until the states of Q7, Q6, Q5, and Q4 become 0001, and the amplification factor of v B and i B is the largest, corresponding to the minimum value range of i B .

[0035] Based on the voltage detection circuit and current signal conditioning circuit shown in Attachment Figure 1 and Figure 2 , in the SOC estimation module in Attachment Figure 1 , the main control chip can obtain the open circuit voltage value VOC of the battery after standing still and the charge and discharge current value i B during operation in real time, and then the SOC value of the battery at any time can be obtained. Therefore, the implementation principle steps of SOC state estimation are as follows:

[0036] Step 1: When the battery starts to work, the SOC estimation module obtains the open-circuit voltage VOC of the battery pack, calculates the battery SOC value based on the pre-stored battery model and VOC data, and uses it as the initial value SOC0;

[0037] In this step, the pre-stored battery model usually adopts the form of an open-circuit voltage (VOC)-SOC mapping table combined with capacity parameters. For example:

[0038] Lithium battery model parameter table

[0039] SOC(%) VOC(V) Capacity (Ah) 100 4.20 200 90 4.15 200 80 4.10 200 ... ... ... 20 3.60 200 10 3.40 200 0 3.00 200

[0040] Model application logic:

[0041] Initial SOC calculation: When the battery is static, by measuring VOC (such as 3.85V) and looking up the table, the corresponding SOC value (such as 65%) can be obtained;

[0042] This model establishes a monotonic correspondence between VOC and SOC through experimental data, is applicable to common battery types such as lithium iron phosphate and ternary lithium, and has the advantages of fast table lookup speed and low calculation complexity.

[0043] Step 2: After the battery starts to work, the current signal conditioning circuit realizes the detection of a wide-range current i B through adaptive resistance switching. Subsequently, the SOC estimation module calculates the SOC value of the battery at any time according to the current i B and the ampere-hour integration method.

[0044] The specific calculation process of the SOC value of the battery at any time is as follows:

[0045] Step 2.1: Obtain the drive signal status values of the dual N-channel MOS transistors M1, M2, M3, and M4 in the current conditioning circuit, and then determine the equivalent matching resistance value R CT ;

[0046] Step 2.2: Obtain the value of the signal v1 at the output end of the operational amplifier OP in the current conditioning circuit, and obtain the value of the signal v B at the output end of the current-to-voltage module according to v B = v1 - 2.5;

[0047] Step 2.3: Calculate the battery current i CT according to the current attenuation coefficient K CT of the current transformer CT and the CT equivalent matching resistance R B = v B / K CT R CT ;

[0048] Step 2.4: Calculate the increment of the SOC at time k using the ampere-hour integration method, i.e., calculate ΔSOC k = i B (k)T value; where: k is the calculation time of the increment, T is the interval time of the increment calculation, and the corresponding time t at time k k = kT;

[0049] Step 2.5: The BMS is based on the SOC k = SOC k-1 + i B (k)T to calculate the SOC value at time k, where: k ≥ 1.

[0050] In summary, the present invention realizes the SOC detection of the battery by combining the open-circuit voltage method and the ampere-hour integration method, and has the advantages of simplicity, practicality and accurate results.

Claims

1. A SOC state estimation system for a BMS, characterized in that: The invention comprises a current signal conditioning circuit, a voltage detection circuit and a SOC estimation module; the input end of the current signal conditioning circuit is connected to the positive electrode of the battery pack; the input end of the voltage detection circuit is connected to the positive and negative electrodes of the battery pack respectively; the voltage detection circuit is used to obtain the open circuit voltage VOC of the battery pack and is connected to the data sampling port of the SOC estimation module; the current signal conditioning circuit is used to detect the current i of the battery pack B , and connected to the data sampling port of the SOC estimation module; The SOC estimation module calculates the initial value SOC0 of the battery pack when it is working based on the pre-stored battery model and the open circuit voltage VOC, and calculates the initial value SOC0 of the battery pack when it is working based on the current i B Calculate the SOC value of the battery at any time using the ampere-hour integration method; The current signal conditioning circuit includes a current-to-voltage module, a DC bias circuit and a CT matching resistance control module; The current-to-voltage module is composed of a current transformer CT, a parallel controllable matching resistor network and a TVS protection circuit, and is used to convert the battery loop current into a proportional voltage signal; the DC bias circuit is composed of an operational amplifier OP and an equivalent resistor network, receives the voltage signal output by the current-to-voltage module, and outputs a positive unipolar voltage after applying a reference bias; the CT matching resistor control module includes a voltage comparator array, a logic gate circuit and a bidirectional shift register group, monitors the voltage amplitude output by the DC bias circuit in real time, and stabilizes the output voltage within the measurement range of the ADC range by dynamically switching the parallel branches of the controllable matching resistor network.

2. The SOC state estimation system for BMS according to claim 1, characterized in that: The current-to-voltage module includes a current transformer CT, a matching resistor R1, a matching resistor R2, a matching resistor R3, a matching resistor R4, a dual N-channel MOS tube M1, a dual N-channel MOS tube M2, a dual N-channel MOS tube M3, a dual N-channel MOS tube M4 and a bidirectional TVS tube D1; the input side of the current transformer CT receives the current i of the battery pack B , one end of the output side of the current transformer CT is respectively connected to one end of the matching resistor R1, one end of the matching resistor R2, one end of the matching resistor R3, one end of the matching resistor R4 and one end of the bidirectional TVS tube D1; the other end of the matching resistor R1 is connected to one end pin of the dual N-channel MOS tube M1, and the other end pin of the dual N-channel MOS tube M1 is grounded; the other end of the matching resistor R2 is connected to one end pin of the dual N-channel MOS tube M2, and the other end pin of the dual N-channel MOS tube M2 is grounded; the other end of the matching resistor R3 is connected to one end pin of the dual N-channel MOS tube M3, and the other end pin of the dual N-channel MOS tube M3 is grounded; the other end of the matching resistor R4 is connected to one end pin of the dual N-channel MOS tube M4, and the other end pin of the dual N-channel MOS tube M4 is grounded; the other end of the bidirectional TVS tube D1 is grounded; the dual N-channel MOS tube M1, the dual N-channel MOS tube M2, the dual N-channel MOS tube M3 and the dual N-channel MOS tube M4 are also connected to the CT matching resistor control module.

3. The SOC state estimation system for BMS according to claim 2, characterized in that: The DC bias circuit includes an operational amplifier OP, four resistors R5, R6, R7 and R8 with the same resistance value; the in-phase input terminal of the operational amplifier OP is respectively connected to one end of the resistor R5 and one end of the resistor R6, the other end of the resistor R5 is connected to the output end of the current-to-voltage module, and the other end of the resistor R6 is connected to a 2.5V reference voltage; the inverting input terminal of the operational amplifier OP is connected to one end of the resistor R7 and one end of the resistor R8, the other end of the resistor R7 is grounded, and the other end of the resistor R8 is connected to the output end of the operational amplifier OP.

4. The SOC state estimation system for BMS according to claim 3, characterized in that: The CT matching resistance control module includes a voltage comparator CP1, a voltage comparator CP2, a voltage comparator CP3, a voltage comparator CP4, an OR gate OR1, an OR gate OR2, an OR gate OR3, an OR gate OR4, an OR gate OR5, an OR gate OR6, a bidirectional shift register U1 and a bidirectional shift register U2; the in-phase input terminal of the voltage comparator CP1, the inverting input terminal of the voltage comparator CP2, the inverting input terminal of the voltage comparator CP3 and the in-phase input terminal of the voltage comparator CP4 are respectively connected to the output terminal of the operational amplifier OP; the inverting input terminal of the voltage comparator CP1 is connected to a 3V reference The output end of the voltage comparator CP1 is respectively connected to an input end of the OR gate OR1 and the S0 pin of the bidirectional shift register U1; the non-inverting input end of the voltage comparator CP2 is connected to the 2.6V reference voltage, and the output end of the voltage comparator CP2 is respectively connected to the other input end of the OR gate OR1 and the S1 pin of the bidirectional shift register U1; the output end of the OR gate OR1 is connected to the CP pin of the bidirectional shift register U1; the non-inverting input end of the voltage comparator CP3 is connected to the 2V reference voltage, and the output end of the voltage comparator CP3 is respectively connected to an input end of the OR gate OR2 and the S1 pin of the bidirectional shift register U1. The inverting input terminal of the voltage comparator CP4 is connected to the S0 pin of the bidirectional shift register U2; the inverting input terminal of the voltage comparator CP4 is connected to the 2.4V reference voltage, and the output terminal of the voltage comparator CP4 is respectively connected to the other input terminal of the OR gate OR2 and the S1 pin of the bidirectional shift register U2; the output terminal of the OR gate OR2 is connected to the CP pin of the bidirectional shift register U2; the two input terminals of the OR gate OR3 are respectively connected to the Q0 pin of the bidirectional shift register U1 and the Q4 pin of the bidirectional shift register U2, and the output terminal of the OR gate OR3 is connected to the signal receiving terminal of the dual N-channel MOS tube M4; the two input terminals of the OR gate OR4 are respectively connected to the Q0 pin of the bidirectional shift register U1 and the Q4 pin of the bidirectional shift register U2 The Q1 pin of the bit register U1 is connected to the Q5 pin of the bidirectional shift register U2, and the output end of the OR gate OR4 is connected to the signal receiving end of the dual N-channel MOS tube M3; the two input ends of the OR gate OR5 are respectively connected to the Q2 pin of the bidirectional shift register U1 and the Q6 pin of the bidirectional shift register U2, and the output end of the OR gate OR5 is connected to the signal receiving end of the dual N-channel MOS tube M2; the two input ends of the OR gate OR6 are respectively connected to the Q3 pin of the bidirectional shift register U1 and the Q7 pin of the bidirectional shift register U2, and the output end of the OR gate OR6 is connected to the signal receiving end of the dual N-channel MOS tube M1.

5. The method for estimating the SOC state in the BMS according to any one of claims 1 to 4, characterized in that: The steps include: Step 1: When the battery starts working, the SOC estimation module obtains the open circuit voltage VOC of the battery pack, and calculates the battery SOC value based on the pre-stored battery model and VOC data, and uses it as the initial value SOC0; Step 2: After the battery starts working, the current signal conditioning circuit realizes a wide range of current i through adaptive resistor switching. B The SOC estimation module then uses the current i B The SOC value of the battery at any time is calculated using the ampere-hour integration method.

6. The estimation method of the SOC state estimation system in the BMS according to claim 5, characterized in that: The specific process of calculating the SOC value of the battery at any time is as follows: Step 2.1, obtain the driving signal state values ​​of the dual N-channel MOS tube M1, the dual N-channel MOS tube M2, the dual N-channel MOS tube M3 and the dual N-channel MOS tube M4 in the current conditioning circuit, and then determine the equivalent matching resistance value R of the current transformer CT in the current-to-voltage module CT ; Step 2.2, obtain the value of the output signal v1 of the operational amplifier OP in the current conditioning circuit, according to v B =v1-2.5 to get the output signal v of the current-to-voltage module B The value of Step 2.3: Based on the current transformer CT current attenuation coefficient K CT And CT equivalent matching resistance R CT , calculate the battery current i B =v B / K CT R CT ; Step 2.4: Use the ampere-hour integration method to calculate the increment of SOC at time k, that is, calculate ΔSOC k =i B (k)T value; where k is the calculation time of the increment, T is the interval time of the increment calculation, and the corresponding time t at the k moment k = kT; Step 2.5, BMS based on SOC k =SOC k-1 +i B (k)T calculates the SOC value at time k, where: k ≥ 1.

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