Test fixture, test system and test method

Abstract

The invention discloses a test fixture, a test system and a test method, and relates to the technical field of server tests.The test fixture comprises a first controller, the first controller stores line sequence relation information, and the first controller is sequentially connected with an output connector, a test accompanying virtual board, a second controller, a to-be-tested virtual board and an input connector; the first controller is connected with the to-be-tested virtual board, so that the to-be-tested virtual board is controlled by the second controller to send a test pulse signal from the preset port, and when the first controller receives the test pulse signal, the conduction port information associated with the test pulse signal is obtained, and the conduction port connection is configured, so that the communication between the preset port and the target port is realized. Therefore, the problems that manual cable detection and wiring adjustment are tedious in work, long in consumed time and very low in efficiency are solved, the wiring sequence of the cables on the board card can be automatically corrected, the states of the cables on the board card can be automatically detected, and the quality inspection efficiency and the detection quality are improved.

Description

Technical Field

[0001] This application relates to the technical field of server testing, and particularly relates to a test fixture, a test system, and a test method. Background Art

[0002] Generally, a test fixture is used to perform relevant functional tests on the assembled server board. In order to implement the tests for different functions in the board, a huge wiring system needs to be configured in the test fixture, and it is necessary to ensure that all cables are correctly configured.

[0003] In some related technologies, when judging whether the cable wiring in the test fixture is correct, usually a quality inspector manually uses two test pens of a multimeter to respectively measure the head and tail ends of the connected cables. Due to the huge test system, often two quality inspectors need to cooperate to complete the test; when an abnormal wiring is found, the worker also needs to manually correct the wiring sequence, which is cumbersome, time-consuming and very inefficient. Moreover, in the case where the PIN pitch in the connector is dense and very small, it is easy to miss or misdetect during manual inspection; there may be inspection blind spots during the manual inspection process, some narrow spaces cannot be inspected in place, and due to different professional qualities of the workers, the quality of the inspected products is uneven. Summary of the Invention

[0004] This application provides a test fixture, a test system, and a test method, which can realize the automatic correction of the cable wiring sequence in the test fixture and the automatic detection of the cable state between the board under test and the accompanying test board, so as to at least solve the problems of missed detection and misdetection caused by manual inspection, and improve the efficiency and detection quality of quality inspection.

[0005] This application provides a test fixture, including: A first controller, one end of the first controller is connected to an input connector, and the other end is connected to an output connector; A second controller, the first controller stores line sequence relationship information, one end of the second controller is connected to a virtual board under test, and the other end is connected to a virtual accompanying test board. The other end of the virtual board under test is connected to the input connector, and the other end of the virtual accompanying test board is connected to the output connector; Query the line sequence relationship information to obtain the target port number of the virtual accompanying test board associated with the preset port of the virtual board under test, and control the preset port to send a test pulse signal according to the target port number through the second controller; The first controller receives the test pulse signal sent by the input connector, and obtains the conduction port information associated with the test pulse signal, and configures the connection of the conduction port to realize the connection between the preset port and the target port.

[0006] Further, an operational amplifier buffer is provided between the input connector and the first controller. The operational amplifier buffer is configured to convert the signal from the input connector and send the converted signal to the first controller.

[0007] Further, a drive buffer and a relay module are further included. The first end of the drive buffer is connected to the first controller, the second end of the drive buffer is connected to the first end of the relay module, the second end of the relay module is connected to the input connector, and the third end of the relay module is connected to the output connector. In response to the first controller confirming that the test pulse signal is a power signal, the first controller controls the relay module to conduct the power signal and transmit the power signal to the virtual board under test.

[0008] Further, the conduction port includes an input end and an output end, and at least one of the input ends is configured to communicate with at least one of the output ends to enable the conduction port to communicate.

[0009] Further, the second controller controls the preset port to send different numbers of the test pulse signals to the first controller, and the number of the test pulse signals is determined according to the target port number.

[0010] Further, the second controller includes a control module and a debugging interface board. The debugging interface board is provided with a signal sending end and a signal receiving end. The signal sending end is connected to the debugging interface of the virtual board under test and is configured to send the test pulse signal generated by the control module. The signal receiving end is connected to the debugging interface of the virtual board for accompanying test and is configured to receive the test pulse signal.

[0011] Further, a plurality of connection interfaces are provided on the debugging interface board, and the number of the connection interfaces is greater than or equal to the number of PINs of the virtual board under test.

[0012] Further, a plurality of receiving PINs and a plurality of indicator lights are provided at the signal receiving end of the debugging interface board, and the receiving PINs and the indicator lights are arranged in one-to-one correspondence.

[0013] Further, the control module controls the sending PIN of the signal sending end to send a diagnostic pulse signal. The signal receiving end receives the diagnostic pulse signal and records the port number of the diagnostic pulse signal. The port number of the diagnostic pulse signal is compared and analyzed with the line sequence relationship information. In response to an abnormality in the port number of the diagnostic pulse signal, the indicator light associated with the abnormal port number is controlled to light up.

[0014] Further, the virtual board to be tested is provided with a PIN for the interface to be tested. The PIN for the interface to be tested is connected to a probe fixing board, and probes are connected to the probe fixing board. The probes are connected to the input connector through connecting wires.

[0015] Further, one end of the output connector away from the first controller is connected to a terminal on the accompanying virtual board through a connecting wire.

[0016] Further, the number of PINs of the conduction port of the first controller is greater than the number of PINs of the virtual board to be tested.

[0017] Further, the accompanying virtual board is provided with a reserved interface, and the reserved interface is set as a universal connector.

[0018] The present application also provides a test system, and the test system includes the test fixture described in any one of the above.

[0019] The present application also provides a test method based on the test fixture described in any one of the above. The method includes: Querying the wire sequence relationship information to obtain the target port number of the accompanying virtual board associated with the preset port of the virtual board to be tested. The second controller controls the preset port to send a test pulse signal according to the target port number; The first controller receives the test pulse signal sent by the input connector, and obtains the conduction port information associated with the test pulse signal, and configures the conduction port to be connected to realize the connection between the preset port and the target port.

[0020] By setting the first controller in the present application to connect the output connector, the accompanying virtual board, the second controller, the virtual board to be tested, and the input connector in sequence, and controlling the virtual board to be tested to send a test pulse signal from the preset port through the second controller. When the first controller receives the information of this pulse test signal and obtains the conduction port information associated with the test pulse signal, it configures the conduction port inside the first controller to be connected to realize the connection between the preset port and the target port, so as to realize the connection between the corresponding ports on the virtual board to be tested and the accompanying virtual board; so as to realize that when the wiring order needs to be corrected, only the second controller needs to control the virtual board to be tested to send corresponding test pulse signals in sequence according to the port numbers of the preset ports. When the first controller receives this test pulse signal, it connects its internal ports according to the information of this test pulse signal to ensure the correct conduction between the ports on the virtual board to be tested and the ports on the accompanying virtual board, so as to automatically correct the wiring order of the cables on the board and automatically detect the cable status on the board, improving the efficiency and detection quality of quality inspection. Description of the Drawings

[0021] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 Schematic diagram of a test fixture provided for an embodiment of the present application; Figure 2 Schematic diagram of the connection architecture between a first controller and a second controller provided for an embodiment of the present application; Figure 3 Schematic diagram of the structure of a virtual board to be tested provided for an embodiment of the present application; Figure 4 Schematic diagram of the internal circuit of the first controller provided for this embodiment; Figure 5 Schematic diagram of the connection between a black box, a virtual board to be tested, and a companion virtual board provided for this embodiment; Figure 6 Schematic diagram of the connection between a second controller, a virtual board to be tested, and a companion virtual board provided for this embodiment; Figure 7 Schematic diagram of the structure of the companion virtual board provided for this embodiment; Figure 8 Schematic diagram of a test fixture in another embodiment provided for this embodiment; Figure 9 Schematic diagram of the test method provided for this embodiment. Detailed implementation manners

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0024] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0025] To enable those skilled in the art of this technology to better understand the solution of this application, the following further detailed description of this application will be given in conjunction with the accompanying drawings and specific embodiments.

[0026] An embodiment of this application provides a test fixture that can correct and detect the cable wire sequence in the test fixture. As Figure 1 and Figure 2 shown, it specifically includes: a first controller, an output connector, a co-test virtual board, a second controller, a virtual board under test, and an input connector. Among them, the first controller is configured as an MCU module, and an MCU chip is configured in the MCU module. The first end of the first controller is connected to the input connector, the second end of the first controller is connected to the output connector, the other end of the input connector is connected to the virtual board under test, and the other end of the output connector is connected to the co-test virtual board; the second controller is configured as an MCU controller, and wire sequence relationship information is stored in the second controller. The first end of the second controller is connected to the virtual board under test, and the other end of the second controller is connected to the co-test virtual board to form a wiring test architecture for the virtual board under test.

[0027] When correcting the wiring order, first, it will be corrected in sequence according to the ports in the wire sequence relationship information. First, confirm the preset port of the virtual board under test, and then query the wire sequence relationship information to obtain the target port number of the co-test virtual board associated with the preset port of the virtual board under test. The second controller controls the preset port to send test pulse signals according to the target port number. Specifically, the second controller controls the preset port to send different numbers of test pulse signals to the first controller. The number of test pulse signals is determined according to the target port number. Exemplarily, if the target port number is "P1-PIN3", then the number of test pulse signals sent is 3, and if the target port number is "P1-PIN6", then the number of test pulse signals sent is 6.

[0028] Furthermore, the first controller receives the test pulse signals sent by the input connector, obtains the conduction port information associated with the test pulse signals according to the number of test pulse signals, and configures the conduction port connection to achieve the connection between the preset port and the target port, that is, to achieve the correct connection of the ports on the virtual board under test and the co-test virtual board.

[0029] It should be noted that the virtual board under test in this embodiment refers to a board with the same shape, size, and position of the interface to be tested as the actual board to be tested. By simplifying the internal circuit of the virtual board under test, the end-to-end connection with the Debug interface is achieved, so as to facilitate the correction of the wire sequence and quality inspection of the board. Specifically, as Figure 3As shown in the figure, the virtual board to be tested in this embodiment includes N interfaces to be tested, which are respectively named 1, 2, 3... N. Each interface to be tested is provided with a number of PINs, and the PINs are respectively numbered from 1 to X. The Debug interface on the virtual board to be tested is provided with X PINs. The internal connection circuit of the virtual board to be tested is configured such that PIN1 of the interface to be tested corresponds to PIN1 of the Debug interface, PIN2 of the interface to be tested corresponds to PIN2 of the Debug interface, and PINX of the interface to be tested corresponds to PINX of the Debug interface.

[0030] Furthermore, the internal link design of the accompanying virtual board is the same as that of the virtual card to be tested. It is a board card with the same shape, size, and the position of the accompanying interface as the real accompanying board card. There are multiple accompanying virtual boards, and each accompanying virtual board contains one or more accompanying interfaces. In this embodiment, multiple accompanying interfaces are integrated on one board card, and the accompanying interface numbers are respectively set as 1~N, and the PIN numbers are 1~X.

[0031] It should be noted that in order to ensure that the wire sequence correction of all interfaces to be tested on the virtual card to be tested can be realized through the cooperation of the first controller and the second controller in this embodiment, the number of PINs of the conduction port of the first controller is set to be greater than the number of PINs of the virtual board to be tested, based on the maximum number of ports supported by the MCU in the first controller, and the MCU model is not limited either.

[0032] In this embodiment, the test fixture further includes an operational amplifier buffer connected between the first controller and the input connector. The operational amplifier buffer is used to convert the signal of the input connector and send the converted signal to the first controller. Specifically, the operational amplifier buffer inputs through the operational amplifier high impedance state, converts the input connector signal into a standard voltage logic state, and sends it to the first controller for detection to avoid directly inputting high voltage to damage the first controller. At the same time, the operational amplifier buffer realizes the anti-fooling function and avoids the risk of burning the board or damaging the link device in the traditional mode, that is, it not only protects the MCU chip in the first controller, but also isolates the input end and the output end, blocking the abnormal circuit and high voltage outside the operational amplifier. Even if there is a wiring error in the test fixture, the real board to be tested can be directly powered on without being burned.

[0033] It should be noted that in this embodiment, the test pulse signal is a pulse signal with a pulse greater than 0. When the test pulse signal is a 0 pulse, the test pulse signal is a power signal, and at this time, the power signal needs to be configured for correct connection. Specifically, the test fixture further includes a drive buffer and a relay module. The first end of the drive buffer is connected to the first controller, the second end of the drive buffer is connected to the first end of the relay module, the second end of the relay module is connected to the input connector, and the third end of the relay module is connected to the output connector.

[0034] Among them, the drive buffer is used to provide the current and voltage for driving the relay module to work, so that the MCU signal from the first controller can drive the relay to work. The relay module is used to control the drive buffer to drive the relay module to work after the first controller detects the power signal, and transmit the input power signal to the output connector. The power signal includes VCC signal, GND signal, etc. That is, in response to the first controller confirming that the test pulse signal is a power signal, the first controller controls the relay module to conduct the power signal and transmit the power signal to the virtual board under test through the output connector to achieve the configuration and connection of the power signal.

[0035] Exemplarily, such as Figure 4 As shown, configure PIN1 at P2 as the VCC signal, PIN2 at P2 as the GND signal, and PIN3 at P2 as the pulse signal; when the second controller controls the virtual board under test to send the VCC signal at P2 to the first controller, at this time, the MCU module in the first controller recognizes the VCC signal and controls the corresponding conduction of the conduction ports in the relay module, and then transmits the VCC signal to the virtual board under test through the output connector.

[0036] In a specific embodiment, it is set that the conduction ports in the first controller include several input ends and several output ends, and the several input ends and several output ends are numbered respectively. Each input end is set to have a first number, and each output end is set to have a second number. The input ends are 1 to M, and the output ends are set to 1 to N. At least one input end and at least one output end are configured to be connected to form a conduction path, and the conduction path is set to have a third number, and a correspondence table of the input end, output end and conduction path is constructed; it is set that the conduction path number corresponds one-to-one to the number of test pulse signals. Before the wire sequence correction, the above input ends and output ends are in a non-connected state. When the first controller receives the test pulse signal, the conduction path number associated with it is queried according to the number of test pulse signals, and the correspondence table is queried in combination with the third number of the conduction path to obtain the corresponding numbers of the input end and output end that can achieve the connection of the conduction path, and the PINs of the input end and output end with the corresponding numbers are configured to be connected, so as to achieve the connection of the conduction ports.

[0037] Exemplarily, such as Figure 4As shown, by querying the corresponding relationship of the wire sequence, it can be confirmed that PIN3 on the virtual board to be tested should be connected to PIN6 on the virtual board to be accompanied for testing. When the first controller receives the test pulse signal sent by the second controller, it identifies the conduction path number of the test pulse signal pipeline, thereby confirming which port of the input connector the test pulse signal points to, and determining the input end and output end that should be connected. Exemplarily, the MCU inside should control the input end PIN8 to be connected to the output end PIN18, that is, after the MCU module of the first controller receives the pulse signal, it controls the internal link of the chip to connect the input end PIN8 and the output end PIN18, thereby completing the wire sequence correction work. By using the test fixture with the corrected wire sequence for the server board test, the accuracy of the server board test is ensured.

[0038] In a specific embodiment, in order to make the test fixture more conveniently connected to the board to be tested in the actual use scenario, the first controller, operational amplifier buffer, input connector, relay module, drive buffer, and output connector are connected in sequence according to the Figure 1 and Figure 5 shown connection relationship, and the connected architecture is configured as a whole, that is, set as a black box. By setting that there are P1 interface and P2 interface outside the black box, where the P1 interface is used to connect the connection line of the virtual board to be accompanied for testing, and the virtual board to be accompanied for testing includes but is not limited to the hard disk backplane, and the P2 interface is used to connect the connection line of the virtual board to be tested, so as to realize the connection and assembly of the test fixture.

[0039] Through the above settings, the second controller is enabled to control the preset port of the virtual board to be tested to send different numbers of test pulse signals to the first controller. The number of test pulse signals is determined according to the port number of the preset port. Specifically, the wire sequence relationship information is queried according to the port number of the preset port to obtain the preset number of times of the test pulse signal. When performing wire sequence correction, different preset numbers of test pulse signals are sent to the first controller in sequence according to the order of the interfaces to be tested on the virtual board to be tested in the wire sequence relationship information, so as to realize the correction of all wire sequences. After the virtual board to be tested and the virtual board to be accompanied for testing are correspondingly wired according to the above wiring test architecture, the wiring of the interfaces on the virtual board to be tested can be automatically corrected in sequence by sending test pulse signals, greatly improving the correction efficiency of the wiring and avoiding the situation of wiring confusion caused by manual operation.

[0040] In order to realize the further diagnosis of the corrected wiring to ensure that all the lines in the entire wiring system are correctly connected, it is set that the second controller includes a control module and a debugging interface board. The debugging interface board is provided with a signal sending end and a signal receiving end; the signal sending end is connected to the debugging interface of the virtual board to be tested and is used to send the test pulse signal generated by the control module, and the signal receiving end is connected to the debugging interface of the virtual board to be accompanied for testing and is used to receive the test pulse signal.

[0041] It should be noted that the control module uses an MCU as the main control chip, and the control module is used to generate, send, and receive pulse signals. The debugging interface board is used as a connection unit, and a number of connection interfaces are provided on the debugging interface board, where the number of connection interfaces is greater than or equal to the number of PINs of the virtual board to be tested. By arranging multiple connection interfaces on the debugging interface board, the conductivity test of the interfaces on the virtual board to be tested can be realized.

[0042] Furthermore, as Figure 6 shown, a number of receiving PINs and a number of indicator lights are provided at the signal receiving end of the debugging interface board. The receiving PINs and the indicator lights are arranged in one-to-one correspondence, and the indicator lights are controlled by the control module to be lit. The second controller further includes a communication module, and the communication module is used for remote connection with an external server to upload the quality inspection diagnosis results to the external server.

[0043] In the virtual board to be tested in this embodiment, a to-be-tested interface is provided. The to-be-tested interface is connected to a probe fixing plate, and a probe is connected to the probe fixing plate. The probe is connected to an input connector through a connecting wire. One end of the output connector far from the first controller is connected to a wiring terminal on the accompanying virtual board through a connecting wire.

[0044] As Figure 1 shown, when performing wire sequence correction and diagnosis on the board to be tested in the test fixture, only the virtual board to be tested corresponding to the board to be tested needs to be obtained, and the virtual board to be tested is configured to be connected to the connection interface on the debugging interface board, the signal sending end in the first controller, the signal receiving end in the first controller, the connection interface of the accompanying virtual board, the wiring terminal, the original cable of the whole machine, and the second controller in sequence, and the above connection architecture is configured to form a diagnosis platform, where the diagnosis platform has an external signal sending end and signal receiving end to facilitate the assembly and connection of the test fixture. Then, one end of the input connector in the second controller is connected to the probe, the probe fixing plate, and the virtual board to be tested in sequence, so as to form a complete test system. The test fixture is adjusted to the working state, that is, the lid is closed to complete the docking of the upper and lower molds, that is, the PIN feet of the to-be-tested interface on the virtual board to be tested are connected to the probe. After the physical environment connection is completed.

[0045] In a specific embodiment, the diagnostic test process is started: the control module controls the sending PIN of the signal sending end to send a diagnostic pulse signal, the signal receiving end receives the diagnostic pulse signal, and records the port number of the diagnostic pulse signal; the port number of the diagnostic pulse signal is compared and analyzed with the wire sequence relationship information, and in response to the port number of the diagnostic pulse signal being abnormal, the indicator light of the port associated with the abnormal port number is controlled to be lit.

[0046] Exemplarily, as Figure 4As shown, the line sequence correction process is started. The line sequence correspondence information is stored in the MCU module of the first controller. The MCU controls the 1-X1 PINs of the virtual board of the board under test to send different numbers of pulse signals respectively. The number of pulses depends on the target port number that the current PIN needs to be connected to on the accompanying test board. For example, if the target port number is PIN3, then 3 pulses are sent, and so on. All PIN line sequence correction work is completed for each PIN one by one. Then, the line conductivity diagnosis test is started. The first controller controls the interface to send pulse signals in sequence through the signal sending end according to the port sequence in the line sequence relationship information. When the signal receiving end receives this pulse signal, it indicates that the line of the preset port is conductive. If this pulse signal is not received, it indicates that the line of the preset port is not conductive. All ports on the virtual board under test are tested according to the above process, and the diagnosis test results are recorded and output. Combining the abnormal port information in the diagnosis test results, the indicator light corresponding to the abnormal port is controlled to light up.

[0047] In a specific embodiment, in order to ensure that the accompanying test virtual board can be applicable to the test process of the boards under test in various scenarios, such as Figure 7 As shown, several reserved interfaces are set on the accompanying test virtual board. The reserved interfaces are set as universal connectors. Exemplarily, the reserved interfaces adopt universal PHB connectors. When other connectors need to be installed, it only needs to add an adapter board to achieve, saving costs.

[0048] Through the solution in this embodiment, the wiring method is optimized. There is no need to wire one by one according to the line sequence correspondence relationship. Only by using the solution in this embodiment to automatically correct the connected line can the connection between the corresponding ports on the board under test and the accompanying test board be achieved, improving the wiring efficiency. At the same time, with an automatic diagnosis test process, it can automatically diagnose and test the connected wiring architecture, avoiding the problems of missed inspection and misjudgment caused by human factors. At the same time, it is not limited by the fixture size, blind area, etc. The system tests each port one by one, efficiently and accurately, improving the quality of the delivered products, reducing the problems of long time-consuming and cumbersome manual quality inspection, and improving the efficiency and detection quality of quality inspection.

[0049] Corresponding to the above embodiment, a test fixture is provided in this embodiment. The difference between this embodiment and the above embodiment is that the first controller is not set in this embodiment. By setting the first controller as an adapter card and keeping other components unchanged, that is, through as Figure 8The test fixture shown is used to perform diagnostic tests on the virtual board under test. Specifically, it includes the virtual board under test, and configures the virtual board under test to be connected in sequence to the connection interface on the interface board, the signal sending end in the first controller, the signal receiving end in the first controller, the connection interface of the accompanying virtual board, the terminal block, the original cable of the whole machine, and the adapter card. One end of the adapter card is connected to the probe through a cable, and the other end is connected to the terminal block on the accompanying virtual board through the original cable of the whole machine. Through the above test architecture, the first controller can control the interface to send pulse signals in sequence according to the port sequence in the line sequence relationship information through the signal sending end. When the signal receiving end receives this pulse signal, it indicates that the line of the preset port is conducting. If this pulse signal is not received, it indicates that the line of the preset port is not conducting, thereby realizing the conductivity test of the connection line between the virtual board under test and the accompanying virtual board.

[0050] Corresponding to the above embodiment, this embodiment provides a test system, and the test system includes the test fixture of any one of the above.

[0051] In a specific embodiment, the test fixture includes: A first controller, one end of the first controller is connected to the input connector, and the other end is connected to the output connector; A second controller, the line sequence relationship information is stored in the first controller, one end of the second controller is connected to the virtual board under test, the other end is connected to the accompanying virtual board, the other end of the virtual board under test is connected to the input connector, and the other end of the accompanying virtual board is connected to the output connector; Query the line sequence relationship information to obtain the target port number of the accompanying virtual board associated with the preset port of the virtual board under test, and control the preset port to send a test pulse signal according to the target port number through the second controller; The first controller receives the test pulse signal sent by the input connector, and obtains the conduction port information associated with the test pulse signal, and configures the conduction port connection to realize the connection between the preset port and the target port.

[0052] In a specific embodiment, an operational amplifier buffer is provided between the input connector and the first controller, and the operational amplifier buffer is used to convert the signal from the input connector and send the converted signal to the first controller.

[0053] In a specific embodiment, it further includes a drive buffer and a relay module. The first end of the drive buffer is connected to the first controller, the second end of the drive buffer is connected to the first end of the relay module, the second end of the relay module is connected to the input connector, and the third end of the relay module is connected to the output connector; in response to the first controller confirming that the test pulse signal is a power signal, the first controller controls the relay module to conduct the power signal and transmit the power signal to the accompanying virtual board.

[0054] In a specific embodiment, the conduction port includes an input end and an output end, and at least one input end is configured to communicate with at least one output end so that the conduction port is communicated.

[0055] In a specific embodiment, the second controller controls the preset port to send different numbers of test pulse signals to the first controller, and the number of test pulse signals is determined according to the target port number.

[0056] In a specific embodiment, the second controller includes a control module and a debugging interface board. The debugging interface board is provided with a signal sending end and a signal receiving end; the signal sending end is connected to the debugging interface of the virtual board to be tested and is used to send the test pulse signal generated by the control module, and the signal receiving end is connected to the debugging interface of the accompanying virtual board and is used to receive the test pulse signal.

[0057] In a specific embodiment, a plurality of connection interfaces are provided on the debugging interface board, and the number of connection interfaces is greater than or equal to the number of PINs of the virtual board to be tested.

[0058] In a specific embodiment, a plurality of receiving PINs and a plurality of indicator lights are provided at the signal receiving end of the debugging interface board, and the receiving PINs and the indicator lights are arranged in one-to-one correspondence.

[0059] In a specific embodiment, the control module controls the sending PIN of the signal sending end to send a diagnostic pulse signal, the signal receiving end receives the diagnostic pulse signal, and records the port number of the diagnostic pulse signal; the port number of the diagnostic pulse signal is compared and analyzed with the line sequence relationship information, and in response to the abnormality of the port number of the diagnostic pulse signal, the indicator light of the port associated with the abnormal port number is controlled to light up.

[0060] In a specific embodiment, the virtual board to be tested is provided with a PIN to be tested, the PIN to be tested is connected to a probe fixing plate, a probe is connected to the probe fixing plate, and the probe is connected to an input connector through a connecting wire.

[0061] In a specific embodiment, one end of the output connector far from the first controller is connected to a wiring terminal on the accompanying virtual board through a connecting wire.

[0062] In a specific embodiment, the number of PINs in the driving circuit of the first controller is greater than the number of PINs of the virtual board to be tested.

[0063] In a specific embodiment, the accompanying virtual board is provided with a reserved interface, and the reserved interface is set as a universal connector.

[0064] Corresponding to the above embodiments, this embodiment provides a test method based on the above test fixture, as Figure 9 shown, the method includes: Step 101: Query the line sequence relationship information to obtain the target port number of the associated virtual board to be tested for the preset port of the virtual board to be tested. The second controller controls the preset port to send a test pulse signal according to the target port number; Step 102: The first controller receives the test pulse signal sent by the input connector, obtains the conduction port information associated with the test pulse signal, and configures the conduction port to be connected to realize the connection between the preset port and the target port.

[0065] In a specific embodiment, the control module in the second controller controls the sending PIN of the signal sending end to send a diagnostic pulse signal. The signal receiving end receives the diagnostic pulse signal and records the port number of the diagnostic pulse signal; compares and analyzes the port number of the diagnostic pulse signal with the line sequence relationship information. In response to the port number of the diagnostic pulse signal being abnormal, controls the indicator light of the port associated with the abnormal port number to light up.

[0066] For the description of the features in the embodiments corresponding to the test method, reference can be made to the relevant descriptions of the embodiments corresponding to the test fixture, which will not be elaborated here one by one.

[0067] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0068] The embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored, and the computer program is set to execute the steps in any of the above test method embodiments when running.

[0069] In an exemplary embodiment, the above computer-readable storage medium may include but is not limited to: USB flash drive, read-only memory (ROM for short), random access memory (RAM for short), mobile hard disk, magnetic disk or optical disc and other various media that can store computer programs.

[0070] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0071] The above has introduced in detail a test fixture, a test system and a test method provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art of this technology, without departing from the principle of the present application, several improvements and modifications can still be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A test fixture, characterized in that, Including: A first controller, one end of the first controller is connected to an input connector, and the other end is connected to an output connector; A second controller, the first controller stores line sequence relationship information, one end of the second controller is connected to a virtual board under test, the other end is connected to a companion virtual board, the other end of the virtual board under test is connected to the input connector, and the other end of the companion virtual board is connected to the output connector; Query the line sequence relationship information to obtain the target port number of the companion virtual board associated with the preset port of the virtual board under test, and control the preset port to send a test pulse signal according to the target port number through the second controller; The first controller receives the test pulse signal sent by the input connector, and obtains the conduction port information associated with the test pulse signal, and configures the connection of the conduction port to realize the connection between the preset port and the target port.

2. The test fixture according to claim 1, wherein An operational amplifier buffer is provided between the input connector and the first controller, and the operational amplifier buffer is used to convert the signal from the input connector and send the converted signal to the first controller.

3. The test fixture according to claim 1 or 2, characterized in that, It further includes a drive buffer and a relay module. The first end of the drive buffer is connected to the first controller, the second end of the drive buffer is connected to the first end of the relay module, the second end of the relay module is connected to the input connector, and the third end of the relay module is connected to the output connector; In response to the first controller confirming that the test pulse signal is a power signal, the first controller controls the relay module to conduct the power signal and transmit the power signal to the companion virtual board.

4. The test fixture according to claim 3, wherein The conduction port includes an input end and an output end, and at least one of the input ends and at least one of the output ends are configured to be connected to make the conduction port connected.

5. The test fixture according to claim 1 or 2, characterized in that, The second controller controls the preset port to send different numbers of the test pulse signals to the first controller, and the number of the test pulse signals is determined according to the target port number.

6. The test fixture according to claim 1 or 2, characterized in that The second controller includes a control module and a debugging interface board, and the debugging interface board is provided with a signal sending end and a signal receiving end; The signal sending end is connected to the debugging interface of the virtual board under test and is used to send the test pulse signal generated by the control module, and the signal receiving end is connected to the debugging interface of the companion virtual board and is used to receive the test pulse signal.

7. The test fixture according to claim 6, characterized in that, A plurality of connection interfaces are provided on the debugging interface board, and the number of the connection interfaces is greater than or equal to the number of PINs of the virtual board under test.

8. The test fixture according to claim 6, wherein A plurality of receiving PINs and a plurality of indicator lights are provided at the signal receiving end of the debugging interface board, and the receiving PINs and the indicator lights are arranged in one-to-one correspondence.

9. The test fixture according to claim 8, wherein The control module controls the sending PIN of the signal sending end to send a diagnostic pulse signal, the signal receiving end receives the diagnostic pulse signal, and records the port number of the diagnostic pulse signal; Compare and analyze the port number of the diagnostic pulse signal with the line sequence relationship information, and in response to an abnormality in the port number of the diagnostic pulse signal, control the indicator light of the port associated with the abnormal port number to light up.

10. The test fixture according to claim 1 or 2, characterized in that, The virtual board under test is provided with a test interface, the test interface is connected to a probe fixing plate, probes are connected to the probe fixing plate, and the probes are connected to the input connector through connection lines.

11. The test fixture according to claim 10, characterized in that, One end of the output connector far from the first controller is connected to a wiring terminal on the accompanying virtual board through a connection line.

12. The test fixture according to claim 1 or 2, characterized in that, The number of PINs of the conduction port of the first controller is greater than the number of PINs of the virtual board under test.

13. The test fixture according to claim 1 or 2, characterized in that, The accompanying virtual board is provided with a reserved interface, and the reserved interface is set as a universal connector.

14. A test system, characterized in that, The test system includes the test fixture according to any one of claims 1 to 13.

15. A test method for the test fixture according to any one of claims 1 to 13, characterized in that, The method includes: Query the line sequence relationship information according to the port number of the preset port to obtain the preset number of times of the test pulse signal, and the second controller controls the preset port of the virtual board under test to send the test pulse signal of the preset number of times; The first controller receives the test pulse signal sent by the input connector, queries the line sequence relationship information according to the test pulse signal information to obtain the target port number associated with the test pulse signal information, and controls the drive circuit in the first controller to connect to the target port according to the target port number.

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