Data storage device selection

Abstract

One system may include a variety of storage devices, such as pseudo-static random access memory and static random access memory. Techniques for data exchange may include receiving a write request to store data to storage devices, selecting a storage device from one or more storage devices. The data may be stored in the selected device. The method may include receiving a read request and returning data from an appropriate storage device. In some examples, the system may determine data storage locations based on factors such as data size, data type, or address proximity, and may optimize memory usage, balance speed, capacity, or power consumption efficiency. The systems and techniques described herein are particularly beneficial for resource-limited devices, such as systems on chip.

Description

Technical Field

[0001] The systems and techniques described herein relate to computing systems, and more particularly, to systems on a chip (SoC). Background Art

[0002] A system on a chip (SoC) can be used in Internet of Things (IoT) devices. The system on a chip can include a processor, a memory, and input / output components.

[0003] IoT devices can be interconnected or communicate with a server. Examples of IoT devices can be sensors that monitor environmental conditions, smart home controllers, or wearable devices. IoT devices can be implemented using a system on a chip that is configured to perform various tasks such as data collection, processing, or communication. The system on a chip generally maintains low power consumption and a small physical footprint. Summary of the Invention

[0004] The systems and techniques described herein relate to a computing system that includes: one or more processors; a controller; and one or more storage devices including: a first storage device that includes static random access memory (SRAM); a second storage device that includes pseudo-static random access memory (PSRAM) coupled to the controller, where the performance metrics of the SRAM are higher than those of the PSRAM, while the capacity of the SRAM is less than that of the PSRAM; and a cache memory coupled to the controller, where the one or more storage devices store instructions that, when executed by the one or more processors, configure the computing system to perform: receiving, by the one or more processors, a write request to store data at a storage address; selecting, by the one or more processors, a storage device from the one or more storage devices based on the storage address to store the data; and storing the data in the selected storage device. Brief Description of the Drawings

[0005] To facilitate easy identification of the discussion of any particular element or action, the leftmost digit in the reference numeral corresponds to the figure number in which that element is first introduced.

[0006] According to some examples, Figure 1 is a schematic diagram of a computing system in which instructions can be executed to cause the computing system to perform any one or more of the methods discussed herein.

[0007] According to some examples, Figure 2 is a flowchart showing a method of writing data.

[0008] According to some examples, Figure 3 is a flowchart showing a method of reading data.

[0009] According to some examples, Figure 4 is a schematic diagram of additional components of a computing system. Detailed Implementation Modes

[0010] The systems and techniques described herein can solve several technical problems related to data exchange in computing systems, especially those with limited resources. One such problem may be the performance and capacity trade-off between different types of memories. Static random access memory (SRAM) can offer excellent performance but limited capacity, while pseudo-static random access memory (PSRAM) can offer larger capacity but slower performance. To address this technical problem, a computing system can implement a hybrid setup that includes both SRAM and PSRAM, thereby efficiently utilizing both memory types based on specific data characteristics or access patterns.

[0011] Another problem may be optimizing data storage and retrieval in systems with limited resources, such as Internet of Things (IoT) devices or systems-on-chip (SoCs). The technical solutions described herein may involve selecting storage devices based on factors such as data size, type, and storage address.

[0012] For example, smaller, frequently accessed data can be stored in faster SRAM or cache memory, while larger data sets can be directed to PSRAM.

[0013] In some examples, due to the inherent differences in performance characteristics between SRAM and PSRAM, directly combining them may not be the optimal solution. PSRAM may incur significant overhead costs during data exchange, which can degrade overall system performance. These overhead costs may include additional time required for read / write operations.

[0014] To address this technical challenge, the system can implement a controller with a cache memory or buffer as an intermediary for the PSRAM, enabling the entire system to more effectively manage data storage or retrieval operations. By leveraging the cache memory or buffer in the controller, the system can reduce the impact of the higher overhead costs on overall performance. The systems and techniques described herein can enable a computing system to utilize the advantages of PSRAM while minimizing the performance bottlenecks associated with directly accessing PSRAM. The controller can optimize data exchange and reduce overhead costs, potentially improving the overall performance and energy efficiency of computing systems such as IoT devices or SoCs.

[0015] According to some examples, Figure 1 is a block diagram showing the components that may exist in computing system 100. These components can enable computing system 100 to operate according to the techniques discussed herein. As understood, Figure 1 each functional block shown in may include hardware elements (including dedicated or general-purpose circuits), software elements (including computer code stored on a machine-readable medium), or a combination of hardware and software elements. It should also be noted thatFigure 1 This is merely an example of a specific implementation and is only used to illustrate the types of components that may exist in computing system 100.

[0016] Computing system 100 may include a processor 102 and a memory 114, which may be configured to communicate via a main bus 112. In some examples, processor 102 (e.g., a central processing unit (CPU), a reduced instruction set computing processor, a complex instruction set computing processor, a graphics processing unit (GPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a radio frequency integrated circuit (RFIC), other processors, or any suitable combination thereof) may include processors 104 and 106 that execute instructions 108 and 110, respectively. The term "processor" is intended to include a multi-core processor that may include two or more independent processors (sometimes referred to as "cores") that can execute instructions simultaneously. Although Figure 1 multiple processors 102 are shown, computing system 100 may include a single processor with a single core, a single processor with multiple cores (e.g., a multi-core processor), multiple processors with a single core, multiple processors with multiple cores, or any combination thereof.

[0017] Main bus 112 may include a data bus (dbus) 132 or a control bus (cbus) 134. Data bus 132 may be configured to transfer data between components of computing system 100. Control bus 134 may be configured to transfer control signals between different components of computing system 100.

[0018] Memory 114 may include a controller 116, a first storage device 128, and a second storage device 130. Processor 102 may access first storage device 128 via main bus 112 or data bus 132. Controller 116 may be communicatively coupled to processor 102 via main bus 112. In some examples, controller 116 is coupled to main bus 112 via data bus 132 and / or control bus 134. In some examples, processor 102 may access second storage device 130 via controller 116. Memory 114 may include a non-transitory computer-readable storage medium that stores instructions that cause the computing system to perform any one or more of the methods discussed herein.

[0019] Controller 116 may store instructions 118 that embody any one or more of the methods or functions described herein. During execution of computing system 100, instructions 118 may also reside, in whole or in part, within first storage device 128, within second storage device 130, within processor 102, or any suitable combination thereof.

[0020] The controller 116 may include a bus input / output component 120, registers 122, a cache memory 124, or a buffer 126. In some examples, the controller 116 determines the location for storing, retrieving, or transferring data among the cache memory 124, the buffer 126, and the second storage device 130. In some examples, the controller 116 manages the communication interface between the processor 102 and the second storage device 130. In some examples, the controller 116 coordinates with the bus input / output component 120 to regulate the timing or sequence of data exchange.

[0021] In some examples, the controller 116 may be coupled to the main bus 112 via both a data bus 132 and a control bus 134. The exchange of control signals may be carried out via the control bus 134, and other data exchanges may be carried out via the data bus 132 or the control bus 134.

[0022] The bus input / output component 120 may provide a path for data to be transferred among components. In some examples, the bus input / output component 120 processes the input or output of data. The input of data may be referred to as writing (e.g., storing, saving) data into the memory 114. The output of data may be referred to as reading (e.g., fetching, accessing, retrieving, obtaining, extracting) data from the memory 114. The input or output of data may also be referred to as data exchange or data transfer. In some examples, the bus input / output component 120 manages the data exchange between the main bus 112 and the memory 114. The bus input / output component 120 may interpret or execute read requests or write requests from the processor 102 and coordinate the data transfer among the cache memory 124, the buffer 126, the first storage device 128, or the second storage device 130. The bus input / output component 120 may be configured to implement different protocols for different data exchange modes. For example, the bus input / output component 120 implements a burst mode for accessing or storing sequential data or a batch of data containing multiple data items. Sequential data may be data associated with substantially adjacent storage addresses. For example, the storage addresses 0x1000, 0x1001, 0x1002 are substantially adjacent storage addresses because these storage addresses are adjacent to each other in a continuous manner. In some examples, substantially adjacent storage addresses do not need to be continuous. Instead, substantially adjacent storage addresses may be separated by a predetermined number of storage addresses. For example, the storage addresses 0x1000 and 0x1004 are substantially adjacent, separated only by a predetermined number of storage addresses (e.g., 4). In some examples, substantially adjacent storage addresses may include multiple storage addresses falling within a predetermined range. In another example, the bus input / output component 120 implements a single transfer mode for accessing or storing data at random memory locations.

[0023] In some examples, the storage address provided in the write request is converted, decoded, or translated by the bus input / output component 120 into an address format used by the selected storage device so that the storage address can be correctly interpreted or data can be stored in the correct memory location.

[0024] Register 122 can serve as a small, fast storage location for saving or managing data or control information related to the operations performed by the controller 116. Register 122 can store control signals or configuration settings that indicate how to control various storage devices, such as memory timing, refresh rate, and different data exchange modes. Register 122 can save the storage address, enabling the controller 116 to determine the location from which to read data from or write data to the memory 114. In some examples, the register 122 in the controller 116 temporarily saves the data transferred between the memory 114 and the processor 102 or other system components, ensuring an efficient data flow. In some examples, register 122 stores the status of the data exchange, providing feedback on whether the data exchange has been successfully completed or an error has occurred. In some examples, register 122 can contain commands for causing one or more storage devices to perform operations such as reading, writing, or refreshing.

[0025] In some examples, register 122 includes configuration registers that contain preconfigured command codes enabling the controller 116 to communicate with the second storage device 130. The configuration registers can store parameters of the second storage device 130, such as timing configuration, refresh rate, or access mode. The configuration registers can include settings for cache policies, buffer management, or address mapping schemes. In some examples, the controller 116 uses the configuration registers containing different preconfigured command codes to communicate with second storage devices 130 manufactured by different manufacturers.

[0026] Cache memory 124 can be configured to store data or instructions for quick retrieval. In some examples, cache memory 124 stores data or instructions with a size less than or equal to a first predetermined size threshold. Cache memory 124 can implement various cache algorithms, such as write-through, write-back, or write-around strategies. In some examples, cache memory 124 supports prefetching to preload data that may be accessed soon. In some examples, cache memory 124 supports functions such as cache coherence protocols to ensure data consistency among multiple processors (e.g., processor 104 and processor 106). Cache memory 124 can be implemented as a partition of the first storage device 128. Cache memory 124 can be a static random access memory different from the first storage device 128.

[0027] Buffer 126 can be configured to store data transmitted between different components of computing system 100. In some examples, buffer 126 can temporarily hold data during data transmission. In some examples, buffer 126 can be used in burst mode. For example, burst mode is used when transmitting batches of data such as image data. For example, burst mode is used when the data corresponds to multiple addresses and these multiple addresses contain more than a predetermined quantity threshold of storage addresses. Buffer 126 can implement a circular buffer algorithm, which can allow for a continuous data stream without constantly reallocating space. Buffer 126 can assist in data rate matching between components with different processing speeds. For example, buffer 126 temporarily stores data from processor 102 before the data can be written to one or more storage devices. In some examples, buffer 126 can be used to assemble or disassemble data packets for more efficient data exchange with second storage device 130. In some examples, buffer 126 works with cache memory 124 or bus input / output component 120 to optimize data movement within memory 114. Buffer 126 can help reduce data transmission latency and may contribute to more efficient use of the main bus 112 bandwidth.

[0028] First storage device 128 can be a storage area for frequently accessed data or instructions within computing system 100. First storage device 128 can include static random access memory. First storage device 128 can be coupled to processor 102 via main bus 112 or data bus 132. In other words, processor 102 can directly exchange data with first storage device 128. In some examples, when computing system 100 is implemented as a system-on-chip, first storage device 128 is integrated into computing system 100. For example, first storage device 128 is directly built on the same semiconductor die or chip as processor 102. In some examples, first storage device 128 provides fast access to stored information such as data. In some examples, first storage device 128 can support simultaneous read and write operations, potentially improving overall performance. In some examples, first storage device 128 can be organized into multiple partitions, allowing parallel access to multiple partitions. For example, one or more of the multiple partitions are used as cache memory 124 or buffer 126 for controller 116. First storage device 128 can implement an error longitudinal redundancy check code (ECC) function to maintain data integrity. In some examples, the error longitudinal redundancy check code function detects or corrects certain types of data errors, improving the reliability of stored information.

[0029] The second storage device 130 can provide storage space for the computing system 100. The second storage device 130 can include pseudo-static random access memory (PSRAM). In some examples, the second storage device 130 has a larger capacity (e.g., storage space, storage size) than the first storage device 128; however, the first storage device 128 has higher (e.g., better) performance in terms of performance metrics. For example, the performance metrics include read or write speed. For example, the read and write speeds of the first storage device 128 are better than those of the second storage device 130. Another example is that the performance metrics include latency or bandwidth. In some examples, the second storage device 130 is coupled to the computing system 100 through an external connection method. The second storage device 130 including pseudo-static random access memory can be externally coupled to the computing system 100 through a four-wire serial peripheral interface. In some examples, the second storage device 130 is directly integrated into the computing system 100 by sharing the same circuit or being embedded in the same semiconductor die or chip as the processor 102.

[0030] The second storage device 130 can support different modes to improve performance in different scenarios. In some examples, the second storage device 130 can also support a burst mode of data transfer, allowing batches of data to be transferred in a single operation. To reduce power consumption, especially during inactive periods, the second storage device 130 can implement energy-saving features. In some examples, the energy-saving features include partial array refresh, where only the part of the second storage device 130 containing data is refreshed, thus saving energy. In some examples, the second storage device 130 utilizes a temperature-compensated self-refresh mechanism to adjust the refresh rate based on the ambient temperature to optimize power usage while maintaining data integrity. The second storage device 130 can work in cooperation with one or more storage devices (such as the first storage device 128) to leverage the advantages of each storage device, potentially improving the overall system performance or energy efficiency.

[0031] By using a hybrid setup including the first storage device 128 and the second storage device 130, the computing system 100 can use the first storage device 128 to provide fast access to frequently used or critical data or instructions, and use the second storage device 130 to provide sufficient storage space for other types of data. In some examples, the cost per bit of storage space of static random access memory may be higher than that of pseudo-static random access memory. Therefore, the hybrid setup can reduce the overall manufacturing cost of the computing system 100. In summary, the hybrid setup can enable the computing system 100 to achieve a balance among speed, storage capacity (e.g., storage space), power efficiency, and cost-effectiveness.

[0032] According to some examples, Figure 2 is a flowchart showing a data exchange method in a computing system.

[0033] In block 202, the processor 102 may receive (e.g., execute) a write request to store data at a storage address. The write request may include the storage address where the data needs to be written.

[0034] In block 204, the processor 102 may select a storage device from one or more storage devices to store the data. The one or more storage devices may include a first storage device 128 and a second storage device 130. In some examples, the selection may be based on the storage address provided in the write request. For example, data including storage addresses in the range from a first address to a second address is configured to be written to the first storage device 128; data including storage addresses in the range from a third address to a fourth address is configured to be written to the second storage device 130.

[0035] In some examples, the selection is based on a set of rules. The set of rules determines the selection of the storage device based on data size, data type, and other factors. The set of rules may optimize data storage according to the characteristics of one or more storage devices (such as access speed, latency, power consumption, and storage capacity). In some examples, the processor 102 selects the first storage device 128 to store the data based on the data exceeding a second predetermined size threshold. In some examples, the processor 102 selects the second storage device 130 based on the data exceeding a second predetermined size threshold. In some examples, the processor 102 selects the storage device based on access frequency. For example, counter data configured to calculate the number of occurrences of a specific event may need to be accessed frequently. The storage address associated with the counter data falls within the address range associated with the first storage device 128. The storage address associated with the data may be predetermined. For example, the storage address associated with the data is predetermined to be associated with the second storage device 130.

[0036] In some examples, the set of rules may use machine learning algorithms to predict data exchange patterns and optimize data placement between the first storage device 128 and the second storage device 130. The data exchange patterns may be collected through logs generated by the computing system 100. The machine learning algorithms may analyze historical access patterns, including data access frequency, temporal and spatial locality, data type, and data dependencies. By learning the data exchange patterns, the set of rules may adjust the data placement strategy to optimize data placement. The machine learning model may be continuously updated based on newly generated logs indicating new exchange patterns, and the set of rules may be adaptively optimized, potentially improving the overall performance and energy efficiency of the computing system 100.

[0037] In some examples, computing system 100 stores large data scattered across multiple storage devices. For example, the data to be stored includes a graphical user interface that includes one or more interactive buttons and a background graphic. Processor 102 may select first storage device 128 to store one or more interactive buttons and select second storage device 130 to store the background graphic that is not frequently accessed. In these examples, computing system 100 takes advantage of the faster access speed of first storage device 128 to process interactive elements that may require frequent updates or interactions, while taking advantage of the larger capacity of second storage device 130 to store less accessed background graphics. For example, when a user interacts with a button, processor 102 can quickly retrieve and update the state of the button from first storage device 128, ensuring the responsiveness of the graphical user interface. At the same time, the background graphic that remains static after initial loading can be efficiently stored in second storage device 130 without affecting responsiveness. This approach helps balance the performance and capacity requirements of the graphical user interface, potentially optimizing the system responsiveness and storage utilization of resource-constrained devices such as Internet of Things or system-on-chip devices.

[0038] When first storage device 128 is selected as the storage device, first storage device 128 may store the data. In some examples, when first storage device 128 is selected as the storage device, processor 102 instructs first storage device 128 to write the data via main bus 112 or data bus 132. When second storage device 130 is selected as the storage device, controller 116 may receive a write request. In some examples, controller 116 determines the storage location of the data. For example, controller 116 may override the write request to store the data in second storage device 130 by temporarily storing the data in cache memory 124 or buffer 126.

[0039] In block 206, the controller 116 stores data in a cache memory (e.g., cache memory 124). The second storage device 130 may require a prerequisite operation to be performed for each write operation. This prerequisite operation may be referred to as overhead. In some examples, the prerequisite operation includes powering on a storage cell, configuring an operation mode, or converting a storage address to a physical address of a corresponding storage cell. Writing a larger data set may be more efficient than writing a smaller data set. By combining multiple write operations, the number of individual write cycles and associated overhead can be reduced, thereby improving overall performance or efficiency. Writing data related to substantially adjacent storage addresses may be more efficient because the overhead can be shared when writing data to storage locations. In some examples, the controller 116 accumulates multiple write operations by storing the data to be written in the cache memory 124 or buffer 126. In some examples, the controller 116 triggers a refresh of the cache memory 124 by writing the data stored in the cache memory 124 to the second storage device 130. For example, the controller 116 triggers a refresh of the cache memory 124 at a predetermined frequency. As another example, the controller 116 triggers a refresh of the cache memory 124 based on an intelligent refresh policy. The intelligent refresh policy may be determined based on the degree of fill of the cache memory 124, the data survival duration, or the access pattern.

[0040] In block 208, the processor 102 may receive a second write request to store second data at a second storage address. The write request, data, and storage address referred to in block 202 may be referred to as a first write request, first data, and first storage address, respectively. The second write request may be in the same format as the first write request. In response to receiving the second write request, the processor 102 may perform the method in block 204 to select a storage device from one or more storage devices. In some examples, when the second storage device 130 is selected as the storage device, the controller 116 receives the second write request to store the second data at the second storage address.

[0041] In block 210, the controller 116 may cause the second storage device 130 to store the first data and the second data. In some examples, the controller 116 causes the second storage device 130 to store the first data and the second data based on the cumulative size exceeding a first predetermined size threshold. For example, when the cumulative size of the first data and the second data exceeds the first predetermined size threshold, the second storage device 130 stores the first data and the second data. In some examples, the controller 116 causes the second storage device 130 to store the first data and the second data based on a cache line in the cache memory 124 being substantially full. In some examples, the controller 116 causes the second storage device 130 to store the first data and the second data in response to the number of available cache lines in the cache memory 124 being below a preset number (e.g., 1). In some examples, the controller 116 causes the second storage device 130 to store the first data and the second data based on the first storage address and the second storage address being substantially adjacent storage addresses. For example, when the first data and the second data correspond to substantially adjacent storage addresses, the overhead stored in the second storage device 130 is shared between writing the first data and the second data, thereby improving efficiency. In some examples, the controller 116 employs an intelligent cache eviction policy that takes into account the access frequency when deciding which cache lines to evict. Instead of only moving out data when a cache line is substantially full (e.g., when the number of available cache lines in the cache memory 124 exceeds a preset number), the controller 116 retains frequently accessed data in the cache memory 124 even if some less frequently accessed data has been in the cache memory 124 for a long time, thereby preferentially retaining frequently accessed data in the faster cache memory 124 rather than moving this data to the slower second storage device 130. By implementing this access-frequency-based eviction policy, the computing system 100 may optimize storage, reduce unnecessary data transfer between the cache memory 124 and the second storage device 130, and improve overall system performance.

[0042] In some examples, the controller 116 implements a read-before-write mechanism for storing a new data batch in one or more substantially adjacent storage addresses. The read-before-write mechanism includes: receiving a write request for a new data batch that includes a plurality of data items associated with one or more substantially adjacent storage addresses; reading a current data batch in one or more substantially adjacent storage addresses from the second storage device 130; storing the current data batch in the first storage device 128; updating the current data batch with the new data batch to obtain an updated data batch; and writing the updated data batch to the second storage device. The read-before-write mechanism can allow the controller 116 to efficiently write a data batch in substantially adjacent storage addresses by taking advantage of the faster write speed of the first storage device 128 (e.g., static random access memory), while optimizing the write operation to the larger but slower second storage device 130 (e.g., pseudo-static random access memory).

[0043] In some examples, the controller 116 implements a direct-write mechanism for storing a new data batch in one or more substantially adjacent storage addresses. The direct-write mechanism includes directly writing the new data batch to the second storage device 130 based on determining that the number of one or more substantially adjacent storage addresses exceeds a predetermined quantity threshold.

[0044] In some examples, the processor 102 implements a data lifecycle management mechanism that tracks the duration of existence and access patterns of stored data. The processor 102 can monitor and analyze the access frequency, time since last access, and other relevant metrics of the data stored in the first storage device 128 and the second storage device 130. Based on this analysis, the processor 102 can identify whether the data stored in the first storage device 128 has become less accessed or has not been accessed within a specified period. In response to making this identification, the processor 102 can initiate a data migration process to move the identified data from the first storage device 128 to the second storage device 130. The processor 102 can coordinate with the controller 116 to efficiently execute this data migration process. For example, the processor 102 reads the identified data from the first storage device 128 and instructs the controller 116 to write the identified data to the second storage device 130. In response to receiving the instruction from the processor 102 to write the identified data to the second storage device 130, the controller 116 can temporarily store the identified data in the cache memory 124 or the buffer 126. The controller 116 can write the identified data to the second storage device 130 according to the techniques described herein. In some examples, the data migration process can be performed during periods of low system activity to minimize the impact on overall system performance. In some examples, the processor 102 can update the address associated with the identified data to reflect the new location of the migrated data in the second storage device 130, ensuring that subsequent read or write requests for the migrated data are directed to the correct storage device. The processor 102 can also implement a reverse migration process for data that becomes frequently accessed again. In response to determining that a subset of the data stored in the second storage device 130 begins to show an increased access frequency, the processor 102 can initiate the migration of the data subset to the first storage device 128 to improve the access speed of the frequently accessed data subset. By implementing such a data lifecycle management mechanism, the processor 102 can help maintain the optimal performance of frequently accessed data while efficiently utilizing the larger capacity of the second storage device 130 to store less active data. This approach may contribute to overall system efficiency and may improve the performance and energy usage efficiency of resource-constrained devices such as Internet of Things or system-on-chip devices.

[0045] In some examples, the controller 116 may implement a data compression mechanism that compresses data stored in the cache memory 124. This approach can allow for more efficient utilization of the cache memory 124 or the second storage device 130. The compression algorithm can be selected based on the data type and the characteristics of the data stored in the cache memory 124. For example, the controller 116 may employ lightweight compression techniques (such as the LZ77 or LZ78 algorithms), which provide a balance between compression ratio and computational overhead. The lightweight compression techniques can provide a certain degree of compression while maintaining fast access times. Traditional systems may be reluctant to implement compression techniques because the computational overhead associated with compression and decompression operations may consume valuable processing resources and may affect the overall system responsiveness of resource-constrained devices. In some examples, the controller 116 may perform data compression in the cache memory 124 during periods of low system activity or when the computing system 100 is relatively idle, so as not to affect system performance during high-demand periods. The controller 116 may implement adaptive compression on the data in the cache memory 124, where the controller 116 can dynamically adjust the compression level based on factors such as the current load, the available space in the cache memory 124, or the access pattern associated with the data. For example, during periods of high utilization of the cache memory 124, the controller 116 may apply more aggressive compression to optimize the use of the cache memory 124, while during periods of low utilization, the controller 116 may prioritize faster access by using lighter compression or no compression.

[0046] By compressing the data in the cache memory 124, the controller 116 may increase the amount of data that can be saved in the cache, thereby reducing the frequency of data transfer between the cache memory 124 and the slower storage device (such as the second storage device 130). This approach may help optimize cache utilization, especially in resource-constrained devices such as Internet of Things or system-on-chip devices, and may improve the overall system performance and responsiveness.

[0047] According to some examples, Figure 3 is a flowchart showing more details of the data exchange method in the computing system.

[0048] In block 302, the controller 116 may receive a read request for reading data associated with a storage address. In some examples, the controller 116 receives the read request when the processor 102 determines that the data is associated with the second storage device 130 based on the storage address or the main identifier.

[0049] In block 304, if the data is stored in the cache memory, the controller 116 may return the data from the cache memory. Block 304 may be executed when it is determined that the data is stored in the cache memory 124. In response to receiving a read request, the controller 116 may cause the cache memory 124 to return the data. For example, when the controller 116 determines that the data is stored in the cache memory 124, it causes the cache memory 124 to return the data stored in the cache memory 124.

[0050] In block 306, the controller 116 may cause the second storage device 130 to return the data. In some examples, the controller 116 uses the second storage device 130 when the data is not found in the cache memory 124. In some examples, the controller 116 causes the second storage device 130 to return the data based on determining that the data is stored in the second storage device 130. In some examples, when storing a data batch including first data and second data in the second storage device 130, the controller 116 causes the second storage device 130 to return the first data. In some examples, the controller 116 may select a command code from a plurality of pre-configured command codes and send it to the second storage device 130 to cause the second storage device 130 to return the data. These command codes may include different command codes configured for establishing communication with pseudo-static random access memories produced by different manufacturers.

[0051] In block 308, the controller 116 may implement a prefetch mechanism. The prefetch mechanism may include causing the second storage device 130 to return a data batch associated with a plurality of addresses. In some examples, reading from the second storage device 130 includes a preparatory operation. In some examples, the preparatory operation includes decoding the storage address to locate the requested data within the second storage device 130. In some examples, the preparatory operation includes activating an appropriate memory array or precharging bit lines to prepare for reading the data. In some examples, the prefetch mechanism includes retrieving a data batch including data associated with substantially adjacent storage addresses. For example, the size of the data batch is 16 to 256 bytes. By prefetching additional data, subsequent read requests for adjacent addresses may be returned from a temporary location (such as the cache memory 124), potentially reducing pseudo-static random access memory read operations or associated overhead. In some examples, the controller 116 implements an adaptive prefetch mechanism that dynamically adjusts the prefetch size (such as the size of the data batch to be prefetched) based on the access pattern. For example, the prefetch size may be increased in response to detecting sequential data access. The prefetch size may be decreased in response to detecting a random access pattern. The adaptive prefetch mechanism may optimize memory usage and reduce unnecessary data transfers.

[0052] The controller 116 can help maintain data consistency among multiple processors, such as processors 104 and 106. For example, the controller 116 can determine whether data is stored in the cache memory 124 or the second storage device 130. When a processor sends a read request associated with a storage address, the controller 116 returns the data associated with the storage address without the processor 102 directly accessing the memory location, thus preventing inconsistencies. In some examples, the controller 116 manages the translation between the storage addresses used by the processors and the physical addresses in different storage devices, maintaining a consistent view of the storage space for the processor 102.

[0053] According to some examples, Figure 4 is a schematic diagram showing more details of the computing system 100.

[0054] The computing system 100 can include input / output components (I / O components) 402. The I / O components 402 can include various components for receiving input, providing output, generating output, transmitting information, exchanging information, or capturing measurements. The specific I / O components 402 included in a particular machine depend on the type of the machine. For example, a portable machine such as a mobile phone may include a touch input device or other such input mechanisms, while a headless server machine may not include such touch input devices. The I / O components 402 can include Figure 4 many other components not shown. In various examples, the I / O components 402 can include an output component 426 and an input component 428. The output component 426 can include visual components (such as a display, such as a plasma display panel (PDP), a light-emitting diode (LED) display, a liquid crystal display (LCD), a projector, or a cathode ray tube (CRT)), acoustic components (such as speakers), tactile components (such as a vibration motor, a resistance mechanism), or other signal generators. The input component 428 can include alphanumeric input components (such as a keyboard, a touch screen configured to receive alphanumeric input, an optical keyboard, or other alphanumeric input components), point-based input components (such as a mouse, a touchpad, a trackball, a joystick, a motion sensor, or other pointing tools), tactile input components (such as a physical button, a touch screen providing touch location and / or force or touch gestures, or other tactile input components), audio input components (such as a microphone), etc.

[0055] In a further example, the I / O component 402 may include a biometric component 430, a motion component 432, an environmental component 434, or a location component 436, as well as many other components. For example, the biometric component 430 includes components for detecting expressions (such as hand expressions, facial expressions, voice expressions, body postures, or eye movement tracking), measuring biometric signals (such as blood pressure, heart rate, body temperature, sweating, or brain waves), or identifying a person (such as voice recognition, retina recognition, facial recognition, fingerprint recognition, or electroencephalogram recognition). The motion component 432 includes an acceleration sensor component (such as an accelerometer), a gravity sensor component, a rotation sensor component (such as a gyroscope). The environmental component 434 includes, for example, one or more cameras, an illuminance sensor component (such as a photometer), a temperature sensor component (such as one or more thermometers for detecting ambient temperature), a humidity sensor component, a pressure sensor component (such as a barometer), an acoustic sensor component (such as one or more microphones for detecting background noise), a proximity sensor component (such as an infrared sensor for detecting nearby objects), a gas sensor (such as a gas detection sensor for detecting the concentration of harmful gases for safety purposes or measuring air pollutants), or other components that can provide indications, measurements, or signals corresponding to the surrounding physical environment. The location component 436 includes a location sensor component (such as a Global Positioning System (GPS) receiver component), an altitude sensor component (such as a barometer or altimeter from which altitude can be derived), a direction sensor component (such as a magnetometer), and so on.

[0056] Communication can be achieved using various techniques. The I / O component 402 also includes a communication component 438, which can couple the computing system 100 to the network 422 or the device 424 through their respective couplings or connections. For example, the communication component 438 may include a network interface component or other devices suitable for interfacing with the network 422. In a further example, the communication component 438 may include a wired communication component, a wireless communication component, a cellular communication component, a Near Field Communication (NFC) component, components (such as low power), components, and other communication components to provide communication in other ways. The device 424 can be another machine or any of various peripheral devices (such as a peripheral device coupled via USB).

[0057] In addition, the communication component 438 can detect an identifier or a component including a detectable identifier. For example, the communication component 438 can include a radio frequency identification (RFID) tag reader component, an NFC smart tag detection component, an optical reader component (e.g., an optical sensor for detecting one-dimensional barcodes such as Universal Product Code (UPC) barcodes, multi-dimensional barcodes such as Quick Response (QR) codes, Aztec codes, Data Matrix, Data Graphic, Maxi codes, PDF417, Ultra codes, UCC RSS-2D barcodes, and other optical codes), or an acoustic detection component (e.g., a microphone for identifying tagged audio signals). In addition, various information can be obtained through the communication component 438, such as the location geolocated by Internet Protocol (IP), the location by signal triangulation, or the location by detecting an NFC beacon signal that can indicate a specific location.

[0058] Example

[0059] Example 1 is a method that includes: generating a write request for writing data to a second storage device of a memory, the memory including a first storage device and a second storage device, the first storage device including static random access memory (SRAM), the second storage device including pseudo-static random access memory (PSRAM), the performance metric of the first storage device being superior to that of the second storage device, and the capacity of the first storage device being less than that of the second storage device; receiving the write request by a controller coupled to the second storage device, wherein the controller includes a cache memory having one or more cache lines, and the performance metric of the cache memory being superior to that of the second storage device; overriding the write request for writing data to the second storage device by alternatively writing the data to one of the one or more cache lines in the memory; and writing the data to the second storage device in response to one or more cache lines being substantially filled.

[0060] Example 2 further includes, based on Example 1, wherein the write request is a first write request and the data is first data, and the method further includes: receiving, by the controller, a second write request for storing second data in the second storage device; and storing the first data and the second data in the second storage device based on the storage addresses of the first data and the second data being substantially adjacent.

[0061] Example 3 further includes, based on Examples 1-2, wherein the write request is a first write request and the data is first data, and the method further includes: receiving, by the controller, a second write request for storing second data in the second storage device; and storing the first data and the second data in the second storage device in response to the number of available cache lines in the cache memory being lower than a preset number.

[0062] Example 4 further includes, based on Example 3, receiving a read request for reading first data from a second storage device; and after storing the first data and the second data in the second storage device, causing the second storage device to return the first data.

[0063] Example 5 further includes, based on Examples 1 - 4, receiving a read request for reading data from a second storage device; and returning the data from a cache memory based on the data being stored in one of one or more cache lines of the cache memory.

[0064] Example 6 further includes, based on Examples 1 - 5, reading a current data batch located at one or more substantially adjacent storage addresses from a second storage device; storing the current data batch in a first storage device; updating the current data batch with data to obtain an updated data batch; and writing the updated data batch to the second storage device.

[0065] Example 7 further includes, based on Examples 1 - 6, receiving a read request for reading data from a second storage device; and causing the second storage device to return a data batch including a plurality of data items, the plurality of data items including the data, and a plurality of addresses associated with the plurality of data items being substantially adjacent storage addresses.

[0066] Example 8 further includes storing second data in a first storage device, based on Examples 1 - 7.

[0067] Example 9 further includes, based on Examples 1 - 8, wherein the controller further includes a buffer, and the method further includes overriding a write request by storing the data in the buffer based on the data size exceeding a predetermined size threshold.

[0068] Example 10 is at least one machine - readable medium that includes instructions which, when executed by a processing circuit, cause the processing circuit to perform operations to implement any one of Examples 1 - 9.

[0069] Example 11 is an apparatus that includes means for implementing any one of Examples 1 - 9.

[0070] Example 12 is a system for implementing any one of Examples 1 - 9.

[0071] Example 13 is a method for implementing any one of Examples 1 - 9.

Claims

1. A computing system, characterized in that: include: one or more processors; as well as One or more storage devices, including a first storage device and a second storage device, wherein the first storage device includes a static random access memory (SRAM), the second storage device includes a pseudo-static random access memory (PSRAM), the performance index of the first storage device is better than that of the second storage device, and the capacity of the first storage device is smaller than that of the second storage device.

2. The computing system according to claim 1, characterized in that The second storage device is connected to a controller, the controller includes a memory, the performance index of the memory is better than that of the second storage device, the one or more storage devices store instructions, and when the instructions are executed by the one or more processors, the computing system is configured to perform the following operations: receiving a write request to write data into the second storage device; storing the data in the memory; receiving a read request for reading the data from the second storage device; as well as Based on the data being stored in the memory, the data is returned from the memory.

3. The computing system according to claim 2, characterized in that The write request is a first write request, the data is first data, the first write request includes a first storage address, and the instruction further configures the computing system to perform the following operations: receiving a second write request for storing second data in the second storage device based on a second storage address; as well as Based on the first storage address and the second storage address being substantially adjacent, the first data and the second data are stored in the second storage device.

4. The computing system according to claim 2, characterized in that: The write request is a first write request, the data is first data, the memory includes a cache memory, the cache memory includes one or more cache lines, and the instruction further configures the computing system to perform the following operations: receiving a second write request for storing second data in the second storage device; as well as In response to the number of available cache lines in the memory being less than a predetermined number, the first data and the second data are stored in the second storage device.

5. The computing system according to claim 4, characterized in that: The read request is a first read request, and the instruction further configures the computing system to perform the following operations: receiving a second read request for reading the data from the second storage device; as well as In response to storing the first data and the second data in the second storage device, causing the second storage device to return the data.

6. The computing system according to claim 2, characterized in that: The instructions also configure the computing system to perform the following operations: reading from the second storage device a current batch of data stored in one or more substantially contiguous storage addresses; storing the current data batch in the first storage device; updating the current data batch using a plurality of data items to obtain an updated data batch; as well as The updated data batch is written to the second storage device.

7. The computing system according to claim 2, characterized in that: The instructions also configure the computing system to perform the following operations: In response to receiving the read request, the second storage device is caused to return a data batch including a plurality of data items, wherein the plurality of data items include the data, and a plurality of addresses associated with the plurality of data items are substantially adjacent storage addresses.

8. The computing system according to claim 2, characterized in that: The write request is a first write request, the data is first data, and the instruction further configures the computing system to perform the following operations: receiving a second write request for writing second data to the first storage device; and The second data is stored in the first storage device.

9. The computing system according to claim 2, characterized in that: The controller includes a buffer, and the instructions further configure the computing system to perform the following operations: Based on the size of the data exceeding a predetermined size threshold, the data is stored in the buffer.

10. The computing system according to claim 2, characterized in that: The instructions also configure the computing system to perform the following operations: identifying information of the second storage device; selecting a command code corresponding to the second storage device from a plurality of preconfigured command codes based on the identified information; as well as Communication is established between the controller and the second storage device using the selected command code corresponding to the second storage device.

11. A method, characterized in that include: Generate a write request to write data to a second storage device of a memory, the memory comprising a first storage device and the second storage device, the first storage device comprising a static random access memory (SRAM), the second storage device comprising a pseudo-static random access memory (PSRAM), the performance index of the first storage device is better than that of the second storage device, and the capacity of the first storage device is smaller than that of the second storage device; The write request is received by a controller connected to the second storage device, wherein the controller includes a cache memory, the cache memory includes one or more cache lines, and the cache memory has a performance indicator better than the second storage device; overriding the write request to write data to the second storage device by instead writing the data to one of the one or more cache lines of the memory; as well as In response to the one or more cache lines being substantially filled, the data is written to the second storage device.

12. The method according to claim 11, characterized in that The write request is a first write request, the data is first data, and the method further includes: receiving, by the controller, a second write request for storing second data in the second storage device; and Based on the fact that storage addresses of the first data and the second data are substantially adjacent, the first data and the second data are stored in the second storage device.

13. The method according to claim 11, characterized in that The write request is a first write request, the data is first data, and the method further includes: receiving, by the controller, a second write request for storing second data in the second storage device; and In response to the number of available cache lines in the cache memory being lower than a predetermined number, the first data and the second data are stored in the second storage device.

14. The method according to claim 13, characterized in that Also includes: receiving a read request for reading the first data from the second storage device; as well as In response to storing the first data and the second data in the second storage device, causing the second storage device to return the first data.

15. The method according to claim 11, characterized in that Also includes: receiving a read request for reading the data from the second storage device; as well as The data is returned from the cache memory based on one of the one or more cache lines in which the data is stored in the cache memory.

16. The method according to claim 11, characterized in that Also includes: reading a current batch of data located at one or more substantially adjacent storage addresses from the second storage device; Storing the current data batch in a first storage device; updating the current data batch using the data to obtain an updated data batch; as well as The updated data batch is written to the second storage device.

17. The method according to claim 11, characterized in that Also includes: receiving a read request for reading the data from the second storage device; as well as The second storage device is caused to return a data batch including a plurality of data items, the plurality of data items including the data, a plurality of addresses associated with the plurality of data items being substantially adjacent storage addresses.

18. The method according to claim 11, characterized in that Also included is storing second data in the first storage device.

19. The method according to claim 11, characterized in that The controller further includes a buffer, and the method further includes overriding the write request by storing the data in the buffer instead of writing it to the second storage device based on a size of the data exceeding a predetermined size threshold.

20. A non-transitory computer-readable storage medium comprising instructions that, when executed by a computing system, cause the computing system to: Generate a write request to write data to a second storage device of a memory, the memory comprising a first storage device and the second storage device, the first storage device comprising a static random access memory (SRAM), the second storage device comprising a pseudo-static random access memory (PSRAM), the performance index of the first storage device is better than that of the second storage device, and the capacity of the first storage device is smaller than that of the second storage device; The write request is received by a controller connected to the second storage device, wherein the controller includes a cache memory, the cache memory includes one or more cache lines, and the cache memory has a performance indicator better than the second storage device; overriding the write request to write data to the second storage device by instead writing the data to one of the one or more cache lines of the memory; and In response to the one or more cache lines being substantially full, the data is written to the second storage device.

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