NandFlash control method
By refining the operation instructions into timing operation commands and instruction data, NandFlash's interface operation timing is generated, and the control compatibility problem of different models of NandFlash is solved, and unified operation control is achieved.
Patent Information
- Application Number
- CN202510304830.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-14
- Publication Date
- 2025-07-01
AI Technical Summary
The existing NandFlash controllers are difficult to compatible with different models of NandFlash, and the operation timing and instructions are different, which makes the controller unable to manage in a unified manner.
By dividing operation instructions according to the timing according to the instruction type, converting them into timing operation commands and instruction data, generating the interface operation timing of NandFlash, and outputting the required timing operation commands in combination with the NandFlash operation type, to achieve control of different models of NandFlash.
It realizes the accurate operation and control of different models of NandFlash through a NandFlash controller, with good compatibility and detailed operation instructions into basic operations, to meet the needs of different models of NandFlash.
Smart Images
Figure CN120234043A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of Flash memory, and in particular to a method for controlling NandFlash. Background Art
[0002] There are dozens of operation instructions for existing NandFlash, and the operation timings and instructions of different models of NandFlash are different. It is difficult to operate and control different models of NandFlash through a single NandFlash controller. Summary of the Invention
[0003] The technical problem to be solved by the present invention is to provide a method for controlling NandFlash, so as to operate and control different models of NandFlash through a single NandFlash controller.
[0004] To solve the above technical problem, the present invention provides a method for controlling NandFlash, which is applied to a NandFlash controller connected to a NandFlash, and includes the following steps: dividing operation instructions according to instruction types according to timings, and converting to obtain corresponding timing operation commands and instruction data; parsing and generating an operation timing of an interface of the NandFlash according to the obtained timing operation commands and instruction data; outputting required timing operation commands to the NandFlash according to the generated operation timing of the interface of the NandFlash combined with the operation type required to be executed by the NandFlash, so as to control the NandFlash to perform the required operation.
[0005] The beneficial technical effect of the present invention is as follows: The method for controlling NandFlash of the present invention is applied to a NandFlash controller connected to a NandFlash. By dividing operation instructions according to instruction types according to timings, corresponding timing operation commands and instruction data are obtained through conversion, so that the operation instructions are further refined into basic operations, and the operation instructions are converted into a combination of timing operation commands, that is, the operation instructions are converted into a combination of basic operations, so as to be compatible with the operation instructions of different NandFlash; and by parsing and generating an operation timing of an interface of the NandFlash according to the obtained timing operation commands and instruction data, and outputting required timing operation commands to the NandFlash according to the generated operation timing of the interface of the NandFlash combined with the operation type required to be executed by the NandFlash, the interface of the NandFlash can be accurately instructed to operate according to requirements, and the operation and control of different models of NandFlash through a single NandFlash controller can be realized. Description of the Drawings
[0006] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0007] Figure 1 It is a schematic flowchart of the NandFlash control method provided by the present invention;
[0008] Figure 2 It is a schematic connection framework diagram of a NandFlash controller and a NandFlash applying the NandFlash control method provided by the present invention. Specific embodiments
[0009] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, rather than all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.
[0010] Please refer to Figure 1 as shown Figure 1 It is a schematic flowchart of the NandFlash control method provided by the embodiments of the present invention. The NandFlash control method is applied to a NandFlash controller connected to a NandFlash. The NandFlash control method includes the following steps:
[0011] Step S10: Divide the operation instructions according to the instruction type according to the time sequence, and convert to obtain the corresponding time-sequence operation commands and instruction data. Among them, the instruction data includes fixed data and / or random data;
[0012] Step S20: Parse and generate the operation time sequence of the NandFlash interface according to the obtained time-sequence operation commands and instruction data;
[0013] Step S30: Output the required time-sequence operation commands to the NandFlash according to the generated operation time sequence of the NandFlash interface in combination with the operation type required to be executed by the NandFlash, so as to control the NandFlash to perform the required operation.
[0014] Among them, the read and write access of NandFlash cannot directly perform random read and write of any address in the storage space. The operation instructions of NandFlash can include multiple operation commands. The operation instructions are the operation instructions corresponding to the NandFlash connected to the NandFlash controller, which are related to the model of NandFlash and can be provided by the manufacturer of NandFlash. The NandFlash control method is applied to the NandFlash controller connected to NandFlash. By dividing the operation instructions according to the instruction type in sequence, the corresponding sequential operation commands and instruction data are obtained through conversion, so that the operation instructions are further refined into basic operations, making the operation instructions converted into a combination of sequential operation commands, that is, converting the operation instructions into a combination of basic operations, so as to be compatible with the operation instructions of different NandFlash; and by parsing and generating the operation timing of the NandFlash interface according to the obtained sequential operation commands and instruction data, and outputting the required sequential operation commands to NandFlash according to the generated operation timing of the NandFlash interface combined with the operation type required by NandFlash, so as to accurately perform instruction operations on the NandFlash interface according to the requirements, and realize the operation control of different models of NandFlash through one NandFlash controller.
[0015] Specifically, the instruction types include delay instruction, wait instruction, interrupt instruction, pin setting instruction, data output instruction and data input instruction. Among them, the delay instruction, that is, Delay, can specify the delay period by configuring the delay period parameter. The delay period parameter refers to the number of periods that need to be delayed; the wait instruction, that is, Wait, can specify the level of the Ready (ready) signal or Busy (busy) signal and the timeout time and output wait time by configuring the level parameter and the wait period parameter. The level parameter of 0 represents a low level, and the level parameter of 1 represents a high level. The wait period parameter refers to the number of periods that need to be waited; the interrupt instruction, that is, Interrupt, is used to trigger an interrupt; the pin setting instruction, that is, Set, can be used to set the signal levels of the CEN (Chip enable) pin, ALE (Address latch enable) pin and CLE (Command latch enable) pin; the data output instruction, that is, Dout, is used to set the DQ (Data inputs / outputs) pin to the output mode and output data; the data input instruction, that is, Din, is used to set the DQ (Data inputs / outputs) pin to the input mode, read data and input.
[0016] Preferably, the instruction types further include repeat instructions and combined instructions. Among them, the repeat instruction, i.e., Repeat, can specify the number of repetitions through parameters, and repeat the instructions before the repeat instruction. It can support repeating up to eight instructions at most; the combined instruction refers to the instruction formed by combining multiple instructions according to the combination method preset by the user.
[0017] Specifically, the step S10 specifically includes:
[0018] Dividing the operation instructions into several timing instruction segments according to the timing;
[0019] Classifying and summarizing the obtained timing instruction segments according to the instruction types, and converting the timing instruction segments corresponding to each instruction type into corresponding timing operation commands and instruction data.
[0020] Specifically, the operation types required to be executed by the NandFlash include read operations and write operations. When the operation type required to be executed by the NandFlash is a write operation, the step of outputting the required timing operation command to the NandFlash according to the operation timing of the generated NandFlash interface combined with the operation type required to be executed by the NandFlash in step S30 is specifically as follows:
[0021] Execute the timing operation commands in the order of the timing operation commands, and control the NandFlash interface according to the operation timing of the generated NandFlash interface to output the specified operation state according to the requirements in the timing operation commands, and transmit the timing operation commands to the NandFlash.
[0022] When the operation type required to be executed by the NandFlash is a read operation, the step of outputting the required timing operation command to the NandFlash according to the operation timing of the generated NandFlash interface combined with the operation type required to be executed by the NandFlash is specifically as follows:
[0023] Execute the timing operation commands in the order of the timing operation commands, and control the NandFlash interface according to the operation timing of the generated NandFlash interface to output the specified operation state according to the requirements in the timing operation commands, and transmit the timing operation commands to the NandFlash, sample the state of the data line, and obtain the data stored in the NandFlash. Among them, the data line is the NandFlash data line, which is used to connect the NandFlash and the NandFlash controller. The data of the NandFlash is obtained according to the level state of the data line. By sampling the state of the data line, the level state of the data line is obtained. The high level state and the low level state of the data line represent different data respectively. The low level state can represent that the data is 0, and the high level state can represent that the data is 1.
[0024] Specifically, after the step of obtaining the data stored in the NandFlash, the following steps are further included:
[0025] Obtain and output the required read data from the obtained data.
[0026] Specifically, after the step S30, the following steps are further included:
[0027] The feedback operation is completed.
[0028] Specifically, the NandFlash controller is integrated on the FPGA chip. Referring to Figure 2 , Figure 2 shows a schematic connection framework diagram of the NandFlash controller and the NandFlash. The NandFlash controller 10 includes an AXI bus to register module 11, an instruction and data generation module 12, an instruction execution module 13, and an instruction acceleration module 15. The AXI bus to register module 11 is connected to the main control module through a bus for communication connection with the main control module, and is used to receive and forward the operation instructions sent by the main control module. The AXI bus to register module 11 includes a register interface and an SRAM (static random access memory) interface. The register interface is used to manage the writing and reading of registers and first-in-first-out storage queues. The SRAM interface is connected to the SRAM of the instruction acceleration module 15. The instruction and data generation module 12 is respectively connected to the AXI bus to register module 11 and the instruction execution module 13. The instruction acceleration module 15 is connected to the AXI bus to register module 11 and the instruction execution module 13. The instruction acceleration module 15 is used to store operation instructions. The instruction execution module 13 includes an instruction first-in-first-out storage queue CMD FIFO, an input data first-in-first-out storage queue DIN FIFO, an output data first-in-first-out storage queue DOUT FIFO, and an instruction execution unit 131. The instruction execution unit 131 is respectively connected to the instruction first-in-first-out storage queue CMD FIFO, the input data first-in-first-out storage queue DIN FIFO, and the output data first-in-first-out storage queue DOUT FIFO. The instruction first-in-first-out storage queue CMD FIFO, the input data first-in-first-out storage queue DIN FIFO, and the output data first-in-first-out storage queue DOUT FIFO are connected to the register interface. The instruction first-in-first-out storage queue CMD FIFO and the output data first-in-first-out storage queue DOUT FIFO are connected to the instruction and data generation module 12.
[0029] Specifically, the instruction acceleration module 15 includes a DPRAM (Dual-Port Random Access Memory) for storing and managing macro instructions and their configurations. The number of macro instructions can be sixteen. The instruction acceleration module 15 is connected to the AXI bus-to-register module 11 and the instruction execution unit 131.
[0030] Specifically, the NandFlash controller 10 further includes an input / output module 14. The NandFlash controller 10 is connected to the NandFlash 20 through the input / output module 14, responsible for data input / output management, and can manage SDR (Single Data Rate) input / output, DDR (Double Data Rate) input / output, and calculate DBI (Data Bus Inversion).
[0031] The NandFlash controller 10 further includes an error detection module 16 connected to the AXI bus-to-register module 11 and the input data first-in-first-out storage queue DIN FIFO, which is used to detect whether the data obtained from the NandFlash 20 stored in the input data first-in-first-out storage queue DIN FIFO is in error, count the error data, and give feedback. The error detection module 16 determines whether the data is in error by detecting whether the data obtained from the NandFlash 20 stored in the input data first-in-first-out storage queue DIN FIFO meets the preset rules required when the data is stored in the NandFlash 20, so as to test the stability of the NandFlash controller 10.
[0032] Combined Figure 1 and Figure 2 , correspondingly, the step S10 specifically includes:
[0033] The AXI bus-to-register module 11 forwards the received operation instruction to the instruction and data generation module 12 through the register interface;
[0034] The instruction and data generation module 12 divides the received operation instruction into several timing instruction segments according to the timing, classifies and summarizes the obtained timing instruction segments according to the instruction type, converts the timing instruction segments corresponding to each instruction type into corresponding timing operation commands and instruction data, transmits the generated timing operation commands to the instruction first-in-first-out storage queue CMD FIFO for storage, and transmits the generated instruction data to the output data first-in-first-out storage queue DOUT FIFO for storage.
[0035] The step S20 is specifically as follows:
[0036] The instruction execution unit 131 parses and generates the operation timing of the interface of the NandFlash 20 according to the timing operation commands stored in the instruction first-in-first-out storage queue CMD FIFO and the instruction data stored in the output data first-in-first-out storage queue DOUT FIFO.
[0037] The step S30 specifically includes:
[0038] When the operation type required to be executed by the NandFlash 20 is a write operation, the instruction execution unit 131 executes the timing operation commands in the order of the timing operation commands obtained from the instruction first-in-first-out storage queue CMD FIFO, and controls the interface of the NandFlash 20 to output a specified operation state according to the operation timing of the interface of the generated NandFlash 20 through the input / output module 14, and transmits the timing operation commands to the NandFlash 20 to control the NandFlash 20 to perform the required operation. The instruction data obtained from the output data first-in-first-out storage queue DOUT FIFO is output to the NandFlash 20 through the input / output module 14 to write the data into the NandFlash 20;
[0039] When the operation type required to be executed by the NandFlash 20 is a read operation, the instruction execution unit 131 executes the timing operation commands in the order of the timing operation commands obtained from the instruction first-in-first-out storage queue CMD FIFO, and controls the interface of the NandFlash 20 to output a specified operation state according to the operation timing of the interface of the generated NandFlash 20 through the input / output module 14, and transmits the timing operation commands to the NandFlash 20 to control the NandFlash 20 to perform the required operation. The data obtained from the NandFlash 20 is input and stored in the input data first-in-first-out storage queue DIN FIFO through the input / output module 14; the required read data is obtained and output from the data obtained from the NandFlash 20 and stored in the input data first-in-first-out storage queue DIN FIFO, so as to implement the read operation of the NandFlash 20.
[0040] In summary, the NandFlash control method of the present invention is applied to a NandFlash controller connected to a NandFlash. By dividing operation instructions according to instruction types in sequence, corresponding sequential operation commands and instruction data are obtained through conversion, so that the operation instructions are further refined into basic operations, making the operation instructions converted into a combination of sequential operation commands, that is, the operation instructions are converted into a combination of basic operations, so as to be compatible with the operation instructions of different NandFlashs; and by parsing and generating the operation timing of the NandFlash interface according to the obtained sequential operation commands and instruction data, and outputting the required sequential operation commands to the NandFlash according to the generated operation timing of the NandFlash interface combined with the operation type that the NandFlash needs to execute, so as to accurately perform instruction operations on the NandFlash interface according to requirements, and realize the operation control of different models of NandFlash through a NandFlash controller.
[0041] As described above, the above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims
1. A NandFlash control method, characterized in that: Applicable to a NandFlash controller connected to NandFlash, including the following steps: Divide the operation instructions according to the timing and instruction type, and convert them to obtain the corresponding timing operation commands and instruction data; Analyze and generate the operation timing of the NandFlash interface according to the obtained timing operation command and instruction data; According to the generated operation timing of the NandFlash interface and the type of operation that the NandFlash needs to perform, the required timing operation command is output to the NandFlash to control the NandFlash to perform the required operation.
2. The NandFlash control method according to claim 1, characterized in that: The instruction types include delay instructions, wait instructions, interrupt instructions, pin setting instructions, data output instructions and data input instructions.
3. The NandFlash control method according to claim 2, characterized in that: The instruction types also include repeat instructions and combination instructions.
4. The NandFlash control method according to claim 1, characterized in that: The step of dividing the operation instructions according to the timing and instruction type, and converting to obtain the corresponding timing operation commands and instruction data specifically includes: Divide the operation instruction into a number of sequential instruction segments according to the timing; The obtained sequential instruction fragments are classified and summarized according to the instruction type, and the sequential instruction fragments corresponding to each instruction type are converted to generate corresponding sequential operation commands and instruction data.
5. The NandFlash control method according to claim 1, characterized in that: When the operation type to be performed by the NandFlash is a write operation, the step of outputting the required timing operation command to the NandFlash according to the generated operation timing of the NandFlash interface in combination with the operation type to be performed by the NandFlash is specifically as follows: Execute the timing operation commands in the order of the timing operation commands, and control the NandFlash interface to output the specified operation state according to the requirements in the timing operation commands according to the generated operation timing of the NandFlash interface, and transmit the timing operation commands to the NandFlash.
6. The NandFlash control method according to claim 1, characterized in that: When the operation type to be performed by the NandFlash is a read operation, the step of outputting the required timing operation command to the NandFlash according to the generated operation timing of the NandFlash interface in combination with the operation type to be performed by the NandFlash is specifically as follows: Execute the timing operation commands in the order of the timing operation commands, and control the NandFlash interface according to the generated operation timing of the NandFlash interface to output the specified operation state according to the requirements in the timing operation commands, and transmit the timing operation commands to the NandFlash to obtain the data stored in the NandFlash.
7. The NandFlash control method according to claim 6, characterized in that: After the step of obtaining the data stored in the NandFlash, the method further includes: The data required to be read out is obtained and outputted.
8. The NandFlash control method according to claim 1, characterized in that: The NandFlash controller includes an AXI bus transfer register module, an instruction and data generation module, an instruction execution module and an instruction acceleration module. The AXI bus transfer register module is connected to the main control module through a bus to communicate with the main control module and is used to receive and forward operation instructions sent by the main control module. The AXI bus transfer register module includes a register interface and an SRAM interface. The register interface is used to manage the writing and reading of registers and first-in-first-out storage queues. The SRAM interface is connected to the SRAM of the instruction acceleration module. The instruction and data generation module is respectively connected to the AXI bus transfer register module and the instruction execution module. The instruction acceleration module is connected to the AXI bus transfer register module and the instruction execution module. The I bus transfer register module is connected to the instruction execution module, the instruction acceleration module is used to store operation instructions, the instruction execution module includes an instruction first-in-first-out storage queue, an input data first-in-first-out storage queue, an output data first-in-first-out storage queue and an instruction execution unit, the instruction execution unit is respectively connected to the instruction first-in-first-out storage queue, the input data first-in-first-out storage queue and the output data first-in-first-out storage queue, the instruction first-in-first-out storage queue, the input data first-in-first-out storage queue and the output data first-in-first-out storage queue are connected to the register interface, and the instruction first-in-first-out storage queue and the output data first-in-first-out storage queue are connected to the instruction and data generation module.
9. The NandFlash control method according to claim 8, characterized in that: The step of dividing the operation instructions according to the timing and instruction type, and converting to obtain the corresponding timing operation commands and instruction data specifically includes: The AXI bus to register module forwards the received operation instruction to the instruction and data generation module through the register interface; The instruction and data generation module divides the received operation instructions into a number of timing instruction fragments according to the timing, and classifies and summarizes the obtained timing instruction fragments according to the instruction type, converts the timing instruction fragments corresponding to each instruction type to generate corresponding timing operation commands and instruction data, transmits the generated timing operation commands to the instruction first-in-first-out storage queue for storage, and transmits the generated instruction data to the output data first-in-first-out storage queue for storage.
10. The NandFlash control method according to claim 9, characterized in that: The steps of parsing and generating the operation timing of the NandFlash interface according to the obtained timing operation command and instruction data are specifically as follows: The instruction execution unit generates an operation timing of the NandFlash interface according to the timing operation command stored in the instruction FIFO storage queue and the instruction data stored in the output data FIFO storage queue.