Construction method of chip test case, electronic equipment and medium

Abstract

The invention relates to the technical field of chips, in particular to a chip test case construction method, electronic equipment and a medium, and the method comprises the following steps: S1, constructing a target test case reconstruction structure {C0, (C1, B1), (C2, B2),..., (Cn, Bn),..., (CN, BN)}; s2, analyzing the target test case reconstruction structure to obtain C0, and then obtaining each Cn and Bn in parallel; s3, analyzing each Bn in parallel to obtain each Fin; and S4, generating all chip test cases of the to-be-tested chip design based on each Fin and Cn and C0 corresponding to the Fin. According to the invention, the construction efficiency and accuracy of the chip test case are improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular, to a method for constructing chip test cases, an electronic device, and a medium. Background Art

[0002] In order to ensure that the chip can work properly under various conditions and meet the design specifications and industry standards, a large number of chip test cases need to be constructed during the chip verification process. Chip test cases can be used to verify chip functions, performance, reliability, and compatibility, etc. In the prior art, verification engineers need to set the parameters of each chip test case according to different verification requirements to construct chip test cases, resulting in low construction efficiency and easy errors. Therefore, how to improve the construction efficiency and accuracy of chip test cases has become an urgent technical problem to be solved. Summary of the Invention

[0003] The object of the present invention is to provide a method for constructing chip test cases, an electronic device, and a medium, which improve the construction efficiency and accuracy of chip test cases.

[0004] According to a first aspect of the present invention, there is provided a method for constructing chip test cases, including: Step S1, constructing a target test case reconstruction structure {C0, (C1, B1), (C2, B2),..., (C n , B n ),..., (C N , B N ), where C0 is the shared test case configuration information corresponding to the to-be-tested chip design, C n is the shared test case configuration information corresponding to the nth sub-design of the to-be-tested chip design, B n is the nth group of test case reconstruction information list of the to-be-tested chip design, the value range of n is from 1 to N, N is the total number of sub-designs of the to-be-tested chip design, B n = {F1 n , F2 n ,..., F i n ,..., F a(n) n}, F i n is the ith test case reconstruction information in the nth group of test case reconstruction information list, the value range of i is from 1 to a(n), and a(n) is the total number of test case reconstruction information corresponding to B n ; Step S2, parsing the target test case reconstruction structure to obtain C0, and then obtaining each C n and B n in parallel; Step S3. Parse each B in parallel n and obtain each F i n ; Step S4. Based on each F i n and F i n corresponding C n and C0, generate all chip test cases for the chip design to be tested.

[0005] According to a second aspect of the present invention, there is provided an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method according to the first aspect of the present invention.

[0006] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions for executing the method according to the first aspect of the present invention.

[0007] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solutions, a method for constructing chip test cases, an electronic device and a medium provided by the present invention can achieve considerable technological progress and practicality, and have wide industrial utilization value. It has at least the following beneficial effects: The present invention generates a target test case reconstruction structure by setting a unique test case reconstruction information data structure, hierarchically arranges the necessary information for generating test cases in the test case reconstruction information data structure, extracts multi-level shared configuration information, divides the test cases into test case groups, and generates all chip test cases for the chip design to be tested by parsing the target test case reconstruction structure, thereby improving the construction efficiency and accuracy of chip test cases. Description of the Drawings

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0009] Figure 1 It is a flowchart of the method for constructing chip test cases provided by the embodiment of the present invention. Detailed Embodiments

[0010] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0011] An embodiment of the present invention provides a method for constructing a chip test case, as Figure 1 shown, including: Step S1, construct a target test case reconstruction structure {C0, (C1, B1), (C2, B2),..., (C n , B n ),..., (C N , B N )}, where C0 is the shared test case configuration information corresponding to the chip design to be tested, C n is the shared test case configuration information corresponding to the nth sub-design of the chip design to be tested, B n is the nth set of test case reconstruction information list of the chip design to be tested, the value range of n is from 1 to N, and N is the total number of sub-designs of the chip design to be tested, B n ={F1 n , F2 n ,..., F i n ,..., F a(n) n}, F i n is the ith test case reconstruction information in the nth set of test case reconstruction information list, the value range of i is from 1 to a(n), and a(n) is the total number of test case reconstruction information corresponding to B n .

[0012] It should be noted that multi-level shared test case configuration information is set in the target test case reconstruction structure, which reduces the maintenance quantity of test case configuration information, is convenient for global modification of the same test case configuration information, and reduces the error rate.

[0013] Step S2, parse the target test case reconstruction structure to obtain C0, and then concurrently obtain each C n and B n .

[0014] It should be noted that based on the target test case reconstruction structure, the shared test case configuration information only needs to be parsed once, and consistency can be maintained, improving the test case construction efficiency and avoiding errors.

[0015] Step S3, concurrently parse each B n, obtain each F i n .

[0016] Step S4, based on each F i n 、F i n corresponding C n 、C0 to generate all chip test cases for the chip design to be tested.

[0017] As an embodiment, each F i n includes one or more of user identification, design configuration information to be tested, operating parameters, number of loops, test case group, and running time; C0, C n includes one or more of design configuration information to be tested, operating parameters, number of loops, and running time. It should be noted that the user identification and test case group are maintained separately for each test case reconstruction information, and the design configuration information to be tested, operating parameters, number of loops, and running time can be used as shared test case configuration information, that is, the design configuration information to be tested, operating parameters, number of loops, and running time of the test case can be set in batches through the test case configuration information. Among them, the number of loops is set according to specific test regression requirements, such as set to 10 times, 20 times. The running time can be specifically set to execute within a preset time interval or execute once every preset time period. The preset time interval can specifically be daytime, nighttime, morning, afternoon, etc. The preset time period can specifically be one day, one week, etc.

[0018] As an embodiment, the design configuration information to be tested is used to set the composition form of each component of the chip design to be tested. The composition form includes a first form and a second form. The first form is a form including component ports and internal logic, and the second form is a form including only component ports. Taking the design to be tested including a first component, a second component, a third component, and a fourth component as an example, assuming that the object to be verified is the first component, then the corresponding design configuration information to be tested is to set the first component to the first form, and the second component, the third component, and the fourth component to the second form. Assuming that the verification object is the interaction between the first component and the second component, then the first component and the second component are set to the first form, and the third component and the fourth component are set to the second form.

[0019] As an embodiment, the design configuration information to be measured includes main configuration information and multiple slave configuration information. The main configuration information is the configuration information with the highest usage frequency. When no information is specified in the design configuration information to be measured, it is default set to the main configuration information. When it is necessary to set the slave configuration information, the corresponding slave configuration information needs to be specified in the design configuration information to be measured. By setting the main configuration information and multiple slave configuration information, the default configuration can be directly used in most scenarios, further improving the efficiency of constructing the reconstructed structure of the target test case, and thus improving the generation efficiency of the test case.

[0020] As an embodiment, the operating parameters include environment variables, variables required for the preset script, and options that need to be passed to the Electronic Design Automation (EDA) tool during the running process of the chip test case. Among them, the environment variable can specifically be a linux environment variable, and the preset script is a script for executing the chip test case. The script type can specifically be Python, Perl, Ruby, Rust, Ymal, etc.

[0021] As an embodiment, the test case group includes at least one test case, and the test case group is divided based on the chip function characteristics or based on the running time period. Dividing based on the chip function characteristics can divide the test cases that verify the same chip function characteristics under the same design configuration information to be measured into one test case group. To improve resource utilization, it can also be divided based on the running time period, and the test cases with the same or close running time are divided into one test case group.

[0022] As an embodiment, the test case group further includes a first identifier and a second identifier. If it is set to the first identifier, the test cases in the test case group need to be generated during the current regression test process. If it is set to the second identifier, the test cases in the test case group do not need to be generated during the current regression test process. By setting the test case group identifier, flexible configuration of the regression test can be achieved. When a test case group does not need to participate in the current regression, the test case group can be set to the second identifier without deleting the test case group. When the test case group is needed during the subsequent regression test process, the test case group only needs to be set to the first identifier.

[0023] As an embodiment, step S4 includes: Step S41, obtain F i n The corresponding user identifier and test case group {T1 in , T2 in ,..., T j in ,,..., T b(in)in}, T j in F i n The corresponding j-th test case information, j ranges from 1 to b(in), b(in) is F i n The number of test cases in the corresponding test case group.

[0024] It is understandable that when i and n take different values, the corresponding value of b(in) may also be different.

[0025] Step S42: If F i n If preset parameters are set in F i n The preset parameters in are determined as T j in Corresponding target parameters, otherwise, execute step S43, where the preset parameters are the design configuration information to be tested, operating parameters, number of cycles, test case group or operating time.

[0026] It should be noted that each F i n The user ID and test case group must be set in the test. The design configuration information to be tested, running parameters, number of cycles, test case group or running time can be set or not. If not set, they are generated based on the shared test case configuration information.

[0027] Step S43: If C n If preset parameters are set in C n The preset parameters in are determined as T j in Corresponding target parameters, otherwise, execute step S44.

[0028] Step S44: If a preset parameter is set in C0, the preset parameter of C0 is determined as T j in If the target parameter is corresponding, execute step S55; otherwise, generate prompt information and end the process.

[0029] Through steps S42 to S44, when F i n When preset parameters are set in F i n In the example, the preset parameters are set as the target parameters. The preset parameters can be one or more of the following: the design configuration information to be tested, the running parameters, the number of cycles, the test case group, and the running time. i n If no preset parameters are set in the nSearch for the corresponding preset parameters in it. If they exist, then set C n The preset parameters in it are determined as the corresponding target parameters. If C n does not exist in it, then set the corresponding preset parameters in C0 as the target parameters. Thus, it can be known that the preset parameters that act globally on the design under test are set in C0, and the preset parameters that act on the sub-design of the design under test are set in C n In it, each set of personalized test case reconstruction information is set in F i n In it, a multi-level configuration of test case reconstruction information is realized.

[0030] Step S45: Based on each T j in and each T j in the corresponding user identifier and each T j in Generate each T j in corresponding test cases based on all the corresponding target parameters.

[0031] It should be noted that after all test cases are generated, chip regression testing can be performed. After step S4, the following steps are also included: Step S5: Compile the design code of the chip under test to generate an executable file of the chip under test design.

[0032] Step S6: Run the test cases required for chip regression testing in parallel based on the executable file of the chip under test design, and generate a test case running record. The test case running record includes a running log and a running result. The running result is generated based on the running log, and the running result includes success, failure, and uncertainty.

[0033] Step S7: Generate a chip regression test database based on the test case running record, and display the chip regression test result based on the chip regression test database.

[0034] As an embodiment, step S6 includes: Step S61: Allocate the corresponding CPU quantity P x and the memory storage space Q x for the test cases t x required for chip regression testing. The value range of x is from 1 to X, and X is the total number of test cases required for chip regression testing.

[0035] Step S62: Run all t x in parallel based on the executable file of the chip under test design, and generate the test case running record corresponding to each run of t x . The running log includes the actually required CPU quantity P1 for runningx and the actually required memory storage space Q1 x .

[0036] Step S63, when t x When the cumulative number of corresponding test case running records reaches R, obtain the R t x corresponding to the nearest current test case running records of P1 x After rounding the mean value of the data P2 x and Q1 x After rounding the mean value of the data Q2 x , will P x Update to P x =P2 x +P0 x , will Q x Update to Q x =Q2 x +Q0 x , P0 x is a preset CPU quantity adjustment value, Q0 x is a preset memory storage space adjustment value, and R is a preset cumulative threshold of test case running records.

[0037] Through steps S61 - S63, the resources allocated to test cases can be dynamically adjusted based on the actual running situation of test cases, avoiding resource waste and improving resource utilization rate.

[0038] The step S6 further includes: Step C61, obtain the running log text information corresponding to the test case t x , where the value range of x is from 1 to X, and X is the total number of test cases.

[0039] Step C62, read G1 lines of text information from the running log text information corresponding to t x in the order from front to back, and parse the currently read G1 lines of text information to obtain the test information corresponding to t x , where G1 is a preset first number of lines to be read.

[0040] It should be noted that the test information is usually located at the head of the log text information, and the number of G1 lines can cover the test information corresponding to t x , so first read from the running log text information corresponding to t xRead the text information of line G1 from the corresponding running log text information. The information containing the running result is usually located at the end of the running log text. Therefore, the subsequent analysis reads the text from the end to the front. However, for the case where the number of lines of the log text information is less than or equal to G1, all the running log text information has been read out in step C62. It can be understood that when the number of lines of the log text information is less than or equal to G1, all the text lines corresponding to the running log text information will be read out in step C62. x Read out all the lines in the corresponding running log text information.

[0041] As an embodiment, t x The corresponding test information includes t x The name of the chip design to be tested, t x The configuration of the chip design to be tested, and x The name of the test case.

[0042] Step C6. Determine whether there are unread text lines in the current t x corresponding running log text information. If so, execute step C64. Otherwise, use the currently read G1 line text information as the current text to be analyzed and execute step C65.

[0043] It should be noted that when the number of lines of the log text information is less than or equal to G1, the currently read G1 line text information refers to all the text line information corresponding to the running log text information.

[0044] Step C64. Read the text information of G2 lines from the unread text lines in the t x corresponding running log text information in the reverse order from the end. Use the currently read G2 line text information as the current text to be analyzed and execute step C65. G2 is a preset second read line number.

[0045] It should be noted that if the number of unread text lines in the running log text information is greater than or equal to G2, the currently read G2 line text information is the t x text information of G2 lines read in the reverse order from the end among the unread text lines in the corresponding running log text information. If the number of unread text lines in the running log text information is less than G2, the currently read G2 line text information is the t x remaining all the text line information in the corresponding running log text information. G2 and G1 may be equal or not equal, and the specific data is set according to the specific application scenario.

[0046] Step C65. Scan the current text to be analyzed line by line in the reverse order. If the preset failure text identifier appears, determine that the t x running result is not passed. Otherwise, execute step C66.

[0047] Step C66, determine the current t x Whether there is an unread text line in the corresponding running log text information. If so, return to execute Step C64. Otherwise, determine that the running result of t x is passed.

[0048] In the embodiments of the present invention, Steps C61 - C66 do not need to obtain the file size of the running log text information, and obtain test information by reading the running log text information from front to back, and obtain a preset failure text identifier by reading the running log text information from back to front. For most files of running log text information, it is not necessary to obtain the entire file of running log text information to accurately and quickly determine the situation where the running result is not passed.

[0049] As an embodiment, the Step C65 includes: Step C651, set the line number g to be processed as 1, and the total number of lines of the current text to be analyzed is G3.

[0050] It can be understood that in different situations, the total number of lines of the current text to be analyzed may be different, it may be G1, or it may be G2, or it may be less than G1, or it may be less than G2.

[0051] Step C652, obtain the g-th line text in the current text to be analyzed in the order from back to front, perform word segmentation processing on the g-th line text to obtain the word segmentation corresponding to the g-th line text. If there is a word segmentation of the preset failure text identifier, determine that the running result of t x is not passed. Otherwise, execute Step C653.

[0052] Among them, the word segmentation of the preset failure text identifier can be specifically set to "error". It should be noted that in the application scenario of the embodiments of the present invention, as long as the word segmentation of the preset failure text identifier appears in the running log text information, it can be determined that the running result is not passed.

[0053] Step C653, compare g and G3. If g = G3, execute Step C66. If g < G3, set g = g + 1 and return to Step C652.

[0054] In some cases, the word segmentation of the preset failure text identifier may be distributed on two lines. In this case, only through Steps C651 - C653, the word segmentation of the preset failure text identifier cannot be recognized, which may lead to misjudgment. To avoid the above situation, as an embodiment, the Step C65 includes: Step D651, set a candidate word segmentation combination {(A1, D1), (A2, D2),...,(A z , D z ),...,(AZ ,D Z )},(A z ,D z ) is the z-th group of candidate word segmentation combinations, where the value range of z is from 1 to Z, Z is the total number of candidate word segmentation combinations, and the total number of characters of the preset failure text identifier is Z + 1, A z and D z are concatenated to form the preset failure text identifier, and set the line number g to be processed as 1, and the total number of lines of the current text to be analyzed is G3.

[0055] Among them, taking the word segmentation of the preset failure text identifier as "error" as an example, {(A1, D1), (A2, D2),...,(A z ,D z ),...,(A Z ,D Z )} is {(e, rror), (er, ror), (err, or), (erro, r)}.

[0056] Step D652: Obtain the g-th line text in the current text to be analyzed in reverse order, perform word segmentation on the g-th line text to obtain the word segmentation corresponding to the g-th line text. If there is a word segmentation of the preset failure text identifier, then determine that the x running result is not passed; otherwise, execute step D653.

[0057] Step D653: Judge whether the first word segmentation is one of {(A1, D1), (A2, D2),...,(A z ,D z ),...,(A Z ,D Z )} D z . If so, set this D z as the target D z , set the A z corresponding to the target D z as the target A z , set g = g + 1, and execute step D654; otherwise, execute step D655.

[0058] Step D654: If g ≤ G3, then obtain the g-th line text in the current text to be analyzed in reverse order; if g = G3 + 1, then obtain the first unread text line in the running log text information corresponding to the current x as the g-th line text. Perform word segmentation on the g-th line text to obtain the word segmentation corresponding to the g-th line text. If the last word segmentation corresponding to the g-th line text is the target A z and / or there is a word segmentation of the preset failure text identifier in the g-th line text, then determine that xThe operation result is "failed", otherwise, execute step D655.

[0059] Step D655: Compare g and G3. If g = G3, execute step C66. If g < G3, set g = g + 1 and return to step D652.

[0060] It should be noted that through steps D651 - D655, all the word segmentations of the preset failure text identifiers of the currently to-be-analyzed text can be accurately analyzed, improving the accuracy of the operation result recognition.

[0061] As an embodiment, step S7 includes: Step S71: Generate a corresponding first chip regression test database based on the test case operation records of each chip regression test, and display the regression test results of each chip regression test in real time based on the first chip regression test database corresponding to each chip regression test.

[0062] It should be noted that through step S71, the regression test results of each chip regression test can be displayed in real time, facilitating the timely discovery of abnormalities in each chip regression test.

[0063] Step S72: When all the chip regression tests corresponding to the IP in the to-be-tested chip design y are completed, generate a second chip regression test database corresponding to the IP based on the test case operation records of all the chip regression tests corresponding to the IP in the to-be-tested chip design y and display the regression test results corresponding to the IP based on the second chip regression test database corresponding to the IP. The value range of y is from 1 to Y, where Y is the total number of IPs (Intellectual Property) in the to-be-tested chip design. y y y

[0064] It should be noted that each IP corresponds to a sub-design in the to-be-tested chip design. Through step S72, the abnormalities in the regression tests of each IP in the to-be-tested chip design can be timely discovered.

[0065] Step S73: When all the chip regression tests corresponding to all the IPs in the to-be-tested chip design y are completed, generate a third chip regression test database corresponding to the to-be-tested chip design based on the test case operation records of all the chip regression tests corresponding to all the IPs in the to-be-tested chip design y and display the regression test results corresponding to the to-be-tested chip design based on the third chip regression test database corresponding to the to-be-tested chip design.

[0066] ​​​It should be noted that through step S73, anomalies in regression testing can be detected in a timely manner from the perspective of the overall design of the chip under test.

[0067] As an embodiment, step S71 includes: Step S711: Obtain the passing rate of each chip regression test based on the test case execution records of each chip regression test.

[0068] Step S712: Store the test case execution records with failed execution results of each chip regression test and the passing rate of each chip regression test in the first chip regression test database.

[0069] Step S713: Display the test cases with failed execution results of each chip regression test and the passing rate of each chip regression test based on the first chip regression test database.

[0070] Step S714: Debug the corresponding functional points of each chip regression test based on the displayed test case execution records with failed execution results of each chip regression test and the passing rate of each chip regression test.

[0071] It should be noted that through steps S711 - S714, the passing rate of each chip regression test and the test case execution records with failed execution results can be presented in real time. Based on the passing rate of each chip regression test and the test case execution records with failed execution results, real-time analysis of the chip regression test can be performed.

[0072] As an embodiment, step S72 includes: Step S721: When all chip regression tests corresponding to the IP in the design of the chip under test y are completed, obtain the passing rate corresponding to the IP y in the design of the chip under test based on the test case execution records of all chip regression tests corresponding to the IP y in the design of the chip under test.

[0073] It should be noted that each test case has corresponding design configuration information of the design under test. Based on the design configuration information of the design under test, the IP corresponding to the test case can be determined.

[0074] Step S722: Store the test case execution records with failed execution results corresponding to the IP y in the design of the chip under test and the passing rate corresponding to the IP y in the design of the chip under test in the second chip regression test database.

[0075] Step S723: Display the test cases with failed execution results corresponding to each IP y in the design of the chip under test and the IPy The corresponding pass rate.

[0076] Step S724, based on each displayed IP y The test cases with corresponding running results being failures and the IP y Debug each IP based on the corresponding pass rate y .

[0077] It should be noted that through steps S721 - S724, the pass rate corresponding to each IP y and the running record of test cases with corresponding running results being failures can be presented. Based on the pass rate corresponding to each IP y and the running record of test cases with corresponding running results being failures, the chip regression test can be analyzed.

[0078] As an embodiment, the step S73 includes: Step S731, when all chip regression tests corresponding to all IPs in the chip design under test are completed, based on all IPs in the chip design under test y obtain the pass rate corresponding to the chip design under test based on the running records of test cases for all chip regression tests. y

[0079] Step S732, store the running records of test cases with corresponding running results being failures and the pass rate corresponding to the chip design under test for all IPs in the chip design under test into the third chip regression test database. y

[0080] Step S733, display the running records of test cases with corresponding running results being failures and the pass rate corresponding to the chip design under test for all IPs in the chip design under test based on the third chip regression test database. y

[0081] Step S734, debug the chip design under test based on the running records of test cases with corresponding running results being failures and the pass rate corresponding to the chip design under test for all IPs in the chip design under test displayed. y

[0082] It should be noted that through steps S731 - S734, the pass rate corresponding to each chip design under test and the running record of test cases with corresponding running results being failures can be presented. Based on the pass rate corresponding to each chip design under test and the running record of test cases with corresponding running results being failures, the chip regression test can be analyzed.

[0083] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts depict the steps as sequential processes, many of the steps can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operations are completed, but it can also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, and so on.

[0084] An embodiment of the present invention further provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0085] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions for executing the method described in the embodiment of the present invention.

[0086] In the embodiment of the present invention, by setting a unique test case reconstruction information data structure to generate a target test case reconstruction structure, the necessary information for generating test cases is hierarchically arranged in the test case reconstruction information data structure, and multi-level shared configuration information is extracted. The test cases are divided into test case groups, and all chip test cases for the chip design to be tested are generated by parsing the target test case reconstruction structure, which improves the construction efficiency and accuracy of chip test cases.

[0087] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the equivalent embodiments by using the disclosed technical content within the scope of the technical solution of the present invention. However, as long as the content does not depart from the technical solution of the present invention, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for constructing a chip test case, characterized in that Comprising: Step S1, construct the target test case reconstruction structure {C0, (C1, B1), (C2, B2),..., (C n , B n ),..., (C N , B N )}, where C0 is the shared test case configuration information corresponding to the chip design under test, C n is the shared test case configuration information corresponding to the nth sub - design of the chip design under test, B n is the list of the nth group of test case reconstruction information for the chip design under test. The value range of n is from 1 to N, and N is the total number of sub - designs of the chip design under test. B n = {F1 n , F2 n ,..., F i n ,..., F a(n) n}, where F i n is the ith test case reconstruction information in the list of the nth group of test case reconstruction information. The value range of i is from 1 to a(n), and a(n) is the total number of test case reconstruction information corresponding to B n ; Step S2: Analyze the reconstructed structure of the target test case to obtain C0, and then obtain each C in parallel n and B n ; Step S3: Parse each B in parallel n to obtain each F i n ; Step S4. Based on each F i n and F i n corresponding C n and C0, generate all chip test cases for the chip design to be tested.

2. The method according to claim 1, wherein Each F i n includes one or more of user identification, to-be-tested design configuration information, operating parameters, number of loops, test case groups, and running time; C0, C n includes one or more of to-be-tested design configuration information, operating parameters, number of loops, and running time.

3. The method according to claim 2, wherein The design configuration information to be measured is used to set the composition form of each component of the chip design to be measured. The composition form includes a first form and a second form. The first form is a form including component ports and internal logic, and the second form is a form only including component ports.

4. The method according to claim 2, wherein The design configuration information to be measured includes main configuration information and multiple slave configuration information. The main configuration information is the configuration information with the highest usage frequency. When no information is specified in the design configuration information to be measured, it is default set to the main configuration information. When it is necessary to set the slave configuration information, the corresponding slave configuration information needs to be specified in the design configuration information to be measured.

5. The method according to claim 2, wherein The operating parameters include environment variables, variables required for preset scripts, and options that need to be passed to the EDA tool during the running process of the chip test case.

6. The method according to claim 2, wherein The test case group includes at least one test case, and the test case group is divided based on chip function characteristics or based on the running time period.

7. The method according to claim 2, wherein The test case group further includes a first identifier and a second identifier. If it is set to the first identifier, the test cases in the test case group need to be generated during the current regression test process. If it is set to the second identifier, the test cases in the test case group do not need to be generated during the current regression test process.

8. The method according to claim 2, wherein Step S4 includes: Step S41: Obtain F i n corresponding user identifier and test case group {T1 in , T2 in ,..., T j in ,,..., T b(in) in}, T j in is the j-th test case information corresponding to F i n where the value range of j is from 1 to b(in), and b(in) is the number of test cases in the test case group corresponding to F i n ; Step S42: If there are preset parameters in F i n , then determine the preset parameters in F i n as the target parameters corresponding to T j in . Otherwise, execute Step S43. The preset parameters are the configuration information of the design to be tested, operating parameters, number of loops, test case group, or running time; Step S43: If there is a preset parameter in C n then determine the preset parameter in C n as the target parameter corresponding to T j in otherwise, execute Step S44; Step S44: If there is a preset parameter set in C0, then determine the preset parameter of C0 as the target parameter T, and execute Step S55; otherwise, generate a prompt message and end the process. j in ​ Step S45, based on each T j in , each T j in corresponding user identifier and each T j in corresponding all target parameters to generate each T j in corresponding test case.

9. An electronic device, characterized in that, Comprising: At least one processor; And a memory communicatively connected to the at least one processor; Wherein, the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method according to any one of the preceding claims 1-8.

10. A computer-readable storage medium, characterized in that, Stores computer-executable instructions, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1-8.

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