High-bandwidth signal transmission system and method

Abstract

The invention provides a high-bandwidth signal transmission system and method, and belongs to the technical field of signal transmission, and the system comprises a PCIE interface which is used for transmitting a digital signal input by an external memory to an internal storage unit, the internal storage unit is used for obtaining a descriptor corresponding to the digital signal based on the digital signal, and a read-write control unit, the central processor is in communication connection with the PCIE interface, the external memory, the internal memory unit and the central processor, and is used for realizing data interaction between the external memory and the internal memory unit through the PCIE interface by adopting a direct storage mode, writing a digital signal into the internal memory unit and then sending a first instruction to the central processor; and the processor is in communication connection with the internal storage unit and is used for obtaining the descriptor corresponding to the internal storage unit and obtaining the length of the digital signal received by the internal storage unit based on the descriptor corresponding to the internal storage unit and the descriptor corresponding to the digital signal after receiving the first instruction.

Description

Technical Field

[0001] The present invention relates to the technical field of signal transmission, and particularly to a high-bandwidth signal transmission system and method. Background Art

[0002] According to the Nyquist sampling theorem, the ADC of the sampling signal should be greater than twice the signal bandwidth, which makes the amount of data output by the ADC sampling relatively large. At the same time, with the development of wireless technology, the wireless signal bandwidth is getting larger and larger, and the number of channels is also increasing. Therefore, it has become increasingly difficult to transmit the ADC sampling data to the PC in real time for real-time processing.

[0003] In the traditional solution, the high-speed acquired ADC signal is stored in the local DDR, and the data is transmitted to the PC through a low-speed Ethernet method or the like. This method does not meet the real-time transmission requirement of the sampling signal. Therefore, there is a technical problem in the prior art that the sampling signal cannot be transmitted in real time. Summary of the Invention

[0004] In view of this, it is necessary to provide a high-bandwidth signal transmission system and method to solve the technical problem in the prior art that the sampling signal cannot be transmitted in real time.

[0005] To solve the above technical problem, on the one hand, the present invention provides a high-bandwidth signal transmission system, including: A PCIE interface, communicatively connected to an external memory and an internal storage unit, for transmitting the digital signal input by the external memory to the internal storage unit; An internal storage unit, for obtaining a descriptor corresponding to the digital signal based on the digital signal; the descriptor corresponding to the digital signal is: the starting address and length after the internal storage unit stores the digital signal; A read-write control unit, communicatively connected to the PCIE interface, the external memory, the internal storage unit, and the central processing unit, for realizing data interaction between the external memory and the internal storage unit by means of direct storage through the PCIE interface, and sending a first instruction to the central processing unit after writing the digital signal into the internal storage unit; A central processing unit, communicatively connected to the internal storage unit, for obtaining the descriptor corresponding to the internal storage unit, and based on the descriptor corresponding to the internal storage unit and the descriptor corresponding to the digital signal after receiving the first instruction, obtaining the length of the digital signal received by the internal storage unit; the descriptor corresponding to the internal storage unit is: the starting address and length of the storage space.

[0006] In a possible implementation manner, The read-write control unit is further configured to read the data in the internal storage unit to the external memory and then send a second instruction to the central processing unit; A central processing unit, after receiving a second instruction, is configured to obtain the length of the read data of the internal storage unit based on the descriptor corresponding to the internal storage unit and the descriptor for obtaining the read data of the internal storage unit; the descriptor corresponding to the read data of the internal storage unit is: the starting address and length of the read data of the internal storage unit.

[0007] In a possible implementation manner, the read-write control unit further includes: A signal acquisition card, communicatively connected to the PCIE interface, the internal storage unit, and the central processing unit, is configured to write digital signals into the internal storage unit through the PCIE interface and then send a first instruction to the central processing unit.

[0008] In a possible implementation manner, the read-write control unit further includes: A data pulling unit, communicatively connected to the PCIE interface, the internal storage unit, the external memory, and the central processing unit, is configured to read the data of the internal storage unit into the external memory through the PCIE interface and then send a second instruction to the central processing unit.

[0009] On the other hand, the present invention further provides a high-bandwidth signal transmission method, including: Transmitting digital signals input by an external memory to an internal storage unit through a PCIE interface; Obtaining a descriptor corresponding to the digital signal based on the digital signal by the internal storage unit; the descriptor corresponding to the digital signal is: the starting address and length after the digital signal is stored in the internal storage unit; Implementing data interaction between the external memory and the internal storage unit in a direct storage manner based on the PCIE interface by the read-write control unit, writing the digital signal into the internal storage unit and then sending a first instruction to the central processing unit; Obtaining the descriptor corresponding to the internal storage unit by the central processing unit, and after receiving the first instruction, obtaining the length of the digital signal received by the internal storage unit based on the descriptor corresponding to the internal storage unit and the descriptor corresponding to the digital signal; the descriptor corresponding to the internal storage unit is: the starting address and length of the storage space.

[0010] In a possible implementation manner, the method includes: Reading the data of the internal storage unit into the external memory by the read-write control unit and then sending a second instruction to the central processing unit; Obtaining the length of the read data of the internal storage unit by the central processing unit based on the descriptor corresponding to the internal storage unit and the descriptor for obtaining the read data of the internal storage unit; the descriptor corresponding to the read data of the internal storage unit is: the starting address and length of the read data of the internal storage unit.

[0011] In a possible implementation, the data interaction between the external memory and the internal storage unit is realized by the read-write control unit based on the PCIE interface in a direct storage manner. After writing the digital signal into the internal storage unit, a first instruction is sent to the central processor, including: The data interaction between the external memory and the internal storage unit is realized by the read-write control unit based on the PCIE interface in a direct storage manner. The storage space is divided into first-in-first-out queue data of multiple channels. The first-in-first-out queue data of each channel corresponds to a different type of data transmission. The first-in-first-out queue data of each channel is composed of multiple data circular buffer blocks of the same size; After the read-write control unit writes the digital signal into the circular buffer block of the digital first-in-first-out queue data corresponding to the internal storage unit, a first instruction is sent to the central processor.

[0012] In a possible implementation, when the read-write control unit reads the data of the internal storage unit into the external memory and sends a second instruction to the central processor, it includes: After the read-write control unit reads the data in the circular buffer block of the digital first-in-first-out queue data corresponding to the internal storage unit, a second instruction is sent to the central processor.

[0013] In a possible implementation, based on the descriptor corresponding to the internal storage unit and the descriptor corresponding to the digital signal, obtaining the length of the digital signal received by the internal storage unit includes: Subtracting the length corresponding to the digital signal from the length corresponding to the internal storage unit to obtain the length of the digital signal received by the internal storage unit.

[0014] In a possible implementation, based on the descriptor corresponding to the internal storage unit and obtaining the descriptor corresponding to the read data of the internal storage unit, obtaining the length of the read data of the internal storage unit includes: Subtracting the length corresponding to the output data of the internal storage unit obtained from the length corresponding to the internal storage unit to obtain the length of the read data of the internal storage unit.

[0015] The beneficial effects of the present invention are as follows: The high-bandwidth signal transmission system provided by the present invention includes: a PCIE interface, communicatively connected to an external memory and an internal storage unit, for transmitting digital signals input by the external memory to the internal storage unit; an internal storage unit, for obtaining a descriptor corresponding to the digital signal based on the digital signal; the descriptor corresponding to the digital signal is: the starting address and length after the internal storage unit stores the digital signal; a read-write control unit, communicatively connected to the PCIE interface, the external memory, the internal storage unit, and a central processor, for realizing data interaction between the external memory and the internal storage unit by means of direct storage through the PCIE interface, and sending a first instruction to the central processor after writing the digital signal into the internal storage unit; a central processor, communicatively connected to the internal storage unit, for obtaining the descriptor corresponding to the internal storage unit, and after receiving the first instruction, obtaining the length of the digital signal received by the internal storage unit based on the descriptor corresponding to the internal storage unit and the descriptor corresponding to the digital signal; the descriptor corresponding to the internal storage unit is: the starting address and length of the storage space. The present invention proposes a high-bandwidth signal transmission system, mainly realizing data interaction between the external memory and the internal storage unit by means of direct storage through the read-write control unit based on the PCIE interface, and notifying the central processor by sending a first instruction after writing the digital signal into the internal storage unit; after receiving the first instruction, the central processor obtains the length of the digital input signal received by the internal storage unit based on the descriptor corresponding to the internal storage unit and the descriptor corresponding to the digital signal, and sends the obtained digital signal to the central processor in real time by means of direct storage, meeting the requirement of real-time transmission of digital signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0017] Figure 1 FIG. is a schematic structural diagram of an embodiment of the high-bandwidth signal transmission system provided by the present invention; Figure 2 FIG. is a schematic flowchart of an embodiment of the high-bandwidth signal transmission method provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0019] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0020] In the embodiments of the present invention, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, device, product or equipment including a series of steps or modules does not necessarily have to be limited to those clearly listed steps or modules, but may include other steps or modules not clearly listed or inherent to these processes, methods, products or equipment.

[0021] In the embodiments of the present invention, the naming or numbering of steps does not mean that the steps in the method flow must be executed in the time / logical order indicated by the naming or numbering. The named or numbered process steps can change the execution order according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved.

[0022] Referring to "embodiments" herein means that the specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of the present invention. The phrase appears in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0023] The present invention provides a high-bandwidth signal transmission system and method, which will be described separately below.

[0024] Figure 1 FIG. is a schematic structural diagram of an embodiment of the high-bandwidth signal transmission system provided by the present invention, including: A PCIE (PCI-Express, high-speed serial computer expansion bus standard) interface 101, communicatively connected to an external memory and an internal storage unit 102, for transmitting digital signals input by the external memory to the internal storage unit 102; An internal storage unit 102, configured to obtain a descriptor corresponding to the digital signal based on the digital signal; the descriptor corresponding to the digital signal is: the starting address and length after the internal storage unit 102 stores the digital signal; The read / write control unit 103 is connected to the PCIE interface, the external memory, the internal storage unit 102 and the central processing unit 104 for communicating with each other, and is used to implement data interaction between the external memory and the internal storage unit 102 by direct storage through the PCIE interface, and send a first instruction to the central processing unit 104 after writing the digital signal into the internal storage unit 102; The central processing unit 104 is communicatively connected with the internal storage unit 102, and is used to obtain the descriptor corresponding to the internal storage unit 102, and after receiving the first instruction, obtain the length of the digital signal received by the internal storage unit 102 based on the descriptor corresponding to the internal storage unit 102 and the descriptor corresponding to the digital signal; the descriptor corresponding to the internal storage unit 102 is: the starting address and length of the storage space.

[0025] It can be understood that the main working process of the high-bandwidth signal transmission system provided by the present invention is as follows: Step 1. The HOST allocates a receive data buffer and a descriptor buffer, generates a descriptor from the receive data buffer information (buffer address and length), and writes the descriptor into the descriptor buffer.

[0026] Step 2: The HOST writes the descriptor buffer address, the descriptor generation pointer and the address of the sampling transfer completion pointer to the configuration interface through the PCIe interface.

[0027] Step 3: The descriptor pre-fetch module calculates the number of available ADC data receive descriptors based on the generated pointer and the locally stored completion pointer, and initiates a request to read the ADC (analog-to-digital converter) data receive descriptor to the HOST.

[0028] Step 4: Get the descriptor from the HOST and store it in the ADC data descriptor cache module.

[0029] Step 5: The ADC cross-clock domain conversion module combines the ADC sampling data of multiple channels into a set of data streams.

[0030] Step 6: The ADC data segmentation module segments the sampled data stream according to the descriptor order and length, and writes it into the PCIe data transmission cache module. The PCIe data transmission cache module initiates a write data request operation to PCIe based on the address and length of the ADC received data descriptor.

[0031] Step 7: After the data write operation is completed, the signal acquisition card writes the descriptor completion pointer to the HOST through the PCIe interface and sends a command request to the HOST.

[0032] Step 8: The HOST host receives an instruction, receives ADC sampling data according to the difference between the descriptor head pointer and the completion pointer, and releases the buffer for receiving the data.

[0033] It can be further understood that a high-bandwidth signal acquisition real-time DMA (Direct Memory Access) transmission system and method is a software and hardware collaborative working method. Its purpose is to perform DMA transmission on the sampled signals of the ADC (Analog-to-Digital Converter) and the broadband baseband signals generated by the HOST (host), reduce the CPU usage of the HOST host, and release the CPU performance to signal analysis. The DMA mechanism sends the sampled signals of the ADC (Analog-to-Digital Converter) to the host in real time to meet the real-time processing requirements of the sampled signals. At the same time, the HOST (host) generates broadband baseband signals and sends them to the DAC (Digital-to-Analog Converter) in real time to generate the required analog waveforms in real time.

[0034] In the direction of receiving the sampled signals of the ADC (analog-to-digital converter), the HOST host first generates a buffer (buffer area) for receiving the ADC sampling data. At the same time, it establishes a descriptor for the buffer for receiving the ADC sampling data and places it in the descriptor buffer. At the same time, it notifies the descriptor prefetch module of the head pointer of the descriptor buffer through the configuration interface. The descriptor prefetch module determines the number of buffers available for receiving the ADC sampling data according to the head pointer of the issued descriptor buffer and the tail pointer of the local write ADC sampling data completion buffer, and obtains the descriptors of the buffers for receiving the ADC sampling data. The ADC sampling data stream is cut according to the length of the descriptor of the buffer for receiving the ADC sampling data, and then transmitted to the HOST host according to the address of the descriptor of the buffer for receiving the ADC sampling data. After the data transmission is completed, it sends the completion pointer of the descriptor buffer for the ADC sampling data to the HOST host and sends an instruction at the same time. After receiving the instruction, the HOST can determine the buffer for the ADC sampling data that can be processed currently by querying the completion pointer and the head pointer of the descriptor buffer for the ADC sampling data. After the HOST finishes processing, it releases the corresponding buffer.

[0035] In some embodiments of the present invention, the system further includes: The read-write control unit 103 is further configured to read the data in the internal storage unit 102 to the external memory and then send a second instruction to the central processing unit 104; The central processing unit 104, after receiving the second instruction, is used to obtain the length of the read data of the internal storage unit 102 based on the descriptor corresponding to the internal storage unit 102 and the descriptor corresponding to the read data of the internal storage unit 102; the descriptor corresponding to the read data of the internal storage unit 102 is: the starting address and length of the read data of the internal storage unit 102.

[0036] It can be understood that the main working process of the high-bandwidth signal transmission system provided by the present invention is as follows: Step 1: The HOST host allocates a buffer for sending data and a descriptor buffer, writes the baseband signal data to be sent into the data buffer, and creates a data descriptor for sending data using the data buffer address and the length of the data.

[0037] Step 2: The HOST writes the descriptor of the data to be sent into the descriptor buffer.

[0038] Step 3: The HOST writes the descriptor buffer address, the descriptor generation pointer, and the address of the DAC (Digital-to-Analog Converter) data transmission completion pointer to the configuration interface module through the PCIe interface.

[0039] Step 4: The descriptor prefetch module calculates the number of available descriptors based on the generation pointer and the completion pointer stored locally, and initiates a request to read the DAC data descriptor from the HOST.

[0040] Step 5: Send the DAC data descriptor from the HOST and transfer the DAC send descriptor to the DAC descriptor cache module.

[0041] Step 6: The DAC data fetching module initiates a request to read DAC data from the HOST through the PCIe interface according to the data address and length in the descriptor in the order of the send descriptors.

[0042] Step 7: The DAC data merging module obtains the baseband data, caches the baseband data in the local buffer, and forwards it to the DAC data cross-clock domain conversion module.

[0043] Step 8: After the operation of reading the DAC data is completed, the DAC data fetching module writes the DAC data descriptor completion pointer to the HOST through the PCIe interface, and at the same time sends an instruction request to the HOST.

[0044] Step 9: The HOST host releases the send DAC data buffer according to the difference between the DAC data descriptor completion pointer and the head pointer.

[0045] It can be further understood that in the direction of the HOST (host) sending data to the DAC (digital-to-analog converter), the HOST first allocates a DAC data buffer (buffer), generates broadband baseband data and stores it in the DAC data buffer, generates a descriptor with the address and length of the data buffer, and writes it into the DAC data descriptor buffer. The head pointer of the DAC data descriptor buffer is written to the descriptor prefetch module through the configuration interface module. The descriptor prefetch module determines the number of DAC data buffers from which data can be obtained based on the head pointer and the local completion tail pointer, and obtains the descriptor. The DAC obtains the DAC baseband data according to the descriptor address and length. After the acquisition of the DAC baseband data is completed, the tail pointer and instruction of the DAC data descriptor buffer are sent to the HOST. The HOST determines to release the completed DAC data buffer according to the instruction and the completed tail pointer.

[0046] In some embodiments of the present invention, the read-write control unit 103 further includes: A signal acquisition card, communicatively connected to the PCIE interface 101, the internal storage unit 102, and the central processing unit 104, for writing digital signals into the internal storage unit 102 through the PCIE interface 101 and then sending a first instruction to the central processing unit 104.

[0047] It can be understood that a signal acquisition card, communicatively connected to the PCIE interface 101, the internal storage unit 102, and the central processing unit 104, for writing digital signals into the internal storage unit 102 through the PCIE interface 101 and then sending a first instruction to the central processing unit 104.

[0048] In some embodiments of the present invention, the read-write control unit 103 further includes: A data pull unit, communicatively connected to the PCIE interface 101, the internal storage unit 102, and the central processing unit 104, for reading the data in the internal storage unit 102 to an external memory through the PCIE interface 101 and then sending a second instruction to the central processing unit 104.

[0049] It can be understood that, and it can be further understood that, in the direction of the HOST (host) sending data to the DAC (digital-to-analog converter), the HOST host first allocates a DAC data buffer (buffer), generates broadband baseband data and stores it in the DAC data buffer, generates a descriptor with the address and length of the data buffer and writes it into the DAC data descriptor buffer. The head pointer of the DAC data descriptor buffer is written to the descriptor prefetch module through the configuration interface module. The descriptor prefetch module determines the number of DAC data buffers from which data can be obtained based on the head pointer and the local completion tail pointer, and obtains the descriptor. The DAC obtains the DAC baseband data according to the descriptor address and length. After the DAC baseband data is obtained, the tail pointer and instruction of the DAC data descriptor buffer are sent to the HOST host, and the HOST host determines to release the completed DAC data buffer according to the instruction and the completed tail pointer.

[0050] Figure 2 It is a schematic flowchart of an embodiment of the high-bandwidth signal transmission method provided by the present invention, including: S201. Transmit the digital signal input by the external memory to the internal storage unit through the PCIE interface; S202. Obtain the descriptor corresponding to the digital signal based on the digital signal through the internal storage unit; the descriptor corresponding to the digital signal is: the starting address and length after the digital signal is stored in the internal storage unit; S203. Realize the data interaction between the external memory and the internal storage unit in a direct storage manner based on the PCIE interface through the read-write control unit, and send a first instruction to the central processor after writing the digital signal into the internal storage unit; S204. After the central processor obtains the descriptor corresponding to the internal storage unit and receives the first instruction, based on the descriptor corresponding to the internal storage unit and the descriptor corresponding to the digital signal, obtain the length of the digital signal received by the internal storage unit; the descriptor corresponding to the internal storage unit is: the starting address and length of the storage space.

[0051] In some embodiments of the present invention, the method includes: Read the data in the internal storage unit to the external memory through the read-write control unit and send a second instruction to the central processor; based on the descriptor corresponding to the internal storage unit and the descriptor corresponding to the read data of the internal storage unit obtained by the central processor, obtain the length of the read data of the internal storage unit; the descriptor corresponding to the read data of the internal storage unit is: the starting address and length of the read data of the internal storage unit.

[0052] It can be understood that in the direction of the HOST (host) sending data to the DAC (digital-to-analog converter), the HOST first allocates a DAC data buffer (buffer), generates broadband baseband data and stores it in the DAC data buffer, generates a descriptor with the address and length of the data buffer, and writes it into the DAC data descriptor buffer. The head pointer of the DAC data descriptor buffer is written to the descriptor prefetch module through the configuration interface module. The descriptor prefetch module determines the number of DAC data buffers from which data can be obtained based on the head pointer and the local completion tail pointer, and obtains the descriptor. The DAC obtains the DAC baseband data according to the descriptor address and length. After the DAC baseband data is obtained, the tail pointer and instruction of the DAC data descriptor buffer are sent to the HOST. The HOST determines to release the completed DAC data buffer according to the instruction and the completed tail pointer.

[0053] In some embodiments of the present invention, the data interaction between the external memory and the internal storage unit is realized by the read-write control unit based on the PCIE interface in a direct storage manner. After writing the digital signal into the internal storage unit, a first instruction is sent to the central processing unit, including: The data interaction between the external memory and the internal storage unit is realized by the read-write control unit based on the PCIE interface in a direct storage manner. The storage space is divided into first-in-first-out queue data of multiple channels. The first-in-first-out queue data of each channel corresponds to a different type of data transmission. The first-in-first-out queue data of each channel is composed of multiple data circular buffer blocks of the same size; After the read-write control unit writes the digital signal into the circular buffer block of the digital first-in-first-out queue data corresponding to the internal storage unit, a first instruction is sent to the central processing unit.

[0054] It can be understood that a high-bandwidth signal acquisition real-time DMA (Direct Memory Access) transmission method is a software and hardware collaborative working method. Its purpose is to perform DMA transmission on the ADC sampling signal and the broadband baseband signal generated by the HOST (host), reduce the CPU usage of the HOST, and release the CPU performance to signal analysis. The DMA mechanism sends the ADC (Analog-to-Digital Converter) sampling signal to the host in real time to meet the real-time processing requirements of the sampling signal. At the same time, the HOST (host) generates a broadband baseband signal and sends it to the DAC (Digital-to-Analog Converter) in real time to generate the required analog waveform in real time.

[0055] In the direction of receiving the sampling signal of the ADC (Analog-to-Digital Converter), the HOST host first generates a buffer for receiving the ADC sampling data. At the same time, it creates a descriptor for the buffer of the received ADC sampling data and places it in the descriptor buffer. Then, it notifies the descriptor prefetch module of the head pointer of the descriptor buffer through the configuration interface. The descriptor prefetch module determines the number of buffers available for receiving the ADC sampling data based on the head pointer of the issued descriptor buffer and the tail pointer of the local buffer for writing the completed ADC sampling data, and obtains the descriptors of the buffers for receiving the ADC sampling data. The ADC sampling data stream is cut according to the length of the descriptor of the buffer for receiving the ADC sampling data, and then transmitted to the HOST host according to the address of the descriptor of the buffer for receiving the ADC sampling data. After the data transmission is completed, it sends the completion pointer of the descriptor buffer of the ADC sampling data to the HOST host and also sends an instruction. After receiving the instruction, the HOST can determine the buffer for processing the ADC sampling data by querying the completion pointer and the head pointer of the descriptor buffer of the ADC sampling data. After the HOST finishes processing, it releases the corresponding buffer.

[0056] In some embodiments of the present invention, the step of reading out the data in the internal storage unit to the external memory by the read-write control unit and sending a second instruction to the central processing unit includes: Reading out the data in the circular buffer block of the digital first-in-first-out queue data corresponding to the internal storage unit by the read-write control unit and then sending a second instruction to the central processing unit.

[0057] It can be understood that in the direction of the HOST (host) sending data to the DAC (Digital-to-Analog Converter), the HOST host first allocates a DAC data buffer (buffer area), generates broadband baseband data and stores it in the DAC data buffer, generates a descriptor for the address and length of the data buffer and writes it into the DAC data descriptor buffer. It writes the head pointer of the DAC data descriptor buffer to the descriptor prefetch module through the configuration interface module. The descriptor prefetch module determines the number of DAC data buffers for which data can be obtained based on the head pointer and the local completion tail pointer, and obtains the descriptors. The DAC obtains the DAC baseband data according to the descriptor address and length. After the DAC baseband data is obtained, it sends the tail pointer and an instruction of the DAC data descriptor buffer to the HOST host. The HOST host determines to release the completed DAC data buffer based on the instruction and the completed tail pointer.

[0058] In some embodiments of the present invention, the step of obtaining the length of the digital signal received by the internal storage unit based on the descriptor corresponding to the internal storage unit and the descriptor corresponding to the digital signal includes: Subtract the length corresponding to the digital signal from the length corresponding to the internal storage unit to obtain the length of the digital signal received by the internal storage unit.

[0059] It can be understood that a high-bandwidth signal acquisition real-time DMA (Direct Memory Access) transmission method is a software and hardware collaborative working method. Its purpose is to perform DMA transmission on the ADC sampling signal and the broadband baseband signal generated by the HOST (host), reduce the CPU usage of the HOST host, and release the CPU performance to signal analysis. The DMA mechanism sends the ADC (Analog-to-Digital Converter) sampling signal to the host in real time to meet the real-time processing requirements of the sampling signal. At the same time, the HOST (host) generates a broadband baseband signal and sends it to the DAC (Digital-to-Analog Converter) in real time to generate the required analog waveform in real time.

[0060] In the direction of receiving the ADC (Analog-to-Digital Converter) sampling signal, the HOST host first generates a buffer for receiving ADC sampling data. At the same time, it creates a descriptor for the buffer for receiving ADC sampling data and places it in the descriptor buffer. At the same time, it notifies the descriptor prefetch module of the head pointer of the descriptor buffer through the configuration interface. The descriptor prefetch module determines the number of buffers available for receiving ADC sampling data based on the head pointer of the issued descriptor buffer and the tail pointer of the local write ADC sampling data completion buffer, and obtains the descriptor of the buffer for receiving ADC sampling data. The ADC sampling data stream is cut according to the length of the descriptor of the buffer for receiving ADC sampling data, and then transmitted to the HOST host according to the address of the descriptor of the buffer for receiving ADC sampling data. After the data transmission is completed, it sends the completion pointer of the descriptor buffer for ADC sampling data to the HOST host and sends an instruction at the same time. After receiving the instruction, the HOST can determine the buffer for processing ADC sampling data currently available by querying the completion pointer and the head pointer of the descriptor buffer for ADC sampling data. After the HOST finishes processing, it releases the corresponding buffer.

[0061] In some embodiments of the present invention, the obtaining the length of the read data of the internal storage unit based on the descriptor corresponding to the internal storage unit and the descriptor of the obtained read data of the internal storage unit includes: Subtract the length corresponding to the output data of the obtained internal storage unit from the length corresponding to the internal storage unit to obtain the length of the read data of the internal storage unit.

[0062] It can be understood that in the direction of the HOST (host) sending data to the DAC (digital-to-analog converter), the HOST first allocates a DAC data buffer (buffer), generates broadband baseband data and stores it in the DAC data buffer, generates a descriptor from the address and length of the data buffer, and writes it into the DAC data descriptor buffer. The head pointer of the DAC data descriptor buffer is written to the descriptor prefetch module through the configuration interface module. The descriptor prefetch module determines the number of DAC data buffers from which data can be obtained based on the head pointer and the local completion tail pointer, and obtains the descriptor. The DAC obtains the DAC baseband data according to the descriptor address and length. After the acquisition of the DAC baseband data is completed, the tail pointer and instruction of the DAC data descriptor buffer are sent to the HOST. The HOST determines to release the completed DAC data buffer according to the instruction and the completed tail pointer.

[0063] The high-bandwidth signal transmission system and method provided by the present invention have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A high-bandwidth signal transmission system, characterized in that: include: A PCIE interface is connected to the external memory and the internal storage unit for transmitting the digital signal input from the external memory to the internal storage unit; An internal storage unit, used for obtaining a descriptor corresponding to the digital signal based on the digital signal; The descriptor corresponding to the digital signal is: the starting address and length of the internal storage unit after the digital signal is stored; A read / write control unit is connected to the PCIE interface, the external memory, the internal storage unit and the central processing unit for communicating with each other, and is used to implement data interaction between the external memory and the internal storage unit by direct storage through the PCIE interface, and to send a first instruction to the central processing unit after writing the digital signal into the internal storage unit; The central processing unit is communicatively connected with the internal storage unit, and is used to obtain a descriptor corresponding to the internal storage unit, and after receiving a first instruction, obtains the length of the digital signal received by the internal storage unit based on the descriptor corresponding to the internal storage unit and the descriptor corresponding to the digital signal; the descriptor corresponding to the internal storage unit is: the starting address and length of the storage space.

2. The high-bandwidth signal transmission system according to claim 1, characterized in that: The read / write control unit is also used to read the data of the internal storage unit into the external memory and then send a second instruction to the central processing unit; The central processing unit, after receiving the second instruction, is used to obtain the length of the data read out of the internal storage unit based on the descriptor corresponding to the internal storage unit and the descriptor corresponding to the read data of the internal storage unit; the descriptor corresponding to the read data of the internal storage unit is: the starting address and length of the read data of the internal storage unit.

3. The high-bandwidth signal transmission system according to claim 1, characterized in that: The read-write control unit further includes: The signal acquisition card is connected to the PCIE interface, the internal storage unit and the central processing unit for sending a first instruction to the central processing unit after writing the digital signal into the internal storage unit through the PCIE interface.

4. The high-bandwidth signal transmission system according to claim 3, characterized in that: The read-write control unit further includes: The data pulling unit is connected to the PCIE interface, the internal storage unit, the external memory and the central processing unit for sending a second instruction to the central processing unit after reading the data of the internal storage unit to the external memory through the PCIE interface.

5. A high-bandwidth signal transmission method, based on the high-bandwidth signal transmission system according to any one of claims 1 to 4, characterized in that: The method comprises: The digital signal input from the external memory is transmitted to the internal storage unit through the PCIE interface; Obtaining a descriptor corresponding to the digital signal based on the digital signal through the internal storage unit; the descriptor corresponding to the digital signal is: the starting address and length of the digital signal after the internal storage unit stores the digital signal; The data exchange between the external memory and the internal storage unit is realized by using a read-write control unit based on a PCIE interface in a direct storage manner, and a first instruction is sent to the central processing unit after the digital signal is written into the internal storage unit; The descriptor corresponding to the internal storage unit is obtained through the central processing unit, and after receiving the first instruction, the length of the digital signal received by the internal storage unit is obtained based on the descriptor corresponding to the internal storage unit and the descriptor corresponding to the digital signal; the descriptor corresponding to the internal storage unit is: the starting address and length of the storage space.

6. The high-bandwidth signal transmission method according to claim 5, characterized in that: The method comprises: After the data of the internal storage unit is read out to the external memory by the read-write control unit, a second instruction is sent to the central processing unit; The length of the data read out of the internal storage unit is obtained by the central processing unit based on the descriptor corresponding to the internal storage unit and the descriptor corresponding to the read data of the internal storage unit; the descriptor corresponding to the read data of the internal storage unit is: the starting address and length of the read data of the internal storage unit.

7. The high-bandwidth signal transmission method according to claim 5, characterized in that: The method of implementing data interaction between the external memory and the internal storage unit by using a direct storage method based on a PCIE interface through a read / write control unit, and sending a first instruction to a central processing unit after writing a digital signal into the internal storage unit, includes: The data interaction between the external memory and the internal storage unit is realized by using a direct storage method based on the PCIE interface through the read-write control unit, and the storage space is divided into first-in-first-out queue data of multiple channels. The first-in-first-out queue data of each channel corresponds to a different type of data transmission, and multiple data circular cache blocks of the same size constitute the first-in-first-out queue data of each channel; The digital signal is written into the circular cache block of the digital first-in first-out queue data corresponding to the internal storage unit through the read-write control unit, and then the first instruction is sent to the central processing unit.

8. The high-bandwidth signal transmission method according to claim 6, characterized in that: The method of reading the data of the internal storage unit to the external memory and sending the second instruction to the central processing unit through the read-write control unit includes: The data in the circular cache block of the digital first-in first-out queue data corresponding to the internal storage unit is read out through the read-write control unit and then a second instruction is sent to the central processing unit.

9. The high-bandwidth signal transmission method according to claim 5, characterized in that: The obtaining, based on the descriptor corresponding to the internal storage unit and the descriptor corresponding to the digital signal, the length of the digital signal received by the internal storage unit comprises: The length corresponding to the internal storage unit is subtracted from the length corresponding to the digital signal to obtain the length of the digital signal received by the internal storage unit.

10. The high-bandwidth signal transmission method according to claim 6, characterized in that: The method of obtaining the length of the data read out of the internal storage unit based on the descriptor corresponding to the internal storage unit and the descriptor corresponding to the read data of the internal storage unit comprises: The length corresponding to the internal storage unit is subtracted from the length corresponding to the output data of the internal storage unit to obtain the length of the data read out of the internal storage unit.

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