Register addressing method, device, electronic device and storage medium

Abstract

The present application discloses a register addressing method, device, electronic device and storage medium, which relate to the field of server technology, including: after receiving the starting address data sent by the master device, the slave device first determines in which address mode the starting address data is transmitted based on the starting address data, that is, determines the target address mode. Then, when it is determined based on the target address mode that the device address data corresponding to the target address mode is received, the target address can be extracted from the device address data based on the target address mode. Furthermore, when it is determined that the target address is consistent with the slave device address, it means that the slave device addressing is correct. When a register address matching the target address mode is received, subsequent operations can be performed on the function register corresponding to the register address addressing. By analyzing the starting address data and determining the target address mode, the slave device can flexibly switch the address mode, which is more convenient.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a register addressing method, device, electronic device, and storage medium. Background Art

[0002] In the field of server technology, the baseboard management controller (BMC) and complex programmable logic device (CPLD) are two key components. Communication between the BMC and CPLD is typically achieved through the I2C (Inter-Integrated Circuit) bus. Using a single-byte address mode results in low data transmission efficiency, while using a multi-byte address mode requires the use of multiple CPLDs, increasing hardware costs. Therefore, hardware configuration is typically tailored to actual needs, or address modes are manually switched, which is inconvenient. Summary of the Invention

[0003] The present application provides a register addressing method, device, electronic device, storage medium, and program product to solve the problem of inconvenience in address mode switching.

[0004] The present application provides a register addressing method, which is applied to a data transmission system, the data transmission system including a master device and a slave device, and is executed by the slave device. The method includes:

[0005] Receive the start address data of preset length sent by the master device;

[0006] According to the starting address data, determining a target address mode corresponding to the starting address data;

[0007] When it is determined that device address data corresponding to the target address pattern is received according to the target address pattern, a target address is extracted from the device address data according to the target address pattern;

[0008] When it is determined that the target address matches the address of the slave device and a register address matching the target address pattern is received, a function register corresponding to the register address is determined from a plurality of registers in the slave device according to the register address so as to perform a service operation on the function register.

[0009] The present application also provides a register addressing device, which is applied to a data transmission system, wherein the data transmission system includes a master device and a slave device, and the device includes:

[0010] A receiving module, configured to receive starting address data of a preset length sent by a master device;

[0011] A determination module, configured to determine a target address mode corresponding to the start address data according to the start address data;

[0012] an extraction module for extracting a target address from the device address data according to the target address pattern when it is determined that device address data corresponding to the target address pattern is received according to the target address pattern;

[0013] The determination module is also used to determine, when it is determined that the target address matches the address of the slave device and a register address matching the target address pattern is received, a function register corresponding to the register address from a plurality of registers of the slave device according to the register address, so as to perform business operations on the function register.

[0014] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned register addressing methods when executing the computer program.

[0015] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned register addressing methods are implemented.

[0016] The present application also provides a computer program product, comprising a computer program, which implements the steps of any of the above-mentioned register addressing methods when executed by a processor.

[0017] Through the present application, after receiving the starting address data sent by the master device, the slave device first determines in which address mode the starting address data is transmitted based on the starting address data, that is, determines the target address mode. Then, when it is determined based on the target address mode that the device address data corresponding to the target address mode is received, the target address can be extracted from the device address data based on the target address mode. Furthermore, when it is determined that the target address is consistent with the slave device address, it means that the slave device addressing is correct. When a register address matching the target address mode is received, subsequent operations can be performed based on the function register corresponding to the register address addressing. By analyzing the starting address data and determining the target address mode, the slave device can flexibly switch the address mode, which is more convenient. Specifically, when efficient data transmission is required, there is no need to set up extra slave devices, but directly switch to the corresponding address mode, which can save hardware costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 A schematic diagram of the architecture of a data transmission system provided in an embodiment of the present application;

[0020] Figure 2 A flowchart of a register addressing method provided in an embodiment of the present application;

[0021] Figure 3 A flowchart of another register addressing method provided in an embodiment of the present application;

[0022] Figure 4 A schematic diagram of a state switching process of a state machine provided in an embodiment of the present application;

[0023] Figure 5 A schematic diagram of signal transmission for correctly transmitting an address in a 7-bit address mode provided in an embodiment of the present application;

[0024] Figure 6 A schematic diagram of the architecture of signal transmission of an erroneous transmission address in a 7-bit address mode provided by an embodiment of the present application;

[0025] Figure 7 A schematic diagram of signal transmission of an erroneous transmission address in a 10-bit address mode provided in an embodiment of the present application;

[0026] Figure 8 A schematic diagram of the architecture of signal transmission for correctly transmitting an address in a 10-bit address mode provided by an embodiment of the present application;

[0027] Figure 9 A schematic structural diagram of a register addressing device provided in an embodiment of the present application;

[0028] Figure 10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0031] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0032] The register addressing method provided in this application can be implemented by a data transmission system, such as Figure 1 As shown, the data transmission system may include a master device and a slave device. The master device may be a baseboard management controller (BMC) in a server, and the slave device may be a complex programmable logic device (CPLD) in the server. Data transmission between the master and slave devices can be performed using various address modes. The slave device may include multiple registers, such as status registers, function registers, and error type registers. The status register is used to set the address mode, the function register can be used to record functional data, such as temperature data and voltage data, and the error type register is used to record error flags.

[0033] The embodiment of the present application provides a register addressing method that can be executed by a slave device, such as Figure 2 As shown, the specific processing steps of the register addressing method may include:

[0034] Step S201: receiving start address data of a preset length sent by a master device.

[0035] The preset length may be one byte.

[0036] Specifically, when the master device receives a read instruction (for example, an operation instruction received from another device, or an operation instruction obtained based on its own data processing mechanism), it can parse the address range of the register address, the slave device identification information, and the operation type. Furthermore, based on this address range, a third address mode corresponding to the address range can be determined, and the slave device address can be determined based on the slave device identification information and the third address mode (specifically, the device address of the slave device in multiple address modes can be obtained based on the slave device identification information, and the device address matching the third address mode can be selected as the slave device address). Finally, based on the third address mode, the master device can process the register address and the slave device address according to the third address mode, generate an address frame corresponding to the third address mode, and send data to the slave device based on the address frame. On the master device side, the master device only needs to generate an address frame according to the corresponding address mode and send a signal to the slave device based on the address frame. This allows the slave device to switch address modes after parsing the received signal. This allows flexible address mode switching without adding new slave devices or performing manual operations, making it more convenient.

[0037] When the slave device detects the start signal sent by the master device, it starts to receive data. Each time it receives data of a preset length, it can perform corresponding processing and send a response signal to the master device.

[0038] For example, the third address mode can be the first address mode or the second address mode. The first address mode can be a 7-bit address mode, and the second address mode can be a 10-bit address mode. The operation type can be a read operation or a write operation. When the address mode is the first address mode, the address frame structure can be: start bit (S) + 7-bit slave address + read / write (R / W) bit + single-byte register address + response signal bit. The response signal bit can be the first signal bit, and the first signal can be an acknowledgment (ACK) signal. When the address mode is the second address mode, the address frame structure can be: start bit + flag bit + slave high address + read / write bit + slave low address + response signal bit = register address + double-byte register address + response signal bit.

[0039] Step S202: determining a target address mode corresponding to the start address data according to the start address data.

[0040] Specifically, when the master device receives data of a preset length after detecting the start signal, it determines that the start address data has been received. At this time, the slave device can analyze the start address data to determine in which address mode the start address data is transmitted. Accordingly, the specific process of analyzing the start address data may include the following steps:

[0041] Step 1: Determine whether the starting address data matches any one of the preset multiple configuration rules.

[0042] The starting address data may include multiple actual numerical values, and the configuration rule may include at least one bit identification information and a configuration value corresponding to each bit identification information.

[0043] Step 1: According to the target bit identification information, determine the target bit corresponding to the target bit identification information in the starting address data.

[0044] The target bit identification information may be any bit identification information included in the first configuration rule, and the first configuration rule is any configuration rule among multiple configuration rules.

[0045] Step 2: Extract the target actual value from the target bit.

[0046] Step 3: When it is determined that the target actual value is consistent with the configuration value corresponding to the target bit identification information, the comparison result corresponding to the target bit identification information is determined to be passed.

[0047] Step 4: When the comparison results corresponding to all the bit identification information in the first configuration rule are all passed, the first configuration rule is determined as the target configuration rule that matches the start address data.

[0048] Step 2: When it is determined that the format of the start address data matches the target configuration rule, an address mode corresponding to the target configuration rule is determined according to the target configuration rule.

[0049] The target configuration rule is one of multiple configuration rules.

[0050] Step three: determine the address mode corresponding to the target configuration rule as the target address mode corresponding to the start address data.

[0051] Specifically, in step one, the above-mentioned configuration rules may be stored in the slave device. When the slave device receives the starting address data, the configuration rules may be matched with the starting address data according to the arrangement order of the configuration rules (method one), or various configuration rules may be matched with the starting address data separately in a parallel manner (method two).

[0052] The following describes the matching process between the first configuration rule and the start address data as an example.

[0053] The slave device can extract the target actual value from the target bit of the starting address data based on the target bit identification information and determine whether the extracted target actual value is consistent with the configuration value corresponding to the target bit identification information. If so, the comparison result corresponding to the target bit identification information can be determined to be passed; if not, the comparison result corresponding to the target bit identification information can be determined to be failed. In this way, after completing the matching operation corresponding to each bit identification information in the first configuration rule, it can be determined whether the comparison results corresponding to all bit identification information in the first configuration rule are all passed. If so, it can be determined that the starting address data matches the first configuration rule, and the first configuration rule here is the target configuration rule. If not, it can be determined that the starting address data does not match the first configuration rule. Under the first processing method, when it is determined that the starting address data does not match the first configuration rule, the configuration rules arranged after the first configuration rule can be matched until a target configuration rule that matches the starting address data is determined, or after all configuration rules have been matched, the matching operation can be stopped. Under the second processing method, after completing the matching operation for all configuration rules, the configuration rule with a passing comparison result is used as the target configuration rule. In either the first or second method, after completing the matching operations corresponding to all configuration rules, if the target configuration rule is not determined, an interrupt signal may be sent to the master device to indicate an address matching error.

[0054] In step 2, when it is determined that the format of the start address data matches the target configuration rule, the slave device may determine the address mode corresponding to the target configuration rule according to the target configuration rule and the correspondence between the configuration rule and the address mode.

[0055] In step three, the slave device may determine the address mode corresponding to the target configuration rule as the target address mode corresponding to the starting address data, and set the address mode of the slave device based on the target address mode to switch the addressing range of the register to match the target address mode. Specifically, the operation of setting the address mode of the slave device may be: the slave device may include a status register, and when the target address mode is determined, the status register may be set to a value corresponding to the target address mode. For example, when the target address mode is the first address mode, the value of the status register may be set to a first value (which may be 0), or when the target address mode is the second address mode, the value of the status register may be set to a second value (which may be 1).

[0056] Through this matching operation, the current address mode can be accurately determined, allowing the address processing method to be dynamically switched without manual address mode configuration. In addition, the configuration rules are organized in the form of "bit identification information + configuration value", so when adding a new address mode, only new configuration rules need to be added, without modifying the existing logical structure, which has good scalability.

[0057] In some optional implementations, the slave device may pre-determine the priority of each configuration rule based on the number of bit identifiers included in each configuration rule (the fewer the number, the higher the priority). The slave device then sorts the configuration rules from high to low priority based on the priority of each configuration rule to determine the order of each configuration rule. Because fewer bit identifiers result in a faster matching process, sorting by number of bit identifiers allows subsequent matching to begin with the highest priority and cease matching once a match is found, avoiding unnecessary computation and conserving resources.

[0058] Step S203 : when it is determined that device address data corresponding to the target address pattern is received according to the target address pattern, the target address is extracted from the device address data according to the target address pattern.

[0059] Specifically, after each time the master device sends data of a preset length, it will wait for a response signal. When it detects that the response signal is the first signal, it will continue to send data of the next preset length. In addition, after determining the target address mode, the slave device can determine whether the device address data corresponding to the target address mode is received based on the target address mode. For example, it can determine whether the device address data of the length corresponding to the target address mode is received based on the target address mode. When the target address mode is the first address mode, the starting address data is determined as the device address data corresponding to the target address mode. Alternatively, when the target address mode is the second address mode, after receiving the starting address data, when address data of a preset length is received again, the starting address data and the address data of the preset length received again are jointly determined as the device address data corresponding to the target address mode. Accordingly, the specific steps for extracting the target address from the slave device based on the target address mode may include:

[0060] Step 1: According to the target address pattern, determine the address extraction position information corresponding to the target address pattern.

[0061] Specifically, the slave device may store address extraction position information corresponding to each address pattern, and after determining the target address pattern, the address extraction position information corresponding to the target address pattern may be determined from the address extraction position information. The address extraction position information may include at least one bit identification information.

[0062] Step 2: extract the address location information based on the address, extract the value from the position corresponding to the address extraction location information in the device address data, and form the target address.

[0063] In case 1, when the target address mode is the first address mode, the device address data is the starting address data. According to the address extraction position information, a value is directly extracted from the position corresponding to the address extraction position information in the starting address data to form the target address.

[0064] In the second scenario, when the target address mode is the second address mode, the device address data includes starting address data and padding address data. The padding address data is data of a preset length received after the starting address data. Based on the address extraction position information, the value corresponding to the address extraction position information in the starting address data is extracted as the high-order address (i.e., the slave device high address), and the padding address data is used as the low-order address (i.e., the slave device low address). The target address is generated based on the high-order and low-order addresses.

[0065] Specifically, when extracting the numerical value, each bit identification information included in the address extraction location information may be extracted, and the numerical value corresponding to each bit identification information may be extracted from the device address data.

[0066] In the above scheme, the address extraction position information is defined based on the "bit identification information" to ensure that only valid address bits are extracted, thereby improving the accuracy of address matching and avoiding addressing failures caused by incorrect extraction of invalid bits.

[0067] In some optional implementations, the slave device may extract the value of the read / write bit from the target bit of the start address data. For example, the target bit may be the lowest bit in the start address data.

[0068] Step S204: When it is determined that the target address matches the address of the slave device and a register address matching the target address pattern is received, a function register corresponding to the register address is determined from a plurality of registers of the slave device according to the register address, so as to perform a service operation on the function register.

[0069] Specifically, when the slave device determines that the extracted target address matches its own address, it determines that it has received an instruction to operate on itself. At this time, it can send a first signal to the master device. Alternatively, when the slave device determines that the extracted target address does not match its own address, it can determine that it has received an instruction to operate on another slave device and send a second signal to the master device. In addition, the error flag of the error type register can be updated to a value corresponding to the slave device address mismatch to facilitate subsequent error analysis. The second signal is used to indicate an address mismatch. The second signal can be a negative acknowledgement (NACK) signal.

[0070] When the master device detects the first signal, it will continue to send the register address to the slave device. When it detects the second signal, it can send a third signal to the slave device. The third signal can be a stop signal (P) to indicate the end of the current data transmission.

[0071] When a register address is received from a device, it can be determined whether the register address matches the target address pattern. This can be determined in two ways:

[0072] Method 1: Determine whether the length of the register address is consistent with the length corresponding to the target address pattern. If so, determine that the register address matching the target address pattern is received; if not, determine that the register address matching the target address pattern is not received.

[0073] Method 2: According to the target address pattern, the target address range corresponding to the target address pattern is determined, and then it can be determined whether the register address is within the target address range. If so, it is determined that a register address matching the target address pattern is received; if not, it is determined that a register address matching the target address pattern is not received.

[0074] When determining that the register address matches the target address pattern based on the above two methods, the functional register that matches the register address can be determined from the multiple registers included in the slave device based on the register address in the target address mode, so that the functional register can be subsequently subjected to a business operation corresponding to the operation type based on the operation type. For example, when the operation type is read, the business operation is a read operation, or, when the operation type is write, the business operation is a write operation.

[0075] Alternatively, upon determining that a register address matching the target address pattern has been received, the slave device may send a first signal to the master device. Upon detecting the first signal, the master device may send a third signal to the slave device. Upon detecting the third signal, the slave device may determine that the current data transmission process has ended. Alternatively, upon determining that a register address matching the target address pattern has not been received, the slave device may send a second signal to the master device. Upon detecting the second signal, the master device may determine that an error has occurred and, in this case, proactively send a third signal to the slave device. Upon detecting the third signal, the slave device may determine that the current data transmission process has ended.

[0076] In some optional embodiments, when the slave device determines that it has not received a register address that matches the target address pattern, the slave device can send an interrupt signal to the master device to indicate an address matching error so that the master device can make subsequent processing in a timely manner, for example, resend relevant information.

[0077] In the register addressing method of the embodiment of the present application, after the slave device receives the starting address data sent by the master device, it first determines in which address mode the starting address data is transmitted based on the starting address data, that is, determines the target address mode. Then, when it is determined based on the target address mode that the device address data corresponding to the target address mode is received, the target address can be extracted from the device address data based on the target address mode. Furthermore, when it is determined that the target address is consistent with the slave device address, it means that the slave device addressing is correct. When the register address that matches the target address mode is received, subsequent operations can be performed based on the function register corresponding to the register address addressing. By analyzing the starting address data and determining the target address mode, the slave device can flexibly switch the address mode, which is more convenient. Specifically, when efficient data transmission is required, there is no need to set up redundant slave devices, but directly switch to the corresponding address mode, which can save hardware costs.

[0078] The following is a detailed description of the execution process of the above register addressing method using a specific example. The process can be as follows: Figure 3 shown.

[0079] On the master device side, when the master device detects that the register address to be addressed is in the range [0, 255], it determines that the data length to be transmitted is a single byte and enables 7-bit addressing mode. In this case, it can generate a 7-bit address frame that complies with the I2C standard (for the specific structure, refer to the address frame structure corresponding to the first address mode described above). Alternatively, when the master device detects that the register address to be addressed is in the range [256, 65535], it enables 10-bit addressing mode and determines that the data length to be transmitted is a double byte. In this case, it can generate a 10-bit address frame that complies with the I2C standard (for the specific structure, refer to the address frame structure corresponding to the second address mode described above). After generating the address frame, the master device can send a signal to the slave device according to the address frame.

[0080] When configuring the slave device address, you can configure it as follows to avoid address conflicts: (1) The 7-bit slave device address can be limited to 0x08-0x77 (to avoid prefix conflicts between reserved addresses and the first byte in the 10-bit address frame); (2) The slave device high address in the first byte is forced to be mapped to 0b00-0b11, ensuring that the first byte falls in the range of 0xF0-0xF3.

[0081] On the slave side, when the slave detects the falling edge of the Serial Data Line (SDA) signal while the Serial Clock Line (SCL) signal is high, it detects the start signal, signaling the start of new data transmission. When the first byte of data is received, it determines whether the highest bit in the first byte is 0. If so, it determines that 7-bit addressing mode is currently in use, and the first 7 bits of the first byte are used as the slave address. At this point, the status register is set to 0, switching the register's addressing range to [0, 255]. If not, it checks whether the highest 5 bits of the first byte are 11110. If so, it determines that 10-bit addressing mode is currently in use, and bits 6 and 7 (often represented as bits [2:1]) of the first byte are used as the high slave address. When the second byte of data is received, the 8-bit value of the second byte is used as the low slave address. The slave address is then constructed from the high and low slave addresses. In addition, when it is determined that the current addressing mode is 10-bit, the value of the status register can be set to 1 to switch the addressing range of the register to [256, 65535]. The last bit (i.e., the 8th bit) in the first byte of data is used to indicate the operation type.

[0082] After determining the slave device address, the slave device can determine whether the determined slave device address is consistent with its own address. If so, it can continue to receive subsequent register addresses. If not, it can stop receiving subsequent data, for example, it can send a NACK signal to the master device.

[0083] After the master device receives the register address, the slave device can determine whether the address range to which the received register address belongs is consistent with the address range indicated by the current status register. If so, the slave device can determine the register corresponding to the register address based on the register address, and perform read and write operations corresponding to the operation type on the determined register based on the operation type, for example, reading data information and feeding it back to the master device. If not, error handling operations can be performed, including: immediately pulling down the SDA line to forcibly terminate the transmission, updating the error flag of the error type register to a value corresponding to the register address matching error, storing this register address in the DEBUG register for subsequent analysis to determine the source of the error and avoid further errors, and sending an interrupt signal to the master device.

[0084] The state machine can be set in the slave device. The state machine can be in the idle state (IDLE) and the detection state (DETECT). Among them, when the state machine is in the idle state and the address mode is determined, it can jump to the detection state to switch the address mode. It should be noted that the two address modes cannot be switched directly. After each data transmission is completed, it can jump back to the idle state and wait for the next transmission. The state switching process of the state machine can be as follows Figure 4 shown.

[0085] The following two specific examples illustrate the specific process of the master device and the slave device cooperating with each other to complete register addressing.

[0086] Example 1: The master device needs to address the function register at register address "0x55" on the slave device at address "0x28".

[0087] The master device sends a start signal and then sends the first byte of data, namely the 7-bit slave device address and 1-bit read / write bit. After receiving the first byte of data, the slave device feeds back an ACK signal. After detecting the ACK signal, the master device sends a single-byte register address to the slave device and sends a stop signal. After the slave device detects the stop signal, it determines whether the received register address is within the address range indicated by the current address mode. If so, subsequent read and write operations can continue. Accordingly, the level signals transmitted on SCL and SDA can be as follows: Figure 5 If not, error handling can be performed and the level signals transmitted on SCL and SDA can be as follows: Figure 6 shown.

[0088] For example, if the slave device address is "0x28" and the write flag is "0", the master device can shift one bit to the left, empty the lowest bit and set it to 0 to generate the first byte of data "0x50". The operation process can be expressed as "0x28<<1|0=0x50". When the slave device receives the first byte of data, it can use the opposite operation method to determine the slave device address "0x28" and the write flag "0". Among them, "0x28" can be converted to binary and expressed as "00101000", with the highest bit being "0". From this, it can be determined that the current address mode is 7-bit address mode and the register address length is single byte. Figure 5 In the example, the slave device receives a single byte of register address "0x55". Figure 6 In the example, the slave device receives an extra address "0xAA", determines that the received register address exceeds the address range corresponding to the 7-bit address mode, sends a NACK signal to the master device, and sets the error flag of the error type register (for example, ERR_CODE = 0x01).

[0089] Example 2: The master device needs to address the function register at the register address (0x33, 0x44) of the slave device at address 0x1A0.

[0090] The master device sends a start signal and then sends the first byte of data. After receiving the first byte of data, the slave device feeds back an ACK signal to the master device. After detecting the ACK signal, the master device continues to send the second byte of data. After receiving the second byte of data, the slave device can feed back an ACK signal to the master device, and can extract the slave device high address from the first byte of data and the slave device low address from the second byte of data to form the slave device address. After determining the slave device address, it can be determined whether the slave device address is consistent with the current slave device address. If they are inconsistent, a NACK signal can be sent to the master device, and the error flag of the error type register can be set (for example, ERR_CODE=0x04), and the device enters the IDLE state to wait for a stop signal. After receiving the NACK signal, the master device actively stops data transmission and sends a stop signal to the slave device. Figure 7 As shown in the figure, the address determined by "0xF1" and "0xB0" is not "0x1A0". If they are consistent, an ACK signal can be sent to the master device. After the master device detects the ACK signal, it can send the start signal again (that is, Figure 8 After the repeated start (Sr) in the signal, the data of the first byte is sent again, followed by the register address of the first byte (0x33), and so on, and then the register address of the second byte (0x44), and finally the stop signal is sent. Accordingly, the level signals transmitted on SCL and SDA can be as follows Figure 8shown.

[0091] exist Figure 8 In this example, the first byte sent by the master device might be "0xF1," which converts to binary "11110001." The first five bits indicate a 10-bit address mode. The second byte is "0xA0," which converts to binary "10100000." Combining the seventh and eighth bits of the first byte with the second byte yields "0110100000," which converts to hexadecimal "0x1A0." The register address received by the master device is (0x33, 0x44), which is within the address range corresponding to 10-bit address mode, that is, [256, 65535].

[0092] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0093] The embodiment of the present application also provides a register addressing device, such as Figure 9 Shown, including:

[0094] The receiving module 910 is configured to receive the start address data of a preset length sent by the master device;

[0095] A determination module 920 is configured to determine a target address mode corresponding to the start address data based on the start address data;

[0096] an extraction module 930 for extracting a target address from the device address data according to the target address pattern when it is determined that device address data corresponding to the target address pattern has been received according to the target address pattern;

[0097] The determination module 920 is also used to determine, when it is determined that the target address matches the address of the slave device and a register address matching the target address pattern is received, a function register corresponding to the register address from a plurality of registers of the slave device according to the register address, so as to perform business operations on the function register.

[0098] In some optional implementations, the determination module 920 is specifically configured to:

[0099] Determining whether the starting address data matches any one of a plurality of preset configuration rules;

[0100] When it is determined that the starting address data matches the target configuration rule, determining an address pattern corresponding to the target configuration rule according to the target configuration rule, wherein the target configuration rule is one of the multiple configuration rules;

[0101] An address pattern corresponding to the target configuration rule is determined as a target address pattern corresponding to the start address data.

[0102] In some optional implementations, the starting address data includes multiple actual numerical values, and the configuration rule includes at least one bit identification information and a configuration value corresponding to each bit identification information;

[0103] The determination module 920 is specifically configured to:

[0104] Determining, in the start address data, a target bit corresponding to the target bit identification information according to the target bit identification information, wherein the target bit identification information is any bit identification information included in the first configuration rule, and the first configuration rule is any configuration rule among the plurality of configuration rules;

[0105] Extract the target actual value from the target position;

[0106] When it is determined that the target actual value is consistent with the configuration value corresponding to the target bit identification information, the comparison result corresponding to the target bit identification information is determined to be passed;

[0107] When the comparison results respectively corresponding to all the bit identification information in the first configuration rule are all passed, the first configuration rule is determined as the target configuration rule that matches the start address data.

[0108] In some optional implementations, the extraction module 930 is specifically configured to:

[0109] According to the target address pattern, determining the address extraction position information corresponding to the target address pattern;

[0110] According to the address extraction position information, a numerical value is extracted from a position corresponding to the address extraction position information in the device address data to form a target address.

[0111] In some optional implementations, when the target address mode is the first address mode, the device address data is the starting address data; the extraction module 930 is specifically configured to:

[0112] According to the address extraction position information, a numerical value is directly extracted from a position corresponding to the address extraction position information in the starting address data to form a target address.

[0113] In some optional implementations, when the target address mode is the second address mode, the device address data includes start address data and padding address data, where the padding address data is data of a preset length received again after receiving the start address data; the extraction module 930 is specifically configured to:

[0114] According to the address extraction position information, extracting a value from a position corresponding to the address extraction position information in the starting address data as a high-order address, and taking all the padding address data as a low-order address;

[0115] Generate the target address based on the high address and the low address.

[0116] In some optional embodiments, the apparatus further includes a sending module 940 for sending an interrupt signal to the master device to indicate an address matching error when a register address matching the target address pattern is not received.

[0117] For the description of the features in the embodiment corresponding to the register addressing device, reference can be made to the relevant description of the embodiment corresponding to the register addressing method, which will not be repeated here.

[0118] The embodiment of the present application also provides an electronic device, such as Figure 10 As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to execute the steps in any of the above register addressing method embodiments. The electronic device may be the above slave device.

[0119] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned register addressing method embodiments when run.

[0120] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0121] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned register addressing method embodiments are implemented.

[0122] An embodiment of the present application further provides another computer program product, comprising a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned register addressing method embodiments are implemented.

[0123] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0124] The above is a detailed introduction to a register addressing method, device, electronic device, storage medium, and program product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A register addressing method, characterized in that: The method is applied to a data transmission system, the data transmission system including a master device and a slave device, the master device being a baseboard management controller, the slave device being a complex programmable logic device, the method being executed by the slave device, and the method including: Acquire multiple configuration rules, wherein each of the configuration rules includes at least one bit identification information; sorting each of the configuration rules according to the amount of bit identification information included in each of the configuration rules; receiving start address data of a preset length sent by the master device, wherein the master device receives an operation instruction, parses the operation instruction to determine an address range where a register address is located, determines a target address mode corresponding to the address range, and sends data to the slave device according to the target address mode; After matching the starting address data with one or more configuration rules according to the order of each configuration rule, determine a target configuration rule that matches the starting address data; According to the target configuration rule, determining a target address mode corresponding to the target configuration rule; Switching the addressing space range of the register to a target addressing space range corresponding to the target address mode; When it is determined that device address data corresponding to the target address pattern is received according to the target address pattern, extracting a target address from the device address data according to the target address pattern; When it is determined that the target address matches the address of the slave device and the register address that matches the target address pattern is received, a functional register corresponding to the register address is determined from a plurality of registers included in the slave device based on the register address and the target addressing space range, so as to perform business operations on the functional register.

2. The register addressing method according to claim 1, wherein: The starting address data includes multiple actual numerical values, and the configuration rule also includes a configuration value corresponding to each bit identification information; Matching the starting address data with the configuration rule includes: Determining, in the starting address data, a target bit corresponding to the target bit identification information according to the target bit identification information, wherein the target bit identification information is any bit identification information included in a first configuration rule, and the first configuration rule is any configuration rule among the multiple configuration rules; extracting a target actual value from the target position; When it is determined that the target actual value is consistent with the configuration value corresponding to the target position identification information, determining the comparison result corresponding to the target position identification information as passed; When the comparison results respectively corresponding to all bit identification information in the first configuration rule are all passed, the first configuration rule is determined as a target configuration rule matching the start address data.

3. The register addressing method according to claim 1 or 2, characterized in that: When it is determined according to the target address pattern that device address data corresponding to the target address pattern is received, extracting the target address from the device address data according to the target address pattern includes: Determining, according to the target address pattern, address extraction position information corresponding to the target address pattern; According to the address extraction position information, a value is extracted from a position in the device address data corresponding to the address extraction position information to form the target address.

4. The register addressing method according to claim 3, wherein: When the target address mode is the first address mode, the device address data is the starting address data; extracting the value from a position corresponding to the address extraction position information in the device address data to form the target address according to the address extraction position information, includes: According to the address extraction position information, a value is directly extracted from a position in the start address data corresponding to the address extraction position information to form the target address.

5. The register addressing method according to claim 3, wherein: When the target address mode is the second address mode, the device address data includes the start address data and the padding address data, and the padding address data is data of a preset length received again after receiving the start address data; extracting the position information according to the address, extracting a value from a position corresponding to the address extraction position information in the device address data to form the target address, includes: According to the address extraction position information, extracting a value from a position corresponding to the address extraction position information in the starting address data as a high-order address, and using all the padding address data as a low-order address; The target address is generated according to the high-order address and the low-order address.

6. The register addressing method according to claim 1 or 2, characterized in that: The method further comprises: When a register address matching the target address pattern is not received, an interrupt signal is sent to the master device to indicate an address matching error.

7. A register addressing device, characterized in that: The device is applied to a data transmission system, the data transmission system including a master device and a slave device, the master device being a baseboard management controller, the slave device being a complex programmable logic device, and the device including: a receiving module, configured to obtain a plurality of configuration rules, wherein each of the configuration rules includes at least one bit identification information; sort each of the configuration rules according to the number of bit identification information included in each of the configuration rules; receive starting address data of a preset length sent by the master device, wherein the master device receives an operation instruction, parses the operation instruction to determine an address range where a register address is located, determines a target address mode corresponding to the address range, and sends data to the slave device according to the target address mode; a determination module, configured to match the starting address data with one or more configuration rules according to the order of each configuration rule, and thereby determine a target configuration rule that matches the starting address data; determine a target address mode corresponding to the target configuration rule based on the target configuration rule and the correspondence between the configuration rule and the address mode; and switch the addressing space range of the register to a target addressing space range corresponding to the target address mode; an extraction module, configured to extract a target address from the device address data according to the target address pattern when it is determined that device address data corresponding to the target address pattern is received according to the target address pattern; The determination module is further configured to, when it is determined that the target address matches the address of the slave device and the register address matching the target address pattern is received, determine, based on the register address, a function register corresponding to the register address from a plurality of registers included in the slave device, so as to perform business operations on the function register.

8. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the register addressing method according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the register addressing method according to any one of claims 1 to 6 are implemented.

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