Chip first-in-first-out queue automatic generation method, electronic device and medium

Abstract

The present invention relates to the field of chip technology, and in particular to a method, electronic device, and medium for automatically generating a chip first-in-first-out queue. The method comprises the following steps: S1, obtaining a chip component module combination that needs to be interconnected based on a Credit-Debit bus protocol in a chip; S2, n Insert Credit‑Debit bus protocol information C n ; Step S3, based on C n In A n Foreign C n The corresponding depth is generated as D n The sending end first enters the FIFO module E n , in B n Exogenous B n The corresponding depth is D n The receiving end FIFO module F n ; Step S4, based on C n A n The output port and E n The input ports of E n The output port and F n The input ports of F n The output port is connected to B n The present invention improves the accuracy of FIFO generation of chip components modules interconnected based on the Credit-Debit bus protocol.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip first-in-first-out queue automatic generation method, electronic equipment and medium. Background Art

[0002] During chip design, chip components can be interconnected using the Credit-Debit bus protocol. The Credit-Debit bus protocol is a data transmission and communication protocol used on a bus within a chip or between chips. It uses a credit and debit mechanism to control data flow, ensuring efficient, reliable, and orderly data transmission. This protocol is similar to the accounting system of a bank account: both the sender and receiver of data on the bus have corresponding "credit limits" and "debit operations" to manage data transmission and reception. Two chip components interconnected using the Credit-Debit bus protocol must each have a first-in-first-out (FIFO) queue with the same depth to record the number of requests and responses. During chip design, the FIFO depth is passed as a parameter. Due to various factors, such as different teams responsible for the two chip components or parameter transmission errors, the FIFO depths of the two chip components interconnected using the Credit-Debit bus protocol may differ, leading to data overflow and other problems during operation. Due to the large scale of the chip, debugging is difficult. Therefore, how to improve the accuracy of FIFO generation of chip components interconnected based on the Credit-Debit bus protocol has become a technical problem that needs to be solved urgently. Summary of the Invention

[0003] The present invention aims to provide a method, electronic device and medium for automatically generating a chip first-in-first-out queue, thereby improving the accuracy of FIFO generation of chip component modules interconnected based on a Credit-Debit bus protocol.

[0004] According to a first aspect of the present invention, a method for automatically generating a chip first-in-first-out queue is provided, comprising:

[0005] Step S1: Obtain the chip module combination {(A1, B1), (A2, B2), ..., (A n ,B n ),...,(A N ,B N )},A nThe nth transmitter chip in the chip needs to be interconnected based on the Credit-Debit bus protocol, B n A n For the corresponding receiving module, the value of n ranges from 1 to N, where N is the total number of chip component module combinations that need to be interconnected based on the Credit-Debit bus protocol in the chip;

[0006] Step S2: n Insert Credit-Debit bus protocol information C n , C n Contains A n and B n Corresponding FIFO depth D n ;

[0007] Step S3: Based on C n In A n Foreign C n The corresponding depth is generated as D n The sending end first enters the FIFO module E n , in B n Exogenous B n The corresponding depth is D n The receiving end FIFO module F n ;

[0008] Step S4: Based on C n A n The output port and E n The input ports of E n The output port and F n The input ports of F n The output port is connected to B n The input ports are interconnected.

[0009] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.

[0011] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above technical solution, the present invention provides a method for automatically generating a chip first-in, first-out queue, an electronic device, and a medium that achieve considerable technological advancement and practicality, and has wide industrial application value, with at least the following beneficial effects:

[0012] The present invention inserts Credit-Debit bus protocol information containing FIFO depth into each sending-end chip component module interconnected based on the Credit-Debit bus protocol, generates FIFOs with FIFO depths for the sending-end chip component module and the receiving-end chip component module based on the Credit-Debit bus protocol information, and establishes an interconnection relationship. The present invention can ensure that the FIFO depths generated by the sending-end chip component module and the receiving-end chip component module interconnected based on the Credit-Debit bus protocol are the same, thereby improving the accuracy of FIFO generation of the chip component modules interconnected based on the Credit-Debit bus protocol. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 This is a flow chart of a method for automatically generating a chip first-in-first-out queue according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0016] The embodiment of the present invention provides a method for automatically generating a chip first-in first-out queue, such as Figure 1 Shown, including:

[0017] Step S1: Obtain the chip module combination {(A1, B1), (A2, B2), ..., (A n ,B n ),...,(A N ,B N)},A n The nth transmitter chip in the chip needs to be interconnected based on the Credit-Debit bus protocol, B n A n For the corresponding receiving module, the value of n ranges from 1 to N, where N is the total number of chip component module combinations in the chip that need to be interconnected based on the Credit-Debit bus protocol.

[0018] The Credit-Debit bus protocol is a protocol used for data transmission and communication on a bus within a chip or between chips. It uses a credit and debit mechanism to control the flow of data, ensuring efficient, reliable, and orderly data transmission. This protocol is similar to the accounting method of a bank account. The sender and receiver of data transmitted on the bus have corresponding "credit limits" and "debit operations" to manage the sending and receiving of data.

[0019] Step S2: n Insert Credit-Debit bus protocol information C n , C n Contains A n and B n Corresponding FIFO depth D n .

[0020] It should be noted that the embodiment of the present invention only needs to insert the Credit-Debit bus protocol information into the transmitting chip component module. The transmitting chip component module and the corresponding receiving chip component module both generate corresponding FIFO modules based on the Credit-Debit bus protocol information inserted into the transmitting chip component module.

[0021] As an embodiment, Cn also includes signal description information, timing diagram information, direction information, signal width information, reset value, and default value. The signal description information is used to describe the signal and can be used to generate documentation. The direction information includes input, output, and inout, and is configured based on the specific direction of the signal. The signal width information can be a fixed value or a configurable value. The reset value and default value are pre-configured based on the specific signal.

[0022] Step S3: Based on C n In A n Foreign C n The corresponding depth is generated as D n The sending end first enters the FIFO module E n , in B n Exogenous B n The corresponding depth is D nThe receiving end FIFO module F n .

[0023] It should be noted that in the prior art, corresponding FIFO modules are generated in the transmitting chip component module and the receiving chip component module based on the FIFO depth parameters received by the transmitting chip component module and the receiving chip component module, respectively. However, the present invention generates corresponding FIFO modules independently outside the transmitting chip component module and the receiving chip component module based on the same FIFO depth, ensuring that the FIFO modules generated by the transmitting chip component module and the receiving chip component module have the same depth.

[0024] Step S4: Based on C n A n The output port and E n The input ports of E n The output port and F n The input ports of F n The output port is connected to B n The input ports are interconnected.

[0025] It should be noted that, through step S4, the sending-end chip component module, the FIFO module corresponding to the sending-end chip component module, the receiving-end chip component module, and the FIFO module corresponding to the receiving-end chip component module are interconnected, ensuring that the sending-end chip component module and the sending-end chip component module interact based on the Credit-Debit bus protocol. The FIFO module corresponding to the sending-end chip component module is used to record the number of requests, and the receiving-end chip component module is used to record the number of responses.

[0026] As an embodiment, step S4 includes:

[0027] Step S41: E n The input port name is set to A n Set the output port name to the same port name.

[0028] Step S42: E n Output port names and F n The input port names are set to the same port names.

[0029] Step S43: F n Output port name and B n The input port names are set to the same port names.

[0030] Step S44: Ports with the same port name are based on the corresponding C n Establish connections.

[0031] It should be noted that through steps S41 to S44, A n The output port and E n The input ports of E n The output port and F n The input ports of F n The output port is connected to B n The input ports of A are interconnected. n The output port is connected to B n The input ports of the present invention are interconnected, and the embodiment of the present invention is equivalent to A n The output port and B n The FIFO module corresponding to the transmitting chip component module and the FIFO module corresponding to the receiving chip component module are inserted between the input ports, and the FIFO module corresponding to the transmitting chip component module and the FIFO module corresponding to the receiving chip component module are generated based on the same depth, so they must have the same depth.

[0032] After the FIFO modules corresponding to the transmitting chip component module and the FIFO modules corresponding to the receiving chip component module are set up, when the number of FIFO module caches reaches the corresponding depth, the first-in-first-out queue reaches a full (FIFO full) state, which triggers the logic corresponding to the FIFO full state for verification. However, due to various factors, many FIFO modules may be released before reaching the FIFO full state. As a result, many FIFOs never reach the FIFO full state during the entire verification process, resulting in a lot of logic corresponding to the FIFO full state not being verified, resulting in low chip verification coverage. Based on this, an embodiment of the present invention further proposes a solution. As an embodiment, step S4 further includes:

[0033] Step S5: Set the corresponding virtual depth for the FIFO to be tested in the chip design. The virtual depth corresponding to the FIFO to be tested is less than or equal to the actual depth corresponding to the FIFO to be tested. The FIFO to be tested is E n or F n .

[0034] Step S6: When the depth of the information currently stored in the FIFO to be tested reaches the virtual depth corresponding to the FIFO to be tested, a logic simulation of a full state of the FIFO to be tested is triggered.

[0035] As an embodiment, the method further includes:

[0036] Step S0: Set the FIFO virtual depth configuration file {F1, F2, ..., F m ,...,F M}, Fm Design the virtual depth configuration information of the mth FIFO to be tested for the chip, F m ={F1 m ,F2 m ,F3 m}, F1 m F m The corresponding virtual depth configuration mode includes fixed mode and random mode. m F m The corresponding time window, F m The corresponding time window is less than or equal to the chip simulation time. When F1 m For fixed mode, F3 m To fix the virtual depth value, when F1 m In random mode, F3 m is a virtual depth interval, and the maximum value of the virtual depth interval is less than or equal to the actual depth corresponding to the FIFO to be tested.

[0037] It should be noted that the FIFO virtual depth can be set to a fixed value through the fixed mode, the FIFO virtual depth value can be reasonably set within the virtual depth range through the random mode, and the time interval for setting the virtual depth can be controlled through the time window, thereby meeting the different FIFO virtual depth configuration requirements of different FIFOs to be tested. If a part of the FIFO modules in the chip can be verified as FIFO full state without setting the depth, the FIFO virtual depth configuration information of this part of the FIFO modules can be set, and the actual depth corresponding to the FIFO can be used by default. That is, the embodiment of the present invention only uses the FIFO modules with virtual depth setting requirements as the FIFO to be tested.

[0038] As an embodiment, step S5 includes:

[0039] Step S51: If the depth configuration mode of the FIFO to be tested is fixed, the virtual depth of the FIFO to be tested is set to the corresponding fixed virtual depth value in the corresponding time window, and the virtual depth of the FIFO to be tested is set to the actual depth of the FIFO to be tested outside the corresponding time window.

[0040] It should be noted that based on {F1,F2,...,F m ,...,F M} can determine the corresponding {F1 m ,F2 m ,F3 m}, based on {F1 m ,F2 m ,F3 m}Implement step S51.

[0041] As an embodiment, step S5 includes:

[0042] Step C51: If the depth configuration mode corresponding to the FIFO to be tested is the random mode, a random depth value is generated as the virtual depth corresponding to the FIFO to be tested based on the corresponding virtual depth interval in the time window, and the virtual depth corresponding to the FIFO to be tested is set to the actual depth corresponding to the FIFO to be tested during the time outside the corresponding time window.

[0043] It should be noted that based on {F1,F2,...,F m ,...,F M} can determine the corresponding {F1 m ,F2 m ,F3 m}, based on {F1 m ,F2 m ,F3 m}Implement step C51.

[0044] As an embodiment, step S5 includes:

[0045] Step E51: Setting a corresponding interface module for the FIFO to be tested, and interconnecting the FIFO to be tested with the interface module corresponding to the FIFO to be tested.

[0046] It should be noted that the FIFO under test is a FIFO configured in the chip design. The FIFO under test and the interface module corresponding to the FIFO under test can be interconnected using a binding mechanism. Specifically, the interface module corresponding to the FIFO under test can be connected to the clock signal line, reset signal line, and full status signal line of the FIFO under test.

[0047] Step E52: Setting a virtual depth corresponding to the FIFO to be tested in the interface module corresponding to the FIFO to be tested.

[0048] It should be noted that the size of the virtual depth corresponding to the FIFO to be tested is determined according to the specific situation of the FIFO to be tested. Step E52 is specifically implemented through step S51 or step C51 based on the interface module corresponding to the FIFO to be tested.

[0049] As an implementation, step S6 includes:

[0050] Step S61: During chip simulation, if the depth of information currently stored in the FIFO to be tested reaches the virtual depth corresponding to the FIFO to be tested, the interface module corresponding to the FIFO to be tested will force the full state signal corresponding to the FIFO to be tested to be high, triggering the execution of logic simulation of the full state of the FIFO to be tested.

[0051] It should be noted that by setting the virtual depth corresponding to the FIFO to be tested, and triggering the execution of the logic simulation of the full state of the FIFO to be tested when the depth of the current stored information in the FIFO to be tested reaches the virtual depth corresponding to the FIFO to be tested, the FIFO full state of the FIFO to be tested is made easier to verify, thereby improving the chip verification coverage.

[0052] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0053] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0054] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0055] The embodiment of the present invention inserts Credit-Debit bus protocol information including FIFO depth into each transmitting-end chip component module interconnected based on the Credit-Debit bus protocol, generates FIFOs with FIFO depths for the transmitting-end chip component module and the receiving-end chip component module based on the Credit-Debit bus protocol information, and establishes an interconnection relationship. The present invention can ensure that the FIFO depths generated by the transmitting-end chip component module and the receiving-end chip component module interconnected based on the Credit-Debit bus protocol are the same, thereby improving the accuracy of FIFO generation of the chip component modules interconnected based on the Credit-Debit bus protocol.

[0056] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A chip first-in first-out queue automatic generation method, characterized in that: include: Step S1: Obtain the chip module combination {(A1, B1), (A2, B2), ..., (A n ,B n ),...,(A N ,B N )},A n The nth transmitter chip in the chip needs to be interconnected based on the Credit-Debit bus protocol, B n A n For the corresponding receiving module, the value of n ranges from 1 to N, where N is the total number of chip component module combinations that need to be interconnected based on the Credit-Debit bus protocol in the chip; Step S2: n Insert Credit-Debit bus protocol information C n , C n Contains A n and B n Corresponding FIFO depth D n ; Step S3: Based on C n In A n Foreign C n The corresponding depth is generated as D n The transmitting end FIFO module E n , in B n Exogenous B n The corresponding depth is D n The receiving end FIFO module F n ; Step S4: Based on C n A n The output port and E n The input ports of E n The output port and F n The input ports of F n The output port is connected to B n The input ports are interconnected.

2. The method according to claim 1, characterized in that C n It also includes signal description information, timing diagram information, direction information, signal width information, reset value and default value.

3. The method according to claim 1, characterized in that The step S4 comprises: Step S41: E n The input port name is set to A n The output port name is set to the same port name; Step S42: E n Output port names and F n The input port names are set to the same port names; Step S43: F n Output port name and B n The input port names are set to the same port names; Step S44: Ports with the same port name are based on the corresponding C n Establish connections.

4. The method according to claim 1, wherein After step S4, the following steps are also included: Step S5: Set the corresponding virtual depth for the FIFO to be tested in the chip design. The virtual depth corresponding to the FIFO to be tested is less than or equal to the actual depth corresponding to the FIFO to be tested. The FIFO to be tested is E n or F n ; Step S6: When the depth of the information currently stored in the FIFO to be tested reaches the virtual depth corresponding to the FIFO to be tested, a logic simulation of a full state of the FIFO to be tested is triggered.

5. The method according to claim 4, characterized in that The method further comprises: Step S0: Set the FIFO virtual depth configuration file {F1, F2, ..., F m ,...,F M }, F m Design the virtual depth configuration information of the mth FIFO to be tested for the chip, F m ={F1 m ,F2 m ,F3 m }, F1 m F m The corresponding virtual depth configuration mode includes fixed mode and random mode. m F m The corresponding time window, F m The corresponding time window is less than or equal to the chip simulation time. When F1 m In fixed mode, F3 m To fix the virtual depth value, when F1 m In random mode, F3 m is a virtual depth interval, and the maximum value of the virtual depth interval is less than or equal to the actual depth corresponding to the FIFO to be tested.

6. The method according to claim 5, characterized in that The step S5 comprises: Step S51: If the depth configuration mode of the FIFO to be tested is fixed, the virtual depth of the FIFO to be tested is set to the corresponding fixed virtual depth value in the corresponding time window, and the virtual depth of the FIFO to be tested is set to the actual depth of the FIFO to be tested outside the corresponding time window.

7. The method according to claim 5, characterized in that The step S5 comprises: Step C51: If the depth configuration mode corresponding to the FIFO to be tested is the random mode, a random depth value is generated as the virtual depth corresponding to the FIFO to be tested based on the corresponding virtual depth interval in the time window, and the virtual depth corresponding to the FIFO to be tested is set to the actual depth corresponding to the FIFO to be tested during the time outside the corresponding time window.

8. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions to be executed by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 7.

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