An 8-bit ADC digital compensation circuit applied to FLASH memory and computing

Abstract

The present invention discloses an 8-bit ADC digital compensation circuit applied to FLASH memory and computing, belonging to the field of digital integrated circuits. The error compensation selection switch in the present invention is used to select the correction strategy of the enabled ADC; the gain error compensation module is used to correct the linear gain error of the ADC; the offset error compensation module is used to correct the offset error of the ADC; the segmented error compensation module is used to correct the segmented linear error of the ADC and supports single-bit correction. The present invention can significantly improve the reliability of the calculation results. Through a lightweight digital correction algorithm, without the need for additional analog modules, high-precision and low-latency ADC error compensation is achieved, while maintaining the energy efficiency advantage of the memory and computing integrated architecture.

Description

Technical Field

[0001] The present invention relates to the field of digital integrated circuit technology, and particularly relates to an 8-bit ADC digital compensation circuit applied to FLASH computing-in-memory. Background Art

[0002] With the rapid development of technologies such as artificial intelligence and edge computing, the computing-in-memory (CIM) architecture has become one of the core technologies for realizing high-density parallel computing due to its high energy efficiency and low latency characteristics. As a typical implementation scheme of computing-in-memory, the FLASH computing-in-memory circuit directly completes the analog domain computing operation in the storage unit (such as a FLASH memory), which can significantly reduce the data transfer overhead and is suitable for scenarios such as low-power AI accelerators and Internet of Things terminals. However, in the FLASH computing-in-memory system, the accuracy of the analog-to-digital converter (ADC) directly affects the reliability of the computing result, and its error problem has become the key bottleneck restricting the system performance.

[0003] Existing ADC compensation schemes need to introduce additional analog circuits, resulting in an increase in chip area and power consumption. Moreover, software algorithms based on two-point calibration or multi-point piecewise linearization need to be pre-calibrated and are difficult to cope with real-time disturbances such as dynamic load changes and temperature drift in the computing-in-memory circuit. Summary of the Invention

[0004] The purpose of the present invention is to provide an 8-bit ADC digital compensation circuit applied to FLASH computing-in-memory to solve the problems in the background art.

[0005] To solve the above technical problems, the present invention provides an 8-bit ADC digital compensation circuit applied to FLASH computing-in-memory, including:

[0006] An error compensation selection switch for selecting to enable the correction strategy of the ADC;

[0007] A gain error compensation module for correcting the linear gain error of the ADC;

[0008] A bias error compensation module for correcting the bias error of the ADC;

[0009] A piecewise error compensation module for correcting the piecewise linear error of the ADC and supporting single-bit correction; wherein,

[0010] In one embodiment, when the ADC error belongs to a linear error, the error compensation selection switch is configured as 2'b011, indicating that the gain compensation and bias compensation are turned on;

[0011] Configure two registers for gain compensation. The register with a bit width of 16 bits is multiplied by the ADC input value in a multiplicative form for correction, and the register with a bit width of 8 bits shifts the ADC input value to the right in a shift form for correction. Fill in the corresponding values A and B according to the coefficients fitted by the software;

[0012] Configure the register for offset compensation, and fill in the corresponding value C according to the coefficients fitted by the software;

[0013] At this time, the value input to the ADC is X. After correction, a new value is obtained, and the Y value is the input value of the ADC after correction;

[0014] In one embodiment, when the ADC error belongs to piecewise linear error, configure the error compensation selection switch to 2'b111, indicating that the gain compensation, offset compensation, and piecewise compensation functions are enabled;

[0015] Configure two registers for gain compensation. The register with a bit width of 16 bits is multiplied by the ADC input value in a multiplicative form for correction, and the register with a bit width of 8 bits shifts the ADC input value to the right in a shift form for correction. Fill in the corresponding values A and B according to the coefficients fitted by the software;

[0016] Configure the register for offset compensation, and fill in the corresponding value C according to the coefficients fitted by the software;

[0017] Configure the register for piecewise compensation. Each bit of the ADC input is multiplied by the value of each 16-bit register to correct the piecewise error; set the values of these 8 registers to D0, D1, D2, D3, D4, D5, D6, and D7 respectively;

[0018] At this time, the value input to the ADC is X. Set each bit of it to X0, X1, X2, X3, X4, X5, X6, and X7. After correction, a new value is obtained, and the Y value is the input value of the ADC after correction.

[0019] In one embodiment, the error compensation selection switch includes a register with a 3-bit width. When the register value is 0, the ADC compensation function is not started; when the lowest bit is 1, the gain error compensation module is started; when the middle bit is 1, the offset error compensation module is started; when the highest bit is 1, the piecewise error compensation module is started; the error compensation selection switch starts a single type of compensation or, according to different situations, simultaneously enables multiple compensation functions.

[0020] In one embodiment, the gain error compensation module includes a register with a bit width of 16 bits and a register with a bit width of 8 bits, supporting a maximum amplification of 65535 times and a reduction correction of 2 255 times.

[0021] In one embodiment, the bias error compensation module includes a signed register with a bit width of 8 bits, supporting a maximum positive and negative bias compensation of 128.

[0022] In one embodiment, the segmented error compensation module is composed of 8 16-bit registers, corresponding to each bit input of the 8-bit ADC, so as to correct each bit input.

[0023] In one embodiment, the segmented error compensation module is used in combination with the gain error compensation module. The correction of the input of the ADC by the segmented error compensation module will expand the input value of the ADC, and then the reduction function of the gain error compensation module is used to reduce the value of the ADC to a specified number of digits.

[0024] An 8-bit ADC digital compensation circuit applied to FLASH memory and computing provided by the present invention realizes high-precision and low-latency ADC error compensation through a lightweight digital correction algorithm without the need for an additional analog module. The present invention integrates the signal characteristics of the memory and computing system and the non-linear model of the ADC, and can effectively compensate for the linear or non-linear errors of the ADC according to different configurations, significantly improving the reliability of the calculation results while maintaining the energy efficiency advantage of the memory and computing integrated architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic structural diagram of an 8-bit ADC digital compensation circuit applied to FLASH memory and computing provided by the present invention.

[0026] Figure 2 is a schematic diagram of the correction process when the ADC error belongs to a linear error.

[0027] Figure 3 is a schematic diagram of the correction process when the ADC error belongs to a segmented linear error. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The following further describes in detail an 8-bit ADC digital compensation circuit applied to FLASH memory and computing proposed by the present invention with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0029] The present invention provides an 8-bit ADC digital compensation circuit applied to FLASH memory and computing, as Figure 1As shown, it mainly includes an error compensation selection switch, a gain error compensation module, a bias error compensation module, and a segmented error compensation module; the error compensation selection switch is used to select the correction strategy for enabling the ADC; the segmented error compensation module is used to correct the segmented linear error of the ADC and supports single-bit correction; the gain error compensation module is used to correct the linear gain error of the ADC; the bias error compensation module is used to correct the bias error of the ADC. Embodiment

[0030] First, fit the error curve of the ADC according to the software. When the ADC error belongs to the linear error, configure the error compensation selection switch to 2'b011, indicating that the gain compensation and bias compensation are enabled;

[0031] Configure two registers for gain compensation, including a register with a bit width of 16 bits and a register with a bit width of 8 bits. The first register with a bit width of 16 bits is multiplied by the ADC input value in a multiplicative form for correction, and the second register with a bit width of 8 bits shifts the ADC input value to the right in a shift form for correction, where a maximum amplification of 65535 times and a reduction of 2 255 times are supported. Fill in the corresponding values A and B according to the coefficients fitted by the software.

[0032] Then configure the register for bias compensation, including a signed register with a bit width of 8 bits, which supports a maximum bias compensation of plus or minus 128. Fill in the corresponding value C according to the coefficients fitted by the software.

[0033] At this time, the value input to the ADC is X. After correction, a new value is obtained. The Y value is the input value of the ADC after correction, and the process is as Figure 2 shown. Embodiment

[0034] First, fit the error curve of the ADC according to the software. When the ADC error belongs to the segmented linear error, configure the error compensation selection switch to 2'b111, indicating that the gain compensation, bias compensation, and segmented compensation functions are enabled;

[0035] Configure two registers for gain compensation, including a register with a bit width of 16 bits and a register with a bit width of 8 bits. The first register with a bit width of 16 bits is multiplied by the ADC input value in a multiplicative form for correction, and the second register with a bit width of 8 bits shifts the ADC input value to the right in a shift form for correction, where a maximum amplification of 65535 times and a reduction of 2 255 times are supported. Fill in the corresponding values A and B according to the coefficients fitted by the software.

[0036] Next, configure the register for offset compensation, which includes an 8-bit signed register, supporting a maximum offset compensation of plus or minus 128. Fill in the corresponding value C according to the coefficients obtained by software fitting.

[0037] Next, configure the register for segmented compensation, which consists of 8 16-bit registers. Corresponding to each bit input of the 8-bit ADC, the input of each bit of the ADC is multiplied by the value of each 16-bit register to correct the segmented error. Set the values of these 8 registers to D0, D1, D2, D3, D4, D5, D6, and D7 respectively.

[0038] At this time, the value input to the ADC is X. Set each of its bits to X0, X1, X2, X3, X4, X5, X6, and X7. After correction, a new value is obtained. The Y value is the input value of the ADC after correction. The process is as Figure 3 shown.

[0039] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. An 8-bit ADC digital compensation circuit applied to FLASH memory and computing, characterized in that Comprising: An error compensation selection switch for selecting the correction strategy that will enable the ADC; A gain error compensation module for correcting the linear gain error of the ADC; An offset error compensation module for correcting the offset error of the ADC; A segmented error compensation module for correcting the segmented linear error of the ADC, supporting single-bit correction; wherein, When the ADC error belongs to a linear error, configure the error compensation selection switch to 2'b011, indicating that gain compensation and offset compensation are enabled; Configure two registers for gain compensation. The register with a bit width of 16 bits is multiplied by the ADC input value in a multiplicative form for correction, and the register with a bit width of 8 bits right-shifts the ADC input value in a shift form for correction. Fill in the corresponding values A and B according to the coefficients fitted by the software; Configure the register for offset compensation, and fill in the corresponding value as C according to the coefficients fitted by the software; At this time, the value input to the ADC is X, and after correction, a new value is obtained , and the value of Y is the input value of the ADC after correction; When the ADC error belongs to a segmented linear error, configure the error compensation selection switch to 2'b111, indicating that gain compensation, offset compensation, and segmented compensation functions are enabled; Configure two registers for gain compensation. The register with a bit width of 16 bits is multiplied by the ADC input value in a multiplicative form for correction, and the register with a bit width of 8 bits right-shifts the ADC input value in a shift form for correction. Fill in the corresponding values A and B according to the coefficients fitted by the software; Configure the register for offset compensation, and fill in the corresponding value as C according to the coefficients fitted by the software; Configure the register for segmented compensation. Multiply each bit of the ADC input by the value of each 16-bit register to correct the segmented error; set the values of these 8 registers to D0, D1, D2, D3, D4, D5, D6, D7 respectively; At this time, the value input to the ADC is X. Let each bit of it be X0, X1, X2, X3, X4, X5, X6, X7. After correction, a new value is obtained , and the value of Y is the input value of the ADC after correction.

2. The 8-bit ADC digital compensation circuit applied to FLASH memory and computing as claimed in claim 1, wherein The error compensation selection switch includes a register with a 3-bit width. When the register value is 0, the ADC compensation function is not started; when the lowest bit is 1, the gain error compensation module is started; when the middle bit is 1, the offset error compensation module is started; when the highest bit is 1, the segmented error compensation module is started; the error compensation selection switch starts a single type of compensation or, according to different situations, simultaneously enables multiple compensation functions.

3. The 8-bit ADC digital compensation circuit applied to FLASH memory and computing as claimed in claim 2, wherein The gain error compensation module includes a register with a bit width of 16 bits and a register with a bit width of 8 bits, supporting a maximum amplification of 65,535 times and a 255 correction of 2-fold reduction.

4. The 8-bit ADC digital compensation circuit applied to FLASH memory and computing as described in claim 3, wherein The offset error compensation module includes a signed register with a bit width of 8 bits, supporting a maximum offset compensation of plus or minus 128.

5. The 8-bit ADC digital compensation circuit applied to FLASH memory and computing as claimed in claim 4, wherein The segmented error compensation module is composed of 8 16-bit registers, corresponding to each bit of the 8-bit ADC input, and correcting each bit of the input accordingly.

6. The 8-bit ADC digital compensation circuit applied to FLASH memory and computing as described in claim 5, characterized in that The segmented error compensation module is used in combination with the gain error compensation module. The correction of the ADC input by the segmented error compensation module will expand the ADC input value, and then use the shrinking function of the gain error compensation module to shrink the ADC value to the specified number of digits.

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