An event-driven CSR parser supporting multiple computing modes

Abstract

The present invention discloses an event-driven CSR parser supporting multiple computing modes, comprising a pointer counter, an index counter, a flag array generator, and a data matcher. The pointer counter is driven by a startup event and is used to access the pointer data of an input matrix or vector. The index counter is used to extract index data from a compressed format. The flag array generator is used to generate a flag array of a matrix or vector based on the index of the current valid data. The data matcher is used to determine whether the current non-zero element is successfully matched based on the matching situation in the flag array, and at the same time guide the pointer counter and index counter to perform the next round of decoding and calculate the accurate position of the current non-zero element in the overall matrix. The CSR parser provided by the present invention is compatible with multiple common sparse matrix computing modes and has good computing mode adaptability and versatility. The CSR parser adopts an asynchronous, clock-free circuit design, which effectively reduces dynamic energy consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of CSR parsers, and in particular relates to an event-driven CSR parser supporting multiple computing modes. Background Art

[0002] Low-order tensors are fundamental data structures that represent data in the form of multidimensional arrays and support mathematical operations and hardware acceleration. Low-order tensor operations play an important role in scientific computing fields such as finite element analysis, computational fluid dynamics, and image processing. The matrices and vectors involved in scientific computing are often irregular and sparse, posing the following challenges to the efficient computation of low-order tensor operations: (1) efficiently accessing nonzero elements in sparse matrices and sparse vectors; and (2) reducing operations on intermediate results.

[0003] Sparse matrices are typically stored in the Compressed Sparse Row (CSR) format to improve storage efficiency. Therefore, a CSR parser is required to parse sparse matrices and sparse vectors. The CSR parser parses and schedules compressed sparse matrices and sparse vectors in the matrix accelerator. It extracts the locations of nonzero elements based on the corresponding computational model, generates executable computational tasks, and distributes them to computational units. It dynamically adapts execution paths, supports parallel and asynchronous data flow operations, and improves system throughput.

[0004] However, existing CSR parsers have the following defects:

[0005] 1. Single computing mode and insufficient flexibility. Most existing CSR parsers use a specific operation mode, such as sparse matrix multiplication and sparse matrix-vector multiplication. However, in the field of actual scientific computing, a single computing mode is difficult to meet system requirements. Multiple computing modes are often required to coordinate and cooperate to obtain the final result. This single CSR parsing technology limits its applicability to general sparse computing tasks.

[0006] 2. Low resource utilization and high power consumption. Most existing CSR parsers use a synchronous execution model, requiring the previous round of computation or memory access to complete before the next round of operations can proceed. This can easily lead to idle computing units and memory access waits. In terms of timing, synchronous chips must ensure that the combinational logic delay is strictly less than the clock period. In terms of power consumption, synchronous chips cannot meet the requirements of extremely low-power application scenarios. The rapid increase in chip size has brought substantial challenges to the design of synchronous clock circuits due to problems such as clock skew and clock jitter. Summary of the Invention

[0007] In view of the problems existing in the above background technology, the purpose of the present invention is to provide an event-driven CSR parser that supports multiple computing modes.

[0008] In order to achieve the above object, the present invention adopts the following technical solutions:

[0009] An event-driven CSR parser supporting multiple calculation modes includes a pointer counter, an index counter, a flag array generator, and a data matcher, wherein:

[0010] Pointer counter: Receives external start events or events sent by the data matcher, is used to access the pointer data of the input matrix or vector, extracts the pointer group and selects the current start position pointer and end position pointer, outputs the matching row number of the current parsing, determines whether to update the start position pointer and end position pointer based on the relevant flag bits provided by the data matcher, and outputs the flag bit of whether the offset buffer is empty; when the input is a vector, the start position pointer and end position pointer are only updated once and then remain unchanged;

[0011] Index counter: used to extract index data from the compressed format; during the parsing process, if the current data counter is less than the end position pointer set by the pointer, the index of the current valid element is output and the flag bit is generated; otherwise, a driving event is sent to the flag array generator;

[0012] Flag array generator: used to generate the flag array of the compressed matrix or vector according to the index of the current valid element output by the index counter, and calculate the current minimum matching index;

[0013] Data matcher: used to determine whether the current non-zero element is successfully matched based on the matching status in the flag array, and calculate the exact position of the current non-zero element in the compressed sparse matrix or sparse vector. At the same time, it generates a control signal based on the current calculation mode and the matching counter status to guide the pointer counter and index counter to perform the next round of decoding. After the match is successful, the index of the matched non-zero element that needs to be calculated is sent to the calculation unit for calculation and the CSR parsing stage is terminated.

[0014] Furthermore, the control circuit in the CSR parser is based on the "send-relay-receive" model and is implemented using a coarse-grained asynchronous micro-pipeline structure. The control circuit consists of three basic modules: FIFO module, Merge module and Split module.

[0015] Furthermore, the methods for transmitting events and data of the three basic modules are as follows:

[0016] FIFO module: After receiving an activation event, the FIFO module generates multiple pulse signals in sequence to control the gradual transmission of data. After the last pulse event is generated, after a certain delay, it sends a response signal to the previous micro-pipeline and a request signal to the next micro-pipeline, thus achieving complete relay of events;

[0017] Merge module: The Merge module contains two control structures: ConfMerge and WaitMerge. In ConfMerge, the inputs are mutually exclusive. When only one event arrives at the same time, ConfMerge sends the incoming event and data to the adjacent module. WaitMerge sends the event and data to the next micro-pipeline after all events arrive.

[0018] Split module: The core module is the SelSplit module, which contains multiple validity flags and valid signals. When the Split module receives an activation event, only the branch with the valid signal set to 1 will pass the event and data to the next micro-pipeline, realizing selective branching based on conditional judgment.

[0019] Furthermore, the pointer counter includes a first ConfMerge control structure, a second ConfMerge control structure, a first-level FIFO module, a second-level FIFO module and a SelSplit module. After the pointer counter receives an external start event or an event sent by a data matcher, the event is passed to the SelSplit module for selection through the first ConfMerge control structure. If the internal offset buffer is not empty, the event is directly generated and then drives the second-level FIFO module through the second ConfMerge control structure; if the internal offset buffer is empty, the first-level FIFO module is driven to generate a pulse signal, drive the generation of the address of the next set of pointers and extract the pointers from the storage; the event returned by the storage is passed to the second-level FIFO module through the second ConfMerge control structure, and a pulse signal is generated to drive the extracted pointers to be stored in the pointer memory; and whether to update the start position pointer and the end position pointer is determined according to the relevant flag bits provided by the data matcher, and a flag bit of whether the buffer is empty is output; finally, the event generated by the second-level FIFO module is sent to the index counter.

[0020] Furthermore, the index counter includes a first ConfMerge control structure, a second ConfMerge control structure, a first-level FIFO module, a second-level FIFO module and a SelSplit module. After the index counter receives an event sent by the pointer counter or the data matcher, the event passes through the first ConfMerge control structure and is passed to the SelSplit module for selection. There are three situations for event transmission: (1) If the index of the current row has not been traversed in full and the internal index buffer is not empty, the event is directly generated and drives the second-level FIFO module after passing through the first ConfMerge control structure; (2) If the index of the current row is If all indexes are not traversed and the internal index buffer is empty, the first-level FIFO module is driven to trigger the index address generation module to generate the address of the next set of indexes and retrieve the indexes from the storage; the event returned by the storage is passed to the second-level FIFO module through the second ConfMerge control structure; the second-level FIFO module generates a pulse signal and writes a set of indexes taken from the storage into the index buffer; during the parsing process, if the current data counter is less than the end position pointer set by the pointer, the index of the current valid element is output through the index selection module, and the flag array generator is driven; (3) If the elements of the current row have been traversed to the end, the event is directly sent to the flag array generator.

[0021] Furthermore, the flag array generator includes a FIFO module, a ConfMerge control structure and a WaitMerge control structure. After the flag array generator receives the event sent by the index counter, the event drives the FIFO module through the ConfMerge control structure. The events generated by the two FIFO modules are fused into an event-driven data matcher through the WaitMerge control structure.

[0022] Furthermore, the data matcher includes a ConfMerge control structure, a FIFO module, and a SelSplit module. After the data matcher receives the event sent by the flag array generator, the event drives the FIFO module to generate a pulse signal through the ConfMerge control structure to start this round of matching. The SelSplit module generates events to control different modules.

[0023] Furthermore, the data matcher calculates the exact position of the current non-zero element in the compressed sparse matrix or sparse vector according to the starting position pointer of the current row and the offset of the non-zero element in the flag array through element index calculation logic.

[0024] Furthermore, the control signal generated in the data matcher includes a row-wrap flag, a column-wrap flag, and an element completion flag.

[0025] Furthermore, the information output by the CSR parser to the computing unit includes:

[0026] (1) The index of the matching non-zero element in the data area of the storage space is used to calculate the starting position of the non-zero element;

[0027] (2) Non-zero element flag, used to indicate whether the non-zero element is valid;

[0028] (3) The column indices of the non-zero elements of the result matrix, or the row / column indices of the non-zero elements of the result vector;

[0029] (4) Non-zero element completion flag, used to indicate whether the current non-zero element is matched;

[0030] (5) Row completion flag, used to mark whether a row of the result matrix is matched;

[0031] (6) Mode end flag, used to indicate whether all matches in the current calculation mode are completed.

[0032] Compared with the shortcomings and deficiencies of the prior art, the present invention has the following beneficial effects:

[0033] 1. The CSR parser provided by this invention is compatible with a variety of common sparse matrix calculation modes, including matrix-vector multiplication, matrix-matrix multiplication, vector-vector multiplication, matrix-matrix addition, and vector-vector calculation modes, and has good calculation mode adaptability and versatility. This CSR parser can not only extract the valid element positions and data content in the CSR format, but also flexibly adjust the accelerator's execution path according to different calculation modes, thereby improving execution efficiency. The built-in matching mechanism enables memory access optimization capabilities, intelligently scheduling access behavior according to data requirements, loading only necessary data, thereby improving bandwidth utilization.

[0034] 2. The CSR parser provided by this invention can be deployed on the same matrix computing unit for various matrix and vector-related calculations at a low cost. It can dynamically parse and adapt to different computing requests, significantly improving system versatility and resource reuse.

[0035] 3. The CSR parser provided by this invention utilizes an asynchronous, clockless circuit design. Modules are driven by events (pulse signals), effectively reducing dynamic energy consumption. Compared to traditional synchronous circuits, the asynchronous architecture effectively mitigates clock skew and jitter issues, making it particularly suitable for systems with complex structures or high uncertainty in operating environments. Furthermore, by binding data to events, the asynchronous circuit reduces power consumption while ensuring stable module operation and system performance. This CSR parser can operate in parallel with the computational unit, avoiding the blocking and waiting often seen in synchronous models, significantly improving overall operational efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Schematic diagram of the internal event flow of an event-driven CSR parser supporting multiple computing modes provided by an embodiment of the present invention;

[0037] Figure 2 Schematic diagram of the structure of three basic modules constituting the control circuit provided by an embodiment of the present invention, in which (a) represents a FIFO module, (b) represents a Merge module, and (c) represents a Split module;

[0038] Figure 3 It is the micro-architecture of PtrFetcherA provided by the embodiment of the present invention;

[0039] Figure 4 This is the micro-architecture of IdxFetcherA provided in an embodiment of the present invention;

[0040] Figure 5 It is the micro-architecture of the BitArray Generator provided by the embodiment of the present invention;

[0041] Figure 6 This is the micro-architecture of the Element Matcher provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0043] This paper provides an event-driven CSR parser that supports multiple computation modes. Based on an inner product algorithm, it supports multiplication of sparse matrices and sparse vectors, and employs a simple matching approach for addition. The CSR parser is designed to asynchronously decode pointer and index information in the CSR format, driving downstream matrix computation units for efficient computation.

[0044] 1. Overall architecture of CSR parser

[0045] The internal event flow diagram of the CSR parser is as follows Figure 1As shown in the figure, the internal workflow of the CSR parser is completed by the collaboration of four major modules: pointer counter PtrFetcher, index counter IdxFetcher, flag array generator BitArrayGenerator and data matcher Element Matcher. After receiving the start event, the CSR parser drives the pointer counter PtrFetcher, and then the index counter IdxFetcher, flag array generator BitArray Generator and data matcher Element Matcher are triggered in sequence. The data matcher Element Matcher determines how the CSR parser performs the subsequent loop calculation process.

[0046] The core functions of the CSR parser are: (1) sending the indices of the matched non-zero elements that need to be calculated to the calculation unit for calculation; (2) generating relevant flag information.

[0047] The CSR parser outputs the following important information to the computation unit:

[0048] (1) Non-zero element A index and non-zero element B index: The index of the matching non-zero element in the data area of the storage space. The calculation unit calculates the starting position of the non-zero element based on the index;

[0049] (2) Non-zero element A flag and non-zero element B flag: used to mark whether the non-zero element is valid; whether the non-zero element is valid is one of the judgment conditions for whether the calculation unit needs to fetch data;

[0050] (3) Result block column index: the column index of the non-zero elements of the result matrix, or the row / column index of the non-zero elements of the result vector;

[0051] (4) Non-zero element completion flag: used to mark whether the current non-zero element is matched;

[0052] (5) Row completion flag: used to mark whether a row of the result matrix is matched; when the calculation result is a matrix and the row completion flag is 1, a row of the result matrix has been matched;

[0053] (6) Mode end flag: used to indicate whether all matches in the current calculation mode are completed.

[0054] 2. Control circuit in CSR parser

[0055] The control circuit in the CSR parser is based on the "send-relay-receive" model and is implemented using a coarse-grained asynchronous micro-pipeline structure. The control circuit consists of three basic modules: FIFO module, Merge module, and Split module. The structural diagrams of the three basic modules are shown in the figure. Figure 2As shown, the method of transmitting events and data is as follows:

[0056] FIFO module: After receiving an activation event, it generates multiple pulse signals in sequence to control the gradual transmission of data. After the last pulse event is generated, after a certain delay, it sends a response signal to the previous micro-pipeline and a request signal to the next micro-pipeline, thereby achieving complete relay of events. The FIFO module used in the CSR parser of the present invention includes cFifo1 and cFifo2. cFifo1 generates one pulse signal and cFifo2 generates two pulse signals.

[0057] Merge module: Contains two control structures: ConfMerge and WaitMerge. In ConfMerge, each input is mutually exclusive. When only one event arrives at the same time, ConfMerge sends the incoming event and data to the adjacent module. WaitMerge sends events and data to the next micro-pipeline after all events arrive.

[0058] Split module: The core module is the SelSplit module, which contains multiple validity flag signals such as valid0 and valid1. When the Split module receives an activation event, only the branch with the validity flag signal 1 will pass the event and data to the next level of micro-pipeline, realizing selective branching based on conditional judgment.

[0059] 3. CSR parser workflow

[0060] After receiving the start event, the CSR parser drives the pointer fetcher PtrFetcher to work. The micro-architecture and workflow of PtrFetcherA and PtrFetcherB are the same, and they are responsible for accessing the pointer data of two input matrices or vectors respectively. Figure 3As shown, the pointer counter receives an external start event or an event from the data matcher Element Matcher. After passing through the first ConfMerge2, the event is selected by SelSplit2. If its internal offset buffer PtrBufferA is not empty, it directly generates an event, which passes through the second ConfMerge2 and drives the subsequent cFifo2. If its internal offset buffer PtrBufferA is empty, it drives cFifo1, generating a pulse signal, which drives the pointer address generation module GenPtrAddr to generate the addresses of the next set of pointers and extract the pointers from the storage memory. The event returned by the storage memory is passed to the next cFifo2 through the second ConfMerge2. The pulse signal drives the extracted pointers to be stored in the pointer storage module PtrBufferA, providing boundary conditions for subsequent index decoding. Simultaneously, the pointer selector module PtrChooserA determines whether to update the start and end position pointers based on the relevant flags provided by the data matcher, and also outputs a buffer empty flag. When the input is a vector, PtrChooser only updates the start and end position pointers once and then remains unchanged. Finally, the event generated by cFifo2 drives the index fetcher IdxFetcherA to start working.

[0061] The index fetcher IdxFetcher is used to extract index data from the compressed format. The micro-architecture and workflow of IdxFetcherA and IdxFetcherB are the same. Taking IdxFetcherA as an example, the micro-architecture of IdxFetcherA is as follows: Figure 4As shown, after the index fetcher receives the event sent by the pointer fetcher PtrFetcherA or the data matcher ElementMatcher, the event passes through the first ConfMerge2 and is selected in SelSplit3. There are three situations: (1) If the index of the current row has not been traversed in full and the internal index buffer IdxBufferA is not empty, the event is directly generated and drives the subsequent cFifo2 after passing through the second ConfMerge2; (2) If the index of the current row has not been traversed in full and the internal index buffer IdxBufferA is empty, the cFifo1 is driven to trigger the index address generation module GenIdxAddrA to generate the address of the next set of indexes and retrieve the indexes from the storage Memory. The event returned by the storage Memory is passed to cFifo2 through the second ConfMerge2, generating a pulse signal and writing the set of indexes retrieved from the storage into IdxBufferA. During the parsing process, if the current data counter is less than the end position pointer set by the pointer, the index of the current valid element is output through the index selection module IdxChooserA and the flag array generator is driven; (3) If the elements of the current row have been traversed to the end, the event is directly sent to the flag array generator BitArray Generator.

[0062] The microarchitecture of the BitArray Generator is as follows: Figure 5As shown, the flag array generator generates a flag array for the matrix or vector based on the indices of the currently valid elements in the index fetcher, restoring the positions of nonzero elements in the sparse matrix or sparse vector. Regardless of whether the index bound to the event sent by IdxFetcher is valid, the event drives cFifo1 through ConfMerge2. If the output of IdxFetcher contains a valid element index, the corresponding flag arrays bitArrayA and bitMapB are generated, and the current minimum matching index is calculated. The events generated by the two cFifo1s are merged through WaitMerge2 to form an event-driven data matcher. Taking the matrix × matrix operator as an example, the matrix on the right side of the operator is parsed repeatedly, so a 32×32 two-dimensional flag array bitMapB is placed in the flag array generator. Therefore, IdxFetcherB only needs to traverse and parse the sparse matrix and sparse vector on the right side of the operator once. A flag array of length 32 is sufficient to record the positions of nonzero elements in the input to the left of the operator. After each flag bit is generated by the flag array generator, it outputs bitArrayA and a row in bitMapB determined by the pointer counter. The flag array generator uses the minimum index judgment logic SetMinIdx to compare and obtain the farthest position that the data matcher can match forward. Taking the matrix 𝐴 × matrix 𝐵 as an example, at the beginning of the calculation, bitArrayA and bitMapB are all 0. If the indices of the valid elements obtained from IdxFetcherA and IdxFetcherB for the first time are 4 and 2 respectively, it means that the farthest position that can be matched in the element matcher is 2, because it is impossible to confirm whether there is a non-zero element with an index of 3 or 4 in the current column of matrix 𝐵. When the bitArrayA of the current row in matrix 𝐴 has been generated and a column of matrix 𝐵 is being parsed, the minimum matching index will be set to the index of the valid element obtained by IdxFetcherB.

[0063] The data matcher Element Matcher is the control center of the CSR parser, controlling the overall work of the CSR parser. The micro-architecture of Element Matcher is as follows: Figure 6As shown in the figure, after the Element Matcher receives an event from the flag array generator, it passes through ConfMerge2 and drives cFifo2 to generate a pulse signal, starting the current round of matching. Based on the matching results in bitArrayA and bitMapB output by the BitArray Generator, the ElementMatcher's internal valid element matching logic, ElementMatch, determines whether the two elements are successfully matched. In multiplication mode, both the left and right inputs must have nonzero elements at the same position; in addition mode, a match is successful if either input has a nonzero element. Subsequently, the element index calculation logic, GetElementID, calculates the exact position of the current nonzero element in the compressed sparse matrix or sparse vector based on the starting position pointer of the current row and the offset of the nonzero element in the flag array. Simultaneously, the parser control logic, ParserControl, generates control signals based on the current calculation mode and the current value of the match counter, including the row break flag, column break flag, and element completion flag, to guide PtrFetcher and IdxFetcher on whether to proceed to the next decoding round. Finally, a SelSplit4 is used to generate events to control different modules. If the currently obtained flag array is not fully matched, an event is generated, causing ConfMerge2 to drive cFifo2 to generate a pulse signal, and then the next match is started. If all the data sent this time is matched, but the two matrices as a whole are not matched, the data matcher will drive PtrFetcher or IdxFetcher to enter the next decoding round. The indices of the matched non-zero elements that need to be calculated are sent to the calculation unit for calculation. If the current matching round is complete and all relevant information of the two matrices has been matched, the indices of the matched non-zero elements that need to be calculated are sent to the calculation unit for calculation, and the CSR parsing phase is terminated.

[0064] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An event-driven CSR parser supporting multiple computing modes, characterized in that: It includes pointer counter, index counter, flag array generator and data matcher, among which: Pointer counter: Receives external start events or events sent by the data matcher, is used to access the pointer data of the input matrix or vector, extracts the pointer group and selects the current start position pointer and end position pointer, outputs the matching row number of the current parsing, determines whether to update the start position pointer and end position pointer based on the relevant flag bits provided by the data matcher, and outputs the flag bit of whether the offset buffer is empty; when the input is a vector, the start position pointer and end position pointer are only updated once and then remain unchanged; Index counter: used to extract index data from the compressed format; during the parsing process, if the current data counter is less than the end position pointer set by the pointer, the index of the current valid element is output and the flag bit is generated; otherwise, a driving event is sent to the flag array generator; Flag array generator: used to generate the flag array of the compressed matrix or vector according to the index of the current valid element output by the index counter, and calculate the current minimum matching index; Data matcher: used to determine whether the current non-zero element is successfully matched based on the matching status in the flag array, and calculate the exact position of the current non-zero element in the compressed sparse matrix or sparse vector. At the same time, it generates a control signal based on the current calculation mode and the matching counter status to guide the pointer counter and index counter to perform the next round of decoding. After the match is successful, the index of the matched non-zero element that needs to be calculated is sent to the calculation unit for calculation and the CSR parsing stage is terminated.

2. The event-driven CSR parser supporting multiple computing modes according to claim 1, characterized in that: The control circuit in the CSR parser is based on the "send-relay-receive" model and is implemented using a coarse-grained asynchronous micro-pipeline structure. The control circuit consists of three basic modules: FIFO module, Merge module and Split module.

3. The event-driven CSR parser supporting multiple computing modes according to claim 2, characterized in that: The methods for transmitting events and data of the three basic modules are as follows: FIFO module: After receiving an activation event, the FIFO module generates multiple pulse signals in sequence to control the gradual transmission of data. After the last pulse event is generated, after a certain delay, it sends a response signal to the previous micro-pipeline and a request signal to the next micro-pipeline, thus achieving complete relay of events; Merge module: The Merge module contains two control structures: ConfMerge and WaitMerge. In ConfMerge, the inputs are mutually exclusive. When only one event arrives at the same time, ConfMerge sends the incoming event and data to the adjacent module. WaitMerge sends the event and data to the next micro-pipeline after all events arrive. Split module: The core module is the SelSplit module, which contains multiple validity flags and valid signals. When the Split module receives an activation event, only the branch with the valid signal set to 1 will pass the event and data to the next micro-pipeline, realizing selective branching based on conditional judgment.

4. The event-driven CSR parser supporting multiple computing modes according to claim 3, characterized in that: The pointer counter includes a first ConfMerge control structure, a second ConfMerge control structure, a primary FIFO module, a secondary FIFO module and a SelSplit module. After the pointer counter receives an external start event or an event sent by a data matcher, the event is passed to the SelSplit module through the first ConfMerge control structure for selection. If the internal offset buffer is not empty, the event is directly generated and then driven through the second ConfMerge control structure to drive the secondary FIFO module; if the internal offset buffer is empty, the primary FIFO module is driven to generate a pulse signal, drive the generation of the address of the next set of pointers and extract the pointers from the storage; The event returned by the storage is passed to the secondary FIFO module through the second ConfMerge control structure, which generates a pulse signal to drive the extracted pointer to be stored in the pointer memory; And decide whether to update the start position pointer and the end position pointer according to the relevant flag bits provided by the data matcher, and at the same time output the flag bit of whether the buffer is empty; Finally, the events generated by the secondary FIFO module are sent to the index counter.

5. The event-driven CSR parser supporting multiple computing modes according to claim 3, characterized in that: The index counter includes a first ConfMerge control structure, a second ConfMerge control structure, a first-level FIFO module, a second-level FIFO module and a SelSplit module. After the index counter receives an event sent by a pointer counter or a data matcher, the event is passed to the SelSplit module for selection after passing through the first ConfMerge control structure. There are three situations for event transmission: (1) If the index of the current row has not been traversed in full and the internal index buffer is not empty, the event is directly generated and the second-level FIFO module is driven after passing through the first ConfMerge control structure; (2) If the index of the current row has not been traversed in full and the internal index buffer is empty, the first-level FIFO module is driven to trigger the index address generation module to generate the address of the next group of indexes and retrieve the indexes from the storage; the event returned by the storage is passed to the second-level FIFO module through the second ConfMerge control structure; The secondary FIFO module generates a pulse signal to write a set of indexes taken from the storage into the index buffer; During the parsing process, if the current data counter is less than the end position pointer set by the pointer, the index of the current valid element is output through the index selection module and the flag array generator is driven; (3) If the elements of the current row have been traversed to the end, the event is directly sent to the flag array generator.

6. The event-driven CSR parser supporting multiple computing modes according to claim 3, characterized in that: The flag array generator includes a FIFO module, a ConfMerge control structure and a WaitMerge control structure. After the flag array generator receives the event sent by the index counter, the event drives the FIFO module through the ConfMerge control structure. The events generated by the two FIFO modules are fused into an event-driven data matcher through the WaitMerge control structure.

7. The event-driven CSR parser supporting multiple computing modes according to claim 3, characterized in that: The data matcher includes a ConfMerge control structure, a FIFO module, and a SelSplit module. After the data matcher receives an event sent by a flag array generator, the event drives the FIFO module to generate a pulse signal through the ConfMerge control structure to start this round of matching. The SelSplit module generates events to control different modules.

8. The event-driven CSR parser supporting multiple computing modes according to claim 1, characterized in that: The data matcher calculates the exact position of the current non-zero element in the compressed sparse matrix or sparse vector according to the starting position pointer of the current row and the offset of the non-zero element in the flag array through the element index calculation logic.

9. The event-driven CSR parser supporting multiple computing modes according to claim 1, wherein: The control signal generated in the data matcher includes a row-wrap flag, a column-wrap flag, and an element completion flag.

10. The event-driven CSR parser supporting multiple computing modes according to claim 1, characterized in that: The information output by the CSR parser to the computing unit includes: (1) The index of the matching non-zero element in the data area of the storage space is used to calculate the starting position of the non-zero element; (2) Non-zero element flag, used to indicate whether the non-zero element is valid; (3) The column indices of the non-zero elements of the result matrix, or the row / column indices of the non-zero elements of the result vector; (4) Non-zero element completion flag, used to indicate whether the current non-zero element is matched; (5) Row completion flag, used to mark whether a row of the result matrix is matched; (6) Mode end flag, used to indicate whether all matches in the current calculation mode are completed.

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