Circuit diagram processing method and device, electronic equipment and storage medium

Abstract

The invention is suitable for the technical field of machine learning, and provides a circuit diagram processing method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a gate-level netlist of a circuit diagram; the gate-level netlist is converted into a text attribute graph, the text attribute graph comprises a plurality of gate nodes and a connectivity set, each gate node represents a logic gate in the circuit diagram, a text of the gate node is used for representing functions and physical characteristics of the logic gate represented by the gate node, and the connectivity set comprises edges used for connecting the gate nodes; and inputting the text attribute graph into the cross-modal embedding model to obtain an embedding vector of the circuit diagram, the embedding vector comprising at least one of a gate-level embedding vector, a register-level embedding vector and a graph-level embedding vector.

Description

Technical Field

[0001] This application belongs to the field of machine learning, and particularly relates to a circuit diagram processing method and apparatus, an electronic device, and a computer-readable storage medium. Background Art

[0002] Machine learning (ML) technology has achieved remarkable achievements in the field of electronic design automation (EDA). Among them, circuit representation learning methods (such as netlist encoders) generate information-rich embeddings for circuit diagrams and can support a series of downstream tasks.

[0003] The netlist encoders in the related art mainly capture circuit functions through graph structures, and use graph learning models, such as graph neural networks (GNNs) or graph transformers (GTs), to directly infer functions through graph topologies or pre-train the models using functional information. However, such netlist encoders essentially prioritize structural information over functions and have obvious limitations, specifically including: (1) being limited to and-inverter graphs (AIGs), and AIGs are only a narrow subset of the standard cell library and cannot handle mapped netlists with multiple gate types; (2) relying on complex functional supervision, when applied to post-synthesis netlists with multi-input complex gates (such as full adders, multiplexers), the truth tables will face the problem of exponential state expansion, which limits the applicability; (3) lacking physical information, not considering physical characteristics, only focusing on logical functions, and performing poorly in tasks of processing post-mapped netlists, especially in tasks of evaluating the quality of physical designs. Summary of the Invention

[0004] Embodiments of this application provide a circuit diagram processing method and apparatus, an electronic device, and a computer-readable storage medium, which can solve the problem that the netlist encoder based only on the graph structure in the related art has obvious limitations.

[0005] In a first aspect, embodiments of this application provide a circuit diagram processing method, which includes: obtaining a gate-level netlist of a circuit diagram; converting the gate-level netlist into a text attribute graph, where the text attribute graph includes multiple gate nodes and a connectivity set, each gate node represents a logic gate in the circuit diagram, the text of the gate node is used to represent the function and physical characteristics of the logic gate represented by the gate node, and the connectivity set includes edges for connecting the gate nodes; inputting the text attribute graph into a cross-modal embedding model to obtain an embedding vector of the circuit diagram, where the embedding vector includes at least one of a gate-level embedding vector, a register-level embedding vector, and a graph-level embedding vector.

[0006] Second aspect, an embodiment of the present application provides a circuit diagram processing method, which includes: obtaining a training sample set, the training sample set includes a plurality of training samples, each training sample includes a text attribute graph, a layout graph and a register transfer level code of the circuit diagram, the text attribute graph is converted from the gate-level netlist of the circuit diagram, the text attribute graph includes a plurality of gate nodes and a connectivity set, each gate node represents a logic gate in the circuit diagram, the text of the gate node is used to represent the function and physical characteristics of the logic gate represented by the gate node, and the connectivity set includes edges for connecting the gate nodes; using the training sample set to train a cross-modal embedding model.

[0007] Third aspect, an embodiment of the present application provides a circuit diagram processing device, which includes: a first obtaining module, configured to obtain the gate-level netlist of the circuit diagram; a conversion module, configured to convert the gate-level netlist into a text attribute graph, the text attribute graph includes a plurality of gate nodes and a connectivity set, each gate node represents a logic gate in the circuit diagram, the text of the gate node is used to represent the function and physical characteristics of the logic gate represented by the gate node, and the connectivity set includes edges for connecting the gate nodes; an input module, configured to input the text attribute graph into a cross-modal embedding model to obtain an embedding vector of the circuit diagram, the embedding vector includes at least one of a gate-level embedding vector, a register-level embedding vector and a graph-level embedding vector.

[0008] Fourth aspect, an embodiment of the present application provides a circuit diagram processing device, which includes: a second obtaining module, configured to obtain a training sample set, the training sample set includes a plurality of training samples, each training sample includes a text attribute graph, a layout graph and a register transfer level code of the circuit diagram, the text attribute graph is converted from the gate-level netlist of the circuit diagram, the text attribute graph includes a plurality of gate nodes and a connectivity set, each gate node represents a logic gate in the circuit diagram, the text of the gate node is used to represent the function and physical characteristics of the logic gate represented by the gate node, and the connectivity set includes edges for connecting the gate nodes; a training module, configured to use the training sample set to train a cross-modal embedding model.

[0009] Fifth aspect, an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable by the processor. When the processor executes the computer program, the circuit diagram processing method described in the above first aspect or second aspect is implemented.

[0010] Sixth aspect, an embodiment of the present application provides a computer-readable storage medium, storing a computer program, and when the computer program is executed by a processor, the circuit diagram processing method described in the above first aspect or second aspect is implemented.

[0011] In a seventh aspect, an embodiment of the present application provides a computer program product. When the computer program product runs on an electronic device, it causes the electronic device to execute the circuit diagram processing method described in the above first aspect or second aspect.

[0012] The beneficial effects of the embodiments of the present application compared with the prior art are as follows: By obtaining the gate-level netlist of the circuit diagram; converting the gate-level netlist into a text attribute graph, the text attribute graph includes a plurality of gate nodes and a connectivity set, each gate node represents a logic gate in the circuit diagram, the text of the gate node is used to represent the function and physical characteristics of the logic gate represented by the gate node, and the connectivity set includes edges for connecting the gate nodes; inputting the text attribute graph into a cross-modal embedding model to obtain an embedding vector of the circuit diagram, the embedding vector includes at least one of a gate-level embedding vector, a register-level embedding vector, and a graph-level embedding vector. The text attribute graph can represent any type of gate, so that the circuit diagrams that can be processed go beyond the limitations of the AIG format; compared with the netlist encoder that relies on complex function supervision, the text makes static analysis simple, covers all input conditions, and does not have the problem of exponential growth due to exhaustive truth table simulation; the physical characteristics in the text enable the model to evaluate the physical design quality, thus effectively expanding the range of circuit diagrams that the cross-modal embedding model can process and the applicable range of the obtained embedding vectors, and improving the generality of the cross-modal embedding model. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0014] Figure 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0015] Figure 2 is a schematic flowchart of a circuit diagram processing method provided by an embodiment of the present application;

[0016] Figure 3 is a schematic diagram of generating a symbolic expression of a logic gate in a specific example of the present application;

[0017] Figure 4 is Figure 2 the specific flowchart of S13 in

[0018] Figure 5 is a schematic architecture diagram of a cross-modal embedding model provided by an embodiment of the present application;

[0019] Figure 6In the case where the embedded vector includes a register-level embedded vector Figure 4 The specific process schematic diagram of S340 in

[0020] Figure 7 In the case where the embedded vector does not include a register-level embedded vector Figure 4 The specific process schematic diagram of S340 in

[0021] Figure 8 The process schematic diagram of the circuit diagram processing method provided by another embodiment of the present application;

[0022] Figure 9 Is Figure 8 The specific process schematic diagram of S22 in

[0023] Figure 10 The structural schematic diagram of the circuit diagram processing device provided by an embodiment of the present application;

[0024] Figure 11 The structural schematic diagram of the circuit diagram processing device provided by another embodiment of the present application. Detailed implementation manners

[0025] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system architectures, technologies, etc. are proposed to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.

[0026] It should be understood that when used in the specification and appended claims of the present application, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0027] It should also be understood that the term "and / or" as used in the specification and appended claims of the present application refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0028] As used in the specification and appended claims of the present application, the term "if" can be interpreted as "when" or "once" or "in response to determining" or "in response to detecting" depending on the context. Similarly, the phrase "if determined" or "if detecting [the described condition or event]" can be interpreted as meaning "once determined" or "in response to determining" or "once detecting [the described condition or event]" or "in response to detecting [the described condition or event]" depending on the context.

[0029] In addition, in the description of the specification and the appended claims of the present application, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0030] The reference to "one embodiment" or "some embodiments" etc. described in the specification of the present application means that a specific feature, structure or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, the statements "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in another way.

[0031] The circuit diagram processing method provided by the embodiments of the present application can be applied to an electronic device, and the electronic device includes, but is not limited to, an electronic device with computing functions such as a server, a server cluster, a mobile phone, a tablet computer, a laptop computer, a desktop computer, a personal digital assistant, and a wearable device, etc. The embodiments of the present application do not impose any limitation on the specific type of the electronic device.

[0032] Figure 1 Shown is a block diagram of a part of the structure of the electronic device provided by the embodiments of the present application. Refer to Figure 1 , the electronic device includes: a processor 10, a memory 20, a bus 30, an input device 40, an output device 50, and a communication device 60. The processor 10 and the memory 20 are connected to each other through the bus 30, and the input device 40, the output device 50, and the communication device 60 are also connected to the bus 30. Those skilled in the art can understand that Figure 1 the structure of the electronic device shown in

[0033] does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements. Figure 1 The following specifically introduces each component of the electronic device:

[0034] The processor 10 is the control center of the electronic device. It can execute various functions and process data by running programs stored in the memory 20. The processor 10 can be a Central Processing Unit (CPU), and it can also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor, or it can be any conventional processor, etc. In some embodiments, the processor 10 can include an AI (Artificial Intelligence) processor, which is used to process computational operations related to machine learning.

[0035] The memory 20 is used to store the operating system, application programs, BootLoader, data, and other programs, such as the program code of computer programs. The memory 20 can also be used to temporarily store the data required for and generated during the execution of programs. The memory 20 can include high-speed random access memory, and can also include non-volatile memory, such as flash memory, hard disks, multimedia cards, card-type memories, etc. The memory 20 can include storage units provided inside the electronic device, such as the hard disk of the electronic device, and / or removable external storage units, such as external hard disks, USB flash drives, Smart Media Cards (SMCs), Secure Digital (SD) cards, etc.

[0036] The input device 40 can include at least one of a keyboard, a mouse, a touch panel, a joystick, etc., and is used to collect the input operations of the user to generate corresponding operation instructions.

[0037] The output device 50 is used to output the information to be provided to the user. The output device 50 generally includes a display, and optionally, a Liquid Crystal Display (LCD), an Organic Light-Emitting Diode (OLED), etc. can be used. In addition, the output device can further include a speaker.

[0038] The communication device 60 can include a modem, a network card, etc., and is used to establish a network connection with other electronic devices and communicate with each other.

[0039] The circuit diagram processing method provided by the embodiments of the present application can be implemented as a computer software program. For example, an embodiment of the present application provides a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes program codes for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 60, and / or installed from a removable external storage unit. When the computer program is executed by the processor 10, various functions defined in the circuit diagram processing method provided by the embodiments of the present application are implemented.

[0040] Figure 2 The schematic flowchart of the circuit diagram processing method provided by an embodiment of the present application is shown. By way of example and not limitation, this method can be applied to the above-mentioned electronic device.

[0041] S11: Obtain the gate-level netlist of the circuit diagram.

[0042] The gate-level netlist is an important concept in digital circuit design. It is the output result after the synthesis of the hardware description language (HDL) and is used to describe the specific implementation of the circuit at the logic gate level. The gate-level netlist usually includes logic gates (such as AND gates, OR gates, NOT gates, etc.) and the connection relationships between them. The gate-level netlist is a key step in the hardware design process and provides a basis for subsequent layout and physical design.

[0043] S12: Convert the gate-level netlist into a text attribute graph.

[0044] The text attribute graph, that is, a graph with text attributes, adds text for representing the attributes of each node on the basis of the traditional graph structure. Specifically, the text attribute graph includes multiple gate nodes and a connectivity set. Each gate node represents a logic gate in the circuit diagram, that is, the logic gates in the netlist correspond one-to-one with the nodes in the graph. The connectivity set includes edges for connecting the gate nodes. The edges are generally directed edges, and the direction of the edges is used to represent the signal flow direction in the circuit diagram, specifically flowing from the logic gate represented by the starting node to the logic gate represented by the target node.

[0045] The text of the gate node is used to represent the function and physical characteristics of the logic gate represented by the gate node, and specifically may include the symbolic expression and physical characteristics of the gate node. In order to represent the function of the logic gate, we extract its symbolic expression according to the k-hop input cone of the logic gate. The symbolic expression is the Boolean function expression of the gate nodes in the input cone of the gate node and provides a formal definition for the function of the gate. The physical characteristics include the information of the logic gate extracted from the standard cell library, specifically including power consumption, area, delay, switching rate, probability, load, capacitance, and resistance, etc.

[0046] For example, as Figure 3As shown, the 2-hop expression of the NOR gate named "U3" is derived from the Boolean functions of the logic gates within its 2-hop input cone, and is specifically expressed as: "U3 =!( (R1 ⊕ R2) |!R2 )". Each expression contains the symbolic names of the input logic gates and Boolean operations.

[0047] S13: Input the text attribute graph into the cross-modal embedding model to obtain the embedding vector of the circuit diagram.

[0048] As Figure 4 shown, S13 can include the following parts.

[0049] S310: Input the text of each gate node in the text attribute graph into the text encoder in the cross-modal embedding model to obtain the text embedding vector.

[0050] S320: Obtain the initial gate-level embedding vector based on the text embedding vector.

[0051] The functional part of the text can be input into the text encoder, and then the text embedding vector is combined with the physical property part in the text to obtain the initial gate-level embedding vector; or, the complete text can be input into the text encoder, and then the text embedding vector is combined with the physical property part in the text to obtain the initial gate-level embedding vector; or, the complete text can be input into the text encoder, and then the text embedding vector is directly used as the initial gate-level embedding vector.

[0052] S330: Replace the text of all nodes in the text attribute graph with the initial gate-level embedding vector.

[0053] S340: Input the text attribute graph into the graph transformer module in the cross-modal embedding model to obtain the embedding vector.

[0054] As Figure 5 shown, the cross-modal embedding model includes a text encoder and a graph transformer module.

[0055] The text encoder uses an encoder in the field of natural language processing as the backbone network, and the specific type is not restricted again here. For example, by converting causal attention to bidirectional attention, the large language model (LLM) that only decodes can be converted into a text encoder (ExprLLM), which is superior to the only encoding model (such as the bidirectional encoder representation BERT) in terms of encoding performance.

[0056] The graph transformer module (such as TAGFormer) uses a graph transformer model (i.e., a graph neural network of the Transformer type) to process the text attribute graph, and this model captures the graph structure through global attention to obtain the encoding result.

[0057] The embedding vector includes at least one of a gate-level embedding vector, a register-level embedding vector, and a graph-level embedding vector. According to the specific type of the embedding vector, this step can be implemented in different ways, as specifically described in the following embodiments.

[0058] As Figure 6 shown, when the embedding vector includes a register-level embedding vector, S340 may specifically include the following parts.

[0059] S341: Divide the text attribute graph into multiple subgraphs according to registers.

[0060] For each register, we start from its output logic gate (i.e., the logic gate responsible for external output), and perform a reverse search for all logic gates directly or indirectly connected to the output logic gate until we encounter other registers. All the logic gates finally searched and the output logic gate form a register cone representing the register, and the register cone is used as the subgraph representing the register. This partitioning process significantly reduces the scale of the graph that the cross-modal embedding model needs to process, enhancing the scalability of the model, especially in the scenario of processing large-scale sequential circuits.

[0061] S342: Insert graph nodes into each subgraph respectively.

[0062] The graph nodes are connected to all gate nodes in the text attribute graph. Correspondingly, edges between the graph nodes and all gate nodes are added to the connectivity set.

[0063] S343: Input the subgraph into the graph transformer module to obtain the encoding result.

[0064] S344: Use the text of the graph nodes in the encoding result as the register-level embedding vector.

[0065] The text of the graph nodes is the graph-level embedding vector of the subgraph. Since this subgraph is register-level, the text of the graph nodes is used as the register-level embedding vector.

[0066] S345: Perform pooling on all register-level embedding vectors to obtain the graph-level embedding vector.

[0067] S346: Use the text of the gate nodes in the encoding result as the gate-level embedding vector.

[0068] The execution order between S344 - S345 and S346 is only for illustration and is not actually limited.

[0069] As Figure 7 shown, when the embedding vector does not include a register-level embedding vector (for example, when processing combinational circuits), S340 may specifically include the following parts.

[0070] S351: Insert graph nodes into the text attribute graph.

[0071] The graph nodes connect all the gate nodes in the text attribute graph. Correspondingly, edges between the graph nodes and all the gate nodes are added to the connectivity set.

[0072] S352: Input the text attribute graph into the graph transformer module to obtain the encoded result of the text attribute graph.

[0073] S353: Use the text of the graph nodes in the encoded result as the graph-level embedding vector.

[0074] S354: Use the text of the gate nodes in the encoded result as the gate-level embedding vector.

[0075] The execution order between S353 and S354 is only for illustration and there is no actual limitation.

[0076] S14: Perform downstream tasks based on the embedding vectors.

[0077] In some embodiments, this step can be omitted.

[0078] For downstream tasks, a lightweight task model (such as a multi-layer perceptron or a tree-based model) can be used to further process the embedding vectors. The multi-granularity embedding vectors that the cross-modal embedding model can output support downstream tasks that can include regression and classification of circuit diagrams in functional and physical tasks, such as logic gate function recognition, timing register function recognition, endpoint register timing margin prediction, overall circuit power consumption / area, etc. For functional tasks, the lightweight task model predicts early register transfer level (RTL) information on the netlist, such as gate functions and register types; for physical tasks, it predicts metrics in the later layout stage, such as register endpoint timing margin, power consumption, and area.

[0079] Through the implementation of this embodiment, the text attribute graph can represent any type of gate, thus enabling the processed circuit diagrams to go beyond the limitations of the AIG format; compared with the netlist encoder that relies on complex functional supervision, the text makes static analysis simple, covering all input conditions without the exponential growth problem caused by exhaustive truth table simulation; the physical characteristics in the text enable the model to evaluate the physical design quality, thus effectively expanding the range of circuit diagrams that the cross-modal embedding model can process and the applicable range of the obtained embedding vectors, and improving the generality of the cross-modal embedding model.

[0080] Figure 8 The schematic flowchart of the circuit diagram processing method provided by another embodiment of the present application is shown. As an example but not a limitation, this method can be applied to the above-mentioned electronic device.

[0081] S21: Obtain a training sample set.

[0082] The training sample set includes multiple training samples, and each training sample includes a text attribute graph, a layout graph, and RTL code of a circuit diagram. The text attribute graph is converted from the gate-level netlist of the circuit diagram, and the specific description refers to the foregoing embodiments and will not be repeated here.

[0083] RTL (Register-Transfer Level) code is an abstraction level in a hardware description language (HDL, such as Verilog or VHDL) used to describe digital circuits. The RTL code describes the flow of data between registers and the operations performed on these registers. It is a key stage in digital circuit design, usually used to implement specific hardware functions and ultimately synthesized into an actual hardware circuit.

[0084] The text attribute graph can correspond to the complete circuit diagram or the register cone in the complete circuit diagram, which is not limited here, but needs to be consistent with the RTL and layout data to ensure functional equivalence during subsequent alignment.

[0085] S22: Train the cross-modal embedding model using the training sample set.

[0086] The cross-modal embedding model includes a text encoder and a graph transformer module. The cross-modal embedding model is trained in stages.

[0087] As Figure 9 shown, in a specific embodiment of the present application, S22 includes the following parts.

[0088] S221: Train the text encoder using the text of the gate nodes in the training sample.

[0089] During the training process of the text encoder, the graph transformer module does not work.

[0090] The training of the text encoder adopts symbolic expression contrastive learning, and the goal is to enhance its understanding of Boolean expressions. Specifically, a dataset of expressions is constructed from the symbolic expressions in the text of the gate nodes in the training sample, and each expression is transformed using randomly applied Boolean equivalence rules to generate corresponding transformed samples. The symbolic expression and its transformed sample form a positive sample pair, and two different symbolic expressions form a negative sample pair. The loss function used for training is InfoNCE (InfoNCE), as follows:

[0091]

[0092] where represents the temperature scaling factor, used to control the sharpness of the distribution; T represents the expression dataset, T +denote the conversion samples, k denote the total number of symbolic expressions, and T ori denote a symbolic expression in T, and T i denote the other samples in T except T ori That is, i ≠ ori.

[0093] S222: Freeze the text encoder, perform self-supervised training on the graph transformer module using the text attribute graph in the training samples, and then perform cross-stage alignment on the graph transformer module using the layout graph and register transfer level code in the training samples.

[0094] Freezing means that during the process of training the graph transformer module, the parameters of the text encoder will not change.

[0095] To support the output of multi-granularity embedding vectors, the graph transformer module adopts self-supervised training, and the goals include gate level and graph level. For example, the goals of self-supervised training can include the following 3.

[0096] Goal #2.1: Masked logic gate reconstruction. This goal aims to capture the structural roles of different logic gates by leveraging the connectivity of each logic gate in the graph. Specifically, use a special [MASK] node to randomly mask a part of the logic gates in the graph, and the task of the model is to predict the type of the masked logic gate (e.g., NOR, MUX, AND, etc.) based on the remaining unmasked nodes.

[0097] This goal is defined as a multi-objective classification problem, and the type of the logic gate is the target to be predicted. During the training process, first mask some of the logic gates in the graph. The masked logic gates are called masked gates, and use the graph transformer module to generate masked node embeddings for each masked gate Then, a classification multi-layer perceptron (MLP class ) takes the masked node embeddings as input and outputs the predicted probability distribution of the gate type. The loss function of this goal is as follows.

[0098]

[0099] where denote all the masked gates, denote the true gate type of the masked gate i.

[0100] Objective #2.2: Graph Contrastive Learning. This objective captures global structural and functional information by clustering similar text attribute graphs and separating dissimilar ones. Positive samples are generated by functionally equivalent transformation of text attribute graphs, while negative samples are different text attribute graphs from different samples in the training set. The loss function for this objective is also the InfoNCE loss, which minimizes the distance between positive sample pairs while maximizing the separation from negative samples, as shown below.

[0101]

[0102] Where N cls represents the encoding result of text attribute graphs in the training set, and represents the generated positive samples.

[0103] Objective #2.3: Graph Size Prediction. This objective aims to predict the number of each type of gate in a given text attribute graph based on the graph-level embedding vector, which is formulated as a regression problem. Let the vector y size represent the true gate count of the text attribute graph G N . An auxiliary model MLPregr is adopted, which takes the graph-level embedding vector N cls as input and outputs the predicted logic gate count, which is a vector with the same dimension as y size . The objective is to minimize the mean squared error (MSE) between the predicted gate count and the actual gate count, and the specific loss function is shown below.

[0104]

[0105] Where n represents the total number of gate types, that is, the number of elements in y size , and each element corresponds to the total number of a certain type of logic gate in the text attribute graph.

[0106] After completing self-supervised training, we use the layout graphs and RTL codes in the training samples to perform cross-stage alignment on the graph transformer module to improve the cross-stage alignment of the model, which is beneficial for downstream functional and physical tasks.

[0107] The RTL code is directly processed as text containing functional semantics, while the layout data is represented as a connected graph with physical characteristics. Specifically, the nodes in the layout graph are annotated with capacitance, resistance, and delay values extracted from the standard parasitic extraction format (SPEF) file.

[0108] The RTL code is processed using a pre-trained RTL encoder to generate RTL embeddings The layout encoder is a pre-trained graph transformer used to process the layout graph to generate layout embeddings These two encoders are only used during training. The alignment loss function is as follows.

[0109]

[0110] In summary, the loss function of the cross-modal embedding model (NetTAG) is as follows.

[0111]

[0112] Among them, Step1 represents the training process of the text encoder, and Step2 represents the training process of the graph transformer module.

[0113] Figure 10 The structural schematic diagram of a circuit diagram processing device provided by an embodiment of the present application is shown. The circuit diagram processing device includes a first acquisition module 11, a conversion module 12, and an input module 13.

[0114] The first acquisition module 11 is used to acquire the gate-level netlist of the circuit diagram.

[0115] The conversion module 12 is used to convert the gate-level netlist into a text attribute graph. The text attribute graph includes multiple gate nodes and a connectivity set. Each gate node represents a logic gate in the circuit diagram. The text of the gate node is used to represent the function and physical characteristics of the logic gate represented by the gate node. The connectivity set includes edges for connecting the gate nodes.

[0116] The input module 13 is used to input the text attribute graph into the cross-modal embedding model to obtain the embedding vector of the circuit diagram. The embedding vector includes at least one of the gate-level embedding vector, the register-level embedding vector, and the graph-level embedding vector.

[0117] Figure 11 The structural schematic diagram of a circuit diagram processing device provided by another embodiment of the present application is shown. The circuit diagram processing device includes a second acquisition module 21 and a training module 22.

[0118] The second acquisition module 21 is used to acquire a training sample set. The training sample set includes multiple training samples. Each training sample includes the text attribute graph, the layout graph, and the register transfer level code of the circuit diagram. The text attribute graph is converted from the gate-level netlist of the circuit diagram. The text attribute graph includes multiple gate nodes and a connectivity set. Each gate node represents a logic gate in the circuit diagram. The text of the gate node is used to represent the function and physical characteristics of the logic gate represented by the gate node. The connectivity set includes edges for connecting the gate nodes.

[0119] The training module 22 is used to train the cross-modal embedding model using the training sample set.

[0120] It should be noted that for the information interaction, execution process, etc. among the above-mentioned devices / modules / units, since they are based on the same concept as the method embodiments of this application, for their specific functions and the technical effects brought, reference can be specifically made to the method embodiment part, and details will not be repeated here.

[0121] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution is prior or posterior. The execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this application.

[0122] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the above division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of this application. The specific working process of the units and modules in the above system can refer to the corresponding process in the foregoing method embodiments, and details will not be repeated here.

[0123] The embodiments of this application also provide a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0124] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above-described embodiment methods of this application, a computer program can be used to instruct the relevant hardware to complete. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-described method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the photographing device / electronic device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal, and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk, or an optical disc, etc. In some jurisdictions, according to legislation and patent practice, the computer-readable medium cannot be an electrical carrier signal and a telecommunication signal.

[0125] In the above embodiments, the descriptions of the various embodiments have their own focuses. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0126] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0127] In the embodiments provided in this application, it should be understood that the disclosed device / network device and method can be implemented in other ways. For example, the device / network device embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0128] The unit described as a separation component may or may not be physically separated. The component shown as a unit may or may not be a physical unit, that is, it may be located in one place or may be distributed over multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0129] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A circuit diagram processing method, characterized in that: The method comprises: Get the gate-level netlist of the circuit diagram; Converting the gate-level netlist into a text attribute graph, wherein the text attribute graph includes a plurality of gate nodes and a connectivity set, each of the gate nodes represents a logic gate in the circuit diagram, the text of the gate node is used to represent the function and physical characteristics of the logic gate represented by the gate node, and the connectivity set includes edges for connecting the gate nodes; The text attribute graph is input into a cross-modal embedding model to obtain an embedding vector of the circuit diagram, wherein the embedding vector includes at least one of a gate-level embedding vector, a register-level embedding vector, and a graph-level embedding vector.

2. The method according to claim 1, characterized in that The step of inputting the text attribute graph into a cross-modal embedding model to obtain an embedding vector of the circuit diagram includes: Inputting the text of each gate node in the text attribute graph into a text encoder in the cross-modal embedding model to obtain a text embedding vector; Obtaining a gate-level initial embedding vector according to the text embedding vector; Replacing the text of all the nodes in the text attribute graph with the gate-level initial embedding vector; The text attribute graph is input into a graph transformer module in the cross-modal embedding model to obtain the embedding vector.

3. The method according to claim 2, characterized in that The embedding vector includes the register-level embedding vector, and the inputting the text attribute graph into the graph transformer module in the cross-modal embedding model to obtain the embedding vector includes: Dividing the text attribute graph into a plurality of sub-graphs according to registers; Inserting a graph node into each of the subgraphs respectively, wherein the graph node connects all the gate nodes in the subgraph; Inputting the sub-graph into the graph converter module to obtain an encoding result; The text of the graph node in the encoding result is used as the register-level embedding vector.

4. The method according to claim 3, characterized in that The embedding vector includes the graph-level embedding vector, and the step of inputting the text attribute graph into the graph transformer module in the cross-modal embedding model to obtain the embedding vector further includes: All the register-level embedding vectors are pooled to obtain the graph-level embedding vector.

5. The method according to claim 2, characterized in that The embedding vector includes the graph-level embedding vector, and the inputting the text attribute graph into the graph transformer module in the cross-modal embedding model to obtain the embedding vector includes: Inserting a graph node into the text attribute graph, wherein the graph node connects all the gate nodes in the text attribute graph; Inputting the text attribute graph into the graph converter module to obtain an encoding result of the text attribute graph; The text of the graph node in the encoding result is used as the graph-level embedding vector.

6. The method according to any one of claims 3 to 5, characterized in that: The embedding vector includes the gate-level embedding vector, and the inputting the text attribute graph into the graph transformer module in the cross-modal embedding model to obtain the embedding vector further includes: The text of the gate node in the encoding result is used as the gate-level embedding vector.

7. The method according to any one of claims 1 to 5, characterized in that: The text of the gate node includes a symbolic expression and physical properties of the gate node, wherein the symbolic expression is a Boolean function expression of the gate node in an input cone of the gate node.

8. A circuit diagram processing method, characterized in that: The method comprises: Acquire a training sample set, the training sample set includes a plurality of training samples, each of the training samples includes a text attribute graph, a layout graph and a register transfer level code of a circuit diagram, the text attribute graph is converted from a gate-level netlist of the circuit diagram, the text attribute graph includes a plurality of gate nodes and a connectivity set, each of the gate nodes represents a logic gate in the circuit diagram, the text of the gate node is used to represent the function and physical characteristics of the logic gate represented by the gate node, and the connectivity set includes edges for connecting the gate nodes; The cross-modal embedding model is trained using the training sample set.

9. The method according to claim 8, characterized in that The cross-modal embedding model includes a text encoder and a graph transformer module, and the training of the cross-modal embedding model using the training sample set includes: Using the text of the gate node in the training sample to train the text encoder; The text encoder is frozen, the graph transformer module is self-supervised trained using the text attribute graph in the training sample, and then the graph transformer module is cross-stage aligned using the layout graph and the register transfer level code in the training sample.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable by the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 9 is implemented.

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