Pixel circuit, driving method thereof, display substrate and display device

Abstract

A pixel circuit comprises a driving sub-circuit (11), a data writing sub-circuit (13), a compensation sub-circuit (12), a coupling sub-circuit (14) and a first control sub-circuit (15). The coupling sub-circuit (14) is coupled with a first node (N1) and a third node (N3). The first control sub-circuit (15) is configured to, after the data writing sub-circuit (13) writes a data signal into the third node (N3), write a first reference voltage signal provided by a first reference voltage line (REF1) into the third node (N3) under the control of a first control line (S1), so that the data signal is coupled to the first node (N1) through the coupling sub-circuit (14).

Description

[0001] This application is a divisional application of the application with the application number 202480001490.9 and the application name “Pixel Circuit and Driving Method Thereof, Display Substrate and Display Device” filed on July 30, 2024. TECHNICAL FIELD

[0002] The present document relates to, but is not limited to, the technical field of display, in particular to a pixel circuit and driving method thereof, a display substrate and a display device. BACKGROUND

[0003] Organic light emitting diode (OLED) has the advantages of ultra-thin, large viewing angle, active light-emitting, high brightness, continuous adjustable light-emitting color, low cost, fast response speed, low power consumption, wide working temperature range and flexible display, etc., and has gradually become the next generation display technology with great development prospects and is attracting more and more attention. According to the different driving modes, OLED can be divided into passive matrix (PM) and active matrix (AM). AMOLED is a current-driven device, which uses independent thin film transistors (TFT) to control each sub-pixel, and each sub-pixel can be continuously and independently driven to emit light. SUMMARY

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present embodiment provides a pixel circuit and driving method thereof, a display substrate and a display device.

[0006] In one aspect, the embodiment provides a pixel circuit, comprising a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a coupling sub-circuit, and a first control sub-circuit. The driving sub-circuit is coupled to a first node, a fourth node, and a fifth node, and is configured to provide a driving signal to the fourth node under the control of the first node. The compensation sub-circuit is coupled to a second scan line, the first node, and the fourth node, and is configured to turn on the first node and the fourth node under the control of the second scan line, so that the threshold voltage of the driving sub-circuit is written to the first node. The coupling sub-circuit is coupled to the first node and a third node. The data writing sub-circuit is coupled to a first scan line, a data line, and the third node, and is configured to provide a data signal provided by the data line to the third node under the control of the first scan line. The first control sub-circuit is coupled to a first control line, the third node, and a first reference voltage line, and is configured to write a first reference voltage signal provided by the first reference voltage line to the third node under the control of the first control line after the data writing sub-circuit writes the data signal to the third node, so that the data signal is coupled to the first node through the coupling sub-circuit.

[0007] In some example embodiments, the data writing sub-circuit writes the data signal to the third node for a time period shorter than that for the compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first node; and the data writing sub-circuit writes the data signal to the third node at a time later than that for the compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first node.

[0008] In some example embodiments, the second scan line provides an active level signal configured to control the compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first node. The data writing sub-circuit writes the data signal to the third node at a time a first time period after the second scan line provides an active level signal, and writes the data signal to the third node at a time a second time period after the second scan line provides an active level signal; and the second time period is shorter than the first time period.

[0009] In some example embodiments, the second scan line provides an active level signal configured to control the compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first node. The active level signal provided by the second scan line comprises three equal stages: a first signal stage, a second signal stage, and a third signal stage, and the active level signal provided by the first scan line starts after the first signal stage.

[0010] In some example embodiments, the coupling sub-circuit includes a first coupling sub-circuit and a second coupling sub-circuit, the first coupling sub-circuit is coupled to the first node and the second node, and the second coupling sub-circuit is coupled to the second node and the third node. The pixel circuit further includes a second control sub-circuit coupled to a second control line, the second node and a first voltage terminal, and configured to turn on the second node and the first voltage terminal under the control of the second control line, so that the second coupling sub-circuit stores a data signal written to the third node.

[0011] In some example embodiments, the first coupling sub-circuit includes a first capacitor, a first electrode of the first capacitor is coupled to the first node, and a second electrode of the first capacitor is coupled to the second node; and the second coupling sub-circuit includes a second capacitor, a first electrode of the second capacitor is coupled to the second node, and a second electrode of the second capacitor is coupled to the third node. The compensation sub-circuit includes a compensation transistor, a gate of the compensation transistor is coupled to the second scan line, a first electrode of the compensation transistor is coupled to the fourth node, and a second electrode of the compensation transistor is coupled to the first node. The second control sub-circuit includes a second control transistor, a gate of the second control transistor is coupled to the second control line, a first electrode of the second control transistor is coupled to the first voltage terminal, the first voltage terminal is coupled to a first power supply line, and a second electrode of the second control transistor is coupled to the second node.

[0012] In some example embodiments, the compensation transistor and the second control transistor are oxide thin film transistors, and the second control line and the second scan line are configured to provide the same signal.

[0013] In some example embodiments, the data writing sub-circuit includes a data writing transistor, a gate of the data writing transistor is coupled to the first scan line, a first electrode of the data writing transistor is coupled to the data line, and a second electrode of the data writing transistor is coupled to the third node. The first control sub-circuit includes a first control transistor, a gate of the first control transistor is coupled to the first control line, a first electrode of the first control transistor is coupled to the first reference voltage line, and a second electrode of the first control transistor is coupled to the third node. The compensation sub-circuit includes a compensation transistor, a gate of the compensation transistor is coupled to the second scan line, a first electrode of the compensation transistor is coupled to the fourth node, and a second electrode of the compensation transistor is coupled to the first node.

[0014] In some example embodiments, the data write transistor and the first control transistor are of the same transistor type, and different from the transistor type of the compensation transistor. The first control line and the second scan line are configured to provide the same signal.

[0015] In some example embodiments, the pixel circuit further comprises a first light emitting control sub-circuit coupled with the first light emitting control line, the first power line and the fifth node, and configured to write, under control of the first light emitting control line, a first power signal provided by the first power line to the fifth node. The first control line and the first light emitting control line are configured to provide the same signal.

[0016] In some example embodiments, the data write transistor and the first control transistor are of different transistor types, and the data write transistor and the compensation transistor are of the same transistor type.

[0017] In some example embodiments, the first control line and the first scan line are configured to transmit the same signal.

[0018] In some example embodiments, the pixel circuit further comprises a second light emitting control sub-circuit and a fourth reset sub-circuit. The second light emitting control sub-circuit is coupled with a second light emitting control line, the fourth node and a sixth node, and configured to turn on the fourth node and the sixth node under control of the second light emitting control line, the sixth node being coupled with a first electrode of the light emitting element. The fourth reset sub-circuit is coupled with the third node, the first reference voltage line and a third reset control line, and configured to write, under control of the third reset control line, a first reference voltage signal provided by the first reference voltage line to the third node.

[0019] In some example embodiments, the first control line and the second light emitting control line are configured to provide the same signal.

[0020] In some example embodiments, the pixel circuit further comprises: a first reset sub-circuit and a second reset sub-circuit. The first reset sub-circuit is coupled with the first reset control line, the first reset voltage line and the fourth node, and is configured to write, under the control of the first reset control line, a first reset voltage signal provided by the first reset voltage line to the fourth node; or the first reset sub-circuit is coupled with the first reset control line, the first reset voltage line and the first node, and is configured to write, under the control of the first reset control line, a first reset voltage signal provided by the first reset voltage line to the first node. The second reset sub-circuit is coupled with the second reset control line, the second reset voltage line and the sixth node, and is configured to write, under the control of the second reset control line, a second reset voltage signal provided by the second reset voltage line to the sixth node, the sixth node being coupled with the first electrode of the light emitting element.

[0021] In some example embodiments, the pixel circuit further comprises: a third reset sub-circuit coupled with the second reset control line, the second reference voltage line and the fifth node, and configured to write, under the control of the second reset control line, a second reference voltage signal provided by the second reference voltage line to the fifth node.

[0022] In some example embodiments, the pixel circuit further comprises: a third capacitor, a first electrode of the third capacitor being coupled with the first bias signal line, and a second electrode of the third capacitor being coupled with the first node or the second node.

[0023] In some example embodiments, the pixel circuit further comprises: a fourth capacitor, a first electrode of the fourth capacitor being coupled with the second bias signal line, and a second electrode of the fourth capacitor being coupled with the fourth node or the fifth node.

[0024] In another aspect, the present embodiment provides a driving method of a pixel circuit, applied to the pixel circuit as described above, the driving method comprising: under the control of the second scan line, the compensation sub-circuit turns on the first node and the fourth node, so that the threshold voltage of the driving sub-circuit is written to the first node; under the control of the first scan line, the data writing sub-circuit writes the data signal provided by the data line to the third node; under the control of the first control line, the first control sub-circuit writes the first reference voltage signal provided by the first reference voltage line to the third node, so that the data signal is coupled to the first node through the coupling sub-circuit; under the control of the first node, the driving sub-circuit provides a driving signal to the fourth node.

[0025] In another aspect, the embodiment provides a display substrate, comprising: a plurality of sub-pixels and at least one first scan driving circuit, at least one of the plurality of sub-pixels comprising a light emitting element and a pixel circuit for driving the light emitting element to emit light; the first scan driving circuit comprising: a plurality of first scan driving units; the pixel circuit being the pixel circuit as described above. An nth stage first scan driving unit is configured to provide a first scan signal to the pixel circuit of an nth row of sub-pixels; n being an integer greater than 0. Wherein, a 2i-1 stage first scan driving unit is cascaded with a 2i+1 stage first scan driving unit, a 2i stage first scan driving unit is cascaded with a 2i+2 stage first scan driving unit, i being an integer greater than 0.

[0026] In some example embodiments, the display substrate further comprises: a first light emitting driving circuit, the first light emitting driving circuit comprising a plurality of cascaded first light emitting driving units. An nth stage first light emitting driving unit is configured to provide a first light emitting control signal to the pixel circuit of an nth row of sub-pixels; or, configured to provide a first light emitting control signal to the pixel circuit of an 2n-1 row and an 2n row of sub-pixels.

[0027] In some example embodiments, the display substrate further comprises: a second scan driving circuit, a second light emitting driving circuit; the second scan driving circuit comprising a plurality of cascaded second scan driving units; the second light emitting driving circuit comprising a plurality of cascaded second light emitting driving units. An nth stage second scan driving circuit is configured to provide a second scan signal to the pixel circuit of an 2n-1 row and an 2n row of sub-pixels. An nth stage second light emitting driving circuit is configured to provide a second light emitting control signal to the pixel circuit of an 2n-1 row and an 2n row of sub-pixels. Wherein, the second scan driving circuit and the second light emitting driving circuit are located on the same side of the plurality of sub-pixels along the row direction of the sub-pixels.

[0028] In some example embodiments, the display substrate further comprises: a first reset driving circuit, a second reset driving circuit; the first reset driving circuit comprising a plurality of cascaded first reset driving units; the second reset driving circuit comprising a plurality of cascaded second reset driving units. An nth stage first reset driving circuit is configured to provide a first reset control signal to the pixel circuit of an 2n-1 row and an 2n row of sub-pixels. An nth stage second reset driving circuit is configured to provide a second reset control signal to the pixel circuit of an 2n-1 row and an 2n row of sub-pixels. Wherein, the first reset driving circuit and the second reset driving circuit are located on different sides of the plurality of sub-pixels along the row direction of the sub-pixels.

[0029] In another aspect, the embodiment provides a display device, comprising the display substrate as described above.

[0030] Other aspects can become apparent from a review of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0031] The accompanying drawings are included to provide a further understanding of the present technology and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present technology and, together with the description, serve to explain the principles of the present technology.

[0032] Figure 1 An equivalent circuit diagram of a pixel circuit;

[0033] Figure 2 A structure schematic diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0034] Figure 3 Another structure schematic diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0035] Figure 4 Another structure schematic diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0036] Figure 5 An equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0037] Figure 6 A working timing diagram of the pixel circuit shown in Figure 5

[0038] Figure 7 A driving architecture schematic diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0039] Figure 8 Another equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0040] Figure 9 A working timing diagram of the pixel circuit shown in Figure 8

[0041] Figure 10 Another driving architecture schematic diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0042] Figure 11 Another equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0043] Figure 12 A working timing diagram of the pixel circuit shown in Figure 11

[0044] Figure 13 Another driving architecture schematic diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0045] Figure 14 ​​​This is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0046] Figure 15 for Figure 14 The timing diagram of the pixel circuit shown is shown.

[0047] Figure 16 This is another schematic diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0048] Figure 17 This is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0049] Figure 18 for Figure 17 The timing diagram of the pixel circuit shown is shown.

[0050] Figure 19 This is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0051] Figure 20 for Figure 19 The timing diagram of the pixel circuit shown is shown.

[0052] Figure 21 This is another schematic diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0053] Figure 22 This is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0054] Figure 23 This is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0055] Figure 24 for Figure 23 The timing diagram of the pixel circuit shown is shown.

[0056] Figure 25 This is a schematic diagram of another driving architecture for a pixel circuit according to at least one embodiment of the present disclosure;

[0057] Figure 26 This is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0058] Figure 27 This is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0059] Figure 28 for Figure 27 The timing diagram of the pixel circuit shown is shown.

[0060] Figure 29 This is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0061] Figure 30 Flowchart of a driving method of a pixel circuit according to at least one embodiment of the present disclosure;

[0062] Figure 31 Schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. Embodiments can be implemented in a variety of different ways. It is readily apparent to one of ordinary skill in the art that a manner and content can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the content described in the following embodiments. Embodiments in the present disclosure and features in the embodiments can be arbitrarily combined so long as there is no conflict.

[0064] In the drawings, the size, the thickness, or the region of one or more constituent elements shown in the drawings can be exaggerated for clarity. Therefore, one embodiment of the present disclosure should not be construed as being limited to the size, the shape, and the relative arrangement of the components illustrated in the drawings. The embodiment of the present disclosure is not limited to the shape, the numerical value, and the like illustrated in the drawings.

[0065] In the present specification, ordinal terms such as "first", "second", and "third" are used to avoid confusion among constituent elements, and are not used to constitute a limitation as to the number thereof. In the present disclosure, "a plurality of" means two or more.

[0066] In the present specification, words of a similar meaning to "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the orientation or positional relationship of constituent elements are used to describe the positional relationship of the constituent elements with reference to the drawings, and are used only for convenience in describing the present specification and simplifying the description, and thus cannot be construed to indicate or imply that a device or an element directed thereby must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of the constituent elements described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0067] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", "connected", "coupled" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the meaning of the above terms in this disclosure can be understood according to the circumstances. Among them, "coupled" can include "electrically connected", "electrically connected" can include the case where the constituent elements are connected together through elements with certain electrical effects. "Elements with certain electrical effects" are not particularly limited as long as they can transmit electrical signals between the connected constituent elements. Examples of "elements with certain electrical effects" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements with multiple functions, and the like.

[0068] In this specification, a transistor refers to an element including at least three terminals of a gate (gate electrode), a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to a region where current flows mainly.

[0069] In this specification, the first electrode can be a drain, and the second electrode can be a source, or the first electrode can be a source, and the second electrode can be a drain. In addition, the gate can also be referred to as a control electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in circuit operation, the functions of the "source" and the "drain" are sometimes exchanged with each other. Therefore, in this specification, the "source" and the "drain" can be exchanged with each other.

[0070] In this specification, "about", "approximately", and the like mean that the limit is not strictly defined, and the range within the process and measurement error is allowed. In this disclosure, "the same" includes the case where the numerical value differs by 10% or less, such as the case where the numerical value differs by 5% or less.

[0071] In this disclosure, the active level signal includes a level signal for turning on a transistor, such as a low level signal for turning on a P-type transistor and a high level signal for turning on an N-type transistor.

[0072] Figure 1 An equivalent circuit diagram of a pixel circuit. As Figure 1As shown, the pixel circuit includes seven transistors (i.e., transistors T01 to T07) and one storage capacitor Cst. The seven transistors are of the same type, for example, all of the seven transistors are P-type transistors. The gates of the transistors T02 and T04 are connected to the first gate line GATE1, the gate of the transistor T01 is connected to the second gate line GATE2, the gate of the transistor T07 is connected to the third gate line GATE3, and the gates of the transistors T05 and T06 are connected to the emission control line EML. In the pixel circuit, the data voltage provided by the data signal line DATA can drive the transistor T03 to write the data voltage and compensate the threshold voltage Vth. In the data writing stage, the transistors T02 and T04 use the same scanning signal provided by the first gate line GATE1 to realize data writing and threshold voltage compensation.

[0073] However, with the increase of the resolution and the increase of the frequency of the display device, the above-mentioned scheme of threshold voltage compensation using data voltage will appear a driving bottleneck. For example, with the increase of the display refresh rate, the data writing time length (1H) of a single row of pixel circuits in a frame will gradually decrease, and with the decrease of the data writing time length, the phenomenon of difficult data writing and insufficient threshold voltage compensation will appear.

[0074] The present embodiment provides a pixel circuit and a driving method thereof, a display substrate and a display device, which can improve the compensation effect of the threshold voltage and thus improve the display performance.

[0075] Figure 2 A structural schematic diagram of a pixel circuit of at least one embodiment of the present disclosure. In some examples, as shown in FIG. 1, the pixel circuit includes seven transistors (i.e., transistors T01 to T07) and one storage capacitor Cst. The seven transistors are of the same type, for example, all of the seven transistors are P-type transistors. The gates of the transistors T02 and T04 are connected to the first gate line GATE1, the gate of the transistor T01 is connected to the second gate line GATE2, the gate of the transistor T07 is connected to the third gate line GATE3, and the gates of the transistors T05 and T06 are connected to the emission control line EML. In the pixel circuit, the data voltage provided by the data signal line DATA can drive the transistor T03 to write the data voltage and compensate the threshold voltage Vth. In the data writing stage, the transistors T02 and T04 use the same scanning signal provided by the first gate line GATE1 to realize data writing and threshold voltage compensation. Figure 2As shown, the pixel circuit of the embodiment can at least include a driving sub-circuit 11, a data writing sub-circuit 13, a compensation sub-circuit 12, a coupling sub-circuit 14 and a first control sub-circuit 15. The driving sub-circuit 11 is coupled with the first node N1, the fourth node N4 and the fifth node N5, and is configured to provide a driving signal to the fourth node N4 under the control of the first node N1. The compensation sub-circuit 12 is coupled with the second scan line GL2, the first node N1 and the fourth node N4, and is configured to turn on the first node N1 and the fourth node N4 under the control of the second scan line GL2, so that the threshold voltage of the driving sub-circuit 11 is written to the first node N1. The coupling sub-circuit 14 is coupled with the first node N1 and the third node N3. The data writing sub-circuit 13 is coupled with the first scan line GL1, the data line DL and the third node N3, and is configured to provide a data signal provided by the data line DL to the third node N3 under the control of the first scan line GL1. The first control sub-circuit 15 is coupled with the first control line S1, the third node N3 and the first reference voltage line REF1, and is configured to write a first reference voltage signal provided by the first reference voltage line REF1 to the third node N3 under the control of the first control line S1 after the data writing sub-circuit 13 writes the data signal to the third node N3, so that the data signal is coupled to the first node N1 through the coupling sub-circuit 14.

[0076] The pixel circuit provided by the embodiment can separate the data writing process and the threshold voltage compensation process through the coupling sub-circuit, which is beneficial to improve the compensation effect of the threshold voltage, thereby improving the display performance.

[0077] In some examples, the duration for which the data writing sub-circuit 13 writes the data signal to the third node N3 can be less than the duration for which the compensation sub-circuit 12 writes the threshold voltage of the driving sub-circuit 11 to the first node N1. The starting time at which the data writing sub-circuit 13 writes the data signal to the third node N3 can be later than the starting time at which the compensation sub-circuit 12 writes the threshold voltage of the driving sub-circuit 11 to the first node N1. The present example can control the data writing process and the threshold voltage compensation process separately, and by increasing the compensation duration of the threshold voltage, the compensation effect of the threshold voltage can be improved, thereby improving the picture display uniformity. Moreover, the writing time of the data signal is later than the writing time of the threshold voltage, which can be beneficial to ensure the effectiveness of the data signal.

[0078] In some examples, the first scan line GL1 can be configured to provide a first scan signal, and the second scan line GL2 can be configured to provide a second scan signal. The first scan signal can be configured to control the data writing sub-circuit 13 to write the data signal to the third node N3, and the second scan signal can be configured to control the compensation sub-circuit 12 to write the threshold voltage of the driving sub-circuit 11 to the first node N1. The first scan signal can be different from the second scan signal. For example, the duration of the active level signal of the first scan signal can be less than the duration of the active level signal of the second scan signal. The first scan signal and the second scan signal can be provided by different scan driving circuits; for example, the first scan signal can be provided by a first scan driving circuit, and the second scan signal can be provided by a second scan driving circuit. This example can increase the compensation duration of the threshold voltage by separating the data signal writing and the threshold voltage compensation stages, so that the threshold voltage compensation time is sufficient, which is conducive to improving the compensation effect of the threshold voltage.

[0079] In some examples, the second scan line GL2 can be configured to provide an active level signal to control the compensation sub-circuit 12 to write the threshold voltage of the driving sub-circuit 11 to the first node N1. The end time of the data writing sub-circuit 13 writing the data signal to the third node N3 can be a first duration from the start time of the active level signal provided by the second scan line GL2, and the end time of the data writing sub-circuit 13 writing the data signal to the third node N3 can be a second duration from the end time of the active level signal provided by the second scan line GL2; the second duration is less than the first duration. This example can increase the compensation duration of the threshold voltage by performing the data writing process in the second half of the threshold voltage compensation stage, so that the threshold voltage compensation time is sufficient, which is conducive to improving the compensation effect of the threshold voltage.

[0080] In some examples, the second scan line GL2 can be configured to provide an active level signal to control the compensation sub-circuit 12 to write the threshold voltage of the driving sub-circuit 11 to the first node N1. The active level signal provided by the second scan line GL2 can include the following three equalization stages: a first signal stage, a second signal stage, and a third signal stage, and the start time of the active level signal provided by the first scan line GL1 can be located after the first signal stage. This example can increase the compensation duration of the threshold voltage by performing the data writing process in the second half of the threshold voltage compensation stage, so that the threshold voltage compensation time is sufficient, which is conducive to improving the compensation effect of the threshold voltage.

[0081] Figure 3 Another structural schematic diagram of the pixel circuit of at least one embodiment of the present disclosure. In some examples, as shown in FIG. 8, the pixel circuit can include a driving sub-circuit 11, a compensation sub-circuit 12, a data writing sub-circuit 13, a first scan line GL1, and a second scan line GL2. The driving sub-circuit 11 can include a driving transistor M1, and the driving transistor M1 can be configured to receive a driving signal Vdd and provide a driving current Id to a pixel electrode. The compensation sub-circuit 12 can include a compensation transistor M2, and the compensation transistor M2 can be configured to receive a compensation signal Vcomp and provide a compensation current Icomp to the first node N1. The data writing sub-circuit 13 can include a data writing transistor M3, and the data writing transistor M3 can be configured to receive a data signal Vdata and provide a data current Idatato the third node N3. The first scan line GL1 can be configured to provide a first scan signal, and the second scan line GL2 can be configured to provide a second scan signal. The first scan signal can be configured to control the data writing sub-circuit 13 to write the data signal to the third node N3, and the second scan signal can be configured to control the compensation sub-circuit 12 to write the threshold voltage of the driving sub-circuit 11 to the first node N1. The first scan signal can be different from the second scan signal. For example, the duration of the active level signal of the first scan signal can be less than the duration of the active level signal of the second scan signal. The first scan signal and the second scan signal can be provided by different scan driving circuits; for example, the first scan signal can be provided by a first scan driving circuit, and the second scan signal can be provided by a second scan driving circuit. This example can increase the compensation duration of the threshold voltage by separating the data signal writing and the threshold voltage compensation stages, so that the threshold voltage compensation time is sufficient, which is conducive to improving the compensation effect of the threshold voltage. Figure 3As shown, the pixel circuit of the embodiment can at least include: a driving sub-circuit 11, a data writing sub-circuit 13, a compensation sub-circuit 12, a coupling sub-circuit 14, a first control sub-circuit 15 and a second control sub-circuit 16.

[0082] In some examples, the coupling sub-circuit 14 can include: a first coupling sub-circuit 141 and a second coupling sub-circuit 142. The first coupling sub-circuit 141 is coupled with the first node N1 and the second node N2, and the second coupling sub-circuit 142 is coupled with the second node N2 and the third node N3. The second control sub-circuit 16 is coupled with the second control line S2, the second node N2 and the first voltage terminal VL, and is configured to turn on the second node N2 and the first voltage terminal VL under the control of the second control line S2, so that the second coupling sub-circuit 142 stores the data signal written to the third node N3. The remaining structure of the pixel circuit of the present example can refer to the description of the foregoing embodiments, and will not be described here.

[0083] In some examples, the first control line S1 can be configured to provide a first control signal, and the second control line S2 can be configured to provide a second control signal. The first control signal can be configured to control the writing of the first reference voltage signal to the third node N3, and the second control signal can be configured to control the writing of the voltage signal provided by the first voltage terminal VL to the second node N2. The second control signal can be the same as the second scanning signal. The first control signal can be the same as the second control signal, or can be different from the second control signal. For example, the duration of the active level signal of the first control signal can be greater than or equal to the duration of the active level signal of the second control signal. In some examples, the first control signal, the second control signal and the second scanning signal can be the same. The present example utilizes the first control signal provided by the first control line S1 to control the potential of the third node N3, which can improve the leakage of the third node.

[0084] Figure 4 Another structural schematic diagram of the pixel circuit of at least one embodiment of the present disclosure is shown. In some examples, as shown, Figure 4 The pixel circuit of the embodiment can include: a driving sub-circuit 11, a compensation sub-circuit 12, a data writing sub-circuit 13, a first coupling sub-circuit 141, a second coupling sub-circuit 142, a first control sub-circuit 15, a second control sub-circuit 16, a first light emitting control sub-circuit 21, a second light emitting control sub-circuit 22, a first reset sub-circuit 23, a second reset sub-circuit 24 and a third reset sub-circuit 25.

[0085] In some examples, the first light emitting control sub-circuit 21 is coupled with the first light emitting control line EM1, the first power supply line VDD and the fifth node N5, and is configured to write, under the control of the first light emitting control line EM1, the first power signal provided by the first power supply line VDD to the fifth node N5. The second light emitting control sub-circuit 22 is coupled with the second light emitting control line EM2, the fourth node N4 and the sixth node N6, and is configured to turn on the fourth node N4 and the sixth node N6 under the control of the second light emitting control line EM2. The first reset sub-circuit 23 is coupled with the first reset control line RST1, the first reset voltage line INIT1 and the fourth node N4, and is configured to write, under the control of the first reset control line RST1, the first reset voltage signal provided by the first reset voltage line INIT1 to the fourth node N4. The second reset sub-circuit 24 is coupled with the second reset control line RST2, the second reset voltage line INIT2 and the sixth node N6, and is configured to write, under the control of the second reset control line RST2, the second reset voltage signal provided by the second reset voltage line INIT2 to the sixth node N6. The third reset sub-circuit 25 is coupled with the second reset control line RST2, the second reference voltage line REF2 and the fifth node N5, and is configured to write, under the control of the second reset control line RST2, the second reference voltage signal provided by the second reference voltage line REF2 to the fifth node N5. The first electrode of the light emitting element is coupled with the sixth node N6, and the second electrode of the light emitting element is coupled with the second power supply line VSS. The remaining structure of the pixel circuit in this example can refer to the description of the foregoing embodiments, and will not be described here.

[0086] In some examples, the light emitting element can be an organic light emitting diode (OLED). The first electrode of the light emitting element can be an anode, and the second electrode can be a cathode. However, the present embodiment is not limited thereto.

[0087] In some examples, the second reset sub-circuit 24 resets the sixth node N6, which can eliminate the leakage current of the second light emitting control sub-circuit 22, avoid the light emitting element from emitting light in the dark state due to the leakage current, and improve the display quality. Moreover, the second reset sub-circuit 24 can eliminate the residual positive charges on the surface of the first electrode of the light emitting element, and improve the service life of the light emitting element. The third reset sub-circuit 25 can write the second reference voltage to the fifth node N5 to reset the fifth node N5. The first reset sub-circuit 23 can reset the fourth node N4.

[0088] In some examples, the first light emitting control line EM1 can be configured to provide a first light emitting control signal, and the second light emitting control line EM2 can be configured to provide a second light emitting control signal. The first light emitting control signal can be configured to control the first light emitting control sub-circuit 21 to write the first power signal to the fifth node N5, and the second light emitting control signal can be configured to control the second light emitting control sub-circuit 22 to turn on the fourth node N4 and the sixth node N6 to provide the driving signal to the light emitting element, so that the light emitting element emits light. The first light emitting control signal can be different from the second light emitting control signal. For example, the first control signal can be the same as the first light emitting control signal, or the first control signal can be the same as the second light emitting control signal. The first light emitting control signal and the second light emitting control signal can be provided by different light emitting driving circuits; for example, the first light emitting control signal can be provided by a first light emitting driving circuit, and the second light emitting control signal can be provided by a second light emitting driving circuit.

[0089] In some examples, the first reset control line RST1 can be configured to provide a first reset control signal, and the second reset control line RST2 can be configured to provide a second reset control signal. The first reset control signal can be configured to control the first reset sub-circuit 23 to reset the fourth node N4, and the second reset control signal can be configured to control the second reset sub-circuit 24 to reset the sixth node N6, and control the third reset sub-circuit 25 to reset the fifth node N5. The first reset control signal can be different from the second reset control signal. The first reset control signal and the second reset control signal can be provided by different reset driving circuits; for example, the first reset control signal can be provided by a first reset driving circuit, and the second reset control signal can be provided by a second reset driving circuit.

[0090] In some examples, the first power line VDD can continuously provide a constant high level signal, for example, the first power line VDD can provide the first power signal. The second power line VSS can continuously provide a constant low level signal, for example, the second power line VSS can provide the second power signal. The first power signal can be greater than the second power signal.

[0091] In some examples, the first voltage terminal VL can be coupled with a wire providing a stabilized voltage signal, for stabilizing the potential of the second node N2. For example, the first voltage terminal VL can be coupled with the first power line VDD.

[0092] In some examples, the first reference voltage line REF1 can be configured to provide a first reference voltage signal, and the second reference voltage line REF2 can be configured to provide a second reference voltage signal. The first reference voltage signal and the second reference voltage signal can be different. For example, the first reference voltage signal and the second reference voltage signal can both be less than the first power signal.

[0093] In some examples, the first reset voltage line INIT1 can be configured to provide a first reset voltage signal, and the second reset voltage line INIT2 can be configured to provide a second reset voltage signal. The first reset voltage signal and the second reset voltage signal can be the same or different. This embodiment is not limited in this respect.

[0094] Figure 5 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, such as... Figure 5 As shown, the driving sub-circuit 11 may include a driving transistor T3; the compensation sub-circuit 12 may include a compensation transistor T2; the data writing sub-circuit 13 may include a data writing transistor T4; the first coupling sub-circuit 141 may include a first capacitor C1; the second coupling sub-circuit 142 may include a second capacitor C2; the first control sub-circuit 15 may include a first control transistor T10; the second control sub-circuit 16 may include a second control transistor T9; the first light-emitting control sub-circuit 21 may include a first light-emitting control transistor T5; the second light-emitting control sub-circuit 22 may include a second light-emitting control transistor T6; the first reset sub-circuit 23 may include a first reset transistor T1; the second reset sub-circuit 24 may include a second reset transistor T7; and the third reset sub-circuit 25 may include a third reset transistor T8.

[0095] In some examples, such as Figure 5As shown, the gate of the driving transistor T3 is coupled with the first node N1, the first electrode of the driving transistor T3 is coupled with the fifth node N5, and the second electrode of the driving transistor T3 is coupled with the fourth node T4. The gate of the compensation transistor T2 is coupled with the second scan line GL2, the first electrode of the compensation transistor T2 is coupled with the fourth node N4, and the second electrode of the compensation transistor T2 is coupled with the first node N1. The gate of the data write transistor T4 is coupled with the first scan line GL1, the first electrode of the data write transistor T4 is coupled with the data line DL, and the second electrode of the data write transistor T4 is coupled with the third node N3. The first electrode of the first capacitor C1 is coupled with the first node N1, and the second electrode of the first capacitor C1 is coupled with the second node N2. The first electrode of the second capacitor C2 is coupled with the second node N2, and the second electrode of the second capacitor C2 is coupled with the third node N3. The gate of the second control transistor T9 is coupled with the second control line S2, the first electrode of the second control transistor T9 is coupled with the first power supply line VDD, i.e., the first voltage terminal is coupled with the first power supply line VDD, and the second electrode of the second control transistor T9 is coupled with the second node N2. The gate of the first control transistor T10 is coupled with the first control line S1, the first electrode of the first control transistor T10 is coupled with the first reference voltage line REF1, and the second electrode of the first control transistor T10 is coupled with the third node N3. The gate of the first light emitting control transistor T5 is coupled with the first light emitting control line EM1, the first electrode of the first light emitting control transistor T5 is coupled with the first power supply line VDD, and the second electrode of the first light emitting control transistor T5 is coupled with the fifth node N5. The gate of the second light emitting control transistor T6 is coupled with the second light emitting control line EM2, the first electrode of the second light emitting control transistor T6 is coupled with the fourth node N4, and the second electrode of the second light emitting control transistor T6 is coupled with the sixth node N6. The gate of the first reset transistor T1 is coupled with the first reset control line RST1, the first electrode of the first reset transistor T1 is coupled with the first reset voltage line INIT1, and the second electrode of the first reset transistor T1 is coupled with the fourth node N4. The gate of the second reset transistor T7 is coupled with the second reset control line RST2, the first electrode of the second reset transistor T7 is coupled with the second reset voltage line INIT2, and the second electrode of the second reset transistor T7 is coupled with the sixth node N6. The gate of the third reset transistor T8 is coupled with the second reset control line RST2, the first electrode of the third reset transistor T8 is coupled with the second reference voltage line REF2, and the second electrode of the third reset transistor T8 is coupled with the fifth node N5. The first electrode of the light emitting element EL is coupled with the sixth node N6, and the second electrode of the light emitting element EL is coupled with the second power supply line VSS.

[0096] In some examples, the first node N1 is the connection point of the first capacitor C1, the compensation transistor T2, and the driving transistor T3. The second node N2 is the connection point of the first capacitor C1, the second capacitor C2, and the second control transistor T9. The third node N3 is the connection point of the second capacitor C2, the data writing transistor T4, and the first control transistor T10. The fourth node N4 is the connection point of the first reset transistor T1, the compensation transistor T2, the driving transistor T3, and the second light-emitting control transistor T6. The fifth node N5 is the connection point of the first light-emitting control transistor T5, the third reset transistor T8, and the driving transistor T3. The sixth node N6 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7, and the light-emitting element EL.

[0097] Figure 5 An exemplary structure of the driving sub-circuit 11, compensation sub-circuit 12, data writing sub-circuit 13, first coupling sub-circuit 141, second coupling sub-circuit 142, first control sub-circuit 15, second control sub-circuit 16, first light emission control sub-circuit 21, second light emission control sub-circuit 22, first reset sub-circuit 23, second reset sub-circuit 24, and third reset sub-circuit 25 is shown. It will be readily understood by those skilled in the art that the implementation of the above sub-circuits is not limited to this, as long as their functions can be achieved.

[0098] In some examples, such as Figure 5 As shown, the compensation transistor T2 and the second control transistor T9 can be N-type thin-film transistors, such as oxide thin-film transistors; the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, the third reset transistor T8, and the first control transistor T10 can be P-type thin-film transistors, such as low-temperature polycrystalline silicon (LTPS) thin-film transistors. The active layer of the LTPS thin-film transistor can be made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide thin-film transistor can be made of oxide semiconductor (Oxide). LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, reducing power consumption and improving display quality.

[0099] Figure 6 for Figure 5 The timing diagram of the pixel circuit shown is as follows. Figure 5As shown, the pixel circuit of the present example can include: 10 transistors (i.e., transistors T1-T10), 2 capacitor units (i.e., a first capacitor C1 and a second capacitor C2), 13 input terminals (i.e., a data line DL, a first scan line GL1, a second scan line GL2, a first control line S1, a second control line S2, a first emission control line EM1, a second emission control line EM2, a first reset control line RST1, a second reset control line RST2, a first reference voltage line REF1, a second reference voltage line REF2, a first reset voltage line INIT1, and a second reset voltage line INIT2), and 2 power terminals (i.e., a first power line VDD and a second power line VSS).

[0100] In some examples, as shown, the working process of the pixel circuit in a frame period can include the following stages. In the present example, the second control line S2 and the second scan line GL2 can be configured to provide the same signal, i.e., the second control signal provided by the second control line S2 can be the same as the second scan signal provided by the second scan line GL2. The gate of the second control transistor T9 can be coupled to the second scan line GL2, and the first electrode of the second control transistor T9 can be coupled to the first power line VDD. Figure 6

[0101] The first stage t11 can also be referred to as a first reset stage. The first reset signal provided by the first reset control line RST1 is at a low level, and the first reset transistor T1 is turned on. The second scan signal provided by the second scan line GL2 is at a high level, and both the compensation transistor T2 and the second control transistor T9 are turned on. The first reset voltage signal provided by the first reset voltage line INIT1 can be provided to the first node N1 through the turned-on first reset transistor T1 and the compensation transistor T2, so that the first node N1 is reset to the first reset voltage Vinit1. The first power signal provided by the first power line VDD can be provided to the second node N2 through the turned-on second control transistor T9, and the voltage of the second node N2 is the first power voltage Vdd. The first control signal provided by the first control line S1 is at a low level, the first control transistor T10 is turned on, the first reference voltage signal provided by the first reference voltage line REF1 is provided to the third node N3, and the voltage of the third node N3 is the first reference voltage Vref1.

[0102] In the first stage t11, the first emission control signal provided by the first emission control line EM1 is at a high level, and the first emission control transistor T5 is turned off. The second emission control signal provided by the second emission control line EM2 is at a high level, and the second emission control transistor T6 is turned off. The second reset control signal provided by the second reset control line RST2 is at a high level, and both the second reset transistor T7 and the third reset transistor T8 are turned off. The first scan signal provided by the first scan line GL1 is at a high level, and the data write transistor T4 is turned off.​

[0103] In the transition stage between the first stage t11 and the second stage t12, the second scan signal provided by the second scan line GL2 jumps to low level, the first reset control signal provided by the first reset control line RST1 jumps to high level, the second reset control signal provided by the second reset control line RST2 jumps to low level, and the rest of the signals remain in the state of the first stage t11.

[0104] The second stage t12 can also be referred to as a second reset stage or a first bias stage. The second reset control signal provided by the second reset control line RST2 is low level, and the second reset transistor T7 and the third reset transistor T8 are both turned on. The second reset voltage signal provided by the second reset voltage line INIT2 is written into the sixth node N6 through the turned-on second reset transistor T7, and the voltage of the sixth node N6 is the second reset voltage Vinit2, so as to reset the first electrode of the light emitting element EL; the second reference voltage signal provided by the second reference voltage line REF2 is written into the fifth node N5 through the turned-on third reset transistor T8, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is low level, and the compensation transistor T2 and the second control transistor T9 are both turned off. The first reset control signal provided by the first reset control line RST1 is high level, and the first reset transistor T1 is turned off. In this stage, the driving transistor T3 is in a bias state.

[0105] In the transition stage between the second stage t12 and the third stage t13, the first emission control signal provided by the first emission control line EM1 jumps to low level, the second scan signal provided by the second scan line GL2 jumps to high level, the second reset control signal provided by the second reset control line RST2 jumps to high level, and the rest of the signals remain in the state of the second stage t12.

[0106] The third stage t13 can also be referred to as a threshold compensation stage. The second scan signal provided by the second scan line GL2 is at a high level, and the compensation transistor T2 and the second control transistor T9 are both turned on. The first node N1 is in communication with the fourth node N4 through the turned-on compensation transistor T2. The first power signal provided by the first power supply line VDD can be provided to the second node N2 through the turned-on second control transistor T9, and the voltage of the second node N2 is the first power voltage Vdd. The first light-emitting control signal provided by the first light-emitting control line EM1 is at a low level, the first light-emitting control transistor T5 is turned on, and the first power signal provided by the first power supply line VDD is provided to the fifth node N5 through the turned-on first light-emitting control transistor T5. In this stage, the driving transistor T3 is turned on, and the threshold voltage Vth of the driving transistor T3 is written to the first node N1 by using the first power signal provided by the first power supply line VDD to compensate the threshold voltage of the driving transistor T3. The voltage of the first node N1 is Vdd+Vth, and Vdd is the first power voltage of the first power signal provided by the first power supply line VDD. The second reset control signal provided by the second reset control line RST2 is at a high level, and the second reset transistor T7 and the third reset transistor T8 are turned off. The remaining transistors remain in the state of the second stage t12.

[0107] The fourth stage t14 can also be referred to as a data writing stage. The first scan signal provided by the first scan line GL1 jumps to a low level, the data writing transistor T4 is turned on, and the data signal provided by the data line DL is written to the third node N3 through the turned-on data writing transistor T4. The first control signal provided by the first control line S1 is at a high level, and the first control transistor T10 is turned off. The remaining transistors remain in the state of the third stage t13.

[0108] In the transition stage between the fourth stage t14 and the fifth stage t15, the first scan signal provided by the first scan line GL1 jumps to a high level, the second scan signal provided by the second scan line GL2 jumps to a low level, the first control signal provided by the first control line S1 jumps to a low level, the first light-emitting control signal provided by the first light-emitting control line EM1 jumps to a high level, and the second reset control signal provided by the second reset control line RST2 jumps to a low level. The remaining signals remain in the state of the fourth stage t14.

[0109] The fifth stage t15 can also be referred to as a second bias stage, the second reset control signal provided by the second reset control line RST2 is at a low level, and the second reset transistor T7 and the third reset transistor T8 are both turned on. The second scan signal provided by the second scan line GL2 is at a low level, and the compensation transistor T2 and the second control transistor T9 are both turned off. The first scan signal provided by the first scan line GL1 is at a high level, and the data write transistor T4 is turned off. The first emission control signal provided by the first emission control line EM1 is at a high level, and the first emission control transistor T5 is turned off. The first control signal provided by the first control line S1 is at a low level, and the first control transistor T10 is turned on. The second reference voltage signal provided by the second reference voltage line REF2 can be provided to the third node N3 through the turned-on first control transistor T10. The second control transistor T9 is turned off, and the second node N2 is floating. The data signal written to the third node N3 in the data write stage can be coupled to the first node N1 through the second capacitor C2 and the first capacitor C1. In this stage, the driving transistor T3 is in a bias state. The second emission control transistor T6 is in a turned-off state, and the first reset transistor T1 is in a turned-off state.

[0110] The sixth stage t16 can also be referred to as an emission stage. The first control signal provided by the first control line S1 is at a low level, and the first control transistor T10 is turned on. The voltage of the third node N3 remains at the first reference voltage Vref1. The first emission control signal provided by the first emission control line EM1 is at a low level, and the first emission control transistor T5 is turned on. The second emission control signal provided by the second emission control line EM2 is at a low level, and the second emission control transistor T6 is turned on. The compensation transistor T2, the second control transistor T9, the data write transistor T4, the first reset transistor T1, the second reset transistor T7, and the third reset transistor T8 are all turned off. In this stage, the driving transistor T3 is turned on. The first node N1 can record the compensation information of the data voltage and the threshold voltage at the same time. The voltage of the first node N1 is Vdd+Vth+Vref1-Vdata, where Vdata is the data voltage. The gate-source voltage difference Vgs of the driving transistor T3 is Vdd+Vth+Vref1-Vdata-Vdd=Vth+Vref1-Vdata. In the driving process of the pixel circuit, the driving current flowing through the driving transistor T3 is determined by the gate-source voltage difference thereof. Therefore, the driving current of the driving transistor T3 is:

[0111] Id=0.5×K×(Vgs-Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 =0.5×K×(Vref1-Vdata) 2 .

[0112] where K is a constant.

[0113] In the example, the driving signal output by the driving transistor T3 is irrelevant to the threshold voltage Vth of the driving transistor T3, and the influence of the threshold voltage of the driving transistor on the driving signal can be eliminated, so that the display brightness is uniform, and the display effect is improved.

[0114] In the working timing of the pixel circuit in the example, the driving transistor T3 can be in a bias state in the first bias stage (i.e., the second stage t12) and the second bias stage (i.e., the fifth stage t15), which can calibrate the voltage and improve the residual image. In other examples, only the first bias stage or the second bias stage can be provided in the working timing of the pixel circuit.

[0115] In the working timing of the pixel circuit in the example, the threshold voltage of the driving transistor T3 and the data signal can be written to the first node N1 and the third node N3, respectively. Through the control of the second control transistor T9 on the second node N2 and the control of the first control transistor T10 on the third node N3, the data signal can be written from the third node N3 to the first node N1, and the writing of the data signal is realized. The charging process of writing the data signal to the first node and the compensation process of the threshold voltage in the example are separated, the duration of threshold compensation can be flexibly controlled, and the threshold voltage compensation effect is improved.

[0116] In some examples, the effective level signal (low level signal in the example) provided by the first scan line GL1 can be configured to control the data writing transistor T4 to write the data signal to the third node N3. The effective level signal (high level signal in the example) provided by the second scan line GL2 can be configured to control the compensation transistor T2 to write the threshold voltage of the driving transistor T3 to the first node N1. The end time of the data writing transistor T4 writing the data signal to the third node N3 is first duration L1 from the start time of the effective level signal provided by the second scan line GL2, and the end time of the data writing transistor T4 writing the data signal to the third node N3 is second duration L2 from the end time of the effective level signal provided by the second scan line GL2. The second duration L2 is less than the first duration L1. For example, the second duration L2 can be 0.

[0117] In some examples, the effective level signal provided by the second scan line GL2 can include the following three equalization stages: the first signal stage X1, the second signal stage X2, and the third signal stage X3, and the start time of the effective level signal provided by the first scan line GL1 is after the first signal stage X1. For example, the start time of the effective level signal provided by the first scan line GL1 can be after the second signal stage X2.

[0118] The data writing process is performed in the second half of the compensation stage of the threshold voltage, the compensation time of the threshold voltage is increased, the threshold voltage compensation time is sufficient, and the threshold voltage compensation effect is improved.

[0119] The first capacitor C1 and the second capacitor C2 are arranged, the written data signal can be effectively maintained, and the data signal writing effect is ensured.

[0120] In the pixel circuit provided by the example, the compensation transistor T2 and the second control transistor T9 are oxide thin film transistors, the leakage of the first node N1 and the second node N2 can be prevented, and the circuit performance is ensured.

[0121] Figure 7 A driving architecture schematic diagram of a pixel circuit of at least one embodiment of the present disclosure is shown. In some examples, as shown in Figure 7 The display substrate can include a plurality of sub-pixels and a plurality of gate driving circuits. The plurality of sub-pixels can be arranged in a first direction X and a second direction Y. The first direction X can intersect the second direction Y, for example, the first direction X can be perpendicular to the second direction Y. The plurality of sub-pixels arranged in the first direction X is a row of sub-pixels, and the plurality of sub-pixels arranged in the second direction Y is a column of sub-pixels. The first direction X can also be referred to as a row direction, and the second direction Y can also be referred to as a column direction. One sub-pixel can include a pixel circuit and a light emitting element electrically connected to the pixel circuit. The pixel circuit can be configured to drive the light emitting element to emit light.

[0122] In some examples, the light emitting element can be any one of a light emitting diode (LED), an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro LED (including: mini-LED or micro-LED), etc. For example, the light emitting element can be an OLED, and the light emitting element can emit red light, green light, blue light, or white light, etc. under the driving of its corresponding pixel circuit. The color of the light emitted by the light emitting element can be determined as needed. In some examples, the light emitting element can include an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting element can be electrically connected to the corresponding pixel circuit. However, the present embodiment is not limited thereto.

[0123] In some examples, the display substrate can include a display area and a frame area located at least one side of the display area. The plurality of sub-pixels can be located in the display area, and the plurality of gate driving circuits can be located in the frame area at two sides of the display area along the first direction X. However, the present embodiment is not limited thereto. In other examples, the plurality of sub-pixels and the plurality of gate driving circuits can be located in the display area to achieve a narrow frame design.

[0124] In some examples, the pixel circuit included in the sub-pixel can be as shown in the example. Figure 5 As shown in the example. Figure 7 As shown in the example, the plurality of gate driving circuits can include: a first scan driving circuit (for example, including first scan driving circuits 31a and 31b), a second scan driving circuit 32, a first light-emitting driving circuit 33, a second light-emitting driving circuit 34, a first reset driving circuit 35, a second reset driving circuit 36, and a first control driving circuit 37.

[0125] In some examples, the first scan driving circuits 31a and 31b can be configured to provide a first scan signal to the pixel circuits of the plurality of sub-pixels through the first scan lines; the second scan driving circuit 32 can be configured to provide a second scan signal to the pixel circuits of the plurality of sub-pixels through the second scan lines; the first light-emitting driving circuit 33 can be configured to provide a first light-emitting control signal to the pixel circuits of the plurality of sub-pixels through the first light-emitting control lines; the second light-emitting driving circuit 34 can be configured to provide a second light-emitting control signal to the pixel circuits of the plurality of sub-pixels through the second light-emitting control lines; the first reset driving circuit 35 can be configured to provide a first reset control signal to the pixel circuits of the plurality of sub-pixels through the first reset control lines; the second reset driving circuit 36 can be configured to provide a second reset control signal to the pixel circuits of the plurality of sub-pixels through the second reset control lines; and the first control driving circuit 37 can be configured to provide a first control signal to the pixel circuits of the plurality of sub-pixels through the first control lines. In the present example, the second control signal can be the same as the second scan signal.

[0126] In some examples, as shown in the example. Figure 7 The first scan driving circuits 31a and 31b can be located at two sides of the plurality of sub-pixels along the first direction X, for example, in the frame areas at two sides of the display area along the first direction X. For example, the first scan driving circuit 31a can be located in the left frame area, and the first scan driving circuit 31b can be located in the right frame area. The first light-emitting driving circuit 33 and the second light-emitting driving circuit 34 can be located at different sides of the plurality of sub-pixels along the first direction X; the first reset driving circuit 35 and the second reset driving circuit 36 can be located at different sides of the plurality of sub-pixels along the first direction X.

[0127] In some examples, the first scan driving circuit 31a, the first light emitting driving circuit 33, the first control driving circuit 37 and the second reset driving circuit 36 can be located on the same side of the plurality of sub-pixels along the first direction X, for example, all located in the left frame area. In the left frame area, the first scan driving circuit 31a, the first light emitting driving circuit 33, the first control driving circuit 37 and the second reset driving circuit 36 can be sequentially arranged along the direction away from the sub-pixel. The first scan driving circuit 31b, the second light emitting driving circuit 34, the first reset driving circuit 35 and the second scan driving circuit 32 can be located on the same side of the plurality of sub-pixels along the first direction X, for example, all located in the right frame area. In the right frame area, the first scan driving circuit 31b, the second light emitting driving circuit 34, the first reset driving circuit 35 and the second scan driving circuit 32 can be sequentially arranged along the direction away from the sub-pixel. The first scan signal of the present example can be double-side driving, and the remaining signals can be single-side driving. In other examples, the first scan signal can be single-side driving. The arrangement of the plurality of gate driving circuits of the present example is conducive to the arrangement of the wires.

[0128] In some examples, the first scan driving circuit 31a and 31b can each include a plurality of first scan driving units. The plurality of first scan driving units can be arranged at intervals along the second direction Y. The nth stage first scan driving unit can be configured to provide the pixel circuit of the nth row of sub-pixels with the first scan signal, and n is an integer greater than 0. Among them, the 2i-1 stage first scan driving unit is cascaded with the 2i+1 stage first scan driving unit, the 2i stage first scan driving unit is cascaded with the 2i+2 stage first scan driving unit, and i is an integer greater than 0. For example, the first scan driving units of the first row, the third row, the fifth row, the seventh row and the like odd rows can be sequentially cascaded; the first scan driving units of the second row, the fourth row, the sixth row, the eighth row and the like even rows can be sequentially cascaded. The first scan area unit of the present example adopts the mode of cascading the odd and even rows separately, which can make the effective level signals output by the adjacent two rows of first scan driving units have overlap, can give sufficient time for the writing of the data signal, and can make the rise time (Tr) / fall time (Tf) of the output signal smaller.

[0129] In some examples, the second scan driving circuit 32 can include a plurality of cascaded second scan driving units. The nth stage second scan driving circuit can be configured to provide the pixel circuit of two rows (such as the 2n-1 row and the 2n row, for example, the nth row and the nth+1 row) of sub-pixels with the second scan signal; the nth+1 stage second scan driving circuit can be configured to provide the pixel circuit of two rows (for example, the nth+2 row and the nth+3 row) of sub-pixels with the second scan signal.

[0130] In some examples, the first light emitting driving circuit 33 can include a plurality of cascaded first light emitting driving units. An nth stage first light emitting driving unit can be configured to provide the first light emitting control signal to the pixel circuits of two rows (such as the 2n-1th row and the 2nth row, for example, the nth row and the nth+1 row) of sub-pixels; an nth+1 stage first light emitting driving unit can be configured to provide the first light emitting control signal to the pixel circuits of two rows (for example, the nth+2 row and the nth+3 row) of sub-pixels.

[0131] In some examples, the second light emitting driving circuit 34 can include a plurality of cascaded second light emitting driving units. An nth stage second light emitting driving unit can be configured to provide the second light emitting control signal to the pixel circuits of two rows (such as the 2n-1th row and the 2nth row, for example, the nth row and the nth+1 row) of sub-pixels; an nth+1 stage second light emitting driving unit can be configured to provide the second light emitting control signal to the pixel circuits of two rows (for example, the nth+2 row and the nth+3 row) of sub-pixels.

[0132] In some examples, the first reset driving circuit 35 can include a plurality of cascaded first reset driving units. An nth stage first reset driving unit can be configured to provide the first reset control signal to the pixel circuits of two rows (such as the 2n-1th row and the 2nth row, for example, the nth row and the nth+1 row) of sub-pixels; an nth+1 stage first reset driving unit can be configured to provide the first reset control signal to the pixel circuits of two rows (for example, the nth+2 row and the nth+3 row) of sub-pixels.

[0133] In some examples, the second reset driving circuit 36 can include a plurality of cascaded second reset driving units. An nth stage second reset driving unit can be configured to provide the second reset control signal to the pixel circuits of two rows (such as the 2n-1th row and the 2nth row, for example, the nth row and the nth+1 row) of sub-pixels; an nth+1 stage second reset driving unit can be configured to provide the second reset control signal to the pixel circuits of two rows (for example, the nth+2 row and the nth+3 row) of sub-pixels.

[0134] In some examples, the first control driving circuit 37 can include a plurality of cascaded first control driving units. An nth stage first control driving unit can be configured to provide the first control signal to the pixel circuits of two rows (such as the 2n-1th row and the 2nth row, for example, the nth row and the nth+1 row) of sub-pixels; an nth+1 stage first control driving unit can be configured to provide the first control signal to the pixel circuits of two rows (for example, the nth+2 row and the nth+3 row) of sub-pixels.

[0135] In this example, the first scan driving circuits 31a and 31b can drive the pixel circuits of odd-numbered and even-numbered rows separately. The second scan driving circuit 32, the first light-emitting driving circuit 33, the second light-emitting driving circuit 34, the first reset driving circuit 35, the second reset driving circuit 36, and the first control driving circuit 37 all use one driving unit to drive the pixel circuits of two rows of sub-pixels. When using one driving unit to drive the pixel circuits of two rows of sub-pixels, the signal generated by the driving unit can be shifted according to 2H, which can achieve a driving cycle of 2H, thus facilitating high-frequency display. In other examples, when using one driving unit to drive the pixel circuits of one row of sub-pixels, the signal generated by the driving unit can be shifted according to 1H.

[0136] Figure 8 This is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, such as Figure 8 As shown, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1, and a second capacitor C2. The gates of the first control transistor T10, the second control transistor T9, and the compensation transistor T2 are all coupled to the second scan line GL2. In this example, the second control line S2, the first control line S1, and the second scan line GL2 can be configured to provide the same signal. In other words, the second scan signal, the first control signal, and the second control signal in this example can be the same. Further description of the pixel circuit of this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0137] Figure 9 for Figure 8 The timing diagram of the pixel circuit shown is as follows. Figure 8 As shown, the pixel circuit in this example may include: 10 transistors (i.e., transistors T1 to T10), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 11 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first light emission control line EM1, second light emission control line EM2, first reset control line RST1, second reset control line RST2, first reference voltage line REF1, second reference voltage line REF2, first reset voltage line INIT1 and second reset voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS). In this example, the compensation transistor T2 and the second control transistor T9 are N-type transistors, and the remaining transistors are P-type transistors.

[0138] In some examples, such asFigure 9 As shown, in a frame period, the working process of the pixel circuit can include the following stages. The present example takes the working process of the pixel circuit of the nth row of sub-pixels as an example for illustration.

[0139] The first stage t21 can also be referred to as a first reset stage. The first reset control signal provided by the first reset control line RST1 is at a low level, and the first reset transistor T1 is turned on. The second scan signal provided by the second scan line GL2 is at a high level, and the compensation transistor T2 and the second control transistor T9 are turned on, and the first control transistor T10 is turned off. The first emission control signal provided by the first emission control line EM1 is at a high level, and the first emission control transistor T5 is turned off. The second emission control signal provided by the second emission control line EM2 is at a high level, and the second emission control transistor T6 is turned off. The second reset control signal provided by the second reset control line RST2 is at a high level, and the second reset transistor T7 and the third reset transistor T8 are both turned off. The first scan signal provided by the first scan line GL1(n) is at a high level, and the data write transistor T4 is turned off. In this stage, the first node N1 is reset to the first reset voltage Vinit1.

[0140] The second stage t22 can also be referred to as a second reset stage or a first bias stage. The second reset control signal provided by the second reset control line RST2 is at a low level, and the second reset transistor T7 and the third reset transistor T8 are both turned on. The sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is at a low level, and the compensation transistor T2 and the second control transistor T9 are turned off, the first control transistor T10 is turned on, and the voltage of the third node N3 is the first reference voltage Vref1. The data write transistor T4, the first reset transistor T1, the first emission control transistor T5, and the second emission control transistor T6 are all turned off. In this stage, the driving transistor T3 is in a bias state.

[0141] The third stage t23 can also be referred to as a threshold compensation stage. The second scan signal provided by the second scan line GL2 is at a high level, and the compensation transistor T2 and the second control transistor T9 are both turned on, and the first control transistor T10 is turned off. The first emission control signal provided by the first emission control line EM1 is at a low level, and the first emission control transistor T5 is turned on, and the first power signal provided by the first power line VDD is written to the fifth node N5. The data write transistor T4, the second emission control transistor T6, the first reset transistor T1, the second reset transistor T7, and the third reset transistor T8 are all turned off. In this stage, the driving transistor T3 is turned on, and the threshold voltage Vth of the driving transistor T3 is written to the first node N1.

[0142] The fourth stage t24 can also be referred to as a data writing stage, the first scan signal provided by the first scan line GL1(n) jumps to a low level, the data writing transistor T4 is turned on, and the data signal provided by the data line DL is written to the third node N3 through the turned-on data writing transistor T4. The remaining transistors remain in the state of the third stage t23.

[0143] The fifth stage t25 can also be referred to as a second biasing stage, the second reset control signal provided by the second reset control line RST2 is at a low level, and the second reset transistor T7 and the third reset transistor T8 are both turned on. The second scan signal provided by the second scan line GL2 is at a low level, the compensation transistor T2 and the second control transistor T9 are both turned off, the first control transistor T10 is turned on, the first reference voltage Vref1 is written to the third node N3, and the data signal is coupled to the first node N1. The first light-emitting control transistor T5, the second light-emitting control transistor T6, the first reset transistor T1, and the data writing transistor T4 are all turned off. In this stage, the driving transistor T3 is in a biasing state.

[0144] The sixth stage t26 can also be referred to as a light-emitting stage, the second scan signal provided by the second scan line GL2 is at a low level, the compensation transistor T2 and the second control transistor T9 are both turned off, the first control transistor T10 is turned on, the voltage of the third node N3 remains the first reference voltage Vref1, and the leakage of the third node N3 is improved. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both turned on; the compensation transistor T2, the second control transistor T9, the data writing transistor T4, the first reset transistor T1, the second reset transistor T7, and the third reset transistor T8 are all turned off. In this stage, the driving transistor T3 is turned on. The gate-source voltage difference Vgs of the driving transistor T3 is Vth+Vref1-Vdata, and the driving current of the driving transistor T3 is:

[0145] Id=0.5×K×(Vgs-Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 =0.5×K×(Vref1-Vdata) 2 .

[0146] Wherein, K is a constant, Vdata is a data voltage, Vref1 is a first reference voltage, and Vth is a threshold voltage.

[0147] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving display effect.

[0148] The example can separate the charging process of the data signal and the threshold voltage compensation process of the first node, flexibly control the threshold compensation duration, and improve the threshold voltage compensation effect. In the pixel circuit of the example, the second scan signal is used to control the compensation transistor, the first control transistor, and the second control transistor at the same time, which is beneficial to save the signal source and the wire, and is beneficial to improve the leakage of the third node N3.

[0149] Figure 10 Another driving architecture schematic diagram of the pixel circuit of at least one embodiment of the present disclosure is shown. In some examples, as shown in Figure 10 , the pixel circuit included in the sub-pixel is taken as an example, and as shown in Figure 8 , the plurality of gate drive circuits of the example can include a first scan drive circuit 31, a second scan drive circuit 32, a first light-emitting drive circuit 33, a second light-emitting drive circuit 34, a first reset drive circuit 35, and a second reset drive circuit 36.

[0150] In some examples, the first scan drive circuit 31 and the second scan drive circuit 32 can be located on different sides of the plurality of sub-pixels along the first direction X, the first light-emitting drive circuit 33 and the second light-emitting drive circuit 34 can be located on different sides of the plurality of sub-pixels along the first direction X, and the first reset drive circuit 35 and the second reset drive circuit 36 can be located on different sides of the plurality of sub-pixels along the first direction X.

[0151] In some examples, the first scan drive circuit 31, the first light-emitting drive circuit 33, and the second reset drive circuit 36 can be located on the same side of the plurality of sub-pixels along the first direction X, for example, all located in the left frame area. In the left frame area, the first scan drive circuit 31, the first light-emitting drive circuit 33, and the second reset drive circuit 36 can be sequentially arranged in a direction away from the sub-pixel. The second scan drive circuit 32, the second light-emitting drive circuit 34, and the first reset drive circuit 35 can be located on the same side of the plurality of sub-pixels along the first direction X, for example, all located in the right frame area. In the right frame area, the second scan drive circuit 32, the second light-emitting drive circuit 34, and the first reset drive circuit 35 can be sequentially arranged in a direction away from the sub-pixel. The plurality of gate drive circuits in the example can all adopt a single-side drive mode.

[0152] In some examples, as shown in Figure 9 and Figure 10As shown, the first scan driving circuit 31 includes multiple first scan driving units. These multiple first scan driving units can be sequentially arranged along the second direction Y. Specifically, the (2i-1)th level first scan driving unit and the (2i+1)th level first scan driving unit can be cascaded, and the (2i)th level first scan driving unit and the (2i+2)th level first scan driving unit can be cascaded, where i is an integer greater than 0. For example, the first scan driving units of odd-numbered rows such as the first row, third row, fifth row, and seventh row can be cascaded sequentially; the first scan driving units of even-numbered rows such as the second row, fourth row, sixth row, and eighth row can be cascaded sequentially. For example, the first scan signals provided by the (n-1)th to (n+2)th level first scan driving units through the first scan lines GL1(n-1) to GL1(n+2) can be as follows... Figure 9 As shown in the example, the first scan area unit in this example uses a cascaded configuration with odd and even rows separated. This allows for an overlap in the effective level signals (low level signals in this example) output by the first scan drive units of adjacent rows, providing sufficient time for data signal writing and resulting in a smaller rise time (Tr) / fall time (Tf) ratio for the output signal. In other examples, the first scan drive units of the first scan drive circuit can use a conventional row-by-row sequential cascading method, achieving the same result. Figure 9 The output waveform is shown. This embodiment is not limited in this respect.

[0153] In some examples, such as Figure 9 As shown, because the effective level signals output by adjacent first scan drive units overlap during certain periods (for example, the overlap period between the output signals of the (n-1)th and nth first scan drive units is the second period ②), when the (n-1)th row pixel circuit receives the data signal transmitted by the data line, the nth row pixel circuit will also receive the same data signal. Therefore, the (n-1)th stage first scan drive unit needs to be turned off before providing the data signal to the nth row pixel circuit. This ensures that the writing of the previous row's data signal is not affected, and that the current row's data signal is completely written. In other words, the data signals transmitted by the data line are respectively... Figure 9 The second time period ②, the third time period ③, the fourth time period ④, and the fifth time period ⑤ shown provide the data signals of rows n-1, n, n+1, and n+2 to the pixel circuits of the corresponding rows. In this way, since a first scan drive unit outputs a 2H pulse signal, sufficient time is allowed for writing the data signal. This does not refer to the actual 2H duration of the data signal writing, but rather to a sufficient pulse width for the data signal to be written.

[0154] The first scan driving circuit in this example can drive the pixel circuits of odd and even rows individually. The second scan driving circuit, the first light-emitting driving circuit, the second light-emitting driving circuit, the first reset driving circuit, and the second reset driving circuit all use a single driving unit to drive the pixel circuits of two rows of sub-pixels, achieving a 2H driving cycle, which is beneficial for supporting high-frequency displays. Furthermore, the arrangement of multiple gate driving circuits in this example facilitates wiring layout. Further explanation of the driving architecture in this example can be found in [reference needed]. Figure 7 The description of the illustrated embodiment is omitted here.

[0155] Figure 11 This is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, such as Figure 11 As shown, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1, and a second capacitor C2. The gate of the first control transistor T10 is coupled to the first light-emitting control line EM1, and the gates of the second control transistor T9 and the compensation transistor T2 are both coupled to the second scan line GL2. In this example, the second control line S2 and the second scan line GL2 can be configured to transmit the same signal; the first control line S1 and the first light-emitting control line EM1 can be configured to transmit the same signal. In other words, in this example, the second control signal and the second scan signal can be the same, and the first control signal and the first light-emitting control signal can be the same. Further descriptions of the pixel circuit of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0156] Figure 12 for Figure 11 The timing diagram of the pixel circuit shown is as follows. Figure 12 As shown, the pixel circuit in this example may include: 10 transistors (i.e., transistors T1 to T10), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 11 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first light emission control line EM1, second light emission control line EM2, first reset control line RST1, second reset control line RST2, first reference voltage line REF1, second reference voltage line REF2, first reset voltage line INIT1 and second reset voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS). In some examples, the compensation transistor T2 and the second control transistor T9 are N-type transistors, and the remaining transistors are P-type transistors.

[0157] In some examples, such asFigure 12 As shown, in a frame period, the working process of the pixel circuit can include the following stages.

[0158] The first stage t31 can also be referred to as a first reset stage or a first bias stage. The second reset control signal provided by the second reset control line RST2 is at a low level, the second reset transistor T7 and the third reset transistor T8 are turned on, the sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is a high level signal, and the compensation transistor T2 and the second control transistor T9 are both turned on. The first emission control signal provided by the first emission control line EM1 is high, and the first emission control transistor T5 and the first control transistor T10 are both turned off. The first reset control signal provided by the first reset control line RST1 is high, and the first reset transistor T1 is turned off. The second emission control signal provided by the second emission control line EM2 is high, and the second emission control transistor T6 is turned off. The first scan signal provided by the first scan line GL1 is high, and the data write transistor T4 is turned off.

[0159] The second stage t32 can also be referred to as a second reset stage. The first reset control signal provided by the first reset control line RST1 is at a low level, and the first reset transistor T1 is turned on. In this stage, the first node N1 is reset to the first reset voltage Vinit1. The second reset control signal provided by the second reset control line RST2 is at a high level, and the second reset transistor T7 and the third reset transistor T8 are both turned off.

[0160] The third stage t33 can also be referred to as a threshold compensation stage. The second scan signal provided by the second scan line GL2 is a high level signal, and the compensation transistor T2 and the second control transistor T9 are both turned on, and the threshold voltage of the drive transistor T3 is written to the first node N1. The first reset control signal provided by the first reset control line RST1 is at a low level, and the first reset transistor T1 is turned off. The first emission control signal provided by the first emission control line EM1 is at a low level, and the first emission control transistor T5 and the first control transistor T10 are both turned on, and the voltage of the third node N3 is the first reference voltage Vref1.

[0161] The fourth stage t34 can also be referred to as a data write stage. The first scan signal provided by the first scan line GL1 jumps to a low level, the data write transistor T4 is turned on, and the data signal provided by the data line DL is written to the third node N3 through the turned-on data write transistor T4. The first emission control signal provided by the first emission control line EM1 is high, and the first emission control transistor T5 and the first control transistor T10 are both turned off.

[0162] In the fifth stage t35, the first scan signal provided by the first scan line GL1 is high, and the data write transistor T4 is closed. The second scan signal provided by the second scan line GL2 is low, and the compensation transistor T2 and the second control transistor T9 are both closed. The first emission control signal provided by the first emission control line EM1 is low, and the first emission control transistor T5 and the first control transistor T10 are both opened. The second control transistor T9 is closed, and the second node N2 is floating. The data signal written in the third node N3 in the data write stage can be coupled to the first node N1 through the second capacitor C2 and the first capacitor C1.

[0163] In the sixth stage t36, also referred to as the second bias stage, the second reset control signal provided by the second reset control line RST2 is low, and the second reset transistor T7 and the third reset transistor T8 are both opened. The sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is low, and the compensation transistor T2 and the second control transistor T9 are both closed. The first scan signal provided by the first scan line GL1 is high, and the data write transistor T4 is closed. The first emission control signal provided by the first emission control line EM1 is high, and the first emission control transistor T5 and the first control transistor T10 are both closed. In this stage, the driving transistor T3 is in a bias state.

[0164] In the seventh stage t37, also referred to as the emission stage, the first emission control signal provided by the first emission control line EM1 is low, and the first emission control transistor T5 and the first control transistor T10 are both opened. The voltage of the third node N3 remains the first reference voltage Vref1, which is conducive to improving the leakage of the third node N3. The second emission control signal provided by the second emission control line EM2 is low, and the second emission control transistor T6 is opened. The compensation transistor T2, the second control transistor T9, the data write transistor T4, the first reset transistor T1, the second reset transistor T7 and the third reset transistor T8 are all closed. In this stage, the driving transistor T3 is opened. The voltage of the first node N1 is Vdd+Vth+Vref1-Vdata, wherein Vdata is the data voltage. The gate-source voltage difference Vgs of the driving transistor T3 is Vdd+Vth+Vref1-Vdata-Vdd=Vth+Vref1-Vdata. The driving current of the driving transistor T3 is:

[0165] Id=0.5×K×(Vgs-Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 =0.5×K×(Vref1-Vdata) 2 .

[0166] wherein K is a constant, Vdata is a data voltage, Vref1 is a first reference voltage, and Vth is a threshold voltage.

[0167] In this example, the driving signal output by the driving transistor T3 is irrelevant to the threshold voltage Vth of the driving transistor T3, and the influence of the threshold voltage of the driving transistor on the driving signal can be eliminated, thereby ensuring uniform display brightness and improving display effect.

[0168] The present example can separate the charging process of writing the data signal into the first node and the compensation process of the threshold voltage, and can flexibly control the threshold compensation duration to improve the threshold voltage compensation effect. In the pixel circuit of the present example, the second scan signal is used to control the compensation transistor and the first control transistor at the same time, and the first light-emitting control signal is used to control the first light-emitting control transistor and the second control transistor at the same time, which is conducive to saving signal sources and wires, and also conducive to improving the leakage of the third node N3.

[0169] Figure 13 Another driving architecture schematic diagram of the pixel circuit of at least one embodiment of the present disclosure is shown. In some examples, as shown in Figure 13 the pixel circuit included in a sub-pixel is taken as an example, as shown in Figure 11 The plurality of gate drive circuits of the present example can include a first scan drive circuit 31, a second scan drive circuit 32, a first light-emitting drive circuit 33, a second light-emitting drive circuit 34, a first reset drive circuit 35, and a second reset drive circuit 36.

[0170] In some examples, the first light-emitting drive circuit 33 can include a plurality of cascaded first light-emitting drive units. The nth first light-emitting drive unit can be configured to provide the first light-emitting control signal to the pixel circuit of the nth row of sub-pixels; the n+1th first light-emitting drive unit can be configured to provide the first light-emitting control signal to the pixel circuit of the n+1th row of sub-pixels, and n is an integer greater than 0.

[0171] The first light-emitting drive circuit of the present example can separately drive the pixel circuit of each row of sub-pixels, the first scan drive circuit can separately drive the pixel circuit of odd and even rows, the second scan drive circuit, the second light-emitting drive circuit, the first reset drive circuit, and the second reset drive circuit all use one drive unit to drive the pixel circuit of two rows of sub-pixels, which can realize a 2H driving period, thereby being conducive to supporting high-frequency display. Moreover, the first light-emitting control signal provided by the first light-emitting drive circuit of the present example simultaneously controls the second control transistor and the first light-emitting control transistor, which can be conducive to improving the leakage of the third node N3. For other descriptions of the driving architecture of the present example, reference can be made to the foregoing Figure 7 and Figure 10The description of the illustrated embodiment is omitted here.

[0172] Figure 14 This is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, such as Figure 14 As shown, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1, and a second capacitor C2. The gate of the first control transistor T10 is coupled to the first light-emitting control line EM1, and the gates of the second control transistor T9 and the compensation transistor T2 are both coupled to the second scan line GL2. In this example, the driving transistor T3, compensation transistor T2, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, first reset transistor T1, second reset transistor T7, third reset transistor T8, second control transistor T9, and first control transistor T10 can all be P-type transistors. Further descriptions of the pixel circuit of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0173] Figure 15 for Figure 14 The timing diagram of the pixel circuit shown is as follows. Figure 14 As shown, the pixel circuit in this example may include: 10 transistors (i.e., transistors T1 to T10), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 11 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first light emission control line EM1, second light emission control line EM2, first reset control line RST1, second reset control line RST2, first reference voltage line REF1, second reference voltage line REF2, first reset voltage line INIT1 and second reset voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS). All 10 transistors in this example are P-type transistors.

[0174] In some examples, such as Figure 15 As shown, the operation of a pixel circuit can include the following stages within a frame time period.

[0175] In the first stage t51, the second reset control signal provided by the second reset control line RST2 is low, the second reset transistor T7 and the third reset transistor T8 are turned on, the sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is a high level signal, and the compensation transistor T2 and the second control transistor T9 are both turned on. The first emission control signal provided by the first emission control line EM1 is high, and the first emission control transistor T5 and the first control transistor T10 are both turned off. The first reset control signal provided by the first reset control line RST1 is high, and the first reset transistor T1 is turned off. The second emission control signal provided by the second emission control line EM2 is high, and the second emission control transistor T6 is turned off. The first scan signal provided by the first scan line GL1 is high, and the data write transistor T4 is turned off.

[0176] In the second stage t52, the first reset control signal provided by the first reset control line RST1 is low, and the first reset transistor T1 is turned on. In this stage, the first node N1 is reset to the first reset voltage Vinit1.

[0177] In the third stage t53, the second reset control signal provided by the second reset control line RST2 is low, the second reset transistor T7 and the third reset transistor T8 are turned on, the sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is a high level signal, and the compensation transistor T2 and the second control transistor T9 are both turned off.

[0178] In the fourth stage t54, the first emission control signal provided by the first emission control line EM1 is low, the first emission control transistor T5 and the first control transistor T10 are both turned on, and the first reference voltage Vref1 is written to the third node N3. The second scan signal provided by the second scan line GL2 is low, the compensation transistor T2 and the second control transistor T9 are both turned on, and the threshold voltage of the driving transistor T3 is written to the first node N1.

[0179] In the fifth stage t55, the first scan signal provided by the first scan line GL1 jumps to low, the data write transistor T4 is turned on, and the data signal provided by the data line DL is written to the third node N3 through the turned-on data write transistor T4. The first emission control signal provided by the first emission control line EM1 is high, and the first emission control transistor T5 and the first control transistor T10 are both turned off.

[0180] In the sixth stage t56, the first emission control signal provided by the first emission control line EM1 is low, the first emission control transistor T5 and the first control transistor T10 are both turned on, and the first reference voltage Vref1 is written to the third node N3. The second scan signal provided by the second scan line GL2 is high, and the compensation transistor T2 and the second control transistor T9 are both turned off. The second control transistor T9 is turned off, the second node N2 is floating, and the data signal written to the third node N3 in the data writing stage can be coupled to the first node N1 through the second capacitor C2 and the first capacitor C1.

[0181] In the seventh stage t57, the second reset control signal provided by the second reset control line RST2 is low, the second reset transistor T7 and the third reset transistor T8 are turned on, the sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. In this stage, the driving transistor T3 is in a bias state.

[0182] In the eighth stage t58, the first emission control signal provided by the first emission control line EM1 is low, the first emission control transistor T5 and the first control transistor T10 are both turned on, and the voltage of the third node N3 remains the first reference voltage Vref1, which is conducive to improving the leakage of the third node N3. The second emission control signal provided by the second emission control line EM2 is low, and the second emission control transistor T6 is turned on. In this stage, the driving transistor T3 is turned on. The voltage of the first node N1 is Vdd+Vth+Vref1-Vdata, where Vdata is the data voltage. The gate-source voltage difference Vgs of the driving transistor T3 is Vdd+Vth+Vref1-Vdata-Vdd=Vth+Vref1-Vdata. The driving current of the driving transistor T3 is:

[0183] Id=0.5×K×(Vgs-Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 =0.5×K×(Vref1-Vdata) 2 .

[0184] where K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0185] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving display effect.

[0186] In some examples, the effective level signal provided by the first scan line GL1 (a low level signal in this example) can be configured to control the data writing transistor T4 to write the data signal to the third node N3. The effective level signal provided by the second scan line GL2 (a low level signal in this example) can be configured to control the compensation transistor T2 to write the threshold voltage of the driving transistor T3 to the first node N1. The time between the end of the data writing transistor T4 writing the data signal to the third node N3 and the start of the effective level signal provided by the second scan line GL2 can be a first duration L1, and the time between the end of the data writing transistor T4 writing the data signal to the third node N3 and the end of the effective level signal provided by the second scan line GL2 can be a second duration L2. The second duration L2 is less than the first duration L1. In this example, the data writing process is performed in the latter half of the threshold voltage compensation stage, which increases the compensation time for the threshold voltage, ensuring sufficient compensation time and improving the compensation effect.

[0187] This example separates the data signal writing process to the first node's charging process from the threshold voltage compensation process, allowing for flexible control of the threshold compensation duration and improving the threshold voltage compensation effect. Furthermore, the pixel circuits in this example use the same type of transistors, which simplifies the process flow and reduces the manufacturing complexity of the display substrate. The driving architecture of the pixel circuit in this example can be referenced... Figure 10 and Figure 13 The description of the illustrated embodiment is omitted here.

[0188] Figure 16 This is another schematic diagram of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, such as... Figure 16 As shown, the pixel circuit of this example may include: a driving sub-circuit 11, a compensation sub-circuit 12, a data writing sub-circuit 13, a first coupling sub-circuit 141, a second coupling sub-circuit 142, a first control sub-circuit 15, a second control sub-circuit 16, a first light emission control sub-circuit 21, a second light emission control sub-circuit 22, a first reset sub-circuit 23, a second reset sub-circuit 24, and a third reset sub-circuit 25. The first reset sub-circuit 23 is coupled to the first reset control line RST1, the first reset voltage line INIT1, and the first node N1, and is configured to write the first reset voltage signal provided by the first reset voltage line INIT1 to the first node N1 under the control of the first reset control line RST1. The remaining structure of the pixel circuit of this example can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0189] Figure 17 This is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, such as Figure 17As shown, the pixel circuit of the present example can include a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1 and a second capacitor C2. The gate of the first reset transistor T1 is coupled with the first reset control line RST1, the first electrode of the first reset transistor T1 is coupled with the first reset voltage line INIT1, and the second electrode of the first reset transistor T1 is coupled with the first node N1. The gate of the second control transistor T9 and the gate of the compensation transistor T2 are both coupled with the second scan line GL2, the first electrode of the second control transistor T9 is coupled with the first power line VDD, and the gate of the first control transistor T10 is coupled with the first light emitting control line EM1. The remaining description of the pixel circuit of the present example can refer to the foregoing description of the embodiments, and thus will not be repeated here.

[0190] Figure 18 As shown, the pixel circuit of the present example can include a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1 and a second capacitor C2. The gate of the first reset transistor T1 is coupled with the first reset control line RST1, the first electrode of the first reset transistor T1 is coupled with the first reset voltage line INIT1, and the second electrode of the first reset transistor T1 is coupled with the first node N1. The gate of the second control transistor T9 and the gate of the compensation transistor T2 are both coupled with the second scan line GL2, the first electrode of the second control transistor T9 is coupled with the first power line VDD, and the gate of the first control transistor T10 is coupled with the first light emitting control line EM1. The remaining description of the pixel circuit of the present example can refer to the foregoing description of the embodiments, and thus will not be repeated here. Figure 17 As shown, the pixel circuit of the present example can include a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1 and a second capacitor C2. The gate of the first reset transistor T1 is coupled with the first reset control line RST1, the first electrode of the first reset transistor T1 is coupled with the first reset voltage line INIT1, and the second electrode of the first reset transistor T1 is coupled with the first node N1. The gate of the second control transistor T9 and the gate of the compensation transistor T2 are both coupled with the second scan line GL2, the first electrode of the second control transistor T9 is coupled with the first power line VDD, and the gate of the first control transistor T10 is coupled with the first light emitting control line EM1. The remaining description of the pixel circuit of the present example can refer to the foregoing description of the embodiments, and thus will not be repeated here. Figure 17 As shown, the pixel circuit of the present example can include a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1 and a second capacitor C2. The gate of the first reset transistor T1 is coupled with the first reset control line RST1, the first electrode of the first reset transistor T1 is coupled with the first reset voltage line INIT1, and the second electrode of the first reset transistor T1 is coupled with the first node N1. The gate of the second control transistor T9 and the gate of the compensation transistor T2 are both coupled with the second scan line GL2, the first electrode of the second control transistor T9 is coupled with the first power line VDD, and the gate of the first control transistor T10 is coupled with the first light emitting control line EM1. The remaining description of the pixel circuit of the present example can refer to the foregoing description of the embodiments, and thus will not be repeated here.

[0191] As shown, the pixel circuit of the present example can include a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1 and a second capacitor C2. The gate of the first reset transistor T1 is coupled with the first reset control line RST1, the first electrode of the first reset transistor T1 is coupled with the first reset voltage line INIT1, and the second electrode of the first reset transistor T1 is coupled with the first node N1. The gate of the second control transistor T9 and the gate of the compensation transistor T2 are both coupled with the second scan line GL2, the first electrode of the second control transistor T9 is coupled with the first power line VDD, and the gate of the first control transistor T10 is coupled with the first light emitting control line EM1. The remaining description of the pixel circuit of the present example can refer to the foregoing description of the embodiments, and thus will not be repeated here. Figure 18 As shown, the pixel circuit of the present example can include a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1 and a second capacitor C2. The gate of the first reset transistor T1 is coupled with the first reset control line RST1, the first electrode of the first reset transistor T1 is coupled with the first reset voltage line INIT1, and the second electrode of the first reset transistor T1 is coupled with the first node N1. The gate of the second control transistor T9 and the gate of the compensation transistor T2 are both coupled with the second scan line GL2, the first electrode of the second control transistor T9 is coupled with the first power line VDD, and the gate of the first control transistor T10 is coupled with the first light emitting control line EM1. The remaining description of the pixel circuit of the present example can refer to the foregoing description of the embodiments, and thus will not be repeated here.

[0192] As shown, the pixel circuit of the present example can include a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1 and a second capacitor C2. The gate of the first reset transistor T1 is coupled with the first reset control line RST1, the first electrode of the first reset transistor T1 is coupled with the first reset voltage line INIT1, and the second electrode of the first reset transistor T1 is coupled with the first node N1. The gate of the second control transistor T9 and the gate of the compensation transistor T2 are both coupled with the second scan line GL2, the first electrode of the second control transistor T9 is coupled with the first power line VDD, and the gate of the first control transistor T10 is coupled with the first light emitting control line EM1. The remaining description of the pixel circuit of the present example can refer to the foregoing description of the embodiments, and thus will not be repeated here.

[0193] In the second stage t42, the first reset control line RST1 provides the first reset control signal with low level, and the first reset transistor T1 is turned on. The second scan line GL2 provides the second scan signal with low level, and the compensation transistor T2 and the second control transistor T9 are both turned on. In this stage, the first node N1 is reset to the first reset voltage Vinit1.

[0194] In the third stage t43, the compensation transistor T2 and the second control transistor T9 are both turned on; the first emission control line EM1(n-1) provides the low level signal, and the first emission control transistor T5 and the first control transistor T10 are both turned on. The voltage of the third node N3 is the first reference voltage Vref1. In this stage, the driving transistor T3 is turned on, and the threshold voltage Vth of the driving transistor T3 is written into the first node N1.

[0195] In the fourth stage t44, the first scan line GL1(n-1) provides the first scan signal with low level, and the data write transistor T4 is turned on. The data signal provided by the data line DL is written into the third node N3 through the turned-on data write transistor T4. The first emission control signal provided by the first emission control line EM1 is high level, and the first emission control transistor T5 and the first control transistor T10 are both turned off.

[0196] In the fifth stage t45, the first emission control line EM1(n-1) provides the first emission control signal with low level, and the first emission control transistor T5 and the first control transistor T10 are both turned on, so as to write the first reference voltage Vref1 into the third node N3.

[0197] In the sixth stage t46, the second reset control line RST2 provides the second reset control signal with low level, and the second reset transistor T7 and the eighth reset transistor T8 are both turned on. The sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2.

[0198] In the seventh stage t47, the first emission control line EM1(n-1) provides the low level signal, and the first emission control transistor T5 and the first control transistor T10 are both turned on. The voltage of the third node N3 remains the first reference voltage Vref1, which is conducive to improving the leakage of the third node N3. The second emission control transistor T6 is turned on. In this stage, the driving transistor T3 is turned on. The gate-source voltage difference Vgs of the driving transistor T3 is Vth+Vref1-Vdata, and the driving current of the driving transistor T3 is:

[0199] Id=0.5×K×(Vgs-Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth)2 = 0.5 x K x (Vref1 - Vdata) 2 .

[0200] wherein K is a constant, Vdata is a data voltage, Vref1 is a first reference voltage, and Vth is a threshold voltage.

[0201] In this example, the driving signal output by the driving transistor T3 is irrelevant to the threshold voltage Vth of the driving transistor T3, and the influence of the threshold voltage of the driving transistor on the driving signal can be eliminated, so that the display brightness is uniform and the display effect is improved.

[0202] The charging process of writing the data signal to the first node and the compensation process of the threshold voltage are separated in this example, the threshold compensation duration can be flexibly controlled, and the threshold voltage compensation effect is improved. Moreover, the types of the transistors of the pixel circuit in this example are the same, which is beneficial to simplify the process flow and reduce the process difficulty of the display substrate. The driving architecture of the pixel circuit in this example can be described with reference to the description of the embodiments shown in Figure 10 and Figure 13 , and thus will not be described here.

[0203] Figure 19 is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure. In some examples, as shown in Figure 19 , the pixel circuit in this example can include a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1, and a second capacitor C2. The gate of the first control transistor T10 and the gate of the data writing transistor T4 are both coupled with a first scan line GL1. The gate of the second control transistor T9 and the gate of the compensation transistor T2 are both coupled with a second scan line GL2. In this example, the first control line S1 and the first scan line GL1 can be configured to provide the same signal, and the second control line S2 and the second scan line GL2 can be configured to provide the same signal. In other words, the second scan signal and the second control signal in this example can be the same, and the first scan signal and the first control signal can be the same. In this example, the data writing transistor T4, the compensation transistor T2, and the second control transistor T9 are N-type transistors, and the remaining transistors are P-type transistors. The remaining description of the pixel circuit in this example can be described with reference to the foregoing embodiments, and thus will not be described here.

[0204] Figure 20 is a timing diagram of the pixel circuit shown in Figure 19 . As shown in Figure 19As shown, the pixel circuit of the present example can include 10 transistors (i.e., transistors T1-T10), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 11 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first emission control line EM1, second emission control line EM2, first reset control line RST1, second reset control line RST2, first reference voltage line REF1, second reference voltage line REF2, first reset voltage line INIT1, and second reset voltage line INIT2), and 2 power terminals (i.e., first power line VDD and second power line VSS).

[0205] In some examples, as Figure 20 As shown, the working process of the pixel circuit in a frame period can include the following stages.

[0206] The first stage t61 can also be referred to as a first reset stage. The first reset control signal provided by the first reset control line RST1 is at a low level, and the first reset transistor T1 is turned on. The second scan signal provided by the second scan line GL2 is at a high level, and both the compensation transistor T2 and the second control transistor T9 are turned on. The first node N1 is reset to the first reset voltage Vinit1. The first scan signal provided by the first scan line GL1 is at a low level, and the data write transistor T4 is turned off, and the first control transistor T10 is turned on.

[0207] The second stage t62 can also be referred to as a first bias stage or a second reset stage. The second reset control signal provided by the second reset control line RST2 is at a low level, and both the second reset transistor T7 and the third reset transistor T8 are turned on. The sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. In this stage, the driving transistor T3 is in a bias state.

[0208] The third stage t63 can also be referred to as a threshold compensation stage. The second scan signal provided by the second scan line GL2 is at a high level, and both the compensation transistor T2 and the second control transistor T9 are turned on. The first scan signal provided by the first scan line GL1 is at a low level, and the first control transistor T10 is turned on, and the data write transistor T4 is turned off. The first emission control signal provided by the first emission control line EM1 is at a low level, and the first emission control transistor T5 is turned on. In this stage, the driving transistor T3 is turned on, and the threshold voltage Vth of the driving transistor T3 is written to the first node N1. The voltage of the second node N2 is the first power voltage Vdd, and the voltage of the third node N3 is the first reference voltage Vref1.

[0209] The fourth stage t64 can also be referred to as a data writing stage, the first scan signal provided by the first scan line GL1 jumps to a high level, the first control transistor T10 is turned off, and the data writing transistor T4 is turned on, so that the data signal provided by the data line DL is written to the third node N3 through the turned-on data writing transistor T4.

[0210] The fifth stage t65 can also be referred to as a second biasing stage, the second reset control signal provided by the second reset control line RST2 is at a low level, and the second reset transistor T7 and the third reset transistor T8 are both turned on. In this stage, the driving transistor T3 is in a biasing state.

[0211] The sixth stage t66 can also be referred to as a light emitting stage, the first scan signal provided by the first scan line GL1 is at a low level, the data writing transistor T4 is turned off, the first control transistor T10 is turned on, and the voltage of the third node N3 is kept at the first reference voltage Vref1, which is conducive to improving the leakage of the third node N3. The first light emitting control transistor T5, the second light emitting control transistor T6 and the driving transistor T3 are all turned on. The gate-source voltage difference Vgs of the driving transistor T3 is Vth+Vref1-Vdata, and the driving current of the driving transistor T3 is:

[0212] Id=0.5×K×(Vgs-Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 =0.5×K×(Vref1-Vdata) 2 .

[0213] Wherein, K is a constant, Vdata is a data voltage, Vref1 is a first reference voltage, and Vth is a threshold voltage.

[0214] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving display effect.

[0215] The charging process of the data signal to the first node and the threshold voltage compensation process can be separated in this example, the threshold compensation time can be flexibly controlled, and the threshold voltage compensation effect is improved. In the pixel circuit of this example, the first scan signal is used to control the data writing transistor and the second control transistor at the same time, which is conducive to saving signal sources and lines, and is conducive to improving the leakage of the third node N3. The driving architecture of the pixel circuit of this example can be described with reference to the embodiments shown in Figure 10 or Figure 13 The description of the driving architecture of the pixel circuit of this example can be described with reference to the embodiments shown in

[0216] Figure 21 Another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure is shown. In some examples, as shown in Figure 21 the pixel circuit of the present example can include a driving sub-circuit 11, a compensation sub-circuit 12, a data writing sub-circuit 13, a first coupling sub-circuit 141, a second coupling sub-circuit 142, a first control sub-circuit 15, a second control sub-circuit 16, a first light emitting control sub-circuit 21, a second light emitting control sub-circuit 22, a first reset sub-circuit 23, a second reset sub-circuit 24, a third reset sub-circuit 25, and a fourth reset sub-circuit 26. The fourth reset sub-circuit 26 is coupled to the third reset control line RST3, the first reference voltage line REF1, and the third node N3, and is configured to write the first reference voltage signal provided by the first reference voltage line REF1 to the third node N3 under the control of the third reset control line RST3. The remaining structures of the pixel circuit of the present example can be referred to the description of the foregoing embodiments, and thus will not be described here.

[0217] Figure 22 Another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure is shown. In some examples, as shown in Figure 22 the fourth reset sub-circuit can include a fourth reset transistor T11, the gate of the fourth reset transistor T11 is coupled to the second reset control line RST2, the first pole is coupled to the first reference voltage line REF1, and the second pole is coupled to the third node N3. The second reset control line RST2 of the present example and the third reset control line can be configured to provide the same signal, in other words, the second reset control signal and the third reset control signal can be the same. The gate of the first control transistor T10 is coupled to the second light emitting control line EM2. In other words, the second light emitting control line EM2 and the first control line can be configured to provide the same signal, that is, the second light emitting control signal and the first control signal can be the same. The data writing transistor T4, the compensation transistor T2, and the second control transistor T9 in the present example can all be N-type transistors, and the remaining transistors can all be P-type transistors. The remaining descriptions of the pixel circuit of the present example can be referred to the description of the foregoing embodiments, and thus will not be described here.

[0218] The working timing of the pixel circuit of the present example can be referred to the working timing diagram shown in Figure 20 . In the sixth stage t66 (i.e., the light emitting stage), the first control transistor T10 is turned on, which not only can couple the data signal to the first node N1, but also can improve the leakage of the third node N3. The remaining working timing of the pixel circuit can be referred to the description of the foregoing embodiments, and thus will not be described here.

[0219] The example can separate the charging process and the threshold voltage compensation process of the data signal written to the first node, flexibly control the threshold compensation time length, and improve the threshold voltage compensation effect. Moreover, the second light-emitting control signal is used to simultaneously control the second control transistor and the second light-emitting control transistor, which can be beneficial to saving signal sources and wirings and can also improve the leakage of the third node N3. The driving architecture of the pixel circuit of the example can refer to the description of the embodiments shown in Figure 10 or Figure 13 The pixel circuit of the example can refer to the description of the embodiments shown in

[0220] Figure 23 Another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure is shown. In some examples, as shown in Figure 23 the pixel circuit of the example can include a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a second control transistor T9, a first control transistor T10, a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first electrode of the driving transistor T3 is coupled with a first power supply line VDD. The fifth node of the example is directly coupled with the first power supply line VDD. The first electrode of the third capacitor C3 is coupled with a first bias signal line V1, and the second electrode is coupled with the first node N1. The gate of the compensation transistor T2, the gate of the second control transistor T9, and the gate of the first control transistor T10 are all coupled with a second scan line GL2. In the example, the second scan line GL2, the first control line, and the second control line can be configured to provide the same signal; in other words, the second scan signal, the first control signal, and the second control signal of the example can be the same. In the example, the compensation transistor T2 and the second control transistor T9 can both be N-type transistors, and the remaining transistors can all be P-type transistors. The remaining description of the pixel circuit of the example can refer to the description of the foregoing embodiments, and thus will not be repeated here.

[0221] Figure 24 The working timing diagram of the pixel circuit shown in Figure 23 As shown in Figure 23 the pixel circuit of the example can include 8 transistors (i.e., transistors T1, T2, T3, T4, T6, T7, T9, and T10), 3 capacitor units (i.e., a first capacitor C1, a second capacitor C2, and a third capacitor C3), 10 input terminals (i.e., a data line DL, a first scan line GL1, a second scan line GL2, a second light-emitting control line EM2, a first reset control line RST1, a second reset control line RST2, a first reference voltage line REF1, a first coupling signal line V1, a first reset voltage line INIT1, and a second reset voltage line INIT2), and 2 power supply terminals (i.e., a first power supply line VDD and a second power supply line VSS).

[0222] In some examples, as shown, the working process of the pixel circuit in a frame period can include the following stages. In this example, the same signal is provided to the first coupling signal line V1 and the second reset control line RST2. In other words, the first electrode of the third capacitor C3 can be coupled to the second reset control line RST2. Figure 24 The first stage t71 can also be referred to as a first reset stage. The first reset control signal provided by the first reset control line RST1 is at a low level, and the first reset transistor T1 is turned on. The second scan signal provided by the second scan line GL2 is at a high level, and the compensation transistor T2 and the second control transistor T9 are both turned on, and the first control transistor T10 is turned off. The first node N1 is reset to the first reset voltage Vinit1.

[0223] The second stage t72 can also be referred to as a first bias stage or a second reset stage. The second reset control signal provided by the second reset control line RST2 is at a low level, and the second reset transistor T7 is turned on, and the sixth node N6 is reset to the second reset voltage Vinit2. The voltage of the first node N1 is pulled down by the second reset control signal, and the driving transistor T3 is in a bias state. The second scan signal provided by the second scan line GL2 is at a low level, and the compensation transistor T2 and the second control transistor T9 are both turned off, and the first control transistor T10 is turned on, and the voltage of the third node N3 is the first reference voltage Vref1.

[0224] The third stage t73 can also be referred to as a threshold compensation stage. The second scan signal provided by the second scan line GL2 is at a high level, and the compensation transistor T2 and the second control transistor T9 are both turned on, and the first control transistor T10 is turned off. In this stage, the driving transistor T3 is turned on, and the threshold voltage Vth of the driving transistor T3 is written to the first node N1, and the voltage of the first node N1 is Vdd+Vth, and Vdd is the first power voltage provided by the first power line VDD. The voltage of the second node N2 is the first power voltage Vdd.

[0225] The fourth stage t74 can also be referred to as a data write stage. The first scan signal provided by the first scan line GL1 jumps to a low level, and the data write transistor T4 is turned on, and the data signal provided by the data line DL is written to the third node N3 through the turned-on data write transistor T4.

[0226] The fifth stage t75 can also be referred to as a second bias stage. The second reset control signal provided by the second reset control line RST2 is at a low level, and the second reset transistor T7 is turned on, and the potential of the first node N1 is pulled down by the second reset control signal, and the driving transistor T3 is in a bias state.

[0227]

[0228] ​The sixth stage, t76, can also be called the light-emitting stage. The first control transistor T10 is turned on, and the voltage at the third node N3 is the first reference voltage Vref1. The second light-emitting control transistor T6 and the driving transistor T3 are also turned on. The voltage at the first node N1 is Vdd + Vth + Vref1 - Vdata. The gate-source voltage difference of the driving transistor T3, Vgs = Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. The driving current of the driving transistor T3 is:

[0229] Id = 0.5 × K × (Vgs - Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 =0.5×K×(Vref1-Vdata) 2 .

[0230] Where K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0231] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0232] This example separates the data signal writing process of the first node during charging from the threshold voltage compensation process, allowing for flexible control of the threshold compensation duration and improving the threshold voltage compensation effect. Furthermore, the third capacitor C3 and the first bias signal line can be used to control the bias of the driving transistor at the first node N1.

[0233] Figure 25 This is a schematic diagram of another driving architecture for a pixel circuit according to at least one embodiment of the present disclosure. In some examples, such as Figure 25 As shown, the pixel circuits included in the sub-pixels are as follows: Figure 23 As shown in the example, the multiple gate driving circuits in this example may include: a first scan driving circuit (e.g., including first scan driving circuits 31a and 31b), a second scan driving circuit 32, a second light-emitting driving circuit 34, a first reset driving circuit 35, and a second reset driving circuit 36.

[0234] In some examples, the first scan driving circuits 31a and 31b can be located on both sides of the plurality of sub-pixels along the first direction X. The first reset driving circuit 35 and the second reset driving circuit 36 ​​can be located on both sides of the plurality of sub-pixels along the first direction X. The second scan driving circuit 32 and the second light-emitting driving circuit 34 can be located on both sides of the plurality of sub-pixels along the first direction X.

[0235] In some examples, the first scan driving circuit 31a, the second light-emitting driving circuit 34, and the second reset driving circuit 36 ​​can be located on the same side of multiple sub-pixels along the first direction X, for example, all located in the left border region. Within the left border region, the first scan driving circuit 31a, the second light-emitting driving circuit 34, and the second reset driving circuit 36 ​​can be sequentially arranged along a direction away from the sub-pixels. The first scan driving circuit 31b, the second scan driving circuit 32, and the first reset driving circuit 35 can be located on the same side of multiple sub-pixels along the first direction X, for example, all located in the right border region. Within the right border region, the first scan driving circuit 31b, the second scan driving circuit 32, and the first reset driving circuit 35 can be sequentially arranged along a direction away from the sub-pixels. In this example, the first scan signal can be driven from both sides, and the remaining signals can be driven from one side. In other examples, the first scan signal can be driven from one side. The arrangement of the multiple gate driving circuits in this example facilitates wiring layout.

[0236] Further descriptions of the driving architecture of the pixel circuit in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0237] Figure 26 This is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, such as Figure 26 As shown, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a second control transistor T9, a first control transistor T10, a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first electrode of the driving transistor T3 is coupled to the first power supply line VDD. The fifth node in this example is directly coupled to the first power supply line VDD. The first electrode of the third capacitor C3 is coupled to the first bias signal line V1, and the second electrode is coupled to the second node N2. The gates of the compensation transistor T2, the second control transistor T9, and the first control transistor T10 are all coupled to the second scan line GL2. In this example, the compensation transistor T2 and the second control transistor T9 can both be N-type transistors, and the remaining transistors are P-type transistors. Further descriptions of the pixel circuit of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0238] The timing sequence of the pixel circuit in this example can be referenced. Figure 24 The timing diagram shown is illustrated. In this example, the third capacitor and the first bias signal line can be used to control the second node N2 to bias the driving transistor T3, which helps to improve the effect of image retention. The timing description of the pixel circuit and the driving architecture of this example can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0239] Figure 27 Another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure is shown. In some examples, as shown in Figure 27 the pixel circuit of the present example can include a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a second control transistor T9, a first control transistor T10, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4. The first electrode of the fourth capacitor C4 is coupled with the second bias signal line V2, and the second electrode is coupled with the fifth node N5. The gate of the compensation transistor T2, the gate of the second control transistor T9, and the gate of the first control transistor T10 are all coupled with the second scan line GL2. In the present example, the second reset transistor T7, the compensation transistor T2, and the second control transistor T9 can all be N-type transistors, and the remaining transistors can all be P-type transistors. The remaining description of the pixel circuit of the present example can refer to the foregoing description of the embodiments, and thus will not be described again here.

[0240] Figure 28 a timing diagram of the pixel circuit shown. As shown in Figure 27 the pixel circuit of the present example can include 10 transistors (i.e., transistors T1 to T10), 3 capacitor units (i.e., a first capacitor C1, a second capacitor C2, and a fourth capacitor C4), 11 input terminals (i.e., a data line DL, a first scan line GL1, a second scan line GL2, a first light emitting control line EM1, a second light emitting control line EM2, a first reset control line RST1, a second reset control line RST2, a first reference voltage line REF1, a second coupling signal line V2, a first reset voltage line INIT1, and a second reset voltage line INIT2), and 2 power terminals (i.e., a first power line VDD and a second power line VSS). Figure 27 In some examples, as shown in

[0241] the working process of the pixel circuit in a frame period can include the following stages. In the present example, the second coupling signal line V2 and the second reset control line RST2 are taken as an example to provide the same signal. In other words, the first electrode of the fourth capacitor C4 can be coupled with the second reset control line RST2. Figure 28 The first stage t81 can also be referred to as a first reset stage. The first reset control signal provided by the first reset control line RST1 is at a low level, and the first reset transistor T1 is turned on. The second scan signal provided by the second scan line GL2 is at a high level, and the compensation transistor T2 and the second control transistor T9 are both turned on, and the first control transistor T10 is turned off. The first node N1 is reset to the first reset voltage Vinit1.

[0242]

[0243] ​The second stage t82 can also be referred to as a first bias stage or a second reset stage. The second reset control signal provided by the second reset control line RST2 is high, the second reset transistor T7 is turned on, and the sixth node N6 is reset to the second reset voltage Vinit2. The potential of the fifth node N5 is pulled high by the second reset control signal, and the driving transistor T3 is in a bias state. The second scan signal provided by the second scan line GL2 is low, the compensation transistor T2 and the second control transistor T9 are both turned off, and the first control transistor T10 is turned on. The voltage of the third node N3 is the first reference voltage Vref1.

[0244] The third stage t83 can also be referred to as a threshold compensation stage. The second scan signal provided by the second scan line GL2 is high, the compensation transistor T2 and the second control transistor T9 are both turned on, and the first control transistor T10 is turned off. In this stage, the driving transistor T3 is turned on, the threshold voltage Vth of the driving transistor T3 is written to the first node N1, and the voltage of the first node N1 is Vdd+Vth, where Vdd is the first power voltage provided by the first power line VDD. The voltage of the second node N2 is the first power voltage Vdd.

[0245] The fourth stage t84 can also be referred to as a data write stage. The first scan signal provided by the first scan line GL1 jumps to low, the data write transistor T4 is turned on, and the data signal provided by the data line DL is written to the third node N3 through the turned-on data write transistor T4.

[0246] The fifth stage t85 can also be referred to as a second bias stage. The second reset control signal provided by the second reset control line RST2 is high, the second reset transistor T7 is turned on, and the potential of the fifth node N5 is pulled high by the second reset control signal. The driving transistor T3 is in a bias state.

[0247] The sixth stage t86 can also be referred to as a light emitting stage. The first control transistor T10 is turned on, and the voltage of the third node N3 is the first reference voltage Vref1. The first light emitting control transistor T5, the second light emitting control transistor T6, and the driving transistor T3 are turned on. The voltage of the first node N1 is Vdd+Vth+Vref1-Vdata. The gate-source voltage difference Vgs of the driving transistor T3 is Vdd+Vth+Vref1-Vdata-Vdd=Vth+Vref1-Vdata. The driving current of the driving transistor T3 is:

[0248] Id=0.5×K×(Vgs-Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 =0.5×K×(Vref1-Vdata) 2 .

[0249] wherein K is a constant, Vdata is a data voltage, Vref1 is a first reference voltage, and Vth is a threshold voltage.

[0250] In this example, the driving signal output by the driving transistor T3 is irrelevant to the threshold voltage Vth of the driving transistor T3, and the influence of the threshold voltage of the driving transistor on the driving signal can be eliminated, thereby ensuring uniform display brightness and improving display effect.

[0251] This example can separate the charging process of writing the data signal to the first node and the threshold voltage compensation process, flexibly control the threshold compensation duration, and improve the threshold voltage compensation effect. Moreover, the fourth capacitor and the second bias signal line can be used to control the fifth node N5 to bias the driving transistor T3, which is conducive to improving the influence of residual image. The driving architecture of the pixel circuit of this example can be described with reference to the embodiments shown in Figure 10 or Figure 13 The description of the embodiments shown in

[0252] Figure 29 Another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure. In some examples, as shown in Figure 29 the pixel circuit of this example can include a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a second control transistor T9, a first control transistor T10, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4. The first electrode of the fourth capacitor C4 is coupled with the second bias signal line V2, and the second electrode is coupled with the fourth node N4. The gate of the compensation transistor T2, the gate of the second control transistor T9, and the gate of the first control transistor T10 are all coupled with the second scan line GL2. In this example, the second reset transistor T7, the compensation transistor T2, and the second control transistor T9 can all be N-type transistors, and the remaining transistors can all be P-type transistors. The remaining description of the pixel circuit of this example can be described with reference to the foregoing embodiments, and thus will not be repeated here.

[0253] The working timing of the pixel circuit of this example can be described with reference to the working timing diagram shown in Figure 28 This example can use the fourth capacitor and the second bias signal line to control the fourth node N4 to bias the driving transistor T3. The working timing description and the driving architecture of the pixel circuit of this example can be described with reference to the foregoing embodiments, and thus will not be repeated here.

[0254] Figure 30 Flowchart of the driving method of the pixel circuit of at least one embodiment of the present disclosure. In some examples, as shown in Figure 30As shown, the driving method of the pixel circuit of the present example can include the following steps:

[0255] Step 701, under the control of the second scan line, the compensation sub-circuit turns on the first node and the fourth node, so that the threshold voltage of the driving sub-circuit is written to the first node;

[0256] Step 702, under the control of the first scan line, the data writing sub-circuit writes the data signal provided by the data line to the third node;

[0257] Step 703, under the control of the first control line, the first control sub-circuit writes the first reference voltage signal provided by the first reference voltage line to the third node, so that the data signal is coupled to the first node through the coupling sub-circuit;

[0258] Step 704, under the control of the first node, the driving sub-circuit provides a driving signal to the fourth node.

[0259] In some examples, the data writing sub-circuit writes the data signal to the third node for a time period less than that of the compensation sub-circuit writing the threshold voltage of the driving sub-circuit to the first node. The data writing sub-circuit writes the data signal to the third node at a time later than that of the compensation sub-circuit writing the threshold voltage of the driving sub-circuit to the first node. The present example can be beneficial to improve the compensation effect of the threshold voltage, thereby being beneficial to improve the picture display uniformity; moreover, the writing time of the data signal is later than that of the threshold voltage, which can be beneficial to ensure the effectiveness of the data signal.

[0260] In some examples, the pixel circuit further includes: a second reset sub-circuit and a third reset sub-circuit; the second reset sub-circuit is coupled with a second reset control line, a second reset voltage line and a sixth node, the sixth node is coupled with the first electrode of the light emitting element; the third reset sub-circuit is coupled with the second reset control line, a second reference voltage line and a fifth node. The driving method of the present example further includes at least one of the following: before the compensation sub-circuit writes the threshold voltage of the driving sub-circuit to the first node, the second reset sub-circuit writes, under the control of the second reset control line, a second reset voltage signal provided by the second reset voltage line to the sixth node, and the third reset sub-circuit writes, under the control of the second reset control line, a second reference voltage signal provided by the second reference voltage line to the fifth node; after the data writing sub-circuit writes the data signal provided by the data line to the third node, the second reset sub-circuit writes, under the control of the second reset control line, a second reset voltage signal provided by the second reset voltage line to the sixth node, and the third reset sub-circuit writes, under the control of the second reset control line, a second reference voltage signal provided by the second reference voltage line to the fifth node. The present example sets the driving transistor to a bias state before the compensation sub-circuit writes the threshold voltage of the driving sub-circuit to the first node, or after the data writing sub-circuit writes the data signal provided by the data line to the third node, which can calibrate the voltage and improve the residual image.

[0261] In some examples, during the process in which the driving sub-circuit provides the driving signal to the fourth node under the control of the first node, the first control line continuously provides the effective level signal. In the light emitting stage, the first control sub-circuit continuously writes the first reference voltage to the third node under the control of the first control line, which can be beneficial to improve the leakage of the third node.

[0262] The driving method of the pixel circuit of the present embodiment can refer to the description of the foregoing embodiments, and will not be described here again.

[0263] The present embodiment further provides a display substrate, including: a plurality of sub-pixels and at least one first scan driving circuit, at least one sub-pixel in the plurality of sub-pixels includes a light emitting element and a pixel circuit for driving the light emitting element to emit light; the pixel circuit is the pixel circuit as described in the foregoing embodiments. The first scan driving circuit includes: a plurality of first scan driving units. The nth level first scan driving unit is configured to provide a first scan signal to the pixel circuit of the nth row of sub-pixels; n is an integer greater than 0. Among them, the 2i-1 level first scan driving unit is cascaded with the 2i+1 level first scan driving unit, the 2i level first scan driving unit is cascaded with the 2i+2 level first scan driving unit, and i is an integer greater than 0.

[0264] The first scan driving circuit of the display substrate of the embodiment has a plurality of first scan driving units in a mode of cascading odd rows and even rows separately, so that the effective level signals output by two adjacent rows of first scan driving units have an overlap, sufficient time is left for writing of data signals, and the Tr / Tf of the output signals is small.

[0265] In some example embodiments, the display substrate can further include a first light emitting driving circuit including a plurality of cascaded first light emitting driving units; an nth stage of the first light emitting driving units is configured to provide a first light emitting control signal to pixel circuits of an nth row of sub-pixels; or, is configured to provide a first light emitting control signal to pixel circuits of a 2nth-1 row and a 2nth row of sub-pixels.

[0266] In some example embodiments, the display substrate can further include a second scan driving circuit, a second light emitting driving circuit; the second scan driving circuit includes a plurality of cascaded second scan driving units; the second light emitting driving circuit includes a plurality of cascaded second light emitting driving units. An nth stage of the second scan driving units is configured to provide a second scan signal to pixel circuits of a 2nth-1 row and a 2nth row of sub-pixels; an nth stage of the second light emitting driving units is configured to provide a second light emitting control signal to pixel circuits of a 2nth-1 row and a 2nth row of sub-pixels. Wherein, the second scan driving circuit and the second light emitting driving circuit are located on the same side of the plurality of sub-pixels along the row direction of the sub-pixels.

[0267] In some example embodiments, the display substrate can further include a first reset driving circuit, a second reset driving circuit; the first reset driving circuit includes a plurality of cascaded first reset driving units; the second reset driving circuit includes a plurality of cascaded second reset driving units. An nth stage of the first reset driving units is configured to provide a first reset control signal to pixel circuits of a 2nth-1 row and a 2nth row of sub-pixels; an nth stage of the second reset driving units is configured to provide a second reset control signal to pixel circuits of a 2nth-1 row and a 2nth row of sub-pixels. Wherein, the first reset driving circuit and the second reset driving circuit are located on both sides of the plurality of sub-pixels along the row direction of the sub-pixels.

[0268] The description of the display substrate of the embodiment can refer to the description of the foregoing embodiments, and thus will not be repeated here.

[0269] Figure 30 A schematic diagram of a display device of at least one embodiment of the present disclosure. In some examples, as shown in FIG. 1, the display device includes a display substrate 100, a display panel 110, a display driver 120, and a display controller 130. Figure 30As shown, the present embodiment provides a display device 91 comprising the display substrate 910 of the foregoing embodiment. In some examples, the display substrate 910 can comprise an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like. However, the present embodiment is not limited thereto.

[0270] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "an example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. Furthermore, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples, without contradiction.

[0271] Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary and are not to be construed as limiting the present application, and the person skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present application.

Claims

1. A pixel circuit comprising: The driving sub-circuit, the data writing sub-circuit, the compensation sub-circuit, the coupling sub-circuit and the first control sub-circuit; The driving sub-circuit is coupled with the first node, the fourth node and the fifth node, and is configured to provide a driving signal to the fourth node under the control of the first node; The data writing sub-circuit is coupled with the first scan line, the data line and the third node, and is configured to write a data signal provided by the data line to the third node under the control of the first scan line; The compensation sub-circuit is coupled with the second scan line, the first node and the fourth node, and is configured to turn on the first node and the fourth node under the control of the second scan line, so that the threshold voltage of the driving sub-circuit is written to the first node; The coupling sub-circuit is coupled with the first node and the third node; The first control sub-circuit is coupled with the first control line, the third node and the first reference voltage line, and is configured to write a first reference voltage signal provided by the first reference voltage line to the third node under the control of the first control line after the data writing sub-circuit writes the data signal to the third node, so that the data signal is coupled to the first node through the coupling sub-circuit; The first control line is further configured to control the first control sub-circuit to write the first reference voltage signal to the third node before the starting time of the data writing sub-circuit writing the data signal to the third node; The starting time of the data writing sub-circuit writing the data signal to the third node is later than the starting time of the compensation sub-circuit writing the threshold voltage of the driving sub-circuit to the first node; the duration of the data writing sub-circuit writing the data signal to the third node is less than the duration of the compensation sub-circuit writing the threshold voltage of the driving sub-circuit to the first node; The duration of the starting time of the data writing sub-circuit writing the data signal to the third node from the starting time of the compensation sub-circuit writing the threshold voltage of the driving sub-circuit to the first node is greater than the duration of the starting time of the data writing sub-circuit writing the data signal to the third node from the ending time of the compensation sub-circuit writing the threshold voltage of the driving sub-circuit to the first node.

2. The pixel circuit of claim 1, wherein, The effective level signal provided by the second scan line is configured to control the compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first node; The ending time of the data writing sub-circuit writing the data signal to the third node is a first duration from the starting time of the effective level signal provided by the second scan line, and the ending time of the data writing sub-circuit writing the data signal to the third node is a second duration from the ending time of the effective level signal provided by the second scan line; the second duration is less than the first duration.

3. The pixel circuit of claim 2, wherein, The ending time of the data writing sub-circuit writing the data signal to the third node is the same as the ending time of the effective level signal provided by the second scan line.

4. The pixel circuit of claim 1, wherein, The effective level signal provided by the second scan line is configured to control the compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first node; The effective level signal provided by the second scan line includes three equal stages: a first signal stage, a second signal stage and a third signal stage, and the starting time of the effective level signal provided by the first scan line is located after the first signal stage.

5. The pixel circuit of claim 4, wherein, The starting time of the effective level signal provided by the first scan line is located at the third signal stage.

6. The pixel circuit according to any one of claims 1 to 5, wherein The coupling sub-circuit includes a first coupling sub-circuit and a second coupling sub-circuit; the first coupling sub-circuit is coupled with the first node and the second node, and the second coupling sub-circuit is coupled with the second node and the third node. The pixel circuit further includes a second control sub-circuit coupled with a second control line, the second node and a first voltage terminal, and configured to turn on the second node and the first voltage terminal under the control of the second control line, so that the second coupling sub-circuit stores the data signal written to the third node.

7. The pixel circuit of claim 6, wherein, The first coupling sub-circuit includes a first capacitor; a first electrode of the first capacitor is coupled with the first node, and a second electrode of the first capacitor is coupled with the second node. The second coupling sub-circuit includes a second capacitor; a first electrode of the second capacitor is coupled with the second node, and a second electrode of the second capacitor is coupled with the third node. The compensation sub-circuit includes a compensation transistor; a gate of the compensation transistor is coupled with the second scan line, a first electrode of the compensation transistor is coupled with the fourth node, and a second electrode of the compensation transistor is coupled with the first node. The second control sub-circuit includes a second control transistor; a gate of the second control transistor is coupled with the second control line, a first electrode of the second control transistor is coupled with the first voltage terminal, and a second electrode of the second control transistor is coupled with the second node; and the first voltage terminal is coupled with a first power line. The compensation transistor and the second control transistor are oxide thin film transistors, and the second control line and the second scan line are configured to provide the same signal.

8. The pixel circuit according to any one of claims 1 to 5, wherein, The data writing sub-circuit includes a data writing transistor; a gate of the data writing transistor is coupled with the first scan line, a first electrode of the data writing transistor is coupled with the data line, and a second electrode of the data writing transistor is coupled with the third node. The first control sub-circuit includes a first control transistor; a gate of the first control transistor is coupled with the first control line, a first electrode of the first control transistor is coupled with the first reference voltage line, and a second electrode of the first control transistor is coupled with the third node. The compensation sub-circuit includes a compensation transistor; a gate of the compensation transistor is coupled with the second scan line, a first electrode of the compensation transistor is coupled with the fourth node, and a second electrode of the compensation transistor is coupled with the first node.

9. The pixel circuit of claim 8, wherein, The transistor type of the data writing transistor and the first control transistor is the same, and different from the transistor type of the compensation transistor; the first control line and the second scan line are configured to provide the same signal.

10. The pixel circuit of claim 8, further comprising: The first light emitting control sub-circuit is coupled with the first light emitting control line, the first power line and the fifth node, and is configured to write, under the control of the first light emitting control line, a first power signal provided by the first power line into the fifth node; the first control line and the first light emitting control line are configured to provide the same signal.

11. The pixel circuit of claim 8, wherein, The transistor type of the data writing transistor and the first control transistor is different, and the transistor type of the data writing transistor and the compensation transistor is the same. The pixel circuit further comprises: The second light emitting control sub-circuit is coupled with the second light emitting control line, the fourth node and the sixth node, and is configured to turn on the fourth node and the sixth node under the control of the second light emitting control line, the sixth node being coupled with the first electrode of the light emitting element; The fourth reset sub-circuit is coupled with the third node, the first reference voltage line and the third reset control line, and is configured to write, under the control of the third reset control line, a first reference voltage signal provided by the first reference voltage line into the third node; the first control line and the second light emitting control line are configured to provide the same signal.

12. The pixel circuit of any one of claims 1 to 5, further comprising: The first reset sub-circuit is coupled with the first reset control line, the first reset voltage line and the fourth node, and is configured to write, under the control of the first reset control line, a first reset voltage signal provided by the first reset voltage line into the fourth node; or, the first reset sub-circuit is coupled with the first reset control line, the first reset voltage line and the first node, and is configured to write, under the control of the first reset control line, a first reset voltage signal provided by the first reset voltage line into the first node; The second reset sub-circuit is coupled with the second reset control line, the second reset voltage line and the sixth node, and is configured to write, under the control of the second reset control line, a second reset voltage signal provided by the second reset voltage line into the sixth node, the sixth node being coupled with the first electrode of the light emitting element.

13. The pixel circuit of claim 12, further comprising: The third reset sub-circuit is coupled with the second reset control line, the second reference voltage line and the fifth node, and is configured to write, under the control of the second reset control line, a second reference voltage signal provided by the second reference voltage line into the fifth node.

14. The pixel circuit of claim 12, further comprising: The third capacitor has a first electrode coupled with a first bias signal line and a second electrode coupled with the first node or the second node.

15. The pixel circuit of claim 12, further comprising: The fourth capacitor has a first electrode coupled with a second bias signal line and a second electrode coupled with the fourth node or the fifth node.

16. A driving method of a pixel circuit, applied to the pixel circuit of any one of claims 1 to 15, the driving method comprising: The compensation sub-circuit is controlled by the second scan line to turn on the first node and the fourth node, so that the threshold voltage of the driving sub-circuit is written to the first node; The data writing sub-circuit is controlled by the first scan line to write a data signal provided by a data line to the third node; The first control sub-circuit is controlled by the first control line to write a first reference voltage signal provided by a first reference voltage line to the third node, so that the data signal is coupled to the first node through the coupling sub-circuit; The driving sub-circuit is controlled by the first node to provide a driving signal to the fourth node.

17. A display substrate, comprising: A plurality of sub-pixels and at least one first scan driving circuit, at least one of the plurality of sub-pixels comprising a light emitting element and a pixel circuit for driving the light emitting element to emit light; The pixel circuit is the pixel circuit of any one of claims 1 to 15; The first scan driving circuit comprises a plurality of first scan driving units; The nth-stage first scan driving unit is configured to provide a first scan signal to the pixel circuit of the nth row of sub-pixels; n is an integer greater than 0; The 2i-1-stage first scan driving unit is cascaded with the 2i+1-stage first scan driving unit, and the 2i-stage first scan driving unit is cascaded with the 2i+2-stage first scan driving unit; i is an integer greater than 0. 18.The display substrate of claim 17, further comprising: The first light emitting driving circuit, the second scan driving circuit, and the second light emitting driving circuit, the first light emitting driving circuit comprising a plurality of cascaded first light emitting driving units; The second scan driving circuit comprises a plurality of cascaded second scan driving units; The second light emitting driving circuit comprises a plurality of cascaded second light emitting driving units; The nth-stage first light emitting driving unit is configured to provide a first light emitting control signal to the pixel circuit of the nth row of sub-pixels; Alternatively, the nth-stage first light emitting driving unit is configured to provide a first light emitting control signal to the pixel circuit of the 2n-1th row and the 2nth row of sub-pixels; The nth-stage second scan driving circuit is configured to provide a second scan signal to the pixel circuit of the 2n-1th row and the 2nth row of sub-pixels; The nth-stage second light emitting driving circuit is configured to provide a second light emitting control signal to the pixel circuit of the 2n-1th row and the 2nth row of sub-pixels; The second scan driving circuit and the second light emitting driving circuit are located on the same side of the plurality of sub-pixels along the row direction of the sub-pixels.

19. The display substrate of claim 17, further comprising: The first reset driving circuit and the second reset driving circuit; The first reset driving circuit comprises a plurality of cascaded first reset driving units; The second reset driving circuit comprises a plurality of cascaded second reset driving units; the nth-stage first reset driving circuit is configured to provide a first reset control signal to the pixel circuit of the 2n-1th row and the 2nth row of sub-pixels; the nth-stage second reset driving circuit is configured to provide a second reset control signal to the pixel circuit of the 2n-1th row and the 2nth row of sub-pixels; the first reset driving circuit and the second reset driving circuit are located on different sides of the plurality of sub-pixels along the row direction of the sub-pixels.

20. A display device comprising the display substrate of any one of claims 17 to 19.

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