Display device, sub-pixel and driving method

Abstract

The invention discloses a display device, a sub-pixel and a driving method thereof. A sub-pixel circuit of a display device includes a driving transistor, a first transistor controlled by a scan signal and electrically connected to a gate node and a drain node of the driving transistor, a second transistor controlled by the scan signal and electrically connected to a source node of the driving transistor and a data line, a third transistor controlled by the light emission control signal and electrically connected to a high potential voltage supply line and a source node of the driving transistor, a fourth transistor controlled by the light emission control signal and electrically connected to a drain node of the driving transistor and the light emitting element, and a fifth transistor controlled by the scan signal and electrically connected to the initialization voltage supply line and the light emitting element. The scanning signal lines and the light-emitting control signal lines form an integrated structure, so that the number of wires or signal lines is reduced. An internally compensated data writing process of the display device is not affected by a parasitic capacitor.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2023-0194431, filed on December 28, 2023, and Korean Patent Application No. 10-2024-0092331, filed on July 12, 2024, the entire disclosures of which are incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present disclosure relate to a display device, a sub-pixel, and a method of driving a display device. Background Art

[0004] Recently emerging organic light emitting display devices have advantages such as fast response rates, high emission efficiency, high luminous intensity, and wide viewing angles due to the use of self-emitting organic light emitting diodes (OLEDs) therein.

[0005] In an organic light emitting display device, each includes sub-pixels in which an OLED and a driving transistor for driving the OLED are arranged in a matrix form, and the brightness of each sub-pixel selected by a selection signal is controlled according to the gradation of data.

[0006] In an organic light emitting display device, an OLED and a driving transistor for driving the OLED are provided in each sub-pixel defined on a display panel. The characteristic values (e.g., threshold voltage or mobility) of the driving transistors in each sub-pixel may vary according to the driving time, or differences in the driving time of each sub-pixel may cause deviations in the characteristics of the transistors. This may cause brightness deviation (brightness non-uniformity) between sub-pixels, resulting in poor image quality.

[0007] In a conventional organic light emitting display device, in order to solve the brightness deviation between sub-pixels, sensing and compensation techniques have been proposed to sense and compensate for the deviation of characteristic values between driving transistors. However, the method of storing charges corresponding to the image display data voltage in a storage capacitor during a data writing period may be affected by parasitic capacitors. This may result in poor image quality. Summary of the Invention

[0008] Embodiments of the present disclosure may provide a display device, a sub-pixel, and a method of driving a display device that are almost completely unaffected by parasitic capacitors.

[0009] Embodiments of the present disclosure may provide a display device, a sub-pixel, and a method of driving a display device in which the number of wires or signal lines can be reduced by forming a scan signal line and a light emission control signal line into an integrated structure.

[0010] A display device according to an embodiment of the present disclosure may include: a display panel in which data lines and gate lines cross and a plurality of sub-pixels are arranged; a data driver that provides data signals to the data lines; and a gate driver that provides scan signals and light emission control signals to the gate lines. Each of the sub-pixels may include a sub-pixel circuit. The sub-pixel circuit includes: a driving transistor that drives a light emitting element; a first transistor that is controlled by the scan signal and electrically connected to a gate node and a drain node of the driving transistor; a second transistor that is controlled by the scan signal and electrically connected to a source node of the driving transistor and the data line; a third transistor that is controlled by the light emission control signal and electrically connected to a high potential voltage supply line and the source node of the driving transistor; a fourth transistor that is controlled by the light emission control signal and electrically connected to the drain node of the driving transistor and the light emitting element; and a fifth transistor that is controlled by the scan signal and electrically connected to an initialization voltage supply line and the light emitting element.

[0011] The gate node of the first transistor, the gate node of the second transistor, and the gate node of the fifth transistor may be commonly connected to one scan signal line. The gate node of the third transistor and the gate node of the fourth transistor may be commonly connected to one light emission control signal line.

[0012] A sub-pixel according to an embodiment of the present disclosure may include: a light emitting element; a driving transistor that drives the light emitting element; a first transistor that is controlled by a scan signal and electrically connected to a gate node and a drain node of the driving transistor; a second transistor that is controlled by the scan signal and electrically connected to a source node of the driving transistor and a data line; a third transistor that is controlled by a light emission control signal and electrically connected to a high potential voltage supply line and the source node of the driving transistor; a fourth transistor that is controlled by the light emission control signal and electrically connected to the drain node of the driving transistor and the light emitting element; and a fifth transistor that is controlled by the scan signal and electrically connected to an initialization voltage supply line and the light emitting element.

[0013] The gate node of the first transistor, the gate node of the second transistor, and the gate node of the fifth transistor may be commonly connected to a scan signal line. The gate node of the third transistor and the gate node of the fourth transistor may be commonly connected to a light emission control signal line.

[0014] One frame time for driving the sub-pixel according to an embodiment of the present disclosure may include: a first period (i.e., an initialization period), in which the source node of the driving transistor has a high potential voltage provided by the high potential voltage supply line, and the gate node of the driving transistor has an initialization voltage provided by the initialization voltage supply line; and a second period (i.e., a sampling period), in which the source node of the driving transistor has a data voltage provided by the data line, and the gate node of the driving transistor has a tracking voltage different from the data voltage.

[0015] The tracking voltage may correspond to a voltage obtained by subtracting the absolute value of the threshold voltage of the driving transistor from the data voltage.

[0016] During the first period, the initialization voltage may be applied to the gate node of the driving transistor through the fifth transistor, the fourth transistor, and the first transistor.

[0017] A method for driving a display device according to an embodiment of the present disclosure may include: a first operation step (i.e., an initialization period) of applying a high potential voltage to the source node of the driving transistor and applying an initialization voltage to the gate node of the driving transistor; and a second operation step (i.e., a sampling period) of applying a data voltage to the source node of the driving transistor.

[0018] In the second operation step, the driving transistor may be in a diode-connected state, and the gate node of the driving transistor may have a tracking voltage different from the data voltage.

[0019] In the second operation step, the first transistor connected to the drain node and the gate node of the driving transistor may be turned on, so that the driving transistor is in a diode-connected state.

[0020] The tracking voltage may correspond to a voltage obtained by subtracting the absolute value of the threshold voltage of the driving transistor from the data voltage.

[0021] In the first operation step, the initialization voltage may be applied to the gate node of the driving transistor through the first transistor.

[0022] According to an embodiment of the present disclosure, instead of using a method of charging a charge corresponding to an image display data voltage to a storage capacitor during a data writing process, a method of directly applying an image display data voltage to a driving transistor during a sensing phase may be used, so that it is almost completely unaffected by parasitic capacitors.

[0023] According to an embodiment of the present disclosure, data may be directly transmitted to a driving transistor instead of being transmitted to the driving transistor through capacitive coupling, so that accurate data writing can be achieved without being affected by parasitic capacitors.

[0024] According to an embodiment of the present disclosure, by forming a scan signal line and a light emission control signal into an integrated structure, the number of wires or signal lines can be reduced. Therefore, the aperture ratio of the display panel can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram illustrating a system configuration of a display device according to an embodiment of the present disclosure;

[0026] Figure 2 is a perspective view illustrating an exemplary system of a display device;

[0027] Figure 3 illustrates an equivalent circuit of a sub-pixel SP according to an embodiment of the present disclosure;

[0028] Figure 4 illustrates an equivalent circuit of a sub-pixel SP according to other embodiments of the present disclosure;

[0029] Figure 5 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure;

[0030] Figure 6 is a schematic diagram illustrating a gate signal applied to a sub-pixel of a display device according to an embodiment of the present disclosure during sub-pixel driving;

[0031] Figure 7 is a circuit and timing diagram illustrating the driving of a display device according to an embodiment of the present disclosure during an initialization period;

[0032] Figure 8 is a circuit and timing diagram illustrating the driving of a display device according to an embodiment of the present disclosure during a sampling period;

[0033] Figure 9 is a circuit and timing diagram illustrating the driving of a display device according to an embodiment of the present disclosure during a holding period;

[0034] Figure 10is a circuit diagram and timing diagram for driving a display device according to an embodiment of the present disclosure during a light emission period;

[0035] Figure 11 illustrates an exemplary signal line configuration of a display device according to an embodiment of the present disclosure;

[0036] Figure 12 is a schematic diagram of a gate signal applied according to a driving timing in which a light emission period is kept the same in a sub-pixel of a display device according to an embodiment of the present disclosure;

[0037] Figure 13 is a schematic diagram of a gate signal in which a light emission period is kept the same in one frame in a display panel of a display device according to an embodiment of the present disclosure. Detailed Embodiments

[0038] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In the following description of the embodiments or implementations of the present invention, reference will be made to the drawings, in which specific embodiments or implementations that can be implemented are shown by way of example, and the same reference numerals and symbols may be used in the drawings to refer to the same or similar components even if they are shown in different drawings. Further, in the following description of the embodiments or implementations of the present invention, when it is determined that a detailed description of known functions and components incorporated herein would obscure the subject matter in some embodiments of the present invention, the detailed description thereof will be omitted. Terms such as "comprising", "having", "including", "consisting of", "composed of", and "formed of" used herein generally intend to allow addition of other components, unless these terms are used with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0039] Terms such as "first", "second", "A", "B", "(A)", or "(B)" may be used herein to describe elements of the present invention. Each of these terms does not limit the nature, order, sequence, or number, etc. of the element, but is only used to distinguish the corresponding element from other elements.

[0040] When it is mentioned that a first element is "connected or coupled", "contacted or overlapped" with a second element, etc., it should be interpreted that the first element can not only be "directly connected or coupled" or "directly contacted or overlapped" with the second element, but also a third element can be "inserted" between the first element and the second element, or the first element and the second element can be "connected or coupled", "contacted or overlapped", etc. with each other via a fourth element. Herein, the second element may be included in at least one of two or more elements that are "connected or coupled", "contacted or overlapped", etc. with each other.

[0041] When using relative time terms such as "after", "subsequently", "next", "before", etc. to describe the process or operation of an element or structure, or the processes and steps in an operation method, processing method, or manufacturing method, these terms can be used to describe discontinuous or non-sequential processes or operations, unless the terms "directly" or "immediately" are used together.

[0042] In addition, when referring to any scale, relative dimension, etc., even if the relevant description is not specified, the numerical values of elements or features or the corresponding information (e.g., level, range, etc.) should be considered to include the tolerance or error range that can be caused by various factors (e.g., process factors, internal or external shocks, noise, etc.). In addition, the term "may" fully encompasses all the meanings of the term "can".

[0043] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0044] Figure 1 is a schematic diagram illustrating the system configuration of a display device according to an embodiment of the present disclosure.

[0045] Referring to Figure 1 , the display device 100 according to the present embodiment may include a display panel 110 and a driver circuit for driving the display panel 110. A plurality of data lines DL and a plurality of gate lines GL are provided in the display panel 110, and a plurality of sub-pixels SP defined by the plurality of data lines DL and the plurality of gate lines GL are arranged in a matrix form.

[0046] From a functional perspective, the driver circuit may include a data driver circuit 120 for driving the plurality of data lines DL, a gate driver circuit 130 for driving the plurality of gate lines GL, a controller 140 for controlling the data driver circuit 120 and the gate driver circuit 130, etc.

[0047] In the display panel 110, the plurality of data lines DL and the plurality of gate lines GL may be arranged to cross each other. For example, the plurality of gate lines GL may be arranged along rows or columns, and the plurality of data lines DL may be arranged along columns or rows. For ease of description, it is assumed hereinafter that the plurality of gate lines GL are arranged along rows and the plurality of data lines DL are arranged along columns.

[0048] In addition to the plurality of data lines DL and the plurality of gate lines GL, other types of lines (e.g., wires or signal lines) may also be provided on the display panel 110.

[0049] The controller 140 may provide image data (or video data) DATA to the data driver circuit 120.

[0050] In addition, the controller 140 can control the operations of the data driver circuit 120 and the gate driver circuit 130 by providing various control signals DCS and GCS required for the driving operations of the data driver circuit 120 and the gate driver circuit 130.

[0051] The controller 140 starts scanning according to the timing implemented in each frame, converts the externally input image data into a data signal format readable by the data driver circuit 120, outputs the converted image data DATA, and controls data driving at an appropriate time according to the scanning.

[0052] To control the data driver circuit 120 and the gate driver circuit 130, the controller 140 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable signal (DE), and a clock signal (CLK) from an external source (e.g., the host system 200), generates various control signals, and outputs the generated control signals to the data driver circuit 120 and the gate driver circuit 130.

[0053] For example, to control the gate driver circuit 130, the controller 140 outputs various gate control signals GCS including a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), etc.

[0054] To control the data driver circuit 120, the controller 140 also outputs various data control signals DCS including a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE), etc.

[0055] The controller 140 can be a timing controller used in general display technologies, or can be a controller that can include a timing controller and can also perform other control functions.

[0056] The controller 140 can be implemented as a separate component from the data driver circuit 120, or the controller 140 can be integrated with the data driver circuit 120 to form an integrated circuit.

[0057] The data driver circuit 120 receives the image data DATA from the controller 140 and provides data voltages to a plurality of data lines DL, thereby driving the plurality of data lines DL. Here, the data driver circuit 120 is also referred to as a source driver circuit.

[0058] The data driver circuit 120 can include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, etc.

[0059] In some cases, the data driver circuit 120 can further include one or more analog-to-digital converters (ADCs).

[0060] The gate driver circuit 130 sequentially drives a plurality of gate lines GL by sequentially providing scan signals to the plurality of gate lines GL. The gate driver circuit 130 is also referred to as a scan driver circuit.

[0061] The gate driver circuit 130 may include a shift register, a level shifter, etc.

[0062] The gate driver circuit 130 sequentially provides a scan signal of a turn-on voltage or a turn-off voltage to the plurality of gate lines GL under the control of the controller 140.

[0063] When a specific gate line is turned on through the gate driver circuit 130, the data driver circuit 120 converts the image data DATA received from the controller 140 into an analog format data voltage and provides the converted data voltage to the plurality of data lines DL.

[0064] The data driver circuit 120 may be located on one side (e.g., the top side or the bottom side) of the display panel 110, or in some cases, the data driver circuit 120 may be located on both sides (e.g., the top side and the bottom side) of the display panel 110 according to the driving method, the design of the display panel, etc.

[0065] The gate driver circuit 130 may be located on one side (e.g., the right side or the left side) of the display panel 110, or in some cases, the gate driver circuit 130 may be located on both sides (e.g., the right side and the left side) of the display panel 110 according to the driving method, the design of the display panel, etc.

[0066] The data driver circuit 120 may be implemented to include at least one source driver integrated circuit SDIC.

[0067] Each source driver integrated circuit may be connected to a bonding pad on the display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) method, or may be directly disposed on the display panel 110. In some cases, each source driver integrated circuit may be provided as an integrated part of the display panel 110. In addition, each source driver integrated circuit may be implemented by a chip on film (COF) method. In this case, each source driver integrated circuit may be mounted on a circuit film and may be electrically connected to the data lines DL on the display panel 110 through the circuit film.

[0068] The gate driver circuit 130 may include one or more gate driver integrated circuits GDICs connected to the bonding pads of the display panel 110 by a TAB method or a COG method. The gate driver circuit 130 may also be implemented by an in-panel gate (GIP) method and directly disposed on the display panel 110. In addition, the gate driver circuit 130 may be implemented by a COF method. In this case, each gate driver integrated circuit included in the gate driver circuit 130 may be mounted on a circuit film and electrically connected to the gate lines GL on the display panel 110 through the circuit film.

[0069] Figure 2 is a perspective view of an exemplary system of the display device 100.

[0070] With Figure 1 referring together to Figure 2 , the display panel 110 may include a display area DA for displaying an image and a non-display area NDA for not displaying an image.

[0071] According to Figure 2 an embodiment of, the data driver circuit 120 may include a plurality of source driver integrated circuits SDICs and may be implemented by a chip-on-film (COF) method. The plurality of source driver integrated circuits SDICs may be mounted on a source-side circuit film SF connected to the non-display area NDA of the display panel 110. Here, the source-side circuit film SF may also be referred to as a flexible printed circuit.

[0072] According to Figure 2 an embodiment of, the gate driver circuit 130 may be implemented by a GIP method. Hereinafter, the gate driver circuit 130 implemented by a GIP method is also referred to as a "gate driver panel circuit (GPC)".

[0073] The gate driver panel circuit may be disposed in the non-display area NDA of the display panel 110. According to Figure 2 an embodiment of, the gate driver panel circuit may be disposed in the non-display area NDA located on one peripheral portion of the display area DA and the non-display area NDA located on another peripheral portion of the display area DA.

[0074] The plurality of gate driver integrated circuits GDICs included in the gate driver panel circuit may be respectively mounted on a gate-side circuit film GF.

[0075] The plurality of source driver integrated circuits SDICs included in the data driver circuit 120 may be respectively mounted on the source-side circuit film SF.

[0076] The first side of the source-side circuit film SF is electrically connected to the display panel 110. Wires may be provided on the source-side circuit film SF to electrically connect the source driver integrated circuit SDIC and the display panel 110.

[0077] The display device 100 may include at least one source printed circuit board SPCB for circuit connection between a plurality of source driver integrated circuits SDIC and other devices (e.g., 140, L / S, PMIC), and a control printed circuit board CPCB that allows control components and various electronic devices to be mounted therein.

[0078] At least one source printed circuit board SPCB may be connected to the source-side circuit film SF on which the source driver integrated circuit SDIC is mounted. That is, each source-side circuit film SF on which the source driver integrated circuit SDIC is mounted may be electrically connected to the display panel 110 on one side and to the source printed circuit board SPCB on the other side.

[0079] At least one source printed circuit board SPCB may be connected to the other side of the source-side circuit film SF on which the source driver integrated circuit SDIC is mounted.

[0080] The control printed circuit board CPCB may allow a controller 140, a power management integrated circuit (PMIC) 150, etc. to be mounted thereon.

[0081] The controller 140 may execute the entire control function related to the operation of the display panel 110, and may control the operation of a plurality of source driver integrated circuits SDIC and the gate driver panel circuit.

[0082] The power management integrated circuit 150 may supply or control various voltages or currents to a plurality of source driver integrated circuits SDIC and the gate driver panel circuit, etc., or control the various voltages or currents to be supplied.

[0083] At least one source printed circuit board SPCB and the control printed circuit board CPCB may be circuit-connected through at least one connection cable (CBL). The connection cable (CBL) may be, for example, one of a flexible printed circuit (FPC) or a flexible flat cable (FFC).

[0084] At least one source printed circuit board SPCB and the control printed circuit board CPCB may be integrated into one printed circuit board.

[0085] The display device 100 may further include a level shifter (L / S) for adjusting the voltage level of a signal. For example, the level shifter (L / S) may be provided on the control printed circuit board CPCB or the source printed circuit board SPCB.

[0086] In the display device 100, a level shifter (L / S) may output a signal required for gate driving to a gate driver panel circuit (GIP type gate driver circuit 130).

[0087] For example, a power management integrated circuit 150 may output a signal to the level shifter (L / S). The level shifter (L / S) may adjust the voltage level of the signal input from the power management integrated circuit 150. The signal whose voltage level is adjusted by the level shifter (L / S) may be input to the gate driver panel circuit.

[0088] For example, the level shifter (L / S) may output a plurality of clock signals having different phases to the gate driver panel circuit. The gate driver panel circuit may generate a plurality of gate signals (e.g., a scan signal (SC) and a sense signal (SE)) based on the plurality of clock signals input from the level shifter (L / S) and output the plurality of gate signals to a plurality of gate lines (e.g., a scan signal line (SCL) and a sense signal line (SENL)).

[0089] Refer to Figure 2 , a non-display area NDA of the display panel 110 may include a gate border area. The gate border area may refer to an area where a gate driver panel circuit (GIP type gate driver circuit 130) and various lines connected to the gate driver panel circuit are provided.

[0090] Refer to Figure 2 , various lines connected to the gate driver panel circuit may include a plurality of clock lines, a high-level gate voltage line, and a low-level gate voltage line.

[0091] Figure 3 Illustrated is an equivalent circuit of a sub-pixel SP according to an embodiment of the present disclosure.

[0092] Refer to Figure 3 , in each sub-pixel SP arranged in the display panel 110, an organic light emitting diode OLED, a plurality of display driving transistors for driving the organic light emitting diode OLED, and a storage capacitor Cst may be provided.

[0093] Figure 3 Illustrated as an example is a 6T1C structure including six display driving transistors T11, T12, T13, T14, T15, and T16 and one storage capacitor Cst provided in the sub-pixel SP. The sub-pixel SP may be implemented in various forms according to the number of circuit elements provided therein and their connection relationships.

[0094] In the display device according to the present embodiment (i.e., a stretchable display device), in order to compensate for the threshold voltage Vth and voltage drop (i.e., IR drop) of the driving transistor, a 6T1C 1SCAN / 1EM integrated structure can be used. Here, the 1SCAN / 1EM integrated structure can reduce the number of wirings compared to the conventional structure by integrating the scan signal line and the light emission control signal line.

[0095] Although the case where the display driving transistor provided in the sub-pixel SP is a P-type transistor is shown as an example, the sub-pixel SP may also be provided with an N-type display driving transistor.

[0096] The transistor T11 can be located between the data driver circuit 120 that provides the data voltage and the storage capacitor Cst and is electrically connected to the data driver circuit 120 and the storage capacitor Cst. In addition, the transistor T11 can be controlled by the scan signal SCAN provided through the gate line GL.

[0097] When a scan signal having a conductive level is applied through the gate line GL, the transistor T11 causes the data voltage VDATA provided from the data driver circuit 120 to be applied to one side of the storage capacitor Cst.

[0098] The transistor T12 can be located between the line that provides the high potential voltage VDD and the transistor T15 and is electrically connected to the line and the transistor T15. In addition, the gate electrode of the transistor T12 can be electrically connected to the storage capacitor Cst.

[0099] The transistor T12 is called a driving transistor, and it can control the current flowing to the organic light-emitting diode OLED according to the voltage applied to the gate electrode of the transistor T12, thereby controlling the brightness presented by the organic light-emitting diode OLED.

[0100] The transistor T13 can be located between the gate electrode and the drain electrode or the source electrode of the transistor T12 and is electrically connected to the gate electrode and the drain electrode or the source electrode of the transistor T12. In addition, the transistor T13 can be controlled by the scan signal SCAN provided through the gate line GL.

[0101] The transistor T13 is designed to compensate for the threshold voltage of the transistor T12 and is also called a compensation transistor.

[0102] In other words, the transistor T12 is a driving transistor that should control the current flowing to the organic light-emitting diode OLED according to the data voltage applied to the sub-pixel SP. However, due to the deviation of the threshold voltage of the transistor T12 provided in the sub-pixel SP, the light-emitting element provided in the sub-pixel SP, that is, the organic light-emitting diode OLED may not present the desired brightness.

[0103] Therefore, the threshold voltage of the transistor T12 provided in each sub-pixel SP can be compensated by the transistor T13.

[0104] Specifically, an initialization period, a sampling period, a data writing period, and a light emitting period are executed in the sub-pixel SP, and the threshold voltage is compensated by this execution.

[0105] For example, when a scan signal for turning on the transistor T13 is applied through the gate line GL, a voltage equal to the high potential voltage VDD minus the threshold voltage of the transistor T12 is applied to the gate electrode of the transistor T12.

[0106] By applying a data voltage to one side of the storage capacitor Cst in a state where the high potential voltage VDD minus the threshold voltage is applied to the gate electrode of the transistor T12, the threshold voltage of the transistor T12 can be compensated.

[0107] That is to say, during the light emitting period, the current flowing through the transistor T12 and the current supplied to the organic light emitting diode OLED are the same, and the following equation holds.

[0108] Ioled = K * [Vsg - |Vth|] 2 = K * [VDD - VDATA + |Vth| - |Vth|] 2 = K * [VDD - VDATA] 2

[0109] As described above, it can be seen that since the threshold voltage Vth of the transistor T12 is eliminated in the equation for obtaining the current Ioled supplied to the organic light emitting diode OLED, the current Ioled flowing to the organic light emitting diode OLED is not affected by the threshold voltage Vth of the transistor T12.

[0110] That is to say, since the influence of the threshold voltage Vth is eliminated during the sub-pixel driving process, threshold voltage compensation naturally occurs during the sub-pixel driving process.

[0111] Here, the transistor T11 for controlling the application of the data voltage to one side of the storage capacitor Cst and the transistor T13 for compensating the threshold voltage of the transistor T12 can be controlled by the scan signal provided to the same gate line, or can be controlled by the scan signals provided to different gate lines GL.

[0112] In this way, by compensating for the deviation of the threshold voltage of the transistor T12 by the transistor T13, the deviation of the brightness presented by the sub-pixel SP due to the difference in the threshold voltage of the transistor T12 can be prevented.

[0113] The transistor T14 may be located between the storage capacitor Cst and the line providing the reference voltage Vref and is electrically connected to the storage capacitor Cst and the line. In addition, the transistor T14 may be controlled by the light emission control signal EM provided through the gate line GL.

[0114] When the light emission control signal EM having a conductive level is applied through the gate line GL, such a transistor T14 may initialize the voltage on one side of the storage capacitor Cst, or may gradually discharge the data voltage VDATA applied to one side of the storage capacitor Cst and cause the current based on the data voltage VDATA to flow to the organic light emitting diode OLED.

[0115] In other words, the data voltage VDATA stored in the storage capacitor Cst is applied to the gate node of the transistor T12 during the light emission period, so that the transistor T12 adjusts the current Ioled flowing to the organic light emitting diode OLED.

[0116] Specifically, the voltage of the gate node and the voltage of the drain node of the transistor T12 determined during the data writing period (or writing period) may cause a current to flow through the transistor T12, thereby providing a desired current to the organic light emitting diode OLED. Therefore, the organic light emitting diode OLED can adjust the brightness through the data voltage VDATA.

[0117] However, this method of writing data by applying the data voltage VDATA stored in the storage capacitor Cst to the gate node of the driving transistor has the disadvantage of being affected by the parasitic capacitor caused by the storage capacitor Cst.

[0118] In a state where the data voltage is applied to one side of the storage capacitor Cst and the high potential voltage VDD compensated for the threshold voltage is applied to the gate electrode of the transistor T12, when the light emission control signal of the conductive level is applied, the transistor T15 may be turned on, so that the current flows to the organic light emitting diode OLED.

[0119] These transistors T14 and transistor T15 control the light emission timing of the organic light emitting diode OLED, and thus are called light emitting transistors.

[0120] The transistor T16 may be located between the line providing the reference voltage Vref and the anode of the organic light emitting diode OLED and is electrically connected to the line and the anode. In addition, the transistor T16 may be controlled by the scan signal SCAN provided through the gate line GL.

[0121] When a scan signal having an on level is applied through a gate line GL, the transistor T16 can apply a reference voltage Vref to the anode of the organic light-emitting diode OLED, or can initialize, for example, a node between the transistors T12 and T15 using the reference voltage Vref during an initialization period.

[0122] As described above, the display driving transistor provided in the sub-pixel SP is driven by a scan signal and a light emission control signal, and causes a current based on a data voltage to flow to the organic light-emitting diode OLED, so that the sub-pixel SP can present brightness according to image data.

[0123] Figure 4 Illustrated is an equivalent circuit of a sub-pixel SP according to other embodiments of the present disclosure.

[0124] Refer to Figure 4 , in each sub-pixel SP arranged in the display panel 110, a light-emitting element ED and a plurality of display driving transistors for driving the light-emitting element ED may be provided. Figure 4 The equivalent circuit of the sub-pixel shown in Figure 3 is different from the equivalent circuit of the sub-pixel shown in Figure 3 in that a storage capacitor Cst provided at a node between the transistors T11 and T12 in the sub-pixel shown in

[0125] Figure 4 As an example, illustrated is a 6T1C structure including six display driving transistors DRT, T1, T2, T3, T4, and T5 and one storage capacitor Cst provided in the sub-pixel SP. The sub-pixel SP can be implemented in various forms according to the number of circuit elements provided therein and their connection relationships.

[0126] In the display device according to the present embodiment, in order to compensate for the threshold voltage Vth and voltage drop (i.e., IR drop) of the driving transistor DRT, a 6T1C 1SCAN / 1EM integrated structure can be used. Since, as described above, the sub-pixel SP is configured to be driven by only one scan signal SCAN and one light emission control signal EM, the number of a plurality of horizontal signal lines 1100 (see Figure 11 ) including the gate line GL provided on the display panel 110 can be reduced, thereby further improving the stretchable characteristics of the display device 100.

[0127] In addition, although the case where the driving transistor DRT provided in the sub-pixel SP is a P-type transistor is shown as an example, the sub-pixel SP can also be implemented to include an N-type driving transistor DRT.

[0128] Initialize the sub-pixel using the data voltage VDATA, and then drive it by an internal compensation method for sensing the threshold voltage of the driving transistor DRT.

[0129] The light-emitting element ED includes a first electrode, a second electrode, and a light-emitting layer located between the first electrode and the second electrode. The first electrode of the light-emitting element ED can be an anode or a cathode, and the second electrode can be a cathode or an anode. The light-emitting element ED can be, for example, an organic light-emitting diode (OLED), an inorganic-based light-emitting diode (LED), a quantum dot LED, etc.

[0130] The second electrode of the light-emitting element ED can be a common electrode. In this case, a base voltage VSS is applied to the second electrode of the light-emitting element ED. Here, the base voltage VSS can be, for example, a ground voltage or a voltage similar to the ground voltage.

[0131] The driving transistor DRT is a transistor for driving the light-emitting element ED, and includes a first node N1, a second node N2, and a third node N3.

[0132] The second node N2 of the driving transistor DRT can be a node corresponding to the gate node (also referred to as the gate electrode), which can be electrically connected to the storage capacitor Cst and the first transistor T1. The first node N1 of the driving transistor DRT can be the drain node (also referred to as the drain electrode) or the source node (also referred to as the source electrode) of the driving transistor DRT, can be electrically connected to the source node or the drain node of the first transistor T1, and can be electrically connected to the source node or the drain node of the fourth transistor T4. The third node N3 of the driving transistor DRT can be the source node or the drain node of the driving transistor DRT, can be electrically connected to the source node or the drain node of the second transistor T2, and can be electrically connected to the source node or the drain node of the third transistor T3.

[0133] The driving transistor DRT can be turned on according to the voltage applied to the second node N2 (i.e., the gate node) to supply current to the light-emitting element ED, thereby causing the light-emitting element ED to emit light.

[0134] The first transistor T1 can be electrically connected to the first node N1 and the second node N2 of the driving transistor DRT. In addition, the first transistor T1 can be controlled by a scan signal SCAN provided through the scan signal line SCL. The scan signal line SCL can be a type of gate line GL.

[0135] The second transistor T2 can be located between the third node N3 of the driving transistor DRT and the data line DL and be electrically connected to the third node N3 and the data line DL. The second transistor T2 can be controlled by a scan signal SCAN provided through the scan signal line SCL.

[0136] For example, referring to Figure 8 , during the sampling period S20, in a state where a scan signal SCAN for turning on the first transistor T1 and the second transistor T2 is applied through the scan signal line SCL, the second node N2 (i.e., the gate node) of the driving transistor DRT has a voltage VDATA - |Vth| obtained by subtracting the absolute value |Vth| of the threshold voltage of the driving transistor DRT from the data voltage VDATA. Here, the difference between the data voltage VDATA and the absolute value |Vth| of the threshold voltage of the driving transistor DRT can be referred to as a tracking voltage.

[0137] During the sampling period S20, the potential of the second node N2 rises and saturates to a voltage corresponding to the voltage VDATA - |Vth| obtained by subtracting the absolute value |Vth| of the threshold voltage of the driving transistor DRT from the data voltage VDATA (i.e., the tracking voltage).

[0138] In other words, during the sampling period, the gate-source potential difference of the driving transistor DRT, that is, the voltage difference between the second node N2 and the third node N3 can correspond to the magnitude of the threshold voltage.

[0139] When the data voltage VDATA - |Vth| compensated for the threshold voltage is applied to the second node N2 (i.e., the gate node) of the driving transistor DRT, and a light emission control signal EM having a conductive level is applied in this state, the light emitting element ED can be turned on, allowing current to flow to the light emitting element ED.

[0140] The third transistor T3 can be located between the high potential voltage supply line VDDL that provides the high potential voltage VDD and the third node N3 of the driving transistor DRT and is electrically connected to the high potential voltage supply line VDDL and the third node N3. The third transistor T3 can be controlled by the light emission control signal EM provided through the light emission control signal line EML.

[0141] When a light emission control signal EM having a conductive level is applied through the light emission control signal line EML, the third transistor T3 applies the high potential voltage VDD to the third node N3 of the driving transistor DRT.

[0142] The fourth transistor T4 can be located between the first node N1 of the driving transistor DRT and the anode of the light emitting element ED and is electrically connected to the first node N1 and the anode. The fourth transistor T4 can be controlled by the light emission control signal EM provided through the light emission control signal line EML. The light emission control signal line EML can be a type of gate line GL.

[0143] When a light emission control signal EM having a cut-off level is applied through the light emission control signal line EML, the fourth transistor T4 can turn off the light emitting element ED by blocking the current applied to the light emitting element ED. When a light emission control signal EM having a conduction level is applied through the light emission control signal line EML, the third transistor T3 and the fourth transistor T4 can transmit the light emitting element drive current flowing through the third node N3, the first node N1, and the fourth node N4 to the light emitting element ED, thereby causing the light emitting element ED to emit light.

[0144] Specifically, in a state where the high-potential voltage VDD is applied to one side of the storage capacitor Cst and the data voltage VDATA - |Vth| compensated for the threshold voltage is applied to the second node N2 (i.e., the gate node) of the drive transistor DRT, the fourth transistor T4 can be turned on in response to the application of the light emission control signal EM having a conduction level, thereby allowing current to flow to the light emitting element ED.

[0145] The third transistor T3 and the fourth transistor T4 control the light emission timing of the light emitting element ED, and thus are also referred to as light emission control transistors.

[0146] The fifth transistor T5 is controlled by the scan signal SCAN. The fifth transistor T5 can be located between the initialization voltage supply line VINTL and the anode of the light emitting element ED and is electrically connected to the initialization voltage supply line VINTL and the anode.

[0147] When a scan signal SCAN having a conduction level is applied through the scan signal line SCL, the fifth transistor T5 can apply the initialization voltage VINT to the anode of the light emitting element ED or initialize the node (i.e., the first node N1) between the drive transistor DRT and the fourth transistor T4.

[0148] In Figure 4 the sub-pixel SP, the drive transistor DRT and the first transistor T1 to the fifth transistor T5 can be P-type transistors. Therefore, the drive transistor DRT and the first transistor T1 to the fifth transistor T5 can be turned on by a gate voltage of a low level and can be turned off by a gate voltage of a high level. However, this is not intended to be limiting, and the drive transistor DRT and the first transistor T1 to the fifth transistor T5 can be N-type transistors. In this case, the drive transistor DRT and the first transistor T1 to the fifth transistor T5 can be turned on by a high-level gate voltage and turned off by a low-level gate voltage.

[0149] Hereinafter, for convenience, the drive transistor DRT and the first transistor T1 to the fifth transistor T5 will be described as P-type transistors by way of example.

[0150] In addition, as described above, Figure 3The sub-pixel configuration shown in [Figure] has a drawback in that data is written by applying the data voltage VDATA stored in the storage capacitor Cst to the gate node of the driving transistor, and thus is affected by the parasitic capacitor formed by the storage capacitor Cst.

[0151] To improve this, embodiments of the present disclosure may use a method of directly applying the data voltage from the data line to the gate node of the driving transistor in the data writing drive for the sub-pixel, instead of using a method of providing the data voltage stored in the capacitor to the gate node of the driving transistor, so as to be less affected by the parasitic capacitor. This will be described in detail below with reference to Figures 5 to 10 Detailed description.

[0152] Hereinafter, with reference to Figures 5 to 10 The internal compensation drive of the display device 100 according to an embodiment of the present disclosure will be described.

[0153] Figure 5 is a flowchart illustrating a method of driving the display device 100 according to an embodiment of the present disclosure, Figure 6 is a schematic diagram illustrating the gate signals SCAN and EM applied to the sub-pixel SP of the display device 100 according to an embodiment of the present disclosure during the driving of the sub-pixel SP.

[0154] With reference to Figure 5 and Figure 6 The driving time of each sub-pixel SP of the display device 100 according to an embodiment of the present disclosure may include an initialization period (INT) S10, a sampling period (SAMPLING) S20, a holding period (HOLD) S30, and an emission period (EMISSION) S40.

[0155] With reference to Figure 5 and Figure 6 The initialization period S10 is a period for initializing the voltages on the second node N2 and the third node N3 of the driving transistor DRT.

[0156] During the initialization period S10, the scan signal SCAN and the emission control signal EM have a conductive level voltage. Here, since the first transistor T1 to the fifth transistor T5 are P-type transistors, the conductive level voltage may be a low level voltage, and the cut-off level voltage may be a high level voltage. Hereinafter, the conductive level voltage is also referred to as the low level voltage, and the cut-off level voltage is also referred to as the high level voltage.

[0157] The sampling period S20 is a period for detecting and storing the threshold voltage of the driving transistor DRT. During the sampling period S20, the scan signal SCAN has a conductive level voltage, and the emission control signal EM has a cut-off level voltage.

[0158] Here, each of the initialization period S10 and the sampling period S20 can be referred to as a sensing period for sensing a threshold voltage.

[0159] The holding period S30 is a stage (or period) before the start of the light-emitting period S40. During the holding period S30, the scan signal SCAN and the light-emitting control signal EM have a cut-off level voltage.

[0160] The light-emitting period S40 is a period during which the light-emitting element ED emits light. During the light-emitting period S40, the scan signal SCAN has a cut-off level voltage, and the light-emitting control signal EM has a conductive level voltage. Thus, a path for current to flow to the light-emitting element ED can be formed.

[0161] Hereinafter, the initialization period S10, the sampling period S20, the holding period S30, and the light-emitting period S40 will be described in more detail with reference to Figure 5 and Figure 6 the driving method briefly described above.

[0162] Figure 7 FIG. is a circuit diagram and a timing diagram illustrating the driving of the display device 100 according to an embodiment of the present disclosure during the initialization period S10.

[0163] Referring to Figure 7 , during the initialization period S10, the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on by the scan signal SCAN having a conductive level voltage, and the third transistor T3 and the fourth transistor T4 are turned on by the light-emitting control signal EM having a conductive level voltage.

[0164] Thus, by applying the initialization voltage VINT to the second node N2 of the driving transistor DRT and applying the high-potential voltage VDD to the third node N3 of the driving transistor DRT, the second node N2 and the third node N3 of the driving transistor DRT can be initialized.

[0165] During the initialization period S10, the initialization voltage VINT provided to the second node N2 is to initialize the sub-pixel SP to a predetermined level, and the magnitude of the initialization voltage VINT is set to a voltage value lower than the operating voltage of the light-emitting element ED so that the light-emitting element ED does not emit light.

[0166] For example, the initialization voltage VINT can be set to a voltage having a magnitude of -1V to +1V, and more preferably, to a value of 0V or less.

[0167] As the initialization voltage VINT is provided to the second node N2 of the driving transistor DRT, the data voltage VDATA or the corresponding voltage written in the previous frame is initialized to the initialization voltage VINT.

[0168] Figure 8 2 is a circuit and timing diagram illustrating driving of the display device 100 during the sampling period S20 according to an embodiment of the present disclosure.

[0169] Reference Figure 8 During the sampling period S20 after the initialization period S10, the first transistor T1, the second transistor T2 and the fifth transistor T5 are turned on by the scan signal SCAN having an on-level voltage. In addition, during the sampling period S20, the third transistor T3 and the fourth transistor T4 are turned off by the light emission control signal EM having an off-level voltage.

[0170] During the sampling period S20, the data voltage VDATA is applied to the third node N3 of the driving transistor DRT through the second transistor T2. Therefore, the voltage of the third node N3 may be changed from the high potential voltage VDD to the data voltage VDATA.

[0171] During the sampling period S20, the voltage of the second node N2 of the driving transistor DRT may start to change from the initialization voltage VINT applied for initialization in the previous period S10, and then saturate after a predetermined time. The saturation voltage of the second node N2 may correspond to the difference between the data voltage VDATA and the absolute value |Vth| of the threshold voltage of the driving transistor DRT (the saturation voltage of the second node=VDATA-|Vth|, where Vth may be a positive value or a negative value).

[0172] Particularly, in the present disclosure, in the sampling period S20 , the driving current flowing to the light emitting element ED may be determined by performing data writing by directly applying the data voltage VDATA to the second node N2 (ie, the gate node) of the driving transistor DRT.

[0173] In this regard, an image display data voltage must be applied to the gate node of the driving transistor DRT during a data writing period for determining a driving current flowing to the light emitting element ED.

[0174] Conventionally, as above, refer to Figure 3 As described above, during the data writing period, the data voltage VDATA stored in the storage capacitor Cst is supplied to the gate node of the driving transistor DRT.

[0175] In contrast, as mentioned above, Figure 4During the sampling period of the sub-pixels of the embodiment shown, a data voltage VDATA is applied to the third node N3 of the driving transistor DRT through the second transistor T2, such that the potential of the third node N3 becomes the data voltage VDATA. The saturated voltage in the second node N2 corresponds to the difference between the data voltage VDATA and the absolute value |Vth| of the threshold voltage of the driving transistor DRT.

[0176] Therefore, it is not necessary to supply the data voltage VDATA stored in the capacitor to the second node N2 (i.e., the gate node) of the driving transistor DRT. In other words, it can be understood that the data voltage VDATA is directly supplied from the third node N3 of the driving transistor DRT to the second node N2 (i.e., the gate node).

[0177] During the sampling period S20, with the fourth transistor T4 cut off and the first node N1 floating, the second node N2 of the driving transistor DRT can change from the initialization voltage VINT applied for initialization in the previous period S10, and saturates to a voltage corresponding to VDATA - |Vth| after a period of time.

[0178] That is to say, as the data voltage VDATA is applied to the third node N3 of the driving transistor DRT, and the first node N1 floats due to the cut-off driving of the fourth transistor T4, the voltage of the second node N2 of the driving transistor DRT increases until the voltage saturates to a magnitude corresponding to VDATA - |Vth|.

[0179] That is to say, after the sampling period S20, the gate-source potential difference of the driving transistor DRT, i.e., the voltage difference between the second node N2 and the third node N3, can correspond to the magnitude of the threshold voltage Vth, where the threshold voltage Vth is stored in the storage capacitor Cst.

[0180] Here, the voltage of the third node N3 of the driving transistor DRT corresponds to the data voltage VDATA, and the voltage of the second node N2 of the driving transistor DRT corresponds to the voltage difference VDATA - |Vth| between the data voltage VDATA and the absolute value |Vth| of the threshold voltage.

[0181] Therefore, the voltage difference between the third node N3 and the second node N2 of the driving transistor DRT becomes the magnitude of the threshold voltage Vth. Since this threshold voltage is stored in the storage capacitor Cst, the threshold voltage is sampled.

[0182] In other words, it can be understood that during the sampling period S20, the gate-source potential difference of the driving transistor DRT, that is, the voltage difference between the second node N2 and the third node N3 becomes the magnitude of the threshold voltage Vth, and since the voltage corresponding to the magnitude of the threshold voltage is stored in the storage capacitor Cst, the threshold voltage of the driving transistor DRT is sampled.

[0183] The source-gate voltage (Vsg) of the driving transistor DRT is maintained at the voltage |Vth| according to the following formula:

[0184] Vsg = Vs - Vg = VDATA - VDATA - |Vth| = VDATA - VDATA + |Vth| = |Vth|

[0185] As described above, the internal compensation sub-pixel circuit according to an embodiment of the present disclosure does not perform data writing by the capacitive coupling (cap coupling) method of supplying the data voltage stored in the capacitor applied by the sub-pixel structure shown in Figure 3 to the gate node of the driving transistor, but by directly applying the data voltage to the gate node of the driving transistor DRT during the sampling period (sensing period) S20 using the sub-pixel structure shown in Figure 4 , thereby being less affected by parasitic capacitors.

[0186] Figure 9 FIG. is a circuit and timing diagram illustrating the driving of the display device 100 according to an embodiment of the present disclosure during the holding period S30.

[0187] Referring to Figure 9 , during the holding period S30, the first transistor T1, the second transistor T2, and the fifth transistor T5 are cut off by the scan signal SCAN having a cut-off level voltage. In addition, during the holding period S30, the third transistor T3 and the fourth transistor T4 are cut off by the light emission control signal EM having a cut-off level voltage. Therefore, during the holding period S30, the voltage on the second node N2 is maintained at a voltage corresponding to VDATA - |Vth|.

[0188] The third node N3 holds the data voltage VDATA.

[0189] Here, Vs = VDATA = the voltage of the third node N3 = the source node voltage of the driving transistor DRT.

[0190] During the holding period S30, the voltage of the first node N1 of the driving transistor DRT can be increased by the conduction current of the driving transistor DRT. This can be a preparation process for light emission.

[0191] When the voltage of the first node N1 of the driving transistor DRT (i.e., the voltage of the first electrode of the light-emitting element ED) reaches a predetermined voltage (i.e., the voltage of the second electrode of the light-emitting element ED + the threshold voltage of the light-emitting element ED), the light-emitting element ED starts to emit light.

[0192] Figure 10 FIG. is a circuit diagram and a timing diagram illustrating the driving of the display device 100 according to an embodiment of the present disclosure during the light-emitting period S40.

[0193] Referring to Figure 10 , during the light-emitting period S40, the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned off by the scan signal SCAN having a cut-off level voltage. In addition, during the light-emitting period S40, the third transistor T3 and the fourth transistor T4 are turned on by the light-emission control signal EM having a conductive level voltage.

[0194] Therefore, during the light-emitting period S40, the voltage of the third node N3 of the driving transistor DRT becomes the high-potential voltage VDD. The voltage of the third node N3 is the data voltage VDATA during the holding period S30, and during the light-emitting period S40, as the second transistor T2 is turned off, the voltage of the third node N3 can become the high-potential voltage VDD transmitted through the third transistor T3.

[0195] During the light-emitting period S40, the high-potential voltage VDD is supplied to the third node N3, i.e., the source node, of the driving transistor DRT through the turned-on third transistor T3.

[0196] During the light-emitting period S40, the source node voltage Vs of the driving transistor DRT satisfies the equation: Vs = high-potential voltage VDD = the voltage of the third node N3.

[0197] During the light-emitting period S40, the voltage Vg of the gate node of the driving transistor DRT satisfies the equation: Vg = VDATA - |Vth| = the voltage of the second node N2.

[0198] During the light-emitting period S40, due to the relationship Vsd > Vsg > Vth, current flows through the driving transistor DRT to the light-emitting element ED.

[0199] During the light-emitting period S40, the equation is satisfied: Vsg = Vs - Vg = VDD - (VDATA - |Vth|) = VDD - VDATA + |Vth|.

[0200] During the light-emitting period S40, the current (Id) flowing through the driving transistor DRT and the current (Ioled) supplied to the light-emitting element ED are the same. Since the driving transistor DRT operates in the saturation region, the expression of the current is as follows:

[0201] Id = K[Vsg - |Vth|] 2 ,

[0202] where K is (1 / 2)*μ*Cox(W / L), μ is the electron mobility, Cox is the capacitance of the gate oxide layer per unit area, W is the channel width, and L is the channel length.

[0203] Specifically, the current supplied to the light-emitting element can be determined by Equation 1 below.

[0204] [Equation 1]

[0205] Ioled = K * [Vsg - |Vth|] 2 = K * [VDD - VDATA + |Vth| - |Vth|] 2 = K * [VDD - VDATA] 2

[0206] As described above, it can be seen that since the threshold voltage Vth of the driving transistor DRT is eliminated in Equation 1 for obtaining the current Ioled supplied to the light-emitting element ED, the current Ioled supplied to the light-emitting element ED is not affected by the threshold voltage Vth of the driving transistor DRT.

[0207] That is, since the influence of the threshold voltage Vth is eliminated during the sub-pixel driving, threshold voltage compensation is naturally generated during the sub-pixel driving.

[0208] The internal compensation sub-pixel circuit according to an embodiment of the present disclosure does not perform data writing by a capacitive coupling method of supplying the data voltage stored in the capacitor applied to the sub-pixel structure shown in Figure 3 to the gate node of the driving transistor, but directly applies the data voltage to the gate node of the driving transistor DRT during the sampling period (sensing period) S20 by using the sub-pixel structure shown in Figure 4 , thereby being less affected by parasitic capacitors.

[0209] In addition, according to an embodiment of the present disclosure, the scan signal line SCL and the light emission control signal line EML can be set to an integrated structure, so the number of lines can be reduced compared to the conventional structure. In other words, as Figure 4 shown, since the sub-pixel SP can be driven by only one scan signal SCAN and one light emission control signal EM, the number of multiple horizontal signal lines 1100 including the gate lines GL provided on the display panel 110 (see Figure 11 ) can be reduced. Therefore, the stretchable characteristics of the display device 100 can be further improved.

[0210] Figure 11 Illustrates an exemplary signal line configuration of the display device 100 according to an embodiment of the present disclosure.

[0211] The display device 100 according to an embodiment of the present disclosure may be a stretchable display device.

[0212] As Figure 11 shown, the display device 100 may have a plurality of line patterns. Each of the plurality of line patterns may have a zigzag shape including a plurality of bent portions.

[0213] The plurality of line patterns may include a plurality of horizontal signal lines 1100 and a plurality of vertical signal lines 1200.

[0214] For example, the horizontal signal lines 1100 may include scan signal lines SCL and emission control signal lines EML, and the vertical signal lines 1200 may include data lines DL, high potential voltage supply lines VDDL, and initialization voltage supply lines VINTL.

[0215] The plurality of horizontal signal lines 1100 and the plurality of vertical signal lines 1200 have a curved shape (e.g., a zigzag shape including a plurality of bent portions). For example, the plurality of horizontal signal lines 1100 and the plurality of vertical signal lines 1200 may have a sine wave shape.

[0216] However, the shape of the plurality of horizontal signal lines 1100 or the shape of the plurality of vertical signal lines 1200 is not limited thereto. For example, the plurality of horizontal signal lines 1100 and the plurality of vertical signal lines 1200 may extend in a zigzag shape. For another example, the plurality of horizontal signal lines 1100 and the plurality of vertical signal lines 1200 may have various shapes such as those in which a plurality of diamond substrates are connected at vertices and extend.

[0217] In addition, Figure 11 the number and shape of the plurality of horizontal signal lines 1100 or the number and shape of the plurality of vertical signal lines 1200 shown are illustrative, and the number and shape of the plurality of horizontal signal lines 1100 or the number and shape of the plurality of vertical signal lines 1200 may vary according to design.

[0218] Since the various signal lines 1100, 1200 have a zigzag shape as Figure 11 shown, in addition to the effect of increasing the flexibility of the signal lines, the effects of increasing the total cross-sectional area and total length of the signal lines can also be achieved, thereby improving the stretchable characteristics of the display device 100.

[0219] In addition, since as Figure 4In the structure shown in [FIG.], the sub-pixel SP can be driven by only one scan signal SCAN and one emission control signal EM, which can reduce the number of a plurality of horizontal signal lines 1100 including gate lines GL provided on the display panel 110. Therefore, the stretchability of the display device 100 can be further improved.

[0220] Here, the initialization period S10, the sampling period S20, and the holding period S30 correspond to a non-emission period during which the light-emitting element ED does not emit light.

[0221] Since no drive current flows through the light-emitting element ED during the non-emission period, the high-potential voltage VDD supplied to the corresponding sub-pixel hardly experiences a VDD drop. Therefore, the voltage stored in the storage capacitor Cst remains stable during the non-emission period.

[0222] In contrast, during the emission period S40, a drive current flows through the light-emitting element ED, thereby causing a VDD drop in the high-potential voltage VDD applied to the corresponding sub-pixel. Therefore, the voltage stored in the storage capacitor Cst can vary.

[0223] Therefore, at the same time point, the changes in the high-potential voltage VDD of the sub-pixels corresponding to the non-emission period and the sub-pixels corresponding to the emission period are different, and thus a brightness deviation may occur between the sub-pixels.

[0224] To solve this problem, the display device 100 of the present disclosure can reduce the brightness deviation caused by the drop of the high-potential voltage VDD by constantly maintaining the emission period of the emission control signal EM applied through the gate line.

[0225] Figure 12 is a schematic diagram illustrating a gate signal applied according to a driving timing in which the emission period is the same in a sub-pixel of a display device according to an embodiment of the present disclosure.

[0226] Here, for easy understanding, gate signals (i.e., a scan signal and an emission control signal) applied through a first gate line and a second gate line are shown.

[0227] Refer to Figure 12 , in the display device 100 according to an embodiment of the present disclosure, the driving time of the sub-pixel SP driven by the first gate line and the second gate line can include an initialization period, a sampling period, a holding period, and an emission period.

[0228] The second gate line can be driven with a delay of one horizontal blank period compared to the first gate line.

[0229] The initialization period is a period for initializing the voltages on the second node N2 and the third node N3 of the driving transistor DRT connected to each gate line.

[0230] During the initialization period, each of the scan signals SCAN1, SCAN2 and the light emission control signals EM1, EM2 has a conductive level voltage. Here, since the first transistor T1 to the fifth transistor T5 are P-type transistors, the conductive level voltage can be a low level voltage and the cut-off level voltage can be a high level voltage.

[0231] The operation of the sub-pixel during the initialization period is the same as that shown in Figure 7 the figure.

[0232] The first initialization period INT1 caused by the first scan signal SCAN1 and the first light emission control signal EM1 applied through the first gate line and the second initialization period INT2 caused by the second scan signal SCAN2 and the second light emission control signal EM2 applied through the second gate line may have the same time interval.

[0233] The sampling period is a period for detecting and storing the threshold voltage of the driving transistor DRT connected to the respective gate lines. During the sampling period, the scan signals SCAN1, SCAN2 have a conductive level voltage, and the light emission control signals EM1, EM2 have a cut-off level voltage.

[0234] The operation of the sub-pixel during the sampling period is the same as that shown in Figure 8 the figure.

[0235] The first sampling period SAMPLING1 caused by the first scan signal SCAN1 and the first light emission control signal EM1 applied through the first gate line and the second sampling period SAMPLING2 caused by the second scan signal SCAN2 and the second light emission control signal EM2 applied through the second gate line may have the same time interval.

[0236] The initialization period and the sampling period can be a sensing period for sensing the threshold voltage.

[0237] The holding period is a stage (or period) before the start of the light emission period. During the holding period, the scan signals SCAN1, SCAN2 and the light emission control signals EM1, EM2 have a cut-off level voltage.

[0238] The operation of the sub-pixel during the holding period is the same as that shown in Figure 9 the figure.

[0239] The first holding period HOLD1 caused by the first scan signal SCAN1 and the first emission control signal EM1 applied through the first gate line and the second holding period HOLD2 caused by the second scan signal SCAN2 and the second emission control signal EM2 applied through the second gate line may have different time intervals.

[0240] The emission period is the period during which the light-emitting element ED emits light. During the emission period, the scan signals SCAN1 and SCAN2 have a cut-off level voltage, and the emission control signals EM1 and EM2 have a conductive level voltage. As a result, a path for current to flow to the light-emitting element ED can be formed.

[0241] The operation of the sub-pixel during the emission period is the same as that Figure 10 shown in.

[0242] The first emission period EMISSION1 caused by the first scan signal SCAN1 and the first emission control signal EM1 applied through the first gate line and the second emission period EMISSION2 caused by the second scan signal SCAN2 and the second emission control signal EM2 applied through the second gate line may have the same time interval.

[0243] The display device 100 according to the present disclosure can operate in such a manner that scan signals and emission control signals are applied at different time points according to the position of the gate lines, but the emission periods are the same. In this regard, the initialization period, the sampling period, and the emission period can be the same for all gate lines, but the holding period can be controlled differently for each gate line according to the position of the gate line.

[0244] Figure 13 is a schematic diagram illustrating gate signals that maintain the same emission period in one frame in the display panel of the display device according to an embodiment of the present disclosure.

[0245] Referring to Figure 13 According to an embodiment of the present disclosure, the display device 100 can sequentially apply gate signals (i.e., scan signals and emission control signals) to all the gate lines of the display panel 110 within one frame.

[0246] When n gate lines are provided on the display panel 110, the gate signals can be sequentially applied from the first gate line to the nth gate line.

[0247] For example, the first scan signal SCAN1 and the first emission control signal EM1 can be applied to the first gate line according to the Figure 12 timing of.

[0248] Therefore, the signal level of each of the first scan signal SCAN1 and the first light emission control signal EM1 may vary according to the initialization period INT, the sampling period SAMPLING, the holding period HOLD, and the light emission period EMISSION.

[0249] The second gate line may apply the second scan signal SCAN2 and the second light emission control signal EM2 with a delay of, for example, one horizontal blanking period compared to the first gate line.

[0250] The signal level of each of the second scan signal SCAN2 and the second light emission control signal EM2 may vary according to the initialization period INT, the sampling period SAMPLING, the holding period HOLD, and the light emission period EMISSION.

[0251] In addition, the (n - 1)th gate line may apply the (n - 1)th scan signal SCANn - 1 and the (n - 1)th light emission control signal EMn - 1 with a delay of one horizontal blanking period compared to the (n - 2)th gate line.

[0252] In addition, the nth gate line may apply the nth scan signal SCANn and the nth light emission control signal EMn with a delay of one horizontal blanking period compared to the (n - 1)th gate line.

[0253] In this case, one horizontal blanking period refers to the time delay period of the scan signal and the light emission control signal applied through adjacent gate lines, which may vary according to the size and resolution of the display panel 110.

[0254] In the display device 100 of the present disclosure, the initialization period, the sampling period, and the light emission period of the gate signal applied through each gate line may be generated at the same time interval, but the holding period may vary according to the position of the gate line. Therefore, the light emission periods of the light emission control signals applied through the gate lines may have the same time interval.

[0255] As a result, the display device 100 of the present disclosure can reduce the brightness deviation that occurs according to the position of the sub - pixels due to the drop of the high - potential voltage VDD during the light emission period, and can improve the image quality.

[0256] The above - mentioned embodiments of the present disclosure are briefly described as follows.

[0257] A display device according to an embodiment of the present disclosure may include: a display panel in which data lines and gate lines cross and a plurality of sub - pixels are arranged; a data driver configured to provide data signals to the data lines; and a gate driver configured to provide scan signals and light emission control signals to the gate lines.

[0258] Each of the sub-pixels may include a sub-pixel circuit. The sub-pixel circuit includes: a driving transistor for driving a light-emitting element; a first transistor controlled by the scan signal and electrically connected to the gate node and the drain node of the driving transistor; a second transistor controlled by the scan signal and electrically connected to the source node of the driving transistor and the data line; a third transistor controlled by the light-emitting control signal and electrically connected to the high-potential voltage supply line and the source node of the driving transistor; a fourth transistor controlled by the light-emitting control signal and electrically connected to the drain node of the driving transistor and the light-emitting element; and a fifth transistor controlled by the scan signal and electrically connected to the initialization voltage supply line and the light-emitting element.

[0259] The sub-pixel circuit may further include a storage capacitor electrically connected to the high-potential voltage supply line and the gate node of the driving transistor.

[0260] The gate node of the first transistor, the gate node of the second transistor, and the gate node of the fifth transistor may be commonly connected to a scan signal line providing the scan signal.

[0261] The gate node of the third transistor and the gate node of the fourth transistor may be commonly connected to a light-emitting control signal line providing the light-emitting control signal.

[0262] The driving time of each of the sub-pixels may include an initialization period, a sampling period, a holding period, and a light-emitting period.

[0263] During the initialization period, an initialization voltage may be applied to the gate node of the driving transistor, and a high-potential voltage may be applied to the source node of the driving transistor.

[0264] During the initialization period, the initialization voltage may be applied to the gate node of the driving transistor through the fifth transistor, the fourth transistor, and the first transistor.

[0265] During the sampling period, the first transistor, the second transistor, and the fifth transistor may be turned on by the scan signal having a conductive-level voltage, and the third transistor and the fourth transistor may be turned off by the light-emitting control signal having a cut-off-level voltage.

[0266] During the sampling period, a data voltage may be applied to the source node of the driving transistor, and the voltage on the gate node of the driving transistor may change from the initialization voltage applied to the gate node of the driving transistor during the initialization period to a tracking voltage. The tracking voltage may correspond to a voltage obtained by subtracting the absolute value of the threshold voltage of the driving transistor from the data voltage.

[0267] During the sampling period, the tracking voltage may correspond to the difference between the data voltage and the absolute value of the threshold voltage of the driving transistor, and the gate-source potential difference of the driving transistor may correspond to the magnitude of the threshold voltage of the driving transistor.

[0268] During the holding period, the first transistor, the second transistor, and the fifth transistor may be turned off by the scan signal having a cut-off level voltage. During the holding period, the third transistor and the fourth transistor may be turned off by the light emission control signal having a cut-off level voltage.

[0269] During the holding period, the voltage of the drain node of the driving transistor may be increased by the conduction current of the driving transistor.

[0270] During the light emission period, the first transistor, the second transistor, and the fifth transistor may be turned off by the scan signal having a cut-off level voltage, and the third transistor and the fourth transistor may be turned on by the light emission control signal having a conduction level voltage.

[0271] During the light emission period, a high potential voltage may be applied to the source node of the driving transistor through the turned-on third transistor, the voltage on the gate node of the driving transistor may correspond to the difference between the data voltage and the absolute value of the threshold voltage of the driving transistor, and a current may flow through the driving transistor to the light emitting element.

[0272] During the light emission period, the magnitude of the current flowing to the light emitting element may be determined independently of the threshold voltage of the driving transistor.

[0273] At least one of the data line, the gate line, the initialization voltage supply line, and the high potential voltage supply line may have a zigzag shape including a plurality of bent portions.

[0274] In the driving times of sub-pixels driven by different gate lines, the light emission periods may have the same time intervals.

[0275] During the driving time of sub-pixels driven by different gate lines, the initialization period, the sampling period, and the light-emitting period may have the same time interval, and the holding period may have a different time interval.

[0276] A sub-pixel according to an embodiment of the present disclosure may include: a light-emitting element; a driving transistor for driving the light-emitting element; a first transistor controlled by a scan signal and electrically connected to the gate node and the drain node of the driving transistor; a second transistor controlled by the scan signal and electrically connected to the source node of the driving transistor and a data line; a third transistor controlled by a light-emitting control signal and electrically connected to a high-potential voltage supply line and the source node of the driving transistor; a fourth transistor controlled by the light-emitting control signal and electrically connected to the drain node of the driving transistor and the light-emitting element; and a fifth transistor controlled by the scan signal and electrically connected to an initialization voltage supply line and the light-emitting element.

[0277] The sub-pixel may further include a storage capacitor electrically connected to the high-potential voltage supply line and the gate node of the driving transistor.

[0278] The gate node of the first transistor, the gate node of the second transistor, and the gate node of the fifth transistor may be commonly connected to a scan signal line that provides the scan signal.

[0279] The gate node of the third transistor and the gate node of the fourth transistor may be commonly connected to a light-emitting control signal line that provides the light-emitting control signal.

[0280] One frame time for driving the sub-pixel may include: a first period (i.e., an initialization period), in which the source node of the driving transistor has a high-potential voltage provided through the high-potential voltage supply line, and the gate node of the driving transistor has an initialization voltage provided through the initialization voltage supply line; and a second period (i.e., a sampling period), in which the source node of the driving transistor has a data voltage provided through the data line, and the gate node of the driving transistor has a tracking voltage different from the data voltage.

[0281] The tracking voltage may correspond to a voltage obtained by subtracting the absolute value of the threshold voltage of the driving transistor from the data voltage.

[0282] During the first period, the initialization voltage may be applied to the gate node of the driving transistor through the fifth transistor, the fourth transistor, and the first transistor.

[0283] A method of driving a display device according to an embodiment of the present disclosure may include: a first operation step (i.e., an initialization period) of applying a high potential voltage to a source node of the driving transistor in a sub-pixel including a light-emitting element and a driving transistor and applying an initialization voltage to a gate node of the driving transistor; and a second operation step (i.e., a sampling period) of applying a data voltage to the source node of the driving transistor.

[0284] In the second operation step, the gate node of the driving transistor may have a voltage obtained by subtracting an absolute value of a threshold voltage of the driving transistor from the data voltage, and a gate-source potential difference of the driving transistor may correspond to a magnitude of the threshold voltage.

[0285] In the second operation step, a first transistor connected to a drain node and a gate node of the driving transistor may be turned on.

[0286] In the first operation step, the initialization voltage may be applied to the gate node of the driving transistor through the first transistor.

[0287] The above description is presented to enable a person skilled in the art to make and use the inventive concept, and is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. The above description and the drawings are provided by way of example only to illustrate the inventive concept. That is, the disclosed embodiments are intended to exemplify the scope of the inventive concept.

Claims

1. A display device, comprising: A display panel in which data lines and gate lines intersect and a plurality of sub-pixels are arranged; a data driver configured to provide a data signal to the data line; a gate driver configured to provide a scanning signal and a light emitting control signal to the gate line; wherein each of the sub-pixels comprises a sub-pixel circuit, The sub-pixel circuit comprises: a driving transistor configured to drive the light emitting element; a first transistor controlled by the scan signal and electrically connected to a gate node and a drain node of the drive transistor; a second transistor controlled by the scan signal and electrically connected to a source node of the drive transistor and the data line; a third transistor controlled by the light emission control signal and electrically connected to a high potential voltage supply line and a source node of the driving transistor; a fourth transistor controlled by the light emission control signal and electrically connected to a drain node of the driving transistor and the light emitting element; and A fifth transistor is controlled by the scan signal and is electrically connected to an initialization voltage supply line and the light emitting element. 2 . The display device according to claim 1 , further comprising a storage capacitor electrically connected to the high potential voltage supply line and a gate node of the driving transistor.

3. The display device according to claim 1 , wherein the gate node of the first transistor, the gate node of the second transistor, and the gate node of the fifth transistor are commonly connected to a scanning signal line that provides the scanning signal, and A gate node of the third transistor and a gate node of the fourth transistor are commonly connected to a light emission control signal line that provides the light emission control signal.

4. The display device according to claim 1 , wherein the driving time of each of the sub-pixels includes an initialization period, a sampling period, a holding period, and a light emitting period, and During the initialization period, an initialization voltage is applied to a gate node of the driving transistor, and a high potential voltage is applied to a source node of the driving transistor. 5 . The display device of claim 4 , wherein during the initialization period, the initialization voltage is applied to a gate node of the driving transistor through the fifth transistor, the fourth transistor, and the first transistor.

6. The display device according to claim 4, wherein during the sampling period, the first transistor, the second transistor and the fifth transistor are turned on by the scan signal having an on-level voltage, and the third transistor and the fourth transistor are turned off by the light emitting control signal having an off-level voltage.

7. The display device according to claim 6, wherein during the sampling period, A data voltage is applied to the source node of the driving transistor, and A voltage on a gate node of the driving transistor changes from the initialization voltage applied to the gate node of the driving transistor during the initialization period to a tracking voltage.

8. The display device according to claim 7, wherein during the sampling period, The tracking voltage corresponds to a difference between the data voltage and an absolute value of a threshold voltage of the driving transistor, and The gate-source potential difference of the driving transistor corresponds to the magnitude of the threshold voltage of the driving transistor.

9. The display device according to claim 7, wherein during the holding period, the first transistor, the second transistor and the fifth transistor are turned off by the scan signal having a cut-off level voltage, and during the holding period, the third transistor and the fourth transistor are turned off by the light emitting control signal having a cut-off level voltage. 10 . The display device according to claim 7 , wherein during the holding period, a voltage of a drain node of the driving transistor is increased by a conduction current of the driving transistor.

11. The display device according to claim 7, wherein during the light emitting period, the first transistor, the second transistor and the fifth transistor are turned off by the scan signal having a cut-off level voltage, and the third transistor and the fourth transistor are turned on by the light emitting control signal having a turn-on level voltage.

12. A display device according to claim 11, wherein during the light-emitting period, a high potential voltage is applied to the source node of the driving transistor through the turned-on third transistor, a voltage on the gate node of the driving transistor corresponds to the difference between the data voltage and the absolute value of the threshold voltage of the driving transistor, and current flows to the light-emitting element through the driving transistor. 13 . The display device according to claim 12 , wherein during the light emission period, the magnitude of the current flowing to the light emitting element is determined independently of a threshold voltage of the driving transistor. 14 . The display device of claim 1 , wherein at least one of the data line, the gate line, the initialization voltage supply line, and the high potential voltage supply line has a zigzag shape including a plurality of bent portions. 15 . The display device according to claim 4 , wherein the light emitting periods have the same time interval in driving times of the sub-pixels driven by different gate lines.

16. The display device according to claim 4, wherein in the driving time of the sub-pixels driven by different gate lines, The initialization period, the sampling period and the light emitting period have the same time interval, and The holding periods have different time intervals.

17. A sub-pixel comprising: Light emitting element; a driving transistor configured to drive the light emitting element; a first transistor controlled by a scan signal and electrically connected to a gate node and a drain node of the drive transistor; a second transistor controlled by the scan signal and electrically connected to a source node of the drive transistor and a data line; a third transistor controlled by a light emission control signal and electrically connected to a high potential voltage supply line and a source node of the driving transistor; a fourth transistor controlled by the light emission control signal and electrically connected to a drain node of the driving transistor and the light emitting element; as well as A fifth transistor is controlled by the scan signal and is electrically connected to an initialization voltage supply line and the light emitting element. 18 . The subpixel of claim 17 , further comprising a storage capacitor electrically connected to the high potential voltage supply line and a gate node of the driving transistor.

19. The sub-pixel according to claim 17, wherein the gate node of the first transistor, the gate node of the second transistor, and the gate node of the fifth transistor are commonly connected to a scanning signal line that provides the scanning signal, and A gate node of the third transistor and a gate node of the fourth transistor are commonly connected to a light emission control signal line that provides the light emission control signal.

20. The sub-pixel according to claim 17, wherein one frame time for driving the sub-pixel comprises: a first period, in which a source node of the driving transistor has a high potential voltage provided through the high potential voltage supply line, and a gate node of the driving transistor has an initialization voltage provided through the initialization voltage supply line; and a second period, in which a source node of the driving transistor has a data voltage provided by the data line, and a gate node of the driving transistor has a tracking voltage different from the data voltage, The tracking voltage corresponds to a voltage obtained by subtracting an absolute value of a threshold voltage of the driving transistor from the data voltage. 21 . The subpixel of claim 20 , wherein during the first period, the initialization voltage is applied to a gate node of the driving transistor through the fifth transistor, the fourth transistor, and the first transistor.

22. A method of driving a display device comprising sub-pixels, each of the sub-pixels comprising a light emitting element and a driving transistor, the method comprising: A first operation step of applying a high potential voltage to a source node of the driving transistor and applying an initialization voltage to a gate node of the driving transistor; and a second operation step of applying a data voltage to a source node of the driving transistor, In the second operation step of applying the data voltage, the gate node of the driving transistor has a voltage obtained by subtracting the absolute value of the threshold voltage of the driving transistor from the data voltage, and the gate-source potential difference of the driving transistor corresponds to the magnitude of the threshold voltage.

23. The method of claim 22, wherein in the second operation step of applying the data voltage, a first transistor connected to a drain node and a gate node of the driving transistor is turned on. 24 . The method according to claim 23 , wherein in the first operation step of applying the high potential voltage and the initialization voltage, the initialization voltage is applied to a gate node of the driving transistor through the first transistor.

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