Method and system for controlling parallel work of multiple eflash IPs

Abstract

The invention relates to the technical field of memories, and discloses a control method and system for parallel work of multiple eflash IPs, and the method comprises the steps: designing an arbitration mechanism in a control circuit; and the control circuit performs arbitration mechanism processing on the received external instruction operation by using an arbitration mechanism, and performs corresponding operation on the plurality of eflash IPs according to the processed result, so that the parallel work of the plurality of eflash IPs is realized. According to the method, parallel work of a plurality of eflash IPs can be supported, continuous instruction operation can be arbitrated and processed, simultaneous operation of programming of a plurality of addresses and erasing of a plurality of sectors can be controlled, and status bits of flash in operation are enriched so that an instruction sending end can read the working state of each eflash IP.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a control method and system for multiple eflash IPs working in parallel. Background Art

[0002] Flash is a non-volatile memory that is not only electrically erasable and programmable, but also does not lose data during power outages, and has extremely low static power consumption. Flash is made up of transistors that store information in a transistor array. These transistors generally form NOR gates and NAND gates, which record and store information, i.e., high and low levels "1" and "0". Therefore, there are two main implementation technologies for flash: NOR technology and NAND technology, i.e., NAND flash and NOR flash.

[0003] The storage structure of NOR flash is divided into words and sectors. A sector is composed of several words. NOR flash has the following characteristics: First, it has independent data bus and address bus. Second, it can be programmed by single byte, but cannot be erased by single byte. It must be erased by sector or the whole chip.

[0004] Therefore, the existing NOR flash operations include programming operations, sector erase operations, full chip erase operations, and read operations; however, the existing NOR flash operations have the following limitations:

[0005] (1) The programming operation can only support programming of a single address. The flash chip can only receive other instruction operations after the programming of this address is completed;

[0006] (2) Sector erase cannot be performed in parallel with programming operations, and the status bit displays too little information during the operation;

[0007] (3) Continuous operation instructions issued by the instruction sending end cannot be arbitrated and processed.

[0008] Therefore, a control method for multiple eflash IPs working in parallel is urgently needed, which can support the parallel operation of multiple eflash IPs, arbitrate and process continuous instruction operations, realize the simultaneous operation of controlling the programming of multiple addresses and erasing of multiple sectors, and enrich the status bits of the flash in operation so that the instruction sending end can read the working status of each eflash IP. Summary of the invention

[0009] The present invention aims to provide a control method and system for multiple eflash IPs to work in parallel, which can support the parallel operation of multiple eflash IPs, arbitrate and process continuous instruction operations, and realize simultaneous operation of controlling programming of multiple addresses and erasing of multiple sectors.

[0010] To achieve the above object, the present invention provides the following technical solutions:

[0011] In a first aspect, an embodiment of the present invention provides a control method for multiple eflash IPs working in parallel, including:

[0012] Design arbitration mechanisms in control circuits;

[0013] The control circuit uses an arbitration mechanism to process the received external instruction operation, and performs corresponding operations on multiple eflash IPs according to the processed results, thereby realizing the parallel operation of multiple eflash IPs.

[0014] In a second aspect, an embodiment of the present invention provides a control system for multiple eflash IPs to work in parallel, the system comprising a control circuit and an eflash IP.

[0015] The control circuit is respectively connected to a plurality of eflash IPs, an arbitration mechanism is provided in the control circuit, and the control circuit receives external instruction operations;

[0016] The control circuit is used to perform arbitration processing on the external instruction operation by using an arbitration mechanism, and perform corresponding operations on multiple eflash IPs respectively according to the processed results, so as to realize the parallel operation of multiple eflash IPs.

[0017] The technical effects and advantages of the present invention are as follows: in view of the limitations of the prior art NOR flash, the present invention designs a control circuit, and designs an arbitration mechanism in the control circuit, which can support the parallel operation of multiple eflash IPs; the present invention uses the arbitration mechanism to process continuous external instruction operations, effectively reduces the loss of instructions, and can realize the simultaneous operation of controlling the programming of multiple addresses and the erasing of multiple sectors; and sets a corresponding status bit for each sector (i.e., each eflash IP), and when the sector where the read address is located is in an idle state, the data stored in the eflash IP can be read; and an indication bit of a programming error is added to the status bit, and the enriched status bit enables the instruction sending end (i.e., the host computer) to read the working status of each eflash IP.

[0018] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 This is a flowchart of the programming operation of the existing NOR flash;

[0021] Figure 2 This is a flow chart of the sector erase operation of the existing NOR flash;

[0022] Figure 3 A flow chart of a control method for multiple eflash IPs working in parallel according to an embodiment of the present invention;

[0023] Figure 4 This is a flow chart of the control circuit after receiving an external instruction operation in an embodiment of the present invention;

[0024] Figure 5 This is a flow chart after the control circuit receives the whole chip erase instruction in the embodiment of the present invention;

[0025] Figure 6 This is a flow chart after the control circuit receives a sector erase instruction in an embodiment of the present invention;

[0026] Figure 7 A flowchart of the control circuit receiving a read instruction operation in an embodiment of the present invention;

[0027] Figure 8 is a processing flow chart of the status register data2 in an embodiment of the present invention;

[0028] Fig. 9 The present invention is a schematic diagram of a control system in which multiple eflash IPs work in parallel. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] NOR flash in the prior art, such as Figure 1 As shown, the instruction sending end can only perform programming operation on one address in the same time period when sending the programming instruction, which cannot greatly improve the efficiency of erasing and programming.

[0031] The process of NOR flash sector erase operation in the prior art is as follows: Figure 2 As shown, the instruction sending end sends all the sector erase instructions to the flash chip in sequence, and the flash chip cannot be in the erase operation state or the programming operation state before sending; then the flash chip records the sector of the sector erase instruction, and then enters the waiting time. Before the waiting time ends, the instruction sending end can still continue to send the sector erase instruction to the flash chip for adding sector erase; once the flash chip starts to execute the sector erase operation, the flash chip will not be able to receive other instructions sent by the instruction sending end.

[0032] In summary, the NOR flash in the prior art can only program one address or erase one sector in the same time period. Once the flash chip starts the erase operation or programming operation, the flash chip will no longer receive instructions sent by the instruction sending end until the operation is completed.

[0033] During the flash chip programming and erasing operations, the flash chip is read and the flash chip will have a status bit for display, but the displayed information is relatively simple. Generally, two status bits are selected to indicate the status of the flash chip.

[0034] To address the deficiencies of the prior art, the present invention discloses a control method for multiple eflash IPs to work in parallel. Figure 3 As shown, including the following:

[0035] Step S1: designing an arbitration mechanism in a control circuit;

[0036] Step S2: the control circuit uses an arbitration mechanism to perform arbitration processing on the received external instruction operation, and performs corresponding operations on multiple eflash IPs (Embedded flash memory intellectual property) according to the processing results, so as to realize the parallel operation of multiple eflash IPs.

[0037] In some specific embodiments, Fig. 9 As shown, the control circuit in the present invention is for NOR flash, the control circuit is connected to the instruction sending end (the instruction sending end in this embodiment is the host computer), and the control circuit is connected to different eflash IPs respectively; after receiving the external instruction operation sent by the instruction sending end, the control circuit can realize parallel operation processing of multiple eflash IPs. Among them, the instruction sending end is connected to the control circuit through three connection lines (including instruction operation transmission line, instruction address transmission line, and data transmission line).

[0038] The eflash IP in the present invention belongs to a NOR flash structure, and therefore, the eflash IP in the present invention can support single-address programming operation, whole-chip erasing operation and reading operation.

[0039] Therefore, the external command operation includes an erase command operation, a program command operation and a read command operation; wherein the erase command operation includes a whole-chip erase command and a sector erase command.

[0040] The eflash IP has independent address lines and data lines, as well as some control signals; among them, the control signals generally possessed by the eflash IP are shown in Table 1, and these control signals are generally sent to the eflash IP through a control circuit.

[0041] Table 1eflash IP control signal table

[0042] ADDRESS Address Lines DATA Data cable PROG Programming enable signal ERASE Erase enable signal CE Chip select enable signal OE Output enable signal BUSY busy signal

[0043] Because in the prior art, the instruction sending end generally reads the status bit of the flash chip before issuing an instruction operation to the flash to determine whether the current flash chip is in an idle state; if the current flash chip is in an idle state, the instruction sending end sends the instruction operation; if the current flash chip is in a busy state, the instruction sending end waits until the current flash chip is in an idle state before sending the instruction operation; that is, in the prior art, instruction operations can only be executed one by one. If the instruction sending end continuously issues multiple instruction operations to the flash chip, the existing flash chip generally only executes the first instruction operation, which easily causes the loss of instruction operations.

[0044] In view of this defect of the prior art, an arbitration mechanism is designed in the control circuit in step S1 of the present invention, so that the subsequent control circuit arbitrates the external instruction operation issued by the instruction sending end through the arbitration mechanism and then controls the eflash IP operation, thereby realizing the parallel operation of the programming logic, sector erasing logic, whole chip erasing logic, data reading and status bit logic of multiple eflash IPs.

[0045] In some specific embodiments, step S1: designing an arbitration mechanism in a control circuit includes:

[0046] Set the priority of the external command operations except the read command operation, that is, set the priority of the whole chip erase command, sector erase command and program command operation, as shown in Table 2.

[0047] Table 2 Arbitration Priority

[0048] Command Operation Priority Whole chip erase command P0 Sector Erase Instructions P1 Programming command operation P2

[0049] The whole chip erase instruction is to perform the erase operation on all eflash IPs at the same time, that is, to perform the sector erase operation on each eflash IP, and has the highest priority, namely P0;

[0050] The present invention divides each eflash IP into a sector, and the sector erase instruction performs an erase operation on a certain eflash IP (i.e., corresponding to the entire chip erase of an eflash IP), with a P1 priority;

[0051] The programming instruction operation is an operation on a single address in a certain eflash IP (generally each eflash IP includes multiple addresses) and has the lowest priority, namely P2 priority.

[0052] That is, as shown in Table 2, the order of arbitration priorities is: the priority P0 of the whole chip erase instruction> the priority P1 of the sector erase instruction> the priority P2 of the program instruction operation.

[0053] The control circuit is then set to process the received continuous external command operations in order of priority.

[0054] The sector erase instruction and programming instruction operations for different eflash IPs do not conflict and can be performed simultaneously, that is, the priority comparison between the sector erase instruction and the programming instruction operation is only for the same eflash IP.

[0055] In some specific embodiments, step S2: the control circuit uses an arbitration mechanism to perform arbitration processing on the received external instruction operation, and performs corresponding operations on multiple eflash IPs according to the processed results, so as to realize the parallel operation of multiple eflash IPs, including:

[0056] The instruction sending end sends an external instruction operation to the control circuit, and the control circuit receives the external instruction operation;

[0057] If there are multiple instruction operations in the external instruction operation and each instruction operation is for a different eflash IP, the control circuit independently executes the corresponding instruction operation on different eflash IPs according to the external instruction operation, so as to realize the parallel operation of multiple eflash IPs; wherein, since the control circuit is respectively connected to multiple eflash IPs, each eflash IP (i.e., each sector) in the present invention can be operated independently;

[0058] If there are multiple instruction operations for the same eflash IP in the external instruction operation, the control circuit processes the external instruction operation using an arbitration mechanism, and executes multiple instruction operations on the eflash IP according to the processed result, thereby realizing continuous multi-instruction execution of one eflash IP.

[0059] In some specific embodiments, Figure 4 As shown, after the control circuit receives the external instruction operation sent by the instruction sending end, the control circuit determines whether the eflash IP is in an idle state during the external instruction operation;

[0060] If the eflash IP is in an idle state, the control circuit directly executes an external instruction operation on the eflash IP;

[0061] If the eflash IP is in a busy state, the control circuit performs arbitration mechanism processing on the instruction operation being executed by the eflash IP and the external instruction operation sent by the instruction sending end, and performs corresponding operations on the eflash IP according to the processed results.

[0062] The control circuit determines whether the eflash IP is in an idle state during the external instruction operation, including: the control circuit parses the received external instruction operation to obtain the eflash IP address to be operated, and determines whether the eflash IP where the eflash IP address to be operated is located is in an idle state.

[0063] Exemplarily, under the logic of the arbitration mechanism, the arbitration comparison of each instruction operation is as follows:

[0064] (1) Figure 5 As shown in the figure, when the control circuit receives the whole chip erase instruction sent by the instruction sending end:

[0065] The control circuit determines whether each eflash IP (i.e., each sector) is in an idle state;

[0066] If the currently judged eflash IP is in an idle state, the control circuit directly executes a full-chip erase instruction on this eflash IP;

[0067] If the currently judged eflash IP is in a busy state, the control circuit performs the arbitration mechanism processing as shown below on the instruction operation being executed by this eflash IP and the full-chip erase instruction, and performs corresponding operations on this eflash IP according to the processed result. Figure 5 That is, after the control circuit receives the full-chip erase instruction sent by the instruction sender, it compares the priority of the instruction operation being executed by each eflash IP with the full-chip erase instruction, and then performs corresponding operations on the eflash IP according to the priority comparison result.

[0068] Since the operations of the eflash IP include sector erase and programming operations in addition to full-chip erase, and the priorities of these two operations are both lower than that of full-chip erase; but the execution process of the full-chip erase of the eflash IP is to perform sector erase on each eflash IP.

[0069] Therefore, when the instruction operation being executed by this eflash IP is a sector erase instruction, this eflash IP continues to execute the current operation;

[0070] When the instruction operation being executed by this eflash IP is a programming instruction operation, the control circuit terminates the current programming instruction operation of this eflash IP and executes a sector erase instruction on the eflash IP.

[0071] When the instruction operation being executed by this eflash IP is a programming instruction operation, the control circuit terminates the current programming instruction operation of this eflash IP and executes a sector erase instruction on the eflash IP.

[0072] (2) As shown below, when the control circuit receives the sector erase instruction sent by the instruction sender: Figure 6 The control circuit determines whether the eflash IP in the sector erase instruction is in an idle state;

[0073] If the currently judged eflash IP is in an idle state, the control circuit directly executes a sector erase instruction on this eflash IP;

[0074] If the currently judged eflash IP is in a busy state, the control circuit performs the arbitration mechanism processing (i.e., priority comparison) as shown below on the instruction operation being executed by this eflash IP and the sector erase instruction, and then performs corresponding operations on the eflash IP according to the priority comparison result:

[0075] If the currently judged eflash IP is in a busy state, the control circuit performs the arbitration mechanism processing (i.e., priority comparison) as shown below on the instruction operation being executed by this eflash IP and the sector erase instruction, and then performs corresponding operations on the eflash IP according to the priority comparison result: Figure 6 The control circuit performs the arbitration mechanism processing (i.e., priority comparison) as shown below on the instruction operation being executed by this eflash IP and the sector erase instruction, and then performs corresponding operations on the eflash IP according to the priority comparison result:

[0076] When the instruction operation being executed by the eFlash IP is a sector erase instruction, the control circuit discards the received sector erase instruction;

[0077] When the instruction operation being executed by the eFlash IP is a programming instruction operation, the control circuit terminates the programming instruction operation of the eFlash IP and executes a sector erase instruction on the eFlash IP;

[0078] (3) When the control circuit receives a programming instruction operation sent by the instruction sender:

[0079] The control circuit determines whether the eFlash IP where the programming address is located in the programming instruction operation is in an idle state;

[0080] If the currently judged eFlash IP is in an idle state, the control circuit directly executes the programming instruction operation on this eFlash IP;

[0081] If the currently judged eFlash IP is in a busy state, since the programming instruction operation has the lowest priority in the present invention, the control circuit discards the received programming instruction operation.

[0082] In some specific embodiments, as Figure 7 shown, when the external instruction operation received by the control circuit includes a read instruction operation (i.e., when the instruction sender performs a read operation on the eFlash IP), the control circuit parses the external instruction operation to obtain the address in the external instruction operation, and while judging whether the eFlash IP where the address in the external instruction operation is located is in an idle state, provides the instruction sender with the address storage data or the eFlash IP status bit corresponding to the external instruction operation, including:

[0083] If the eFlash IP is in an idle state, the control circuit reads the data stored in the eFlash IP (i.e., the stored data of the eFlash IP) and displays it on the data line, so that the instruction sender can obtain the data stored at the address in the external instruction operation (i.e., the stored data of the address); wherein, the control circuit communicates with the instruction sender through the data line, address line and control line to realize the transmission of data, address and control signals;

[0084] If the eFlash IP is in a busy state, the control circuit further judges the busy state of the eFlash IP and displays the status bit of the eFlash IP on the data line (i.e., Fig. 9 the instruction operation transmission line in) so that the instruction sender can obtain the status bit of this eFlash IP.

[0085] In some specific embodiments, the control circuit further determines the busy state of the eflash IP and displays the status bits of the eflash IP on the data line, including:

[0086] A corresponding status register is set for each eflash IP in the control circuit, and the status register is a three-bit status register;

[0087] When the eflash IP is in the programming operation state, the control circuit displays the status bits of the eflash IP on the data line, and after the instruction sending end completes the read instruction operation, the second status value data1 in the status register of the eflash IP is inverted;

[0088] When the eflash IP is in the erase operation state, the control circuit displays the status bits of the eflash IP on the data line, and after the instruction sending end completes the read instruction operation, the first status value data0 in the status register of the eflash IP is inverted.

[0089] Among them, the status values of the status register include a first status value data0, a second status value data1, and a third status value data2, as shown in Table 3 specifically;

[0090] Table 3 Status register status values

[0091]

[0092] As shown in Table 3, the first status value data0 and the second status value data1 represent the current working state of the eflash IP; the third status value data2 represents whether an error occurs in the programming instruction operation of the eflash IP (i.e., an indication of the programming error state). Under normal conditions, data2 is 0, and when a programming error occurs, data2 will become 1.

[0093] In some specific embodiments, the control circuit determines whether an error occurs in the eflash IP during the execution of the programming instruction operation and displays it on the status register, as Figure 8 shown, including:

[0094] The control circuit receives the programming instruction operation sent by the instruction sending end, and when the eflash IP where the programming address in the programming instruction operation is located is in the idle state, the control circuit extracts the programming address and data in the programming instruction operation and compares and determines the data stored in the programming address with the data to be programmed in the programming instruction operation;

[0095] If the control circuit determines that the programming instruction operation programs the stored data of the eflash IP from 0 to 1, it indicates a programming error. The control circuit discards the programming instruction operation and sets the third status value data2 in the status register of the eflash IP to 1;

[0096] If the control circuit determines that the programming instruction operation programs the stored data of the eflash IP from 1 to 0, it indicates normal programming. The control circuit continues to control the eflash IP to execute the programming instruction operation.

[0097] In view of the limitations of the existing NOR flash technology, the present invention provides a control method for multiple eflash IPs to work in parallel, which can support the parallel operation of multiple eflash IPs; uses an arbitration mechanism to process continuous external instruction operations, effectively reducing the loss of instructions, and can realize the simultaneous operation of programming multiple addresses and erasing multiple sectors; and sets corresponding status bits for each sector (i.e., each eflash IP). When the sector where the read address is located is in an idle state, the stored data in the eflash IP can be read; and an indication bit for programming errors is added to the status bits, enriching the status bits so that the instruction sender can read the working status of each eflash IP.

[0098] Based on the same inventive concept, an embodiment of the present invention discloses a control system for multiple eflash IPs to work in parallel, as Fig. 9 shown. The system includes a control circuit and eflash IPs;

[0099] The control circuit is respectively connected to multiple eflash IPs. An arbitration mechanism is provided in the control circuit, and the control circuit receives external instruction operations;

[0100] The control circuit is used to perform arbitration mechanism processing on the external instruction operations by using the arbitration mechanism, and perform corresponding operations on multiple eflash IPs according to the processed results, so as to realize the parallel operation of multiple eflash IPs.

[0101] In some specific embodiments, the external instruction operations include erase instruction operations, programming instruction operations, and read instruction operations. The erase instruction operations include full-chip erase instructions and sector erase instructions;

[0102] The arbitration mechanism includes designing the priority order of the remaining external instruction operations except the read instruction operation, and setting the control circuit to process the received continuous external instruction operations according to the designed priority order;

[0103] Among them, the priority P0 of the full-chip erase instruction > the priority P1 of the sector erase instruction > the priority P2 of the programming instruction operation;

[0104] The priority of the sector erase instruction is compared with the priority of the programming instruction operation only for the same eflash IP.

[0105] In some specific embodiments, the system includes an instruction sending end, which is a host computer in this embodiment;

[0106] The instruction sending end is communicatively connected to the control circuit. The instruction sending end sends an external instruction operation to the control circuit, and the control circuit receives the external instruction operation.

[0107] The control circuit is used to, when the external instruction operation includes multiple instruction operations and each instruction operation therein is for a different eflash IP operation, control different eflash IPs to execute corresponding instruction operations according to the external instruction operation;

[0108] The control circuit is used to, when the external instruction operation includes multiple instruction operations and there are multiple instruction operations for the same eflash IP operation, process the external instruction operation by using an arbitration mechanism, and execute multiple instruction operations on this eflash IP according to the processed result.

[0109] In some specific embodiments, the control circuit is used to, after receiving the external instruction operation sent by the instruction sending end, judge the status of the eflash IP in the external instruction operation;

[0110] Among them, the control circuit is used to, when the eflash IP is in an idle state, control the eflash IP to execute the external instruction operation;

[0111] The control circuit is used to, when the eflash IP is in a busy state, perform an arbitration mechanism process on the instruction operation being executed by the eflash IP and the external instruction operation sent by the instruction sending end, and perform corresponding operations on the eflash IP according to the processed result.

[0112] Regarding the system in the above embodiments, the specific manners in which each unit module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated here in detail.

[0113] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A control method for multiple eflash IPs working in parallel, characterized in that: include: Design arbitration mechanisms in control circuits; The control circuit uses an arbitration mechanism to perform arbitration processing on the received external instruction operation, and performs corresponding operations on multiple eflashIPs according to the processed results, thereby realizing the parallel operation of multiple eflashIPs.

2. The control method for multiple eflash IPs working in parallel according to claim 1, characterized in that: Design arbitration mechanisms in the control circuit, including: The external instruction operation includes an erase instruction operation, a program instruction operation and a read instruction operation, and the erase instruction operation includes a whole-chip erase instruction and a sector erase instruction; Set the priority of other external instruction operations except the read instruction operation; among them, the priority of the whole chip erase instruction P0> the priority of the sector erase instruction P1> the priority of the programming instruction operation P2; Setting the control circuit to process the received continuous external command operations in order of priority; Among them, the priority comparison between the sector erase instruction and the programming instruction operation is only for the same eflash IP; The whole chip erase instruction performs the erase operation on all eflash IPs at the same time, that is, performs the sector erase operation on each eflash IP; The sector erase instruction performs an erase operation on a certain eflash IP; wherein each eflash IP is divided into a sector; The programming instruction operation is an operation on a single address in a certain eflash IP.

3. A control method for multiple eflash IPs working in parallel according to claim 1 or 2, characterized in that: The control circuit uses the arbitration mechanism to arbitrate the received external command operations, and performs corresponding operations on multiple eflash IPs according to the processed results, including: The control circuit receives an external instruction operation sent by the instruction sending end; If there are multiple instruction operations in the external instruction operation and each instruction operation is for a different eflash IP, the control circuit independently executes corresponding instruction operations on different eflash IPs according to the external instruction operation, thereby realizing parallel operation of multiple eflash IPs; If there are multiple instruction operations for the same eflash IP in the external instruction operation, the control circuit processes the external instruction operation using an arbitration mechanism, and executes multiple instruction operations on the eflash IP according to the processed results, thereby realizing continuous multi-instruction execution of one eflash IP.

4. The control method for multiple eflash IPs working in parallel according to claim 3, characterized in that: After the control circuit receives the external instruction operation sent by the instruction sending end, the control circuit determines whether the eflash IP in the external instruction operation is in an idle state: If the eflash IP is in an idle state, the control circuit directly executes an external instruction operation on the eflash IP; If the eflash IP is in a busy state, the control circuit performs arbitration mechanism processing on the instruction operation being executed by the eflash IP and the external instruction operation sent by the instruction sending end, and performs corresponding operations on the eflash IP according to the processed results.

5. The control method for multiple eflash IPs working in parallel according to claim 4, characterized in that: The control circuit determines whether the eflash IP in the external instruction operation is in an idle state, including: The control circuit parses the received external instruction operation to obtain the address in the external instruction operation, and determines whether the eflash IP where the address in the external instruction operation is located is in an idle state; Wherein, when the external instruction operation includes a read instruction operation, the control circuit determines whether the eflash IP at the address in the external instruction operation is in an idle state, and provides the address storage data or eflash IP status bit corresponding to the external instruction operation to the instruction sending end, including: If the eflash IP is in an idle state, the control circuit reads the stored data in the eflash IP and displays it on the data line, so that the instruction sending end obtains the data stored in the address in the external instruction operation; If the eflash IP is in a busy state, the control circuit further determines the busy state of the eflash IP and displays the state bit of the eflash IP on the data line, so that the instruction sending end obtains the state bit of the eflash IP; Wherein, the control circuit communicates with the instruction sending end via a data line.

6. The control method for multiple eflash IPs working in parallel according to claim 5, characterized in that: The control circuit further determines the busy state of the eflash IP and displays the state bit of the eflash IP on the data line, including: Set the status register corresponding to each eflash IP in the control circuit; If eflashIP is in the programming operation state, the control circuit displays the state bit of eflash IP on the data line, and after the instruction sending end completes the reading instruction operation, the second state value data1 in the state register of eflash IP is flipped; If eflashIP is in the erase operation state, the control circuit displays the state bit of eflash IP on the data line, and after the instruction sending end completes the read instruction operation, the first state value data0 in the state register of eflash IP is flipped; The state value of the state register includes a first state value data0, a second state value data1 and a third state value data2; The first state value data0 and the second state value data1 represent the current working state of the eflash IP, and the third state value data2 represents whether an error occurs in the programming instruction operation of the eflash IP.

7. The control method for multiple eflash IPs working in parallel according to claim 6, characterized in that: The control circuit determines whether an error occurs when the eflash IP executes the programming instruction operation, and displays it on the status register, including: The control circuit receives a programming instruction operation sent by the instruction sending end, and when the eflash IP where the address in the programming instruction operation is located is in an idle state, the control circuit extracts the address and data in the programming instruction operation, and compares and determines the data stored in the address with the data to be programmed in the programming instruction operation; If the control circuit determines that the programming instruction operation programs the storage data of the eflash IP from 0 to 1, it indicates that a programming error occurs, and the control circuit discards the programming instruction operation and sets the third state value data2 in the state register of the eflash IP to 1; If the control circuit determines that the programming instruction operation programs the storage data of the eflash IP from 1 to 0, it means that the programming is normal, and the control circuit continues to control the eflash IP to execute the programming instruction operation.

8. The control method for multiple eflash IPs working in parallel according to claim 4, characterized in that: The control circuit performs arbitration mechanism processing on the instruction operation being executed by the eflash IP and the external instruction operation sent by the instruction sending end, and performs corresponding operations on the eflash IP according to the processed results, including: If the control circuit receives the whole chip erase instruction sent by the instruction sending end, the control circuit compares the priority of the instruction operation being executed by the eflash IP with the whole chip erase instruction: When the instruction operation being executed is a sector erase instruction, the eflash IP continues to execute the current operation; when the instruction operation being executed is a programming instruction operation, the control circuit terminates the current programming instruction operation of the eflash IP and executes the sector erase instruction on the eflash IP; If the control circuit receives a sector erase instruction sent by the instruction sending end, the control circuit compares the priority of the instruction operation being executed by the eflash IP with the sector erase instruction: When the instruction operation being executed is a sector erase instruction, the control circuit discards the received sector erase instruction; when the instruction operation being executed is a programming instruction operation, the control circuit terminates the programming instruction operation of eflashIP and executes the sector erase instruction on eflashIP; If the control circuit receives a programming instruction operation sent by the instruction sending end, the control circuit compares the priority of the instruction operation being executed by eflashIP with the programming instruction operation, and then the control circuit discards the received programming instruction operation.

9. A control system in which multiple eflash IPs work in parallel, characterized in that: The system includes a control circuit and an eflash IP, The control circuit is respectively connected to a plurality of eflash IPs, an arbitration mechanism is provided in the control circuit, and the control circuit receives external instruction operations; The control circuit is used to perform arbitration processing on the external instruction operation by using an arbitration mechanism, and perform corresponding operations on multiple eflash IPs respectively according to the processed results, so as to realize the parallel operation of multiple eflash IPs.

10. A control system for multiple eflash IPs working in parallel according to claim 9, characterized in that: The external instruction operation includes an erase instruction operation, a program instruction operation and a read instruction operation, and the erase instruction operation includes a whole-chip erase instruction and a sector erase instruction; The arbitration mechanism includes designing a priority order of the external instruction operations other than the read instruction operation, and setting the control circuit to process the received continuous external instruction operations according to the designed priority order; Among them, the priority P0 of the whole chip erase instruction> the priority P1 of the sector erase instruction> the priority P2 of the programming instruction operation; The priority comparison between the sector erase command and the programming command operation is only for the same eflash IP; The whole chip erase instruction performs the erase operation on all eflash IPs at the same time, that is, performs the sector erase operation on each eflash IP; The sector erase instruction performs an erase operation on a certain eflash IP; wherein each eflash IP is divided into a sector; The programming instruction operation is an operation on a single address in a certain eflash IP.

11. A control system for multiple eflash IPs working in parallel according to claim 9 or 10, characterized in that: The system comprises an instruction sending end, The instruction sending end is in communication connection with the control circuit, and the control circuit receives an external instruction operation sent by the instruction sending end; The control circuit is used for executing corresponding instruction operations on different eflash IPs according to the external instruction operations when there are multiple instruction operations in the external instruction operations and each instruction operation is for different eflash IPs; The control circuit is used for, when there are multiple instruction operations for the same eflash IP in the external instruction operations, processing the external instruction operations by using an arbitration mechanism, and executing multiple instruction operations on the eflash IP according to the processed results.

12. A control system for multiple eflashIPs working in parallel according to claim 11, characterized in that: The control circuit is used to determine whether the eflash IP in the external instruction operation is in an idle state after receiving the external instruction operation sent by the instruction sending end; Wherein, the control circuit is used to execute external instruction operations on the eflash IP when the eflash IP is in an idle state; The control circuit is used to perform arbitration mechanism processing on the instruction operation being executed by the eflash IP and the external instruction operation sent by the instruction sending end when the eflash IP is in a busy state, and perform corresponding operations on the eflash IP according to the processed results.

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